High-speed data acquisition and storage device
By adopting the CML interface, serial-to-parallel conversion circuit, and ZYNQ architecture XC7Z045 processor, combined with NVMe hard drives, the shortcomings of the LVDS interface in high sampling rate and high-precision video data transmission are solved, realizing high-speed data acquisition and storage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAN LINGKAI ELECTRONIC TECH CO LTD
- Filing Date
- 2025-06-18
- Publication Date
- 2026-05-19
AI Technical Summary
In existing technologies, the LVDS interface cannot meet the requirements for high sampling rate and high precision video data transmission scenarios.
The XC7Z045 processor, which uses a CML interface, serial-to-parallel conversion circuit and ZYNQ architecture, combined with an NVMe hard drive, enables high-speed acquisition and storage of video data.
It achieves high sampling rate and high precision transmission of video data, improves data transmission speed and anti-interference performance, and meets the needs of high-speed data storage.
Smart Images
Figure CN224265030U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of data acquisition and storage technology, and in particular to a high-speed data acquisition and storage device. Background Technology
[0002] Among numerous data acquisition and transmission needs, video data occupies a very important position. Due to the large amount of video data, high speed requirements are placed on the devices during transmission.
[0003] Currently, video data transmission mostly uses the LVDS interface. Although this interface has advantages in conversion speed and anti-interference, with the improvement of converter accuracy, the LVDS interface can no longer meet the requirements in some high sampling rate and high precision acquisition and transmission scenarios. Utility Model Content
[0004] This application provides a high-speed data acquisition and storage device to solve the problem that the existing technology using the LVDS interface to transmit video data cannot meet the requirements of high sampling rate and high precision.
[0005] This application provides a high-speed data acquisition and storage device, including:
[0006] The CML interface is used to acquire video data;
[0007] A serial-to-parallel conversion circuit, connected to the CML interface, is used to convert the serial signal input from the CML interface into a parallel signal.
[0008] The main control chip is connected to the serial-to-parallel conversion circuit. The main control chip adopts the XC7Z045 processor with ZYNQ architecture.
[0009] The storage unit is connected to the main control chip and is used to store video data.
[0010] In one possible implementation, there are two CML interfaces, which support the acquisition of 1280×960×(8+12)bit and 640×512×(8+14)bit video data, respectively.
[0011] In one possible implementation, the serial-to-parallel conversion circuit includes a conversion chip, which is either TLK2501 or TLK2711.
[0012] In one possible implementation, the storage unit uses an NVMe hard drive.
[0013] In one possible implementation, a housing is also included, comprising a top cover, an outer shell, and a bottom plate. The CML interface is located on the top cover, and the serial-to-parallel conversion circuit, the main control chip, and the storage unit are all located on a circuit board, which is located inside the outer shell. The top cover and the bottom plate are located at the top and bottom of the outer shell, respectively.
[0014] In one possible implementation, an inner shell is also provided inside the outer shell, and the circuit board is located in the inner shell.
[0015] In one possible implementation, after the circuit board is installed in the inner housing, both the inner and outer housings are encapsulated with potting compound.
[0016] In one possible implementation, both the outer shell and the inner shell are made of aluminum alloy.
[0017] The high-speed data acquisition and storage device disclosed in this application has the following advantages:
[0018] The CML interface is used to acquire video data, which greatly improves the sampling rate and conversion accuracy compared to the existing LVDS interface. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 This is a block diagram of a high-speed data acquisition and storage device provided in an embodiment of this application.
[0021] Figure 2 The serial-to-parallel conversion circuit provided in the embodiments of this application.
[0022] Figure 3 The peripheral circuit of the main control chip provided in the embodiments of this application.
[0023] Figure 4 This is a schematic diagram of the internal structure of a high-speed data acquisition and storage device provided in an embodiment of this application.
[0024] Figure 5 This is a top view of a high-speed data acquisition and storage device provided in an embodiment of this application.
[0025] The following are the symbols in the attached diagram: 1. Top cover; 2. Outer shell; 3. Inner shell; 4. Circuit board; 5. Base plate; 6. CML interface. Detailed Implementation
[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0027] Figure 1-5 The present application provides a structural and circuit diagram of a high-speed data acquisition and storage device according to an embodiment of the present application. The present application provides a high-speed data acquisition and storage device, including:
[0028] CML interface 6 is used to acquire video data;
[0029] A serial-to-parallel conversion circuit is connected to CML interface 6. The serial-to-parallel conversion circuit is used to convert the serial signal input to CML interface 6 into a parallel signal.
[0030] The main control chip is connected to the serial-to-parallel conversion circuit. The main control chip adopts the XC7Z045 processor with ZYNQ architecture.
[0031] The storage unit is connected to the main control chip and is used to store video data.
[0032] For example, the CML interface 6 can use a connector of model HJ30J-9ZKP, which has a shielded and twisted-pair cable that can transmit high-speed differential serial data.
[0033] In the embodiments of this application, there are two CML interfaces 6, referred to as CML1 and CML2 respectively. The bandwidth of both CML interfaces 6 is 2Gbps. The performance of CML1 interface is 1280×960×(8+12)bit, 50Hz, 1.17Gbps, while the performance of CML2 interface is 640×512×(8+14)bit, 50Hz, 0.318Gbps.
[0034] CML stands for Current Mode Logic. CML circuits are primarily driven by current, making them arguably the simplest of all high-speed data interfaces. Their inputs and outputs are pre-matched, reducing the need for external components. They can be directly connected without requiring external matching. CML circuits also feature smaller swing and lower power consumption. Video transmission based on CML digital signals offers advantages such as good anti-interference performance, simple interface, and large bandwidth capacity, with a theoretical maximum speed of 10Gbps.
[0035] Furthermore, the serial-to-parallel conversion circuit includes a conversion chip, specifically a TLK2501 or TLK2711. Figure 2 In this context, the conversion chip is represented by U1.
[0036] It should be understood that Figure 2 This is only a schematic diagram of the serial-to-parallel conversion circuit connected to the CML1 interface. When the conversion chip used in the CML2 interface is also TLK2501, the serial-to-parallel conversion circuit connected to the CML2 interface will be the same as... Figure 2 The circuits are the same in the present application, therefore the embodiments of this application only differ in that... Figure 2 The image shows a serial-to-parallel conversion circuit connected to the CML1 interface.
[0037] Specifically, the TLK2501 / TLK2711 conversion chip is used to convert the serial data acquired by the CML interface into parallel data. The TLK2501 / TLK2711 are multi-gigabit transceivers used in ultra-high-speed bidirectional point-to-point data transmission systems. The TLK2501 supports effective serial interface speeds from 0.6Gbps to 1.5Gbps, supports 16-bit parallel data, and has a parallel clock range of 30–75MHz, while the TLK2711 supports effective serial interface speeds from 1.6Gbps to 2.5Gbps.
[0038] The video data acquired from CML interface 6 is received and converted by TLK2501 / TLK2711. The PL control logic of the main control chip reads the parallel port data and stores it in the storage unit. At this point, the storage device has completed the acquisition, transmission, and storage of CML video data.
[0039] Furthermore, the storage unit uses NVMe hard drives, which can meet the high-speed data storage requirements.
[0040] exist Figure 3 In this embodiment, the main control chip is represented by U2. The XC7Z045 main control chip used in this application is a fully programmable fusion chip based on the ZYNQ architecture. It inherits a dual-core processing system and programmable logic with rich features on a single chip. This chip integrates diverse programmable systems, rich and fast layers, flexible interconnect resources and advanced process technology into one, which can meet the requirements of high-speed, high-capacity and highly flexible programmable solutions.
[0041] In one possible embodiment, the device further includes a housing, which includes a top cover 1, an outer shell 2, and a bottom plate 5. A CML interface 6 is disposed on the top cover 1. The serial-to-parallel conversion circuit, the main control chip, and the storage unit are all disposed on a circuit board 4, which is disposed inside the outer shell 2. The top cover 1 and the bottom plate 5 are respectively disposed at the top and bottom of the outer shell 2.
[0042] For example, an inner shell 3 is also provided inside the outer shell 2, and the circuit board 4 is disposed in the inner shell 3. After the circuit board 4 is installed in the inner shell 3, the inner shell 3 and the interior of the outer shell 2 are potted with potting compound.
[0043] Furthermore, both the outer shell 2 and the inner shell 3 are made of aluminum alloy.
[0044] Furthermore, considering the assembly of the outer casing 2 and the inner casing 3 in the storage device, in order to prevent compression caused by the deformation difference between the inner and outer casings, the circuit board 4 and the CML interface 6 are connected by wires.
[0045] In this embodiment, the storage device operates with the storage unit connected to the PL of the main control chip. The PL writes data into the storage unit according to the starting storage address given by the PS. The PL and PS of the main control chip work together to complete the high-speed real-time recording, transmission, and storage of video data. The main control chip adopts a heterogeneous architecture. The PL completes the low-level CML video data reception, data transfer, and NVMe writing, which have high bandwidth and real-time requirements, while the PS completes configuration management, such as read / write control and initial read / write address configuration.
[0046] After testing on the same platform and in similar projects, the write speed of a single NVMe hard drive and PCIe Gen2×4 bus using the embodiments of this application can reach 1.2GB / s, and the read speed can reach 1.4GB / s.
[0047] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.
[0048] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.
Claims
1. A high-speed data acquisition and storage device, characterized in that, include: CML interface (6) is used to acquire video data; A serial-to-parallel conversion circuit is connected to the CML interface (6), and the serial-to-parallel conversion circuit is used to convert the serial signal input to the CML interface (6) into a parallel signal; The main control chip is connected to the serial-to-parallel conversion circuit, and the main control chip adopts the XC7Z045 processor with ZYNQ architecture; A storage unit is connected to the main control chip, and the storage unit is used to store the video data.
2. The high-speed data acquisition and storage device according to claim 1, characterized in that, The number of CML interfaces (6) is two, and the two CML interfaces (6) respectively support the acquisition of video data of 1280×960×(8+12)bit and 640×512×(8+14)bit.
3. The high-speed data acquisition and storage device according to claim 1, characterized in that, The serial-to-parallel conversion circuit includes a conversion chip, which is either TLK2501 or TLK2711.
4. The high-speed data acquisition and storage device according to claim 1, characterized in that, The storage unit uses an NVMe hard drive.
5. A high-speed data acquisition and storage device according to claim 1, characterized in that, It also includes a housing, which includes a top cover (1), an outer shell (2) and a bottom plate (5). The CML interface (6) is disposed on the top cover (1). The serial-to-parallel conversion circuit, the main control chip and the storage unit are all disposed on a circuit board (4). The circuit board (4) is disposed inside the outer shell (2). The top cover (1) and the bottom plate (5) are respectively disposed at the top and bottom of the outer shell (2).
6. A high-speed data acquisition and storage device according to claim 5, characterized in that, The outer shell (2) is further provided with an inner shell (3), and the circuit board (4) is disposed in the inner shell (3).
7. A high-speed data acquisition and storage device according to claim 6, characterized in that, After the circuit board (4) is installed in the inner shell (3), both the inner shell (3) and the outer shell (2) are potted with potting compound.
8. A high-speed data acquisition and storage device according to claim 6, characterized in that, Both the outer shell (2) and the inner shell (3) are made of aluminum alloy.