Semiconductor equipment

Abstract

To provide a semiconductor device with parasitic capacitance reduced.SOLUTION: A transistor 10 includes a substrate 100, an insulating layer 110 on the substrate, an oxide insulating layer 121 on the insulating layer, an oxide semiconductor layer 122 on the oxide insulating layer, an oxide insulating layer 123 on the insulating layer and the oxide semiconductor layer, a gate insulating layer 150 on the oxide insulating layer, a gate electrode layer 160 on the gate insulating layer, a side wall insulating layer 176 on the oxide insulating layer, an insulating layer 180 on the oxide insulating layer, a conductive layer 190 on low-resistance regions 125 and 127, and a conductive layer 195 on the conductive layer. The oxide semiconductor layer and the oxide insulating layer include the low-resistance region 125 or the low-resistance region 127. The side wall insulating layer is provided on the oxide insulating layer and includes a region in contact with a side surface of the gate insulating layer and the gate electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a product, a method, or a method of manufacturing; or to a process, a machine , relating to manufacture or composition of matter. In particular The present invention relates to, for example, semiconductor devices, display devices, light-emitting devices, energy storage devices, imaging devices, and the like. The present invention relates to a driving method or a method for manufacturing the same. In particular, one aspect of the present invention relates to a semiconductor device Or, regarding the method of its manufacture.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to the general term. Transistors and semiconductor circuits are forms of semiconductor devices. Also, memory devices, Display devices and electronic equipment may include semiconductor devices. [Background technology]

[0003] A technology that constructs transistors using semiconductor films formed on substrates with insulating surfaces is attracting attention. It is being considered. The transistor in question is used in integrated circuits (ICs) and image display devices (display devices), etc. It is widely applied in electronic devices. Silicon is used as a semiconductor thin film applicable to transistors. While condensate semiconductor materials are widely known, oxide semiconductors are attracting attention as another material. Yes, they are.

[0004] For example, indium (In), gallium (Ga), and as the active layer of a transistor. A transistor using an amorphous oxide semiconductor containing zinc (Zn) is disclosed in Patent Document 1. Yes, they are.

[0005] Furthermore, by forming a conductive layer on an oxide semiconductor layer and then performing a heat treatment, the oxide semiconductor A method for fabricating transistors with reduced layer resistance is disclosed in Patent Document 2 and Non-Patent Documents. Yes, they are. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Patent Document 2] Japanese Patent Publication No. 2013-175710 [Non-patent literature]

[0007] [Non-Patent Document 1] 2015 Symposuim on VLSI Technology Digest of Technical Papers T214-T215 [Overview of the project] [Problems that the invention aims to solve]

[0008] In fabricating semiconductor devices with highly integrated transistors, the miniaturization of transistors This is essential. However, in the miniaturization of transistors, the parasitic capacity of the transistor The problem lies in the increase in quantity.

[0009] In transistor operation, near the channel (for example, between the source electrode and the drain electrode) If raw capacitance exists, time is required to charge the parasitic capacitance, affecting the transistor's response. This reduces responsiveness, and consequently, the responsiveness of semiconductor devices.

[0010] Furthermore, the various processes involved in forming transistors (especially thin-film deposition and processing) are constantly evolving with increasing miniaturization. Controlling this is becoming increasingly difficult, as variations in the manufacturing process affect transistor characteristics, and furthermore... This can have a significant impact on reliability.

[0011] Therefore, one aspect of the present invention aims to reduce parasitic capacitance near a transistor. To do so. Or, one of the objectives is to provide a semiconductor device capable of high-speed operation. One of its objectives is to provide semiconductor devices with good electrical characteristics. Alternatively, reliability One of the objectives is to provide high-performance semiconductor devices. Or, transistors or semiconductors. One of the objectives is to reduce variations in the characteristics of the equipment caused by the manufacturing process. One of the objectives is to provide a semiconductor device having an oxide semiconductor with low loss. One of the objectives is to provide semiconductor devices that can be formed using a simple process. Alternatively, the present invention provides a semiconductor device with a configuration that can reduce the interface state density near an oxide semiconductor. One of the objectives is to provide a low-power semiconductor device. To make one of the objectives. Or, to make one of the objectives to provide a new semiconductor device, etc. Or One of the objectives is to provide a method for manufacturing the above-mentioned semiconductor device.

[0012] Furthermore, the description of these problems does not preclude the existence of other problems. The approach does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract other issues from the descriptions in the surfaces, claims, etc. [Means for solving the problem]

[0013] (1) One aspect of the present invention involves forming a first insulating layer on a substrate, and on the first insulating layer, a first oxide insulating layer, Then, a first oxide semiconductor layer is deposited in sequence, forming a first oxide insulating layer and a first oxide semiconductor layer. By etching it in an island shape using the first mask, the second oxide insulating layer and the second An oxide semiconductor layer is formed, and a second oxide semiconductor layer and a third oxide insulating layer are placed on the first insulating layer. A film is formed, a second insulating layer is formed on the tertiary oxide insulating layer, and a first conductive layer is formed on the second insulating layer. Then, the first conductive layer and the second insulating layer are selectively etched using the second mask. By doing so, a gate electrode layer and a gate insulating layer are formed, and the gate electrode layer is used as a mask. By using this method to add the first ion to the second oxide semiconductor layer, the first low-resistance region is created. Form a gate electrode layer, a third oxide insulating layer, and a third insulating layer on the first insulating layer. A sidewall insulating layer is formed by dry etching the third insulating layer, and the gate electrode A layer, a side wall insulating layer, a third oxide insulating layer, and a second conductive layer are formed on the first insulating layer, and then heat treatment is performed. This process is characterized by forming an alloyed region within the second oxide semiconductor layer. This is a method for fabricating semiconductor devices.

[0014] (2) Another aspect of the present invention involves forming a first insulating layer on a substrate, and on the first insulating layer, a first oxide insulating layer A layer and a first oxide semiconductor layer are sequentially deposited, forming a first oxide insulating layer and a first oxide semiconductor layer. The stacked layers are etched in an island-like manner using the first mask to create a second oxide insulating layer. and a second oxide semiconductor layer is formed, and a third oxide is formed on the second oxide semiconductor layer and the first insulating layer A oxide insulating layer is formed, a second insulating layer is formed on the tertiary oxide insulating layer, and a first insulating layer is formed on the second insulating layer. A conductive layer is formed, and the first conductive layer and the second insulating layer are selectively subjected to an electrolytic coating using a second mask. By cutting, a gate electrode layer and a gate insulating layer are formed, and the gate electrode layer is made By using it as a suction, the first low ion is added to the second oxide semiconductor layer. A resistive region is formed, and a gate electrode layer, a third oxide insulating layer, and a third insulating layer on the first insulating layer By forming a third insulating layer and performing dry etching on it, a side wall insulating layer is formed. Using the gate electrode layer and the sidewall insulating layer as masks, the second oxide semiconductor layer is subjected to A semiconductor characterized by the formation of a second low-resistance region by adding a second ion. This describes the method for manufacturing the device.

[0015] (3) In the above-described method for manufacturing a semiconductor device, the second conductive layer is made of molybdenum, titanium, tantalum, It is preferable that the material is a metal or nitride having one or more of the following: tungsten.

[0016] (4) In the above-described method for fabricating a semiconductor device, the first ion in the addition of the first ion is fluorine. , one or more of phosphorus, argon, and xenon, and the dose of the first ion is 1 × 10 13 ions / cm 2 The above 5 x 10 16 ions / cm 2 The following is preferable .

[0017] (5) In the above-described method for fabricating a semiconductor device, the second ion in the addition of the second ion is titanium. It is preferable that it be one or more of indium, molybdenum, tantalum, or tungsten. It's nice.

[0018] (6) Another aspect of the present invention is a first oxide insulating layer on a first insulating layer and an oxide insulating layer on the first oxide insulating layer A material semiconductor layer, a second oxide insulating layer on the oxide semiconductor layer, and a gate insulating layer on the second oxide insulating layer It has an edge layer, a gate electrode layer on the gate insulating layer, and a sidewall insulating layer on the oxide semiconductor layer, The lower surface of the oxide semiconductor layer is higher than the lower surface of the gate electrode layer in the cross-section in the channel width direction. Located in a certain position, the oxide semiconductor layer faces the gate electrode layer on its top and side surfaces. The sidewall insulating layer has a region that is in contact with the side surface of the gate insulating layer, and the oxide semiconductor layer is It has a first to third region, the first region having a region that overlaps with the gate electrode layer, and the second region This is a region between the first region and the third region, and has a region that overlaps with the side wall insulating layer, and the second The region has a region with lower resistance compared to the first region, and the third region has a region with lower resistance compared to the second region. The first region has a low concentration of the first element, the second region has the first element, and the third region has the first and second elements. This semiconductor device is characterized by having a region that has [a certain characteristic].

[0019] (7) In the semiconductor device described above, a first conductive layer is provided beneath the oxide semiconductor layer, and the first conductive layer It is preferable that it has a region that overlaps with the oxide semiconductor layer.

[0020] (8) In the semiconductor device described above, the first element is one of fluorine, phosphorus, argon, or xenon. One or more elements, the second element being titanium, indium, molybdenum, tungsten, tantalum It is preferable that it be one or more of the following:

[0021] (9) In the semiconductor device described above, it is preferable that the third region has a region containing an alloy.

[0022] (10) Another aspect of the present invention is characterized by comprising the above-described semiconductor device and housing and a speaker. It is an electronic device. [Effects of the Invention]

[0023] Therefore, by using one aspect of the present invention, parasitic capacitance near the transistor can be reduced. This allows for the provision of semiconductor devices capable of high-speed operation. Alternatively, electrical characteristics This can provide a good semiconductor device. Or, it can provide a reliable semiconductor device. It is possible to... Or, the characteristics of a transistor or semiconductor device due to the manufacturing process... Variation can be reduced. Semiconductor devices having oxide semiconductors with low oxygen vacancies It can be provided. Or, it can be provided that a semiconductor device can be formed by a simple process. This can be done. Alternatively, a structure can be created that can reduce the interface state density near the oxide semiconductor layer. We can provide semiconductor devices that are built to last. Or, we can provide semiconductor devices that consume less power. This can be done. Or, a new semiconductor device can be provided. Or the above semiconductor A method for manufacturing the device can be provided.

[0024] Furthermore, the description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. Furthermore, other effects are... This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings Furthermore, it is possible to extract other effects from the descriptions in the claims and other documents. [Brief explanation of the drawing]

[0025] [Figure 1] Top view and cross-sectional view illustrating a transistor. [Figure 2]Cross-sectional view and band diagram of an oxide semiconductor layer transistor. [Figure 3] A diagram explaining the ALD film deposition principle. [Figure 4] ALD device overview diagram. [Figure 5] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 6] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 7] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 8] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 9] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 10] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 11] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 12] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 13] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 14] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 15] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 16] Top view and cross-sectional view illustrating a transistor. [Figure 17] Top view and cross-sectional view illustrating a transistor. [Figure 18] Top view and cross-sectional view illustrating a transistor. [Figure 19] A top view and a cross-sectional view illustrating the method for fabricating a transistor. [Figure 20] Figures illustrating the XRD structural analysis of CAAC-OS and single-crystal oxide semiconductors, as well as a figure showing the limited-field electron diffraction pattern of CAAC-OS. [Figure 21]Cross-sectional TEM images of CAAC-OS, as well as planar TEM images and their image analysis results. [Figure 22] Figure showing the electron diffraction pattern of nc-OS, and a cross-sectional TEM image of nc-OS. [Figure 23] Cross-sectional TEM image of an a-like OS. [Figure 24] A diagram showing the changes in the crystalline structure of In-Ga-Zn oxide due to electron irradiation. [Figure 25] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 26] Cross-sectional view and circuit diagram of a semiconductor device. [Figure 27] A plan view showing the imaging device. [Figure 28] A plan view showing the pixels of an imaging device. [Figure 29] A cross-sectional view showing the imaging device. [Figure 30] A cross-sectional view showing the imaging device. [Figure 31] A circuit diagram and timing chart illustrating a semiconductor device according to one embodiment of the present invention. [Figure 32] Graphs and circuit diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 33] A circuit diagram and timing chart illustrating a semiconductor device according to one embodiment of the present invention. [Figure 34] A circuit diagram and timing chart illustrating a semiconductor device according to one embodiment of the present invention. [Figure 35] A diagram illustrating an example of RF tag configuration. [Figure 36] A diagram illustrating an example of a CPU configuration. [Figure 37] Circuit diagram of a memory element. [Figure 38] A diagram illustrating an example of a display device configuration and a circuit diagram of a pixel. [Figure 39] Top view and cross-sectional view of a liquid crystal display device. [Figure 40] Top view and cross-sectional view of the light-emitting device [Figure 41] A diagram illustrating the display module. [Figure 42]A perspective view showing the cross-sectional structure of a package using a lead frame type interposer, and the configuration of the module. [Figure 43] A diagram illustrating electronic devices. [Figure 44] A diagram illustrating electronic devices. [Figure 45] A diagram illustrating electronic devices. [Figure 46] A diagram illustrating electronic devices. [Modes for carrying out the invention]

[0026] Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. Without departing from the spirit and scope of the present invention, its form and details may be changed in various ways. Those skilled in the art will readily understand that further improvements are possible. Therefore, the present invention can be implemented as follows: The description of the form is not to be interpreted as being limited to the content of the description. Furthermore, the structure of the invention described below In this context, the same reference numeral is used for identical parts or parts having similar functions across different drawings. It is used in this way, and the explanation of its repetition may be omitted. Note that the same elements that make up the figure Matching may be omitted or modified as appropriate between different drawings.

[0027] For example, in this specification, etc., if it is explicitly stated that X and Y are connected The cases are when X and Y are electrically connected and when X and Y are functionally connected. The cases disclosed in this specification, etc., include the case where X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the diagram or text. In addition to the connection relationships shown in the diagram or text, other connections may also be included as described in the diagram or text. do.

[0028] Here, X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer). (etc.)

[0029] One example of a case where X and Y are directly connected is when an electrical connection between X and Y is possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. If the diode, display element, light-emitting element, load, etc. are not connected between X and Y and elements that enable electrical connection between X and Y (e.g., switches, transistors, capacitors). Without the need for elements such as components, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc. This is the case when X and Y are connected.

[0030] One example of a case where X and Y are electrically connected is the ability to make an electrical connection between X and Y possible. Elements such as switches, transistors, capacitive elements, inductors, resistive elements, and dies. One or more devices (such as diodes, display elements, light-emitting elements, and loads) are connected between X and Y. Yes, it is possible. Furthermore, a switch has the function of being controlled to be on or off. In other words, a switch The switch can be in a conductive (on) or non-conductive (off) state, allowing current to flow. It has a function to control whether or not current flows. Alternatively, the switch selects the path through which current flows. It has a function to switch between them. Furthermore, if X and Y are electrically connected, X and This includes cases where Y is directly connected to it.

[0031] One example of a functional connection between X and Y is enabling a functional connection between X and Y. Circuits that perform this function (for example, logic circuits (inverters, NAND gates, NOR gates, etc.), signal transformers) Conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (electric (Source circuits (boost circuits, buck circuits, etc.), level shifter circuits that change the potential level of a signal, etc.) Voltage source, current source, switching circuit, amplification circuit (which can increase signal amplitude or current amount, etc.) Circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc., signal generation One or more circuits (such as memory circuits and control circuits) can be connected between X and Y. For example, even if another circuit is placed between X and Y, the signal output from X If the signal is transmitted to Y, then X and Y are assumed to be functionally connected. When X and Y are functionally connected, the situation is different from when X and Y are directly connected. This includes cases where and are electrically connected.

[0032] Furthermore, if it is explicitly stated that X and Y are electrically connected, then X and Y and When they are electrically connected (i.e., when there is another element or circuit between X and Y) (when connected) and when X and Y are functionally connected (i.e., X and Y are connected) (When functionally connected with another circuit in between) and when X and Y are directly connected In the case of (that is, when X and Y are connected without another element or circuit in between) and However, this shall be as disclosed in this specification, etc. That is, explicitly stated that they are electrically connected. If it is explicitly stated that it is connected, then Similar information is disclosed in this specification, etc.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or via (In short), electrically connected to X, the drain (or second terminal, etc.) of the transistor is connected to Z. If Y is electrically connected via (or without) 2, or if the transistor source (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. They are directly connected, with the transistor's drain (or second terminal, etc.) directly connected to a portion of Z2. If it is connected to and another part of Z2 is directly connected to Y, it can be expressed as follows: It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal) of the transistor." The terminals (such as the X terminal) are electrically connected to each other, and X is the source (or the X terminal) of the transistor. The electrical connections are in the following order: terminal 1, the drain of the transistor (or terminal 2, etc.), and Y. It can be expressed as "It is connected." Or, "The source (or the source) of the transistor." Terminal 1 (or terminal 2) is electrically connected to X, and the drain (or terminal 2) of the transistor is connected to X. (d) is electrically connected to Y, X is the source of the transistor (or the first terminal, etc.), and the transistor The drain (or second terminal, etc.) of the converter, Y, is electrically connected in this order. It can be expressed as "X is the source (or first terminal) of the transistor." Alternatively, "X is the source (or first terminal) of the transistor." Y is electrically connected to X via the drain (or second terminal, etc.) and X, the transistor The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) ), Y is provided in this connection order. By using a specific method of expression to define the order of connections in the circuit configuration, Distinguish between the source (or first terminal, etc.) and drain (or second terminal, etc.) of the zista. This allows us to determine the technical scope.

[0035] Alternatively, another way to express it is, for example, "the source (or first terminal, etc.) of the transistor." It is electrically connected to X via at least a first connection path, and the first connection path is It does not have a second connection path, and the second connection path is via a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor. The path between ( and ), and the above first connection path is a path via Z1, and the transit The drain (or second terminal, etc.) of the terminal is electrically connected to Y via at least a third connection path. They are connected in a manner, and the third connection path does not have the second connection path, and the third The connection path is the path via Z2. This can be expressed as "The transition The source of the starter (or the first terminal, etc.) is connected via Z1 through at least the first connection path. And, electrically connected to X, the first connection path does not have a second connection path. The second connection path described above has a connection path via a transistor, and the drain of the transistor (or a second terminal, etc.) is connected to Y via Z2 by at least a third connection path. It is expressed as, "They are electrically connected, and the third connection path does not have the second connection path." It is possible. Or, "the source (or first terminal, etc.) of the transistor is less Both are electrically connected to X via Z1 through the first electrical path, and the first electrical The target path does not have a second electrical path, and the second electrical path is the transistor From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor It is an electrical path, and the drain (or second terminal, etc.) of the transistor is at least third The electrical path is electrically connected to Y via Z2, and the third electrical path is , it does not have a fourth electrical path, and the fourth electrical path is the drain of the transistor The electrical pulse from (or the second terminal, etc.) to the source (or the first terminal, etc.) of the transistor It can be expressed as "It is S." Using similar methods of expression as these examples, the circuit configuration By defining the connection path in the transistor, the source (or first terminal) To distinguish between the drain (or second terminal, etc.) and the second terminal, and to determine the technical scope. It is possible.

[0036] Note that these methods of expression are just examples and are not limited to these methods. Here, X Y, Z1, and Z2 are the objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, etc.) Let's assume it is a layer, etc.

[0037] Note that, in circuit diagrams, independent components are shown as being electrically connected to each other. Even in such cases, one component may possess the functions of multiple components. For example, if part of the wiring also functions as an electrode, one conductive film will perform the function of the wiring, and It possesses the functions of both components of the electrode's function. Therefore, the electrode in this specification A conductive connection is a situation where a single conductive film combines the functions of multiple components. Combined forms are also included in that category.

[0038] <Notes regarding descriptions of drawings> In this specification, terms indicating placement, such as "above" and "below," refer to the positional relationship between components. These are used for convenience in explaining with reference to the drawings. Also, the positional relationships between the components are as follows: It changes appropriately depending on the direction in which the configuration is described. Therefore, the words and phrases described in the specification It is not limited and can be appropriately rephrased depending on the situation.

[0039] Furthermore, the terms "up" and "down" refer to situations where the relative positions of the constituent elements are directly above or directly below, and are in direct contact. It does not limit the meaning to what is being done. For example, if the expression is "electrode B on insulating layer A", It is not necessary for electrode B to be in direct contact with insulating layer A, but rather between insulating layer A and electrode B. This does not exclude those that include other components.

[0040] In this specification, "parallel" means that two straight lines are positioned at an angle of -10° or more and 10° or less. This refers to a state where the temperature is in a certain condition. Therefore, it also includes cases where the temperature is between -5° and 5°. A "row" refers to a state where two straight lines are positioned at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are positioned at an angle of 80° to 100°. Therefore, it also includes cases where the angle is between 85° and 95°. Also, "approximately perpendicular" means two This refers to a state in which two straight lines are arranged at an angle between 60° and 120°.

[0041] Furthermore, in this specification, if a crystal is trigonal or rhombohedral, it will be represented as a hexagonal crystal system. .

[0042] Furthermore, in the drawings, the size, layer thickness, or area is shown at an arbitrary size for the sake of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are intended to be clear. This is a schematic representation and is not limited to the shapes or values ​​shown in the drawings.

[0043] Furthermore, in drawings, such as top views (also called plan views or layout drawings) and perspective views, To ensure clarity in the drawings, some components may be omitted from the description.

[0044] Furthermore, "identical" means that they may have the same area or the same shape. Due to the manufacturing process, it is possible that the shapes may not be exactly the same, even if they are nearly identical. This can be rephrased as saying they are identical.

[0045] <Notes regarding paraphrasable descriptions> In this specification and other documents, when describing the connection relationships of transistors, one of the source and drain This is referred to as "either the source or the drain" (or the first electrode, or the first terminal), and the source and The other side of the drain is referred to as "the other side of the source or drain" (or the second electrode, or the second terminal). It is noted that the source and drain of a transistor are related to the structure or operation of the transistor. This is because it varies depending on the conditions, etc. Regarding the terminology for the source and drain of a transistor... This can be appropriately rephrased as source (drain) terminal or source (drain) electrode, depending on the situation. It is possible to obtain it.

[0046] Furthermore, in this specification, the terms "electrode" and "wiring" do not limit the functionality of these components. It is not fixed. For example, "electrode" can be used as part of "wiring". The reverse is also true. Furthermore, the terms "electrode" and "wiring" can refer to multiple "electrodes" and "wiring". This also includes cases where the "lines" are formed as a single unit.

[0047] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And, drain (drain terminal, drain A channel between the region (or drain electrode) and the source (source terminal, source region, or source electrode). It has a channel region, and current can be passed through the drain, channel region and source. It is something that can be worn.

[0048] Here, the source and drain vary depending on the transistor's structure or operating conditions. Therefore, it is difficult to determine which is the source and which is the drain. The part that functions as a source and the part that functions as a drain are not called source or drain. Let's refer to one of the source and drain as the first electrode, and the other of the source and drain as the second electrode. It may be written as such.

[0049] The ordinal numbers "1st," "2nd," and "3rd" used in this specification are intended to avoid confusion of constituent elements. This is added to avoid any misunderstanding and does not mean that the number is limited.

[0050] Furthermore, in this specification, the substrate of the display panel may be, for example, FPC (Flexible Printed Circuit). (Tracked Circuits) or TCP (Tape Carrier Pack) Items with ge) etc. attached, or COG (Chip On Glass) on the substrate In some cases, devices in which ICs (integrated circuits) are directly mounted are called display devices.

[0051] Furthermore, the words "membrane" and "layer" can be used interchangeably depending on the context or situation. Therefore, they can be interchanged. For example, the term "conductive layer" can be replaced with "conductive film." In some cases, it may be possible to change the term to "insulating film". Alternatively, for example, the term "insulating film" may be used. In some cases, it may be possible to change the term to "insulating layer."

[0052] <Notes regarding the definition of terms> The following sections will explain the definitions of terms used in this specification.

[0053] <About the connection> In this specification, "A and B are connected" means that A and B are not directly connected. This also includes things that are electrically connected. Here, A and B are electrically connected "Continued" means that there is an object between A and B that has some kind of electrical effect. This refers to a device that enables the exchange of electrical signals between A and B.

[0054] Furthermore, the content described in one embodiment (even a part of it) may vary depending on the form of its implementation. Other content (even partial content) described in the voice, and / or one or more other facts The content described in the form of implementation (even if only a part of it) may be applied, combined, or replaced. It is possible to perform tasks such as drawing.

[0055] Furthermore, the content described in each embodiment refers to the use of various figures in each embodiment. This refers to the content stated, or the content stated using the text described in the specification.

[0056] Furthermore, a diagram (even a partial one) described in one embodiment may refer to another part of that diagram. Further figures (even partial ones) described in that embodiment, and / or one or more In the diagram (or even just a part of it) described in another embodiment of the number, by combining them... This allows for the creation of even more diagrams.

[0057] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention and a method for manufacturing the same are described using drawings. explain.

[0058] <Structure of transistor 10> Figures 1(A), 1(B), and 1(C) are top views of a transistor 10 according to one embodiment of the present invention. These are cross-sectional views. Figure 1(A) is a top view, and Figure 1(B) is a cross-sectional view of the dashed line shown in Figure 1(A). Figure 1(C) is a cross-sectional view between A1 and A2, and between A3 and A4 as shown in Figure 1(A). In (A), some elements have been enlarged, reduced, or omitted from the diagram for clarity. Furthermore, the direction of the dashed line A1-A2 is the channel length direction, and the direction of the dashed line A3-A4 is the channel. This is sometimes referred to as the width direction.

[0059] The transistor 10 consists of a substrate 100, an insulating layer 110, an oxide insulating layer 121, and an oxide semiconductor Body layer 122, oxide insulating layer 123, low resistance region 125, low resistance region 127, gate Insulating layer 150, gate electrode layer 160, side wall insulating layer 176, insulating layer 180, conductive layer It has a 190 and a conductive layer 195.

[0060] The insulating layer 110 is provided on the substrate 100.

[0061] The oxide insulating layer 121 is provided on the insulating layer 110.

[0062] The oxide semiconductor layer 122 is provided on the oxide insulating layer 121.

[0063] The oxide insulating layer 123 is provided on the insulating layer 110 and the oxide semiconductor layer 122. Furthermore, the oxide insulating layer 123 may have a region that is in contact with the side surface of the oxide semiconductor layer 122. This protects the side edges of the oxide semiconductor layer 122, and the electrical properties of the transistor. The characteristics can be stabilized.

[0064] The oxide semiconductor layer 122 and the oxide insulating layer 123 have a low-resistance region 125 and a low-resistance region 1 It has 27. The low resistance region 125 is hydrogen, nitrogen, fluorine, helium, neon, argon. It contains one or more of krypton, xenon, boron, and phosphorus. Also, it has a low resistance region 1 27 includes materials shown in the low-resistance region 125, as well as titanium, molybdenum, tungsten, and chromium. , having one or more of the following: vanadium, niobium, tantalum, zirconium, hafnium The low-resistance regions 125 and 127 function as either a source or a drain. ru.

[0065] Furthermore, in the low-resistance region 127, the material described above and the oxide semiconductor layer 122 and oxide semiconductor layer The marginal layer 123 may also form an alloy. Forming an alloy can reduce resistance. can.

[0066] Low resistance region 125 in oxide semiconductor layer 122 and oxide insulating layer 123, and low The resistive region 127 can be described as an oxide conductive layer.

[0067] Furthermore, the structure does not have either the low-resistance region 125 or the low-resistance region 127. That's good too.

[0068] In the oxide semiconductor layer 122 and the oxide insulating layer 123, the gate electrode layer 160 overlaps The flannel region is the first region, the region overlapping the sidewall insulating layer 176 is the second region, and the gate electrode layer 160, The region where the side wall insulating layer 176 does not overlap is defined as the third region. In this case, the low-resistance region 125 is It can be provided in the second and third regions. The low-resistance region 127 is provided in the third region. This is possible. Furthermore, the low-resistance region 125 may extend into the first region, or the low-resistance region 127 In some cases, this may extend into the second domain. Compared to the third domain, this second domain is LDD. This can be called the (Lightly Doped Drain) region. Also, the low-resistance region. Region 125 and the low-resistance region 127 may extend into the oxide insulating layer 121.

[0069] Furthermore, in the above, the second region has a region with lower resistance compared to the first region, and the third region is It can be said that it has a region with lower resistance compared to the second region. Resistance is measured by resistance value measurement ( For example, it can be expressed by sheet resistance or impurity concentration.

[0070] Furthermore, in the third region, the concentration of the aforementioned elements is 1 × 10⁻⁶ 18 atoms / cm 3 That's all. , 1 x 10 22 atoms / cm 3 It has the following region:

[0071] The gate insulating layer 150 is provided on the oxide insulating layer 123.

[0072] The gate electrode layer 160 is provided on the gate insulating layer 150. The gate insulating layer 150, the oxide insulating layer 123, and the oxide semiconductor layer 122 are superimposed. It will be established.

[0073] The side wall insulating layer 176 is provided on the oxide insulating layer 123, and the gate insulating layer 150, gate electric It has a region that is in contact with the side surface of the polar layer 160.

[0074] The insulating layer 180 is provided on the oxide insulating layer 123.

[0075] The conductive layer 190 is provided on the low-resistance region 125 or the low-resistance region 127. 90 and the low-resistance region 125 or low-resistance region 127 have electrically connected regions. .

[0076] The conductive layer 195 is provided on the conductive layer 190.

[0077] By adopting the above structure, the parasitic capacitance between the gate and source, or between the gate and drain, is reduced. This can be achieved. As a result, the cutoff frequency characteristics of transistor 10 are improved, and so on. This enables high-speed operation of the inverter.

[0078] Furthermore, transistor 10 forms its gate, source, and drain in a self-aligned manner. This allows for a relaxation of alignment accuracy, making it easier to fabricate miniature transistors. It becomes possible.

[0079] Furthermore, as shown in the cross-sectional view of Figure 1(C)A3-A4, the transistor 10 is in the channel width direction. In this configuration, the gate electrode layer 160 is connected to the oxide insulating layer 121 via the gate insulating layer 150, and the acid It has regions facing the sides of the oxide semiconductor layer 122 and the oxide insulating layer 123. That is, gate When a voltage is applied to the electrode layer 160, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide The physical insulating layer 123 is surrounded by the electric field of the gate electrode layer 160 in the channel width direction. The structure of a transistor in which the semiconductor is surrounded by the electric field of the electrode layer 160 is described as surrounding This is called a channel (s-channel) structure. In this configuration, the lower surface of the oxide semiconductor layer 122 is positioned higher than the lower surface of the gate electrode layer 160. It gets kicked.

[0080] Here, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are combined. When an oxide is used, in transistor 10, in the ON state, the oxide semiconductor layer 122 Because channels are formed throughout (bulk), the ON current increases. On the other hand, in the OFF state... In addition, the entire channel region formed in the oxide semiconductor layer 122 is depleted, The flow can be made even smaller.

[0081] <About oxide insulating layers> Furthermore, the oxide insulating layer (for example, oxide insulating layer 121, oxide insulating layer 123) is basically It has insulating properties, and when the gate electric field or drain electric field becomes strong, near the interface with the semiconductor... This refers to a layer through which electric current can flow.

[0082] <Regarding channel length> Note that the channel length in a transistor refers, for example, to the top view of the transistor. A semiconductor (or the part of a semiconductor through which current flows when a transistor is ON) and a gate In the region where the electrode overlaps, or in the region where the channel is formed, the source (source region) This refers to the distance between the source electrode and the drain (drain region or drain electrode). Note that the channel length in a single transistor is not necessarily the same across all regions. No. In other words, the channel length of a single transistor may not be fixed to a single value. Therefore, in this specification, the channel length is any one of the regions in which the channel is formed. This value is the maximum, minimum, or average value.

[0083] <Regarding channel width> Channel width refers to, for example, the width of a semiconductor (or transistor) when it is in the ON state. This refers to the length of the region where the current-carrying part and the gate electrode overlap. In a channel, the channel width is not necessarily the same across all regions. That is, in a channel, The channel width of an inverter may not be fixed to a single value. Therefore, in this specification, The channel width is any one value, maximum value, or minimum value within the region where the channel is formed. The result will be the average value.

[0084] Furthermore, depending on the transistor structure, the channel may actually be formed in the region where the channel is formed. The channel width (hereinafter referred to as the effective channel width) and the top view of the transistor are shown. The channel width (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In transistors with a three-dimensional structure, the effective channel width is shown in the top view of the transistor. The apparent channel width shown in [the relevant section] becomes larger, and its effect can no longer be ignored. There are cases where this occurs. For example, in transistors with a fine and three-dimensional structure, the sides of the semiconductor In some cases, the proportion of the formed channel region may be large. In such cases, it is shown in the top view. The effective channel width in which the channel is actually formed is greater than the apparent channel width. The one becomes larger.

[0085] By the way, in transistors with a three-dimensional structure, the effective channel width is measured Estimation can be difficult in some cases. For example, estimating the effective channel width from the design value. In order to do this, it is necessary to assume that the shape of the semiconductor is known. If this information is not precisely known, it is difficult to accurately measure the effective channel width.

[0086] <SCWについて> Therefore, in this specification, in the top view of a transistor, the semiconductor and the gate electrode overlap. The apparent channel width in the region may be referred to as the "surrounded channel width (SCW)". Also, in this specification, when simply described as channel width, it may refer to the surrounded channel width or the apparent channel width. Or, in this specification, when simply described as channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, surrounded channel width, etc. can be determined by obtaining a cross-sectional TEM image and analyzing the image. In addition, when calculating the field-effect mobility of a transistor or the current value per channel width, etc., the surrounded channel width may be used for calculation, and in that case, the value may be different from the case of calculating using the effective channel width. <Improving Characteristics in Miniaturization> To highly integrate a semiconductor device, miniaturization of transistors is essential. On the other hand, it is known that the electrical characteristics of transistors deteriorate due to miniaturization of transistors, and when the channel width is reduced, the on-current decreases. For example, in the transistor of one aspect of the present invention shown in FIG. 1, as described above, an oxide insulating layer 123 is formed so as to cover the oxide semiconductor layer 122 in which the channel is formed, and the channel formation region and the gate insulating layer are not in contact with each other. Therefore, scattering of carriers generated at the interface between the channel formation region and the gate insulating layer can be suppressed, and the on-current of the transistor can be increased.

[0087]

[0088]

[0089]

[0090]

[0091] In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased. That is, a gate electric field is applied to the entire oxide semiconductor layer 122, and current flows through the entire oxide semiconductor layer 122, so that the on-current can be further increased.

[0091] In addition, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface levels by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 a layer located in the middle. In addition, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface levels by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 a layer located in the middle. In addition, the transistor according to one aspect of the present invention has effects such as making it difficult to form interface levels by forming the oxide insulating layer 123 on the oxide insulating layer 121 and the oxide semiconductor layer 122, and eliminating the influence of impurity mixing from above and below by making the oxide semiconductor layer 122 a layer located in the middle. Therefore, in addition to improving the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Therefore, in addition to improving the on-current of the transistor described above, the threshold voltage can be stabilized and the S value (subthreshold value) can be reduced. Thus, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. Thus, Icut (current when the gate voltage VG is 0V) can be lowered, and power consumption can be reduced. In addition, since the threshold voltage of the transistor is stabilized, the long-term reliability of the semiconductor device can be improved.

[0092] In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. In the transistor according to one aspect of the present invention, since the gate electrode layer 160 is formed so as to electrically surround the channel width direction of the oxide semiconductor layer 122 serving as a channel, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is applied to the oxide semiconductor layer 122. A gate electric field is applied. That is, the entire oxide semiconductor layer 122 is subjected to a gate electric field. This suppresses the influence of the drain electric field and significantly reduces the short-channel effect. Therefore, good characteristics can be obtained even when miniaturized. .

[0093] Furthermore, in one aspect of the present invention, the transistor has a wide oxide semiconductor layer 122 that forms the channel. By having a bandgap material, it has high source-drain breakdown pressure characteristics, and various It can have stable electrical characteristics in various temperature environments.

[0094] In this embodiment, if an oxide semiconductor layer is used in the channel, etc. While an example has been given, the embodiments of the present invention are not limited thereto. For example, a channel Depending on the circumstances, the source region, drain region, etc., may be used in the vicinity of the source region, drain region, etc. , silicon (including strained silicon), germanium, silicon germanium, silicon carbide, Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, organic semiconductors It may be formed from a material having, etc.

[0095] <Components of a transistor> The configuration of each transistor in this embodiment is shown below.

[0096] Circuit board 100 The substrate 100 may be, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. It can also be used. In addition, single-crystal semiconductor substrates made of silicon or silicon carbide, multi-bonded Crystal semiconductor substrate, compound semiconductor substrate made of silicon germanium, SOI (Silico It is also possible to use a substrate such as an n On Insulator substrate, and a substrate provided with semiconductor elements thereon may be used. The substrate 100 is not limited to a mere support material, and may be a substrate on which other devices such as other transistors are formed. In this case, one or more of the gate, source, and drain of the transistor may be electrically connected to the above-mentioned other devices.

[0097] Also, a flexible substrate may be used as the substrate 100. As a method of providing a transistor on the flexible substrate, after manufacturing a transistor on a non-flexible substrate, there is also a method of peeling off the transistor and transferring it to the substrate 100 which is a flexible substrate. In that case, it is preferable to provide a peeling layer between the non-flexible substrate and the transistor. In addition, as the substrate 100, a sheet, film or foil in which fibers are woven may be used. Also, the substrate 100 may have stretchability. Also, when the bending and pulling are stopped, the substrate 100 may have the property of returning to its original shape or may have the property of not returning to its original shape. The thickness of the substrate 100 is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. Making the substrate 100 thinner can reduce the weight of the semiconductor device Also, by making the substrate 100 thinner, in the case of using glass or the like, it may have stretchability, or when the bending and pulling are stopped, it may have the property of returning to its original shape Therefore, the impact applied to the semiconductor device on the substrate 100 due to dropping or the like can be alleviated. That is, a robust semiconductor device can be provided.

[0098] As the substrate 100 which is a flexible substrate, for example, metals, alloys, resins, glass, or their fibers and the like can be used. The substrate 100 which is a flexible substrate preferably has a lower linear expansion coefficient as it is more resistant to deformation caused by the environment. As the substrate 100 which is a flexible substrate, for example, a material with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less, or 1×10 -5 / K or less can be used. Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE), etc. In particular, aramid is suitable as the substrate 100 which is a flexible substrate because it has a low linear expansion coefficient.

[0099] 《Insulating layer 110》 The insulating layer 110 can use an insulating film containing one or more of silicon (Si), nitrogen (N), oxygen (O), fluorine (F), hydrogen ( )), aluminum (Al), gallium (Ga), germanium (Ge), yttrium ( Y), zirconium (Zr), lanthanum (La), neodymium (Nd), hafnium ( )), and tantalum (Ta).

[0100] In addition to preventing the diffusion of impurities from the substrate 100, the insulating layer 110 can play a role in supplying oxygen to the oxide semiconductor layer 122. Therefore, the insulating layer 110 is preferably an insulating film containing oxygen, and more preferably an insulating film containing more oxygen than the stoichiometric composition. For example, in the TDS method, the oxygen release amount in terms of oxygen atoms is 1.0 ×10 ×10 ×10 19 atoms / cm 3 or more. Note that the film during the above TDS analysis The surface temperature range is 100°C to 700°C, or 100°C to 500°C. This is preferable. Also, as described above, if the substrate 100 is a substrate on which other devices are formed The insulating layer 110 also functions as an interlayer insulating film. In that case, the surface becomes flat. Sea urchins are processed using methods such as CMP (Chemical Mechanical Polishing). It is preferable to perform a flattening treatment.

[0101] Furthermore, the presence of fluorine in the insulating layer 110 allows gas to be released from within the insulating layer. Fluorine can stabilize oxygen vacancies in the oxide semiconductor layer 122.

[0102] Oxide insulating layer 121, oxide semiconductor layer 122, oxide insulating layer 123 The oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 are made of In or Zn These are oxide semiconductor films containing [a specific component], typically In-Ga oxide, In-Zn oxide, and In -Mg oxide, Zn-Mg oxide, In-M-Zn oxide (where M is Al, Ti, Ga, Y) These include Sn, Zr, La, Ce, Mg, Hf, or Nd.

[0103] Since it is used as an oxide insulating layer 121, an oxide semiconductor layer 122, and an oxide insulating layer 123, The oxides used should preferably contain at least indium (In) or zinc (Zn). i. Alternatively, it is preferable to include both In and Zn. Also, transients using the oxide To reduce variations in the electrical characteristics of the stabilizers, it is preferable to include stabilizers along with them. It seems so.

[0104] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and aluminum. Examples include aluminum (Al) or zirconium (Zr). Also, other stabilizers... These are lanthanides: lanthanum (La), cerium (Ce), and praseodymium (P). r), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium ( Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium Examples include rhodium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu). .

[0105] Indium and gallium in oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 The amount of um and other elements can be determined by time-of-flight secondary ion mass spectrometry (TOF-SIMS) or X-ray electrolysis. This can be compared using XPS (X-ray Propulsion Spectroscopy) and ICP-MS (Intraductive Cell Mass Spectrometry).

[0106] The oxide semiconductor layer 122 has an energy gap of 2 eV or more, preferably 2.5 eV or more. More preferably, it is 3eV or more, which reduces the off-current of transistor 10. can.

[0107] The thickness of the oxide semiconductor layer 122 is 3 nm or more and 200 nm or less, preferably 3 nm or more and 10 The wavelength should be 0 nm or less, and more preferably 3 nm to 50 nm.

[0108] Furthermore, even if the thickness of the oxide semiconductor layer 122 is formed to be thinner than that of the oxide insulating layer 121 It is fine, it can be the same, or it can be formed thicker. For example, the oxide semiconductor layer 122 If the thickness is increased, the on-current of the transistor can be increased. Also, oxide insulating layer 12 1 is a thickness such that the effect of suppressing the formation of interface states in the oxide semiconductor layer 122 is not lost. It would be good if it were there. For example, the thickness of the oxide semiconductor layer 122 is equal to the thickness of the oxide insulating layer 121. It can be greater than 1x, or more than 2x, more than 4x, or more than 6x. Yes, it is possible. Also, if it is not necessary to increase the on-current of the transistor, the oxide insulating layer 12 The thickness of 1 may be greater than or equal to the thickness of the oxide semiconductor layer 122.

[0109] The oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123, each set If the composition is different, the interface is a scanning transmission electron microscope (STEM). Observation can be performed using a mission electron microscope. It is sometimes possible.

[0110] Furthermore, the oxide semiconductor layer 122 is more insulated than the oxide insulating layer 121 and the oxide insulating layer 123. Increasing the content is beneficial. In oxide semiconductors, the s orbitals of heavy metals are primarily involved in carrier conduction. In contributes to this, and by increasing the In content, more s orbitals overlap, so In Oxides with a higher concentration of In than M are compared to oxides with a concentration of In equal to or less than M. This increases mobility. Therefore, an oxide with a high In content is used in the oxide semiconductor layer 122. By using this method, it is possible to realize transistors with high field-effect mobility.

[0111] Furthermore, the oxide semiconductor layer 122 is made of In-M-Zn oxide (where M is Al, Ti, Ga, Y, Sn For example, in the case of Zr, La, Ce, Mg, Hf, or Nd, the oxide semiconductor layer 122 In a target used for film deposition by sputtering, the atomic ratio of metal elements If we set In:M:Zn=x2:y2:z2, then x2 / (x2+y2+z2) is 1 / 3 It is preferable to keep the above values. Also, x² / y² should be between 1 / 3 and 10, and moreover, 1 or more. It is 6 or less, and z² / y² is between 1 / 3 and 10, and furthermore, between 1 and 6. This is preferable. As a result, the oxide semiconductor layer 122 is CAAC-OS(C Axis Aligned Crystalline Oxide Semiconductor) This facilitates film formation. A typical example of the atomic ratio of the metal elements in the target is In :M:Zn=1:1:1, 1:1:1.2, 2:1:1.5, 2:1:2.3, 2:1: Examples include 3, 3:1:2, 4:2:3, 4:2:4.1, 5:1:7, etc.

[0112] The oxide insulating layer 121 and oxide insulating layer 123 have the function of a stabilizer. Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd, from In Having a high atomic ratio may have the following effects: (1) Oxide insulating layer 12 1. Increase the energy gap of the oxide insulating layer 123. (2) Oxide insulating layer 121 (3) Reduce the electron affinity of the oxide insulating layer 123. (4) Shield against impurities from the outside. (4) Compared to the oxide semiconductor layer 122, the insulating properties are higher. (5) Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd are metal elements with a strong affinity for oxygen. Because they are elements, Al, Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or N Having d in a higher atomic ratio than In makes oxygen deficiency less likely to occur.

[0113] Compared to the oxide semiconductor layer 122, the oxide film is less prone to oxygen vacancies. By providing contact with the top and bottom of the oxide semiconductor layer 122, oxygen vacancies in the oxide semiconductor layer 122 can be reduced. Yes, it is possible. Also, the oxide semiconductor layer 122 is one of the metal elements that make up the oxide semiconductor layer 122. The oxide insulating layer 121 and oxide insulating layer 123 have the above characteristics and are in contact with the oxide insulating layer 12 The interface between 1 and the oxide semiconductor layer 122, and the interface between the oxide semiconductor layer 122 and the oxide insulating layer 123. The interface state density on the surface is extremely low. Therefore, oxide insulating layer 121, oxide insulating layer 1 23. After adding oxygen to the gate insulating layer 150, insulating layer 110, or insulating layer 180, By heat treatment, the oxygen passes through the oxide insulating layer 121 and the oxide insulating layer 123 to form an acid Oxygen moves to the ionized semiconductor layer 122, but at this time, oxygen is trapped at the interface level. This efficiently removes the oxygen contained in the oxide insulating layer 121 or oxide insulating layer 123. It is possible to move it to the conductive layer 122. As a result, it is contained in the oxide semiconductor layer 122. It is possible to reduce oxygen deficiency. Also, oxide insulating layer 121 or oxide insulating layer Since oxygen is also added to 123, oxygen deficiencies occur in oxide insulating layer 121 and oxide insulating layer 123. It is possible to reduce the localized energy level density of at least the oxide semiconductor layer 122. It can be reduced.

[0114] Furthermore, the oxide semiconductor layer 122 contains insulating films with different constituent elements (for example, silicon oxide film). When in contact with the gate insulating layer, an interface state is formed, and this interface state forms a channel. This can happen. In such cases, a second transistor with a different threshold voltage appears, and the transistor The apparent threshold voltage of an inverter can fluctuate. However, oxide semiconductors... Oxide insulating layer 121 and oxide insulating layer 12 containing one or more metal elements that constitute layer 122 Since 3 is in contact with the oxide semiconductor layer 122, the oxide insulating layer 121 and the oxide semiconductor layer 122 It is difficult to form interface states at the interface and at the interface between the oxide insulating layer 123 and the oxide semiconductor layer 122. It will get worse.

[0115] In this embodiment, the amount of oxygen vacancies in the oxide semiconductor layer 122, and furthermore, the oxide semiconductor layer The amount of oxygen deficiency in the oxide insulating layer 121 and oxide insulating layer 123 in contact with 122 can be reduced. This is possible, and the localized level density of the oxide semiconductor layer 122 can be reduced. As a result, The transistor 10 shown in this embodiment has low threshold voltage fluctuation and high reliability. It can have properties. Furthermore, the transistor 10 shown in this embodiment has excellent electrical characteristics. It holds.

[0116] Furthermore, the gate insulating layer 150 and the oxide semiconductor layer 122 are in contact, and a channel is formed at their interface. If this occurs, interfacial scattering will occur at the interface, and the field-effect mobility of the transistor will decrease. Meanwhile, the oxide insulating layer 12 contains one or more metal elements that make up the oxide semiconductor layer 122. 1. Since the oxide insulating layer 123 is provided in contact with the oxide semiconductor layer 122, the oxide semiconductor Carrier scattering occurs at the interface between layer 122 and oxide insulating layer 121 and oxide insulating layer 123. This makes it less likely to cause problems, and allows for a higher field-effect mobility of the transistor.

[0117] The oxide insulating layer 121 and oxide insulating layer 123 are typically made of In-Ga oxide and In-Z oxide. n oxide, In-Mg oxide, Ga-Zn oxide, Zn-Mg oxide, In-M-Zn acid Molds (where M is Al, Ti, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd) Furthermore, the energy level at the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor layer 122. Typically, the energy levels at the lower end of the conduction band of the oxide insulating layer 121 and oxide insulating layer 123 And the difference between this and the energy level at the lower end of the conduction band of the oxide semiconductor layer 122 is 0.05 eV or more. 0.07eV or higher, 0.1eV or higher, or 0.2eV or higher and 2eV or lower, or 1eV or less Below, it is 0.5 eV or less, or 0.4 eV or less. That is, oxide insulating layer 121, oxide The difference between the electron affinity of the insulating layer 123 and the electron affinity of the oxide semiconductor layer 122 is 0.05 eV or higher, 0.07eV or higher, 0.1eV or higher, or 0.2eV or higher and 2eV or lower. , 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that electron affinity is true This shows the difference between the vacant energy level and the energy level at the bottom of the conduction band.

[0118] Furthermore, the oxide insulating layer 121 and oxide insulating layer 123 are made of In-M-Zn oxide (where M is Al, T is Al). For i, Ga, Y, Sn, Zr, La, Ce, Mg, Hf, or Nd, oxide semiconductors Compared to the body layer 122, the oxide insulating layer 121 and oxide insulating layer 123 contain M(Al, The atomic ratio of Ti, Ga, Y, Zr, Sn, La, Ce, Mg, Hf, or Nd is high The element represented by M mentioned above bonds more strongly to oxygen than indium, so oxygen deficiency occurs in oxides. It has the function of suppressing the formation of oxides in the insulating layer 121 and the oxide insulating layer 123. The insulating layer 121 and the oxide insulating layer 123 are less prone to oxygen vacancies than the oxide semiconductor layer 122. It is an oxide semiconductor film.

[0119] Furthermore, the oxide insulating layer 121 is made of In-M-Zn oxide (where M is Al, Ti, Ga, Y, Sn, In the case of Zr, La, Ce, Mg, Hf, or Nd, the oxide insulating layer 121 is sputtered In a target used for film deposition by the densification method, the atomic ratio of metal elements is set to In:M If Zn = x1:y1:z1, then x1 / y1 <z1 / y1であって、z1 / y1は、 It is preferable that the value is between 0.1 and 6, and more preferably between 0.2 and 3.

[0120] Furthermore, the oxide insulating layer 121 and oxide insulating layer 123 are more insulating than the oxide semiconductor layer 122. Due to its high edge-binding properties, it can have the same function as a gate insulating layer.

[0121] Furthermore, the oxide insulating layer 123 is made of metal oxides, such as aluminum oxide (AlOx), oxide Gallium (GaOx), hafnium oxide (HfOx), silicon oxide (SiOx), oxide It can also be replaced with germanium (GeOx) or zirconia oxide (ZrOx). Furthermore, the metal oxide may be present on the oxide insulating layer 123.

[0122] Furthermore, the oxide insulating layer 123 has the effect of suppressing the formation of interface states in the oxide semiconductor layer 122. The thickness should be such that it is not lost. For example, it should be equivalent to or less than the oxide insulating layer 121. The thickness should be such that if the oxide insulating layer 123 is thick, the electric field due to the gate electrode layer 160 is acid Because it may become difficult to reach the oxide semiconductor layer 122, the oxide insulating layer 123 is formed thinly. It is preferable that the oxide insulating layer 123 is thinner than the oxide semiconductor layer 122. This is sufficient. However, it is not limited to this, and the thickness of the oxide insulating layer 123 is the same as the gate insulating layer 150. Considering the voltage rating, the appropriate setting should be adjusted according to the voltage used to drive the transistor.

[0123] For example, the thickness of the oxide insulating layer 123 is 1 nm or more and 20 nm or less, or 3 nm or more and 10 nm or less. It is preferable to use a value of 1 nm or less.

[0124] Furthermore, the oxide insulating layer 123 is In-M-Zn oxide (where M is Al, Ti, Ga, Y, Sn, In the case of Zr, La, Ce, Mg, Hf, or Nd, oxide insulating layer 121, oxide insulating In a target used to deposit layer 123 by sputtering, metal elements If the atomic ratio of In:M:Zn = x3:y3:z3, then x3 / y3 <x2 / y2であ Therefore, z3 / y3 is preferably between 1 / 3 and 6, and more preferably between 1 and 6. Furthermore, by setting z3 / y3 to between 1 and 6, the oxide insulating layer 123 is made of CAAC-O S film formation becomes easier. A typical example of the atomic ratio of metal elements in the target is I n:M:Zn=1:3:2, 1:3:4, 1:3:6, 1:3:8, 1:4:4, 1:4 :5, 1:4:6, 1:4:7, 1:4:8, 1:5:5, 1:5:6, 1:5:7, 1 Other examples include 5:8, 1:6:8, 1:6:4, 1:9:6, etc. Note that atomic ratios are not limited to these. It is not necessary to use a semiconductor with an appropriate atomic ratio depending on the required semiconductor properties.

[0125] Furthermore, the atomic ratio of the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 is Each of these may include a variation of plus or minus 40% in the above atomic ratio as an error.

[0126] For example, when forming an oxide semiconductor film that will become an oxide semiconductor layer 122, In the target, the atomic ratio of the metal elements is set to In:Ga:Zn=1:1:1. When the film is formed, the atomic ratio of metal elements in the oxide semiconductor film is In:Ga:Zn = 1:1:0.6 To that extent, the atomic ratio of zinc may be the same or decrease. Therefore, the atomic ratio If specified, it includes the vicinity of the said atomic ratio.

[0127] <Regarding hydrogen concentration> Hydrogen contained in oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 It reacts with oxygen bonded to metal atoms to form water, and also the lattice from which the oxygen has been removed (or acid An oxygen vacancy is formed in the area where the element has been removed. When hydrogen enters this oxygen vacancy, it becomes a carrier. In some cases, electrons are generated. Also, some of the hydrogen combines with the metal atom and oxygen. This can generate electrons, which are carriers. Therefore, acids containing hydrogen... Transistors using a synthetic semiconductor layer tend to exhibit normally-on characteristics.

[0128] Therefore, the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and so At each interface, it is preferable that hydrogen is reduced as much as possible, along with oxygen vacancies. For example, oxide insulating layer 121, oxide semiconductor layer 122, oxide insulating layer 123, and Secondary ion mass spectrometry (SIMS) is performed at each interface. The hydrogen concentration obtained by mass spectrometry is 1 × 10⁻⁶ 16 at oms / cm 3 The above 2 x 10 20 atoms / cm 3 The following is preferably 1 × 10 16 at oms / cm 3 The above 5 x 10 19 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 More preferably 1×1 0 16 atoms / cm 3 The above 5 x 10 18 atoms / cm3 It is desirable to do the following: As a result, transistor 10 exhibits an electrical characteristic (normally) where the threshold voltage is positive. It can have off-peak characteristics.

[0129] <Regarding carbon and silicon concentrations> Furthermore, the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and each At this interface, if silicon or carbon, which are among the Group 14 elements, are present, oxide insulation occurs. Oxygen vacancies increased in layer 121, oxide semiconductor layer 122, and oxide insulating layer 123. Therefore, an n-type region may be formed. Body layer 122, oxide insulating layer 123, and silicon and carbon at their respective interfaces. It is desirable to reduce the concentration. For example, oxide insulating layer 121, oxide semiconductor layer 122 , oxide insulating layer 123, and silicon obtained by SIMS at each interface. The carbon concentration is 1 × 10 16 atoms / cm 3 The above 1 x 10 19 atoms / cm 3 The following is preferably 1 × 10 16 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 More preferably 1 × 10 16 atoms / cm 3 The above 2 x 10 18 atom / cm 3 It is desirable to do the following. As a result, transistor 10 has a threshold voltage of plus It can have electrical properties that result in a certain state.

[0130] <Regarding the concentrations of alkali metals and alkaline earth metals> Furthermore, alkali metals and alkaline earth metals generate carriers when they bond with oxide semiconductors. This can occur, and the transistor's off-current may increase. Therefore, acid The oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces. It is preferable to reduce the concentration of alkali metals or alkaline earth metals in the mixture. For example, oxide insulating layer 121, oxide semiconductor layer 122, oxide insulating layer 123, and each At the interface, alkali metals or alkaline earths obtained by secondary ion mass spectrometry The concentration of the metal is 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 Atom s / cm 3 The following is preferable. This allows transistor 10 to reach the threshold voltage It can have electrical properties that result in a positive charge.

[0131] <Regarding nitrogen concentration> Furthermore, the oxide insulating layer 121, the oxide semiconductor layer 122, the oxide insulating layer 123, and each If nitrogen is present at this interface, electrons, which are carriers, are generated, increasing the carrier density. An n-type region may be formed. As a result, an oxide semiconductor layer containing nitrogen may form. Transistors using this material tend to exhibit normally-on characteristics. Therefore, oxide insulating layer 121 In the oxide semiconductor layer 122, the oxide insulating layer 123, and their respective interfaces, nitrogen is It is preferable that the oxide insulating layer 121 and oxide semiconductor layer be reduced as much as possible. 122, oxide insulating layer 123, and nitrogen obtained by SIMS at each interface The elementary cardinality is 1 × 10⁻⁶ 15 atoms / cm 3 The above 5 x 10 19 atoms / cm3 below, Preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 18 atoms / cm 3 below, Better 1 × 10 15 atoms / cm 3 The above 1 x 10 18 atoms / cm 3 Below Below, more preferably 1 × 10 15 atoms / cm 3 The above 5 x 10 17 ate / c m 3 The following is preferable. This allows transistor 10 to have a threshold voltage of plastic It can have electrical properties that result in a certain state.

[0132] However, this does not apply if there is excess zinc in the oxide semiconductor layer 122. Excess zinc may form oxygen vacancies in the oxide semiconductor layer 122. Therefore, excess If zinc is present, 0.001 to 3 atomic% of nitrogen is present in the oxide semiconductor layer 122. By possessing this element, it may be possible to inactivate oxygen deficiencies caused by excess zinc. Therefore, the nitrogen eliminates variations in transistor characteristics and improves reliability. It can be made to happen.

[0133] <About carrier density> Impurities in the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 are reduced. By doing so, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 The carrier density can be reduced. Therefore, the oxide insulating layer 121 and the oxide semiconductor layer 122 and the oxide insulating layer 123 have a carrier density of 1 × 10 15 / cm 3 The following are preferred Or 1 x 10 13 / cm 3 More preferably 8 × 10 11 / cm 3 Less than, better Mashiku is 1 x 10 11 / cm 3 Less than 1 × 10 10 / cm 3 It is less than, 1 x 10 -9 / cm 3 That concludes this section.

[0134] Based on the above, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are used. By using oxides with low impurity concentrations and low defect level densities, even better electrical properties can be achieved. A transistor with the following properties can be fabricated. Here, the impurity concentration is low and the defect level is low. A substance with a low nitrate density (low oxygen deficiency) is called high-purity intrinsic or substantially high-purity intrinsic. The oxide, which is of high purity intrinsic or substantially high purity intrinsic, has few carrier sources. Therefore, the carrier density can be lowered in some cases. Consequently, the channel region of the oxide Transistors that form a region tend to have electrical characteristics where the threshold voltage is positive. Furthermore, because the oxide is of high purity intrinsic or substantially high purity intrinsic, it has a low defect level density. Furthermore, the trap level density may also be low. The oxide in question has a remarkably low off-current and a voltage (d) between the source electrode and the drain electrode. When the rain voltage is in the range of 1V to 10V, the off-current is measured by the semiconductor parameter analyzer. Below the measurement limit of the, i.e., 1 × 10⁻⁶ -13 It is possible to obtain the characteristic of being A or less. Therefore, Therefore, transistors in which a channel region is formed in the oxide exhibit small fluctuations in electrical characteristics. It can become a highly reliable transistor.

[0135] Furthermore, the transistor that uses the highly purified oxide in the channel formation region as described above The current is extremely small. For example, if the voltage between the source and drain is 0.1V, 5V, and When the voltage is around 10V, the off-current normalized by the transistor's channel width is several yA. It is possible to reduce the level to / μm or even a few zA / μm.

[0136] Furthermore, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are, for example, Non-single-crystal structures are also acceptable. Non-single-crystal structures include, for example, CAAC-OS, which will be described later, and polycrystalline structures. This includes a single-crystal structure, a microcrystalline structure, or an amorphous structure. Among non-single-crystal structures, the amorphous structure is the least desirable. CAAC-OS has a high defect level density, while CAAC-OS has the lowest defect level density.

[0137] Furthermore, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are, for example, A microcrystalline structure is also acceptable. A microcrystalline oxide insulating layer 121, an oxide semiconductor layer 122, and The oxide insulating layer 123 contains, for example, microcrystals with a size of 1 nm to less than 10 nm in the film. This may occur. Alternatively, the oxide insulating layer 121 and oxide semiconductor layer 122 have a microcrystalline structure. The oxide insulating layer 123, for example, has a crystalline portion of 1 nm to less than 10 nm in the amorphous phase. It has a multiphase structure.

[0138] The oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are, for example, amorphous. A amorphous structure is also acceptable. An amorphous structure, an oxide insulating layer 121, an oxide semiconductor layer 122, and an acid The ionized insulating layer 123, for example, has a disordered atomic arrangement and does not contain crystalline components. Or, The amorphous oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 are For example, it has a completely amorphous structure and does not contain any crystalline parts.

[0139] Furthermore, the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are CA A mixed film having regions of two or more structures: AC-OS, a microcrystalline structure, and an amorphous structure. This may also be the case. As a mixed film, for example, a region with an amorphous structure, a region with a microcrystalline structure, and CAAC - There is a monolayer structure having an OS region. Alternatively, as a mixed film, for example, an amorphous structure. There are regions of crystalline structure, regions of microcrystalline structure, and regions of CAAC-OS, forming a layered structure.

[0140] Note that the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 are, for example, It may also have a single-crystal structure.

[0141] Furthermore, oxide insulating layer 121 and oxide insulating layer 123 are the insulating layer 110 and gate insulating layer, respectively. The constituent elements of layer 150 are mixed into the oxide semiconductor layer 122, forming energy levels due to impurities. It also functions as a barrier film to suppress this process.

[0142] For example, an insulating film containing silicon may be used as the insulating layer 110 or the gate insulating layer 150. In this case, the silicon in the gate insulating layer 150, or the insulating layer 110 and the gate insulating layer 150 Carbon that may be mixed in may enter the oxide insulating layer 121 or oxide insulating layer 123 from the interface. Impurities such as silicon and carbon can be present in the oxide semiconductor layer 122. Upon entering, impurity levels are formed, and these impurity levels act as donors, generating electrons and thus transforming the material into an n-type molecule. There are things that need to be done.

[0143] However, if the film thickness of the oxide insulating layer 121 and oxide insulating layer 123 is thicker than a few nanometers, Therefore, impurities such as silicon and carbon that are mixed in do not reach the oxide semiconductor layer 122. The influence of impurity levels is reduced.

[0144] Therefore, by providing oxide insulating layer 121 and oxide insulating layer 123, the transistor Variations in electrical characteristics (such as threshold voltage) can be reduced.

[0145] Therefore, the oxide is used for the oxide insulating layer 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 By adopting this stacked structure, channels can be formed in the oxide semiconductor layer 122, and high It is possible to form transistors with field-effect mobility and stable electrical characteristics.

[0146] Note that the oxide layer does not necessarily have to be three layers, including the oxide insulating layer; it can be single-layer, double-layer, or four-layer. Furthermore, it may have a structure of five or more layers. In the case of a single layer, as shown in this embodiment, an oxide A layer equivalent to semiconductor layer 122 can be used.

[0147] <Band Diagram> Here, using Figures 2(A) and 2(B), the band diagram of a transistor according to one embodiment of the present invention is shown. Let me explain. The band diagram shown in Figure 2(B) is shown for ease of understanding, with the insulating layer 110 and the oxidation Material insulating layer 121, oxide semiconductor layer 122, oxide insulating layer 123, and gate insulating layer 15 For 0, the energy level at the bottom of the conduction band (Ec) and the energy level at the top of the valence band This indicates (Ev).

[0148] As shown in Figure 2(B), oxide insulating layer 121, oxide semiconductor layer 122, oxide insulating layer 1 At point 23, the energy level at the lower end of the conduction band changes continuously. This is due to the oxide insulating layer. 121, the oxide semiconductor layer 122, and the oxide insulating layer 123 share common elements. This can also be understood from the fact that oxygen diffuses easily between them. Therefore, the oxide insulating layer 121, Although the oxide semiconductor layer 122 and the oxide insulating layer 123 are laminates of films with different compositions, their physical properties It can also be said that it is continuous in a certain sense.

[0149] Oxide semiconductor films stacked with a common main component are not simply stacked layers but are connected in a continuous manner. (Here, in particular, a U-shaped well in which the energy levels at the lower end of the conduction band change continuously between each layer) It is constructed so that a door (U-shaped well) structure is formed. That is, each layer There are no impurities at the interface that would form defect levels such as trap centers or recombination centers. This forms a layered structure. If impurities are present between the layers of the stacked multilayer film, The continuity of the energy bands is lost, and carriers are destroyed at the interface by being trapped or recombined. It will be destroyed.

[0150] Note that the Ec values ​​for oxide insulating layer 121 and oxide insulating layer 123 are shown for the case where they are the same. However, they may be different.

[0151] As shown in Figure 2(B), the oxide semiconductor layer 122 becomes a well, and the transistor 10 It can be seen that the channel is formed in the oxide semiconductor layer 122. A U-shaped well structure in which the energy at the lower end of the conduction band changes continuously with layer 122 as the bottom. Nell can also be called an embedded channel.

[0152] Furthermore, the oxide insulating layer 121 and the oxide insulating layer 123 and an insulating film such as a silicon oxide film Near the interface, trap levels can be formed due to impurities and defects. Oxide insulating layer 1 The presence of 21 and the oxide insulating layer 123 allows the oxide semiconductor layer 122 and the trap The energy levels can be kept away from each other. However, the oxide insulating layer 121, or the oxide insulating layer 12 When the energy difference between Ec of 3 and Ec of oxide semiconductor layer 122 is small, the oxide semiconductor Electrons in layer 122 may exceed this energy difference and reach the trap level. When electrons that become electric charge are trapped in trap levels, a negative fixed charge is formed at the insulating film interface. As a result, the transistor's threshold voltage shifts in the positive direction. Furthermore, the transistor In long-term storage tests of the sta, there are concerns that the traps may not be fixed in place, leading to fluctuations in electrical properties. be.

[0153] Therefore, in order to reduce the fluctuation of the transistor threshold voltage, the oxide insulating layer 121, Furthermore, an energy difference is provided between the Ec of the oxide insulating layer 123 and the oxide semiconductor layer 122. This is necessary. The respective energy differences are preferably 0.1 eV or greater, and 0. A voltage of 2 eV or higher is more preferable.

[0154] Furthermore, the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 have crystalline portions. It is preferable that it be included. In particular, using crystals oriented along the c-axis makes it stable for transistors. It is possible to impart specific electrical characteristics.

[0155] Furthermore, in the band diagram shown in Figure 2(B), if the oxide insulating layer 123 is not provided, Between the semiconductor layer 122 and the gate insulating layer 150 is an In-Ga oxide (for example, with an atomic ratio of I You may also provide an In-Ga oxide (n:Ga=7:93), or gallium oxide, etc. It may also be provided. In-Ga oxide may be provided between the insulating layers 150, or gallium oxide may be provided. You can leave it.

[0156] The oxide semiconductor layer 122 is electron-parenter than the oxide insulating layer 121 and the oxide insulating layer 123. Use an oxide with high summing power. For example, as the oxide semiconductor layer 122, use the oxide insulating layer 12 1 and the oxide insulating layer 123 have an electron affinity of 0.07 eV to 1.3 eV, which is preferable. Or more preferably 0.1eV to 0.7eV, and more preferably 0.2eV to 0.4eV. Larger oxides can be used.

[0157] The transistor shown in this embodiment uses one or more metal elements to constitute the oxide semiconductor layer 122. Because it contains an oxide insulating layer 121 and an oxide insulating layer 123, The interface between layer 121 and oxide semiconductor layer 122, and the interface between oxide insulating layer 123 and oxide semiconductor layer It becomes difficult to form interface states at the interface with 122. Therefore, oxide insulating layer 121, oxide insulating By providing the border layer 123, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. This can reduce fluctuations.

[0158] Gate insulating layer 150 The gate insulating layer 150 contains oxygen (O), nitrogen (N), fluorine (F), and aluminum (Al ), magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge ), yttrium (Y), zirconium (Zr), lanthanum (La), neodymium (Nd) It may contain hafnium (Hf), tantalum (Ta), titanium (Ti), and the like. For example, aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide. (SiOx), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy) Silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx) ), yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (La Ox), neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide ( It may contain one or more types of TaOx. Furthermore, the gate insulating layer 150 is made of the above materials. It may also be the case that the gate insulating layer 150 contains lanthanum (La), nitrogen, and zirconium. It may contain impurities such as (Zr).

[0159] The gate insulating layer 150 preferably contains a large amount of oxygen. The oxygen is then subjected to heat treatment, which allows it to pass through the oxide insulating layer 123 to the oxide semiconductor layer 12 This reaches step 2. This reduces the oxygen vacancies (Vo) present in the oxide semiconductor layer 122. It can be made to happen.

[0160] Furthermore, an example of the laminated structure of the gate insulating layer 150 will be described. The gate insulating layer 150 is For example, it contains oxygen, nitrogen, silicon, hafnium, etc. Specifically, hafnium oxide. , and preferably containing silicon oxide or silicon oxide nitride.

[0161] Hafnium oxide has a higher dielectric constant compared to silicon oxide and silicon oxide nitride. Therefore Therefore, compared to the case where silicon oxide is used, the thickness of the gate insulating layer 150 can be increased. This reduces the leakage current due to tunnel current. In other words, a tunnel with a small off-current Rangista can be realized. Furthermore, hafnium oxide having a crystalline structure is amorphous. It has a higher dielectric constant compared to hafnium oxide, which has a crystalline structure. Therefore, the off-current To create small transistors, it is preferable to use hafnium oxide, which has a crystalline structure. It is so. Examples of crystal structures include monoclinic and cubic systems. However, this invention This is not limited to these aspects.

[0162] Incidentally, the surface of hafnium oxide having a crystalline structure has interface states due to defects. This may occur. The interface level may function as a trap center. Therefore, When hafnium oxide is placed in close proximity to the channel region of a transistor, the interface levels Therefore, the electrical characteristics of the transistor may deteriorate. To reduce the influence of the interface state, To achieve this, another film is placed between the transistor's channel region and the hafnium oxide. It is sometimes preferable to separate them from each other by doing so. This membrane has a buffering function. The film having a buffering function may be a film included in the gate insulating layer 150, or an oxide semiconductor. It may also be a film included in the conductive film. That is, the film having a buffering function may be silicon oxide. Silicon oxide nitride, oxide semiconductors, etc., can be used. The film contains, for example, a semiconductor with a larger energy gap than the semiconductor that forms the channel region. Alternatively, an insulator may be used. Or, a film having a buffering function may have, for example, a channel region. A semiconductor or insulator with lower electron affinity than the semiconductor is used. Alternatively, a semiconductor with a buffering function is used. For example, the film may have a semiconductor with a higher ionization energy than the semiconductor that forms the channel region. Use a conductor or an insulator.

[0163] On the other hand, the interface state (trap) on the surface of hafnium oxide having the above-described crystal structure By trapping charge at the center, the threshold voltage of the transistor can be controlled. There is a combination. In order to keep the charge stable, for example, the channel region and the hafny oxide If you place an insulator with a larger energy gap than hafnium oxide between the um and the other material... Alternatively, if a semiconductor or insulator with a lower electron affinity than hafnium oxide is placed in the environment, Good. Alternatively, for films with buffering properties, a higher ionization energy than hafnium oxide is used. A semiconductor or insulator can be placed. By using such an insulator, the interface state This makes it less likely for trapped charges to be released, and allows the charge to be retained for a long period of time. can.

[0164] Examples of such insulators include silicon oxide and silicon oxide-nitride. In order to trap charges in the interface levels within the insulating layer 150, charges must be released from the oxide semiconductor layer 122. To move electrons toward the electrode layer 160, a specific example is to use high temperature ( For example, under temperatures between 125°C and 450°C (typically between 150°C and 300°C), The potential of the source electrode layer 160 is kept higher than the potential of the source electrode and drain electrode for more than 1 second. Generally, you should maintain it for more than one minute.

[0165] In this way, a desired amount of electrons is trapped in the interface state such as the gate insulating layer 150. The threshold voltage shifts to the positive side. The voltage of the gate electrode layer 160, or the applied voltage... By adjusting the timing, the amount of electrons captured (the amount of variation in the threshold voltage) can be controlled. This is possible. Furthermore, if charge can be captured, within the gate insulating layer 150 It is not necessary. A laminated film with a similar structure may be used for other insulating layers.

[0166] 《Gate Entry Layer 160》 The gate electrode layer 160 may contain, for example, aluminum (Al), titanium (Ti), or chromium (C). r), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y), zirconium Nium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tantalum (T) a) It may have materials such as tungsten (W) or silicon (Si). Furthermore, the gate electrode layer 160 can be laminated. When laminated, for example, the above material It may also be used in combination with nitrogen-containing materials such as nitrides.

[0167] Side wall insulating layer 176 The sidewall insulating layer 176 can have the same material as the gate insulating layer 150.

[0168] Insulating layer 180 The insulating layer 180 can have the same material as the gate insulating layer 150.

[0169] Furthermore, the insulating layer 180 may be laminated. The insulating layer 180 has a composition greater than the stoichiometric composition. It is preferable that it contains oxygen. The oxygen released from the insulating layer 180 is released into the gate insulating layer 150. Because it can diffuse into the channel formation region of the oxide semiconductor layer 122 via this route, Oxygen can be supplied to the oxygen deficiency formed in the channel formation region. Therefore, The electrical characteristics of a transistor can be determined.

[0170] Conductive layer 190 The conductive layer 190 can be made of the same material as the gate electrode layer 160.

[0171] Conductive layer 195 The conductive layer 195 can be made of the same material as the gate electrode layer 160.

[0172] <Method for fabricating transistors> Next, the method for manufacturing the semiconductor device of this embodiment will be described with reference to Figures 5 to 15. Note that any parts that overlap with the parts described above in the transistor configuration will be omitted. Furthermore, the A1-A2 direction shown in Figures 5 to 15 is the channel shown in Figures 1(A) and 1(B). It is sometimes referred to as the longitudinal direction. Also, the A3-A4 direction shown in Figures 5 to 15 is the same as in Figure 1(A ) and the channel width direction shown in Figure 1(C) may also be referred to as the channel width direction.

[0173] In this embodiment, each layer constituting the transistor (insulating layer, oxide semiconductor layer, conductive layer These include sputtering and chemical vapor deposition (CVD). Eposition method, vacuum deposition method, pulsed laser deposition (PLD) It can be formed using the (ser Deposion) method, or by coating or printing. It can be formed by the following methods. Sputtering and plasma CVD are examples of film deposition methods. A typical example is thermal CVD. An example of thermal CVD is organometallic vapor deposition ( MOCVD:Metal Organic Chemical Vapor Depos Methods such as atomic layer deposition (ALD) Method n) may also be used. In addition, in the sputtering method, the long throw method and the collimation method By combining and using formulas, embedding capabilities can be improved.

[0174] <Thermal CVD method> Since the thermal CVD method is a film-forming method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0175] Also, in the thermal CVD method, a source gas and an oxidizing agent are simultaneously fed into the chamber, and the inside of the chamber is under atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate, thereby film formation may be performed.

[0176] Also, thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, semiconductor films, and inorganic insulating films described so far. For example, when forming an In-Ga-Zn-O film trimethylindium, trimethylgallium, and dimethylzinc can be used. The chemical formula of trimethylindium is In(CH3)3 . Also, the chemical formula of trimethylgallium is Ga(CH3)3. Also, dimethylzinc [[ID=CHEMICAL FORMULA]] is Zn(CH3)2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc .

[0177] <ALD method> In a film-forming apparatus using a conventional CVD method, one or more source gases (precursors) for the reaction are simultaneously supplied to the chamber during film formation. A film-forming apparatus using the ALD method introduces the precursors for the reaction into the chamber sequentially, and repeats the order of gas introduction to perform film formation. For example, by switching each switching valve (also called a high-speed valve) ​​ The system is then modified to supply two or more types of precursors to the chamber in sequence, and multiple types of precursors are mixed. To prevent this, an inert gas (such as argon or nitrogen) is applied after the first precursor. We will introduce a second precursor. Also, instead of introducing an inert gas, we will use vacuum evacuation. Therefore, after the first precursor is discharged, the second precursor can be introduced.

[0178] Figures 3(A), 3(B), 3(C), and 3(D) show the film deposition process of the ALD method. Precursor 601 is adsorbed onto the surface of the substrate (see Figure 3(A)), and the first single layer is formed. (See Figure 3(B)). In this case, metal atoms etc. contained in the precursor are present on the substrate surface. It can bond with hydroxyl groups. The metal atom has alkyl groups such as methyl and ethyl groups. They may be coupled. The second precursor is introduced after the first precursor 601 has been exhausted. It reacts with SA602 (see Figure 3(C)) and a second single layer is laminated on top of the first single layer. A film is formed (see Figure 3(D)). For example, an oxidizing agent is included as a second precursor. If present, the metal atom or alkyl bonded to the metal atom present in the first precursor A chemical reaction occurs between the base and the oxidizing agent, allowing for the formation of an oxide film.

[0179] The ALD method is a film deposition method based on surface chemical reactions, in which a precursor is adsorbed onto the surface to be deposited. Further formation occurs due to the action of a self-stopping mechanism. For example, trimethylaluminum The eel precursor reacts with the hydroxyl groups (OH groups) present on the surface of the film to be deposited. At this time, heat Because only surface reactions occur, the precursor comes into contact with the film surface and absorbs thermal energy. Metal atoms and the like in the precursor can be adsorbed onto the surface of the film to be deposited via this. Casa has a high vapor pressure, is thermally stable and does not self-decompose in the pre-deposition stage, and does not form on the substrate. It has characteristics such as rapid chemical adsorption. Also, since the precursor is introduced as a gas, If the precursors introduced to each other have enough time to diffuse, then high aspect Even in areas with uneven surface characteristics, a film can be formed with good coverage.

[0180] Furthermore, in the ALD method, the gas introduction sequence is controlled, and multiple passes are made until the desired thickness is achieved. By repeating the process, a thin film with excellent step coverage can be formed. The thickness of the thin film can be repeated. Because it can be adjusted by the number of times, precise film thickness adjustment is possible. Also, exhaust capacity By increasing the force, the film deposition rate can be increased, and the impurity concentration in the film can be further reduced. It is possible.

[0181] Furthermore, ALD methods include thermal ALD (thermal ALD) and plasma ALD ( There is the plasma ALD method. In the thermal ALD method, thermal energy is used to react the precursor. The plasma ALD method is a method that carries out the precursor reaction in a radical state. ru.

[0182] By using the ALD method for film deposition, extremely thin films can be deposited with high precision. By using this method to form a film, the surface coverage can be increased even on surfaces with uneven surfaces.

[0183] <Plasma ALD> Furthermore, by depositing films using the plasma ALD method, it is possible to achieve results that are superior to the thermal ALD method (thermal ALD method). This enables film deposition at even lower temperatures. For example, the plasma ALD method can be used even below 100°C. It is possible to deposit films without reducing the deposition rate. In addition, in the plasma ALD method, N2 is used Since it can be radicalized by Rasma, not only oxides but also nitrides can be formed into films. This is possible.

[0184] Also, in the plasma ALD method, the oxidizing power of the oxidant can be enhanced. As a result, when film formation is carried out by ALD, the precursors remaining in the film or the organic components desorbed from the precursors can be reduced, and also carbon, chlorine, hydrogen, etc. in the film can be reduced, and a film with a low impurity concentration can be obtained. This is possible.

[0185] Also, when performing plasma ALD, when generating radical species, plasma can be generated in a state separated from the substrate, such as ICP (Inductively Coupled Plasma), and plasma damage to the substrate or the film on which the protective film is formed can be suppressed. This is possible. This is possible.

[0186] From the above, by using the plasma ALD method, compared with other film formation methods, the process temperature can be lowered, and the surface coverage rate can be increased, and the film can be formed. This can suppress the intrusion of water and hydrogen from the outside. Therefore, the reliability of transistor characteristics can be improved. This is possible. This is possible.

[0187] <Explanation of the ALD apparatus> Fig. 4(A) shows an example of a film formation apparatus using the ALD method. The film formation apparatus using the ALD method includes a film formation chamber (chamber 1701), raw material supply parts 1711a, raw material supply parts 1711b, high-speed valves 1712a, high-speed valves 1712b which are flow controllers, raw material inlets 1713 a, raw material inlets 1, raw material outlets 1714, and an exhaust device 1715. The cha The raw material inlet 1713a and raw material inlet 1713b installed inside the bar 1701 are supply pipes and The raw material supply unit 1711a and raw material supply unit 1711b are connected via valves. The raw material discharge port 1714 is connected to the exhaust system 1715 via a discharge pipe, valve, and pressure regulator. It is being done.

[0188] Inside the chamber is a substrate holder 1716 equipped with a heater, and a cover is placed on the substrate holder. Place the substrate 1700 to be coated.

[0189] In the raw material supply units 1711a and 1711b, solids are processed by vaporizers, heating means, etc. A precursor is formed from raw materials or liquid raw materials. Alternatively, a raw material supply unit 1711a, raw material supply The supply unit 1711b may be configured to supply a gas precursor.

[0190] Furthermore, an example is shown in which two raw material supply units 1711a and 1711b are provided. There are no particular limitations, and three or more may be provided. Also, high-speed valve 1712a, high-speed valve 17 12b can be precisely controlled over time by supplying either a precursor or an inert gas. The configuration is such that it supplies fluid. High-speed valve 1712a and high-speed valve 1712b are precursors It is a flow controller, and can also be described as a flow controller for inert gases.

[0191] In the film deposition apparatus shown in Figure 4(A), the substrate 1700 is loaded onto the substrate holder 1716, and After sealing the bar 1701, the substrate 1700 is heated by the heater of the substrate holder 1716. Set the temperature to the desired temperature (e.g., 100°C or above, or 150°C or above), and supply the precursor. Exhaust by exhaust device 1715, supply of inert gas, and exhaust by exhaust device 1715 By repeating this process, a thin film is formed on the substrate surface.

[0192] In the film deposition apparatus shown in Figure 4(A), raw material is prepared in raw material supply section 1711a and raw material supply section 1711b. By appropriately selecting raw materials (such as volatile organometallic compounds), hafnium and aluminum can be produced. Oxides containing one or more elements selected from um, tantalum, zirconium, etc. (complex oxides) An insulating layer can be formed by including (including) hafny oxide. Specifically, An insulating layer composed of aluminum, an insulating layer composed of aluminum oxide, and a humic acid An insulating layer comprising a silicate, or comprising an aluminum silicate An insulating layer can be formed. Also, raw material supply unit 1711a, raw material supply unit 1711b By appropriately selecting the raw materials (such as volatile organometallic compounds) to be prepared, tungsten Thin films such as metal layers (e.g., titanium layers) and nitride layers (e.g., titanium nitride layers) can also be deposited. can.

[0193] For example, when forming a hafnium oxide layer using a film deposition apparatus that utilizes the ALD method, the solvent and a liquid containing hafnium precursor compounds (such as hafnium alkoxide or tetrakisdimethyl A precursor made by vaporizing hafnium amides (such as amide hafnium (TDMAH)), Two types of gases, ozone (O3), are used as oxidizing agents. In this case, raw material supply unit 1711a The first precursor supplied from is TDMAH, and supplied from the raw material supply unit 1711b The second precursor is ozone. The chemical formula for tetrakisdimethylamidehafnium is shown below. It is Hf[N(CH3)2]4. Other materials include tetrakis(ethylmethicone). Examples include hafnium (Luamide). Nitrogen also has the function of eliminating charge trapping levels. Therefore, the presence of nitrogen in the precursor results in a lower charge trapping level density for hafnium oxide. It is possible to form a thin film.

[0194] For example, when forming an aluminum oxide layer using a film deposition apparatus that utilizes the ALD method, A precursor is a vaporized liquid containing a medium and an aluminum precursor compound (such as TMA), and an acid Two types of gas, H2O, are used as nitrifying agents. In this case, the raw material is supplied from the raw material supply unit 1711a. The first precursor is TMA, and the second precursor supplied from the raw material supply unit 1711b The substance becomes H2O. The chemical formula for trimethylaluminum is Al(CH3)3. Other material liquids include tris(dimethylamide)aluminum and triisobutylaluminum. Luminium, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedi Examples include Honor.

[0195] For example, when forming a silicon oxide film using a film deposition apparatus that utilizes ALD, hexa Rolodisilane is adsorbed onto the film-forming surface, and chlorine contained in the adsorbed material is removed, causing an oxidizing gas (O2) A radical (nitrous oxide) is supplied and reacted with the adsorbed material.

[0196] For example, when depositing a tungsten film using a film deposition apparatus that utilizes ALD, WF6 gas The initial tungsten film is formed by sequentially introducing S and B2H6 gas, and then WF6 A tungsten film is formed by sequentially introducing gas and H2 gas. Note that B2H6 gas is also used. SiH4 gas may be used instead.

[0197] For example, oxide semiconductor films, such as In-Ga-Zn-O, can be deposited using an ALD (Advanced Laser Deposition) system. When forming a film, In(CH3)3 gas and O3 gas are introduced sequentially and repeatedly. An O layer is formed, and then Ga(CH3)3 gas and O3 gas are introduced sequentially and repeatedly to form GaO A layer is formed, and then Zn(CH3)2 gas and O3 gas are repeatedly introduced sequentially to form ZnO Layers are formed. Note that the order of these layers is not limited to this example. Also, these gases are mixed. This forms mixed compound layers such as In-Ga-O layers, In-Zn-O layers, and Ga-Zn-O layers. It is also acceptable to use an inert gas such as Ar instead of O3 gas to obtain pure water. While H2O gas can be used, it is preferable to use O3 gas, which does not contain H. In(C2H5)3 gas may be used instead of (CH3)3 gas. Also, Ga(CH 3) Ga(C2H5)3 gas may be used instead of 3 gas. Also, Zn(CH3)2 Instead of gas, Zn(C2H5)2 gas may be used.

[0198] Multi-chamber manufacturing equipment Furthermore, a multi-chamber manufacturing apparatus having at least one film deposition apparatus as shown in Figure 4(A) An example is shown in Figure 4(B).

[0199] The manufacturing apparatus shown in Figure 4(B) can continuously deposit laminated films without exposure to the atmosphere. This aims to prevent the inclusion of impurities and improve throughput.

[0200] The manufacturing apparatus shown in Figure 4(B) consists of a loading chamber 1702, a conveying chamber 1720, a pre-processing chamber 1703, It has at least a deposition chamber 1701 and an unloading chamber 1706. The chambers of the manufacturing equipment (including the loading chamber, processing chamber, transport chamber, film deposition chamber, unloading chamber, etc.) To prevent moisture from adhering, etc., an inert gas (such as nitrogen gas) with a controlled dew point is filled in. It is preferable to leave it as is, and preferably maintain reduced pressure.

[0201] Furthermore, chambers 1704 and 1705 use the same ALD method as chamber 1701. It may be a film deposition apparatus that utilizes the method, or it may be a film deposition apparatus that utilizes the plasma CVD method. Alternatively, a film deposition apparatus utilizing the sputtering method may be used, or a film deposition apparatus utilizing the MOCVD method may be used. It can also be used as a device.

[0202] For example, Chamber 1704 is a film deposition apparatus that utilizes the plasma CVD method, The following is an example of a film deposition apparatus using the MOCVD method, designated as -1705, for the deposition of a multilayer film. show.

[0203] Figure 4(B) shows an example where the top view of the transport chamber 1720 is hexagonal, but depending on the number of layers of the laminated film... Furthermore, it may be used as a manufacturing apparatus with even more polygons, connected to a larger number of chambers. Furthermore, although the top surface shape of the substrate is shown as a rectangle in Figure 4(B), it is not particularly limited. Figure 4(B) shows an example of a single-wafer type, but there is also a batch type where film is deposited on multiple substrates at once. It may also be used as a film deposition apparatus.

[0204] <Formation of insulating layer 110> First, an insulating layer 110 is deposited on the substrate 100. The insulating layer 110 is deposited using plasma CVD, thermal Formed by CVD (MOCVD, ALD) or sputtering, etc. It is preferable.

[0205] Furthermore, when forming the insulating layer 110, it is important that the material does not contain hydrogen, or that the hydrogen content is 1% or less. By using this material, the generation of oxygen vacancies in oxide semiconductors can be suppressed, This can stabilize the operation of the ZISTA.

[0206] For example, silicon oxide nitride with a thickness of 100 nm can be used as the insulating layer 110 by plasma CVD. A membrane can be used.

[0207] Next, a first heat treatment may be performed to remove water, hydrogen, etc., contained in the insulating layer 110. As a result, it is possible to reduce the concentration of water, hydrogen, etc. contained in the insulating layer 110. Heat treatment reduces the amount of water, hydrogen, etc., that diffuses into the first oxide insulating film that is formed later. It is possible.

[0208] <Formation of the first oxide insulating film and oxide semiconductor film> Next, a first oxide insulating film and an oxide semiconductor film, which will become the oxide insulating layer 121, are placed on the insulating layer 110. A first oxide insulating film and an oxide semiconductor film are formed to form body layer 122. The film can be formed by sputtering, MOCVD, PLD, etc. It is more preferable to form it using the sputtering method. As for the sputtering method, RF sputtering Puttering, DC sputtering, AC sputtering, etc. can be used. Furthermore, in sputtering methods, there are opposing target methods (opposing electrode methods, vapor phase sputtering). Ring method, VDSP (Vapor Depotion Sputtering) method By creating the film using this method, plasma damage during film deposition can be reduced. .

[0209] For example, when forming an oxide semiconductor film by sputtering, the sputtering apparatus Each chamber removes as much water and other impurities from the oxide semiconductor layer 122 as possible. To achieve this, a high vacuum (5 × 10) is created using an adsorption-type vacuum pump such as a cryopump. -7 Pa~1×10 -4 It is possible to do this up to approximately Pa, and the substrate to which the film is deposited can be heated to 100°C. In addition, it is preferable that the temperature be heated to 400°C or higher. Alternatively, a turbomolecular pump can be used. By combining this with a cold trap, air containing carbon components and moisture enters the chamber from the exhaust system. It is preferable to prevent backflow of the body. Also, turbomolecular pumps and cryopons An exhaust system combining multiple components may also be used.

[0210] Furthermore, to obtain a high-purity intrinsic oxide semiconductor layer, only high-vacuum evacuation of the chamber is required. Furthermore, it is desirable to increase the purity of the sputtering gas. The oxygen gas or argon gas present has a dew point of -40°C or lower, preferably -80°C or lower, more preferably Alternatively, by using gas purified to below -100°C, moisture and other substances can be removed from the oxide semiconductor film. This can prevent it from being absorbed as much as possible.

[0211] Sputtering gases include noble gases (typically argon), oxygen, and mixtures of noble gases and oxygen. Gas can be used as needed.

[0212] Furthermore, when forming an oxide semiconductor film, for example, using the sputtering method, the substrate temperature The temperature should be between 20°C and 750°C, preferably between 150°C and 450°C, and more preferably between 20°C and 750°C. By depositing an oxide semiconductor film at a temperature between 200°C and 420°C, a CAAC-OS film is formed. It is possible to form this.

[0213] For the first oxide insulating film, a material is selected that has a lower electron affinity than the oxide semiconductor film. It is desirable to choose this option.

[0214] Furthermore, in the first oxide insulating film and oxide semiconductor film, for example, by sputtering, When forming a film, a multi-chamber sputtering apparatus is used to create the first oxide insulating film. And the oxide semiconductor film can be continuously deposited without exposure to the atmosphere. In that case, the first This prevents unwanted impurities from entering the interface between the oxide insulating film and the oxide semiconductor film. This allows for a reduction in the interface state density. As a result, the electrical state of the transistor It can stabilize electrical characteristics, particularly in reliability testing.

[0215] Furthermore, if there is damage in the insulating layer 110, the oxide insulating layer 121 is present. The oxide semiconductor layer 122, which serves as the main conductive path, can be moved away from the damaged area, resulting in As such, it stabilizes the electrical characteristics of transistors, especially in reliability testing. It is possible.

[0216] For example, as the first oxide insulating film, by sputtering, the target is In: Using an oxide insulating film with a thickness of 20 nm, Ga:Zn=1:3:4 (atomic ratio) It is possible to also use the sputtering method to create an oxide semiconductor film as a target. A 15 nm thick oxide semiconductor film was deposited using In:Ga:Zn=1:1:1 (atomic ratio). Body membranes can be used.

[0217] Furthermore, by performing a second heat treatment after the formation of the first oxide insulating film and oxide semiconductor film, The amount of oxygen vacancies in the first oxide insulating film and oxide semiconductor film can be reduced.

[0218] The temperature for the second heat treatment is 250°C or higher and below the substrate strain point, preferably 300°C or higher and 650°C. It is preferable that the temperature be below ℃, and more preferably between 350℃ and 550℃.

[0219] Furthermore, the second heat treatment involves using rare gases such as helium, neon, argon, xenon, and krypton. It is preferable to carry out the procedure in an inert gas atmosphere containing nitrogen or a similar gas. After heating with gas, use an oxygen atmosphere or dry air (with a dew point of -80°C or lower, preferably -100°C). It may be heated in an atmosphere of air at or below ℃, preferably below -120℃. Alternatively, in a reduced pressure state. It should be done in this manner. In addition to the dry air mentioned above, inert gases and oxygen containing hydrogen, water, etc. It is preferable that there is no dew point, and typically the dew point is -80°C or lower, preferably -100°C or lower. It is preferable to do so. The processing time is preferably between 3 minutes and 24 hours.

[0220] Furthermore, in the heat treatment, instead of an electric furnace, heat conduction from a heat source such as a resistance heating element is used. A device that heats the object to be processed by thermal radiation may also be used. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. For this purpose, noble gases such as argon, or inert gases such as nitrogen, are used.

[0221] The second heat treatment is used to form the oxide insulating layer 121 and the oxide semiconductor layer 122, which will be described later. It can be done after etching.

[0222] For example, after heat treatment at 450°C for 1 hour under a nitrogen atmosphere, under an oxygen atmosphere In this case, a heat treatment can be performed at 450°C for 1 hour.

[0223] Through the above process, the oxygen vacancies in the first oxide insulating film and oxide semiconductor film are reduced, and hydrogen is also removed. Impurities such as water can be reduced. In addition, the localized energy level density of the first oxide is reduced. Insulating films and oxide semiconductor films can be formed.

[0224] Furthermore, by irradiating with high-density plasma using oxygen as the material, the same effect as heat treatment can be obtained. This is possible. The irradiation time is 1 minute or more and 3 hours or less, preferably 3 minutes or more and 2 hours or less, more preferably The duration should be between 5 minutes and 1 hour.

[0225] <Formation of the first conductive film> Next, a first conductive film to be used as a hard mask is formed on the oxide semiconductor film. The film is produced using sputtering, chemical vapor deposition (CVD) (organometallic chemical vapor deposition (MOC)). VD) method, metal chemical vapor deposition, atomic layer deposition (ALD) method, or plasma chemical vapor deposition This includes methods such as PECVD, vapor deposition, and pulsed laser deposition (PLD). It is possible.

[0226] The material for the first conductive film is copper (Cu), tungsten (W), molybdenum (Mo), and gold (A). u), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), Nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt ( Co), ruthenium (Ru), platinum (Pt), iridium (Ir), strontium (S) A single element or alloy of low-resistance materials such as r), or a compound mainly composed of these materials. It is preferable to have a single layer or a multilayer of conductive films containing the above.

[0227] For example, a tungsten film with a thickness of 20 to 100 nm is subjected to a first conductive process by sputtering. It can be formed as a membrane.

[0228] In this embodiment, a first conductive film is formed as a hard mask, but the embodiment is not limited to this. Alternatively, an insulating film may be formed.

[0229] <Formation of oxide insulating layer 121 and oxide semiconductor layer 122> Next, a resist mask is formed on the first conductive film by a lithography process. When forming the mask, the first conductive film is selectively etched using the resist mask. Then, a hard mask is formed. Subsequently, the resist on the hard mask is removed, and then the oxide is formed. The semiconductor film and the first oxide insulating film are selectively etched, and the oxide semiconductor layer 122 The oxide insulating layer 121 is formed in an island-like manner (see Figure 5). The etching method is as follows: Dry etching can be used.

[0230] For example, methane gas and argon gas are used as etching gases, and the resist mask and A hard mask is used to selectively etch the first oxide insulating film and the oxide semiconductor film. This allows for the formation of an oxide insulating layer 121 and an oxide semiconductor layer 122. After the formation of the material insulating layer 121 and the oxide semiconductor layer 122, the first conductive film is removed.

[0231] Furthermore, the oxide semiconductor film is etched using the first conductive film as a hard mask. Therefore, compared to the resist mask, the edge roughness of the oxide semiconductor layer after etching is reduced. It can be reduced.

[0232] <Formation of oxide insulating layer 123> Next, an oxide insulating layer 123 is formed on the oxide semiconductor layer 122 and the insulating layer 110 (see Figure 6). (Illuminate). The oxide insulating layer 123 is formed in the same manner as the oxide semiconductor film and the first oxide insulating film. This allows the oxide insulating layer 123 to have a lower electron affinity than the oxide semiconductor film. The material can be selected accordingly. Note that the oxide insulating layer 123 is a resist mask, The gate electrode layer 160 may be used as a mask during processing.

[0233] For example, as an oxide insulating layer 123, by sputtering, In:Ga:Zn=1: Using an oxide semiconductor film with a thickness of 5 nm deposited using a 3:2 (atomic ratio) target, It is possible.

[0234] <Formation of insulating film 150a> Next, an oxide insulating layer 123 is formed, and an insulating film 150a, which will become the gate insulating layer 150, is formed on top of it. The insulating film 150a contains, for example, aluminum oxide, magnesium oxide, silicon oxide, and acid Silicon nitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide Tantalum oxide and the like can be used. The insulating film 150a is made of the laminated material of the above materials. The insulating film 150a may be made by sputtering, CVD (plasma CVD), It can be formed using methods such as MOCVD, ALD, and MBE. The insulating film 150a can be formed using the same method as the insulating layer 110, as appropriate.

[0235] For example, silicon oxidiznitride is formed as insulating film 150a by plasma CVD to a thickness of 10 nm. It is possible.

[0236] <Formation of conductive film 160a> Next, a conductive film 160a, which will become the gate electrode layer 160, is formed on the insulating film 150a. (Figure 7) (See reference). Examples of conductive films 160a include aluminum (Al), titanium (Ti), and cyanoacrylate. Chromium (Cr), cobalt (Co), nickel (Ni), copper (Cu), yttrium (Y) Zirconium (Zr), molybdenum (Mo), ruthenium (Ru), silver (Ag), tan Use tal (Ta), tungsten (W), or alloy materials mainly composed of these. This can be done. Conductive film 160a can be produced by sputtering or CVD (plasma CVD, MOC). It can be formed by methods such as VD method, ALD method, MBE method, vapor deposition method, and plating method. Furthermore, a conductive film containing nitrogen may be used as the conductive film 160a, and the above conductive film and nitrogen A laminate of conductive films containing elements may also be used.

[0237] For example, as the conductive film 160a, titanium nitride is formed to a thickness of 10 nm by the ALD method, and A laminated structure can be used in which gusten is formed to a thickness of 150 nm by metal CVD. .

[0238] <Formation of gate electrode layer 160 and gate insulating layer 150> Next, a resist mask is formed on the conductive film 160a by a lithography process, and the resist Using a tomask, the conductive film 160a is selectively etched to form the gate electrode layer 160. Next, after removing the resist on the gate electrode layer 160, the gate electrode layer 160 is masked. It is used to selectively etch the insulating film 150a and form the gate insulating layer 150. (See Figure 8).

[0239] The method for forming the gate electrode layer 160 and the gate insulating layer 150 is not limited to the method described above. For example, the groove may be formed by first creating a groove and then filling it with an insulating film or a conductive film.

[0240] <Formation of low-resistance region 125> Next, using the gate electrode layer 160 as a mask, the oxide semiconductor layer 122 and the oxide insulating layer 123 The second and third regions are subjected to the addition treatment of ion 167 (see Figure 9). The materials used are hydrogen (H), fluorine (F), boron (B), phosphorus (P), and helium (He). Neon (Ne), Argon (Ar), Krypton (Kr), Xenon (Xe), Tung Stainless steel (W), aluminum (Al), molybdenum (Mo), indium (In), etc. It can be used. Methods of addition include ion doping, ion implantation, and plastic These include the Zuma immersion ion implantation method and the high-density plasma treatment method. Furthermore, in miniaturization, ion By using the ion implantation method, the addition of impurities other than the specified ions can be suppressed, It is preferable. Furthermore, ion doping and plasma immersion ion implantation methods can treat large areas. It is excellent in certain situations.

[0241] In the addition of ion 167, the ion acceleration voltage is adjusted according to the ion species and implantation depth. It is desirable to standardize the voltage. For example, between 1kV and 100kV, and between 3kV and 60kV. It is possible to do so. Also, the dose of ions is 1 × 10⁻⁶. 12 ions / cm 2 The above 1 x 1 0 17 ions / cm 2The following is preferably 1 × 10 13 ions / cm 2 The above 5 x 10 1 6 ions / cm 2 The following is preferable.

[0242] This ion doping treatment results in oxygen deficiency in the oxide semiconductor layer 122 and the oxide insulating layer 123. Damage is formed, and low-resistance regions 125 are formed in the second and third regions (see Figure 10). In the second region, the low-resistance region 125 may be formed over the entire area or in a part of it. Furthermore, a low-resistance region 125 does not necessarily have to be formed in the oxide insulating layer 123.

[0243] Furthermore, by performing a third heat treatment after the ion doping treatment, the heat generated during the ion doping treatment Damage to the film can be repaired. In addition, this heat treatment allows the ion-doped material to It can be diffused to the oxide insulating layer 121.

[0244] <Formation of side wall insulating layer 176> Next, a first insulating film, which will become the side wall insulating layer 176, is formed on the gate electrode layer 160. The first insulating film is subjected to etching by a dry etching method, A side wall insulating layer 176 having a region in contact with the side surface of the gate electrode layer 160 and the gate insulating layer 150. It forms (see Figure 11).

[0245] <Formation of low-resistance region 127> Next, a conductive film 168 is deposited (see Figure 12). The conductive film 168 is titanium (Ti) Molybdenum (Mo), Tungsten (W), Chromium (Cr), Vanadium (V), Nio Metals such as nb (Nb), tantalum (Ta), zirconium (Zr), and hafnium (Hf) In addition to the materials themselves, their nitrided films can also be used.

[0246] It is desirable to perform a fourth heat treatment after the conductive film 168 has been formed. Thus, the metal atoms can be diffused into the oxide semiconductor layer 122 and the oxide insulating layer 123. A low-resistance region 127 can be formed (see Figure 13). By doing so, the resistance of the oxide semiconductor layer 122 and the oxide insulating layer 123 surface (for example, The resistance can be reduced.

[0247] Furthermore, in the low-resistance region 127, the metal atom and the oxide semiconductor layer 122 and the oxide The insulating layer 123 may form an alloy.

[0248] After the low-resistance region 127 is formed, the conductive film 168 is removed. The removal method is wet etching. It can be a mixture of ammonia water and hydrogen peroxide water. The conductive film 168 can be removed using the combined solution.

[0249] The method is not limited to the above, and a low-resistance region 127 may also be formed. For example, ion 16 By adding 9, a low-resistance region 127 can be formed (see Figure 14). Ion 1 69 consists of titanium (Ti), molybdenum (Mo), tungsten (W), and chromium (C). r), vanadium (V), niobium (Nb), tantalum (Ta), zirconium (Zr), It is preferable to use hafnium (Hf) or similar materials.

[0250] Furthermore, by performing a fourth heat treatment after the ion doping treatment, the heat generated during the ion doping treatment Damage to the film can be repaired. In addition, this heat treatment allows the ion-doped material to It can be diffused to the oxide insulating layer 121.

[0251] As a result, the resistance in the second and third regions can be reduced, and the source region and A drain region can be formed. Note that the second region is different from the third region. Because it contains few added elements and alloys, it can effectively be considered within the LDD (Low-Density Deposition) region.

[0252] Next, a third insulating film, which will become the insulating layer 180, is formed. The method for forming the third insulating film is to form the insulating layer The same procedure as in 110 can be used. After forming the third insulating film, a planarization treatment is performed. This forms an insulating layer 180.

[0253] Next, etching is performed using a dry etching method to create an opening in the third insulating film. .

[0254] Next, a second conductive film, which will become the conductive layer 190, is formed in the opening, and then a planarization process is performed to ensure conductivity. Forms layer 190.

[0255] Next, a third conductive film, which will become a conductive layer 195, is formed on the conductive layer 190. By using photolithography, nanoimprinting, etc., a conductive layer Forms 195 (see Figure 15).

[0256] By using the above manufacturing method, a transistor 10 can be formed. By using this method, channel lengths of 100nm or less, 30nm or less, and even 20nm or less can be achieved. The following extremely small transistors can be fabricated.

[0257] <Variation 1 of transistor 10: Transistor 11> Regarding transistor 11, which has a different shape from transistor 10 shown in Figure 1, use Figure 16. explain.

[0258] Figures 16(A), 16(B), and 16(C) show the top view and cross-sectional view of transistor 11. Figure 16(A) is a top view of transistor 11, and Figure 16(B) is a top view of transistor 11. Figure 16(C) shows a cross-sectional view between B3 and B4, as indicated by the dashed line B1-B2.

[0259] The transistor 11 has an oxide insulating layer 123, a gate electrode layer 160, and a gate insulating layer 150. It differs from transistor 10 in that it is provided only in the overlapping portion.

[0260] By having the structure of transistor 11, the resistance of the low resistance region 125 and the low resistance region 127 It can be lowered further. This can improve the electrical characteristics of the transistor. ru.

[0261] <Variation 2 of transistor 10: transistor 12> Regarding transistor 12, which has a different shape from transistor 10 shown in Figure 1, use Figure 17. explain.

[0262] Figures 17(A), 17(B), and 17(C) show the top view and cross-sectional view of transistor 12. Figure 17(A) is a top view of transistor 11, and Figure 17(B) is a top view of transistor 11. Figure 17(C) shows a cross-sectional view between C1 and C2 (marked with a dashed line), and between C3 and C4.

[0263] Transistor 12 differs from transistor 10 in that it has a conductive layer 165.

[0264] 《Conductive layer 165》 The conductive layer 165 can be made of the same material as the gate electrode layer 160. 5 can be a single layer or a multi-layer structure.

[0265] The conductive layer 165 can have the same function as the gate electrode layer 160. The configuration may involve applying the same potential as the gate electrode layer 160, or it may involve applying a different potential. This configuration is also acceptable.

[0266] Furthermore, in the transistor 12 provided with the conductive layer 165, the insulating layer 110 is the gate insulating layer It can have a similar structure and function to the 150.

[0267] The structure of transistor 12 allows for the control of the transistor's electrical characteristics (e.g., threshold current). The pressure can be controlled.

[0268] <Variation 3 of transistor 10: transistor 13> Regarding transistor 13, which has a different shape from transistor 10 shown in Figure 1, use Figure 18. explain.

[0269] Figures 18(A), 18(B), and 18(C) show the top view and cross-sectional view of transistor 13. Figure 18(A) is a top view of transistor 13, and Figure 18(B) is a top view of transistor 13. Figure 18(C) shows a cross-sectional view between D1 and D2 (marked by a dashed line), and between D3 and D4.

[0270] The difference between transistor 13 and transistor 10 is that transistor 13 has an insulating layer 170 and an insulating layer 172. It is different.

[0271] Insulating layer 170 The insulating layer 170 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain nium (Hf), tantalum (Ta), titanium (Ti), etc. Aluminum (AlOx), magnesium oxide (MgOx), silicon oxide (SiOx), Silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), silicon nitride (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), yt oxide Zirconium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx), nexate oxide Odium (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaOx) It can have more than one species.

[0272] The insulating layer 170 preferably contains an aluminum oxide (AlOx) film. The nium film acts as a barrier, preventing the passage of both hydrogen, water, and other impurities, as well as oxygen. It can have an effect. Therefore, aluminum oxide film is used in the fabrication process of transistors. During and after fabrication, hydrogen, moisture, and other factors can cause variations in the electrical characteristics of transistors. Prevention of impurities from entering the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123. , the main component material is an oxide insulating layer 121 of oxygen, an oxide semiconductor layer 122, an oxide insulating layer 1 A protective film that prevents emission from 23 and prevents unnecessary emission of oxygen from the insulating layer 110. It is suitable for use as such.

[0273] Furthermore, it is preferable that the insulating layer 170 be a film that has oxygen supply capacity. During film formation, a mixed layer is formed at the interface with other oxide layers, and acid is applied to the mixed layer or other oxide layers. The element is replenished, and through subsequent heat treatment, oxygen diffuses into the oxide semiconductor layer, and the oxide semiconductor... It is possible to replenish oxygen vacancies in the conductive layer, thereby improving transistor characteristics (for example, This can improve threshold voltage, reliability, etc.

[0274] Furthermore, the insulating layer 170 may be a single layer or a multi-layered layer. Also, on the upper side of the insulating layer 170, Alternatively, it may have another insulating layer on the underside. For example, magnesium oxide, silicon oxide, Silicon oxide nitride, silicon nitride, silicon nitride, gallium oxide, germanium oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide And an insulating film containing one or more types of tantalum oxide can be used. The insulating layer 170 is chemical It is preferable to have more oxygen than the stoichiometric composition. The oxygen released from the insulating layer 170 is Channels in the oxide semiconductor layer 122 via the gate insulating layer 150 or insulating layer 110 Because it can diffuse into the formation region, oxygen deficiencies formed in the channel formation region can be absorbed. Oxygen can be supplied. Therefore, stable transistor electrical characteristics can be obtained. It is possible.

[0275] Insulating layer 172 The insulating layer 172 contains oxygen (O), nitrogen (N), fluorine (F), aluminum (Al), and Magnesium (Mg), silicon (Si), gallium (Ga), germanium (Ge), i Zirconium (Y), Zirconium (Zr), Lanthanum (La), Neodymium (Nd), HAF It can contain elements such as nium (Hf), tantalum (Ta), and titanium (Ti). For example... Aluminum oxide (AlOx), magnesium oxide (MgOx), silicon oxide (Si Silicon oxide (Ox), silicon oxide nitride (SiOxNy), silicon oxide nitride (SiNxOy), nitride Silicon (SiNx), gallium oxide (GaOx), germanium oxide (GeOx), acid Yttrium oxide (YOx), zirconium oxide (ZrOx), lanthanum oxide (LaOx) neodymium oxide (NdOx), hafnium oxide (HfOx), and tantalum oxide (TaO) An insulating film containing one or more of x) can be used. In addition, the insulating layer 172 is a laminate of the above materials. That's fine.

[0276] The insulating layer 172 preferably contains an aluminum oxide film. The aluminum oxide film is It has a barrier effect that prevents both hydrogen, water and other impurities, as well as oxygen, from passing through the membrane. Therefore, the aluminum oxide film is used during the transistor fabrication process and during production. After manufacturing, oxidation of impurities such as hydrogen and moisture, which can cause variations in the electrical characteristics of transistors. Prevention of contamination into the material insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123, and main component material The emission of oxygen from the oxide insulating layer 121, oxide semiconductor layer 122, and oxide insulating layer 123 It is used as a protective film that prevents leakage and prevents unnecessary release of oxygen from the insulating layer 110. It is suitable for this purpose.

[0277] Furthermore, the insulating layer 172 can also function as a protective film. This protects the gate insulating layer 150 from plasma damage. This helps to prevent the formation of electron traps near the channel.

[0278] <Method for fabricating transistor 13> Part of the method for fabricating transistor 13 will be explained using Figure 19. Note that transistor 1 For parts that are similar to the method for creating 0, refer to the explanation provided therein.

[0279] <Formation of insulating layer 172> An insulating layer 172 is formed on the oxide insulating layer 123, the side wall insulating layer 176, and the gate electrode layer 160. The insulating layer 172 is formed by metal-organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD:A It is preferable to use films deposited using the tomic layer deposition method. This makes it possible to suppress damage to the gate insulating layer 150, and also to the gate electrode layer It can suppress oxidation.

[0280] Furthermore, the thickness of the insulating layer 172 is 1 nm to 30 nm, preferably 3 nm to 10 nm. The following applies:

[0281] Furthermore, after forming the insulating layer 172, ion is applied to the oxide semiconductor layer 122 and the oxide insulating layer 123. A treatment to add a certain substance may be performed. This will form a low-resistance region 125 and a low-resistance region 127. Furthermore, damage to the oxide semiconductor layer 122 during ion doping can be reduced.

[0282] Furthermore, the insulating layer 172 can be subjected to lithography, nanoimprinting, and dry etching after film formation. It may be prepared by processing using methods such as the ching method, or it may simply be prepared by forming a film.

[0283] <Formation of insulating layer 170> Next, an insulating layer 170 is formed on the insulating layer 172. The insulating layer 170 may be a single layer, It may be laminated. The insulating layer 170 is formed using the same materials and methods as the insulating layer 110. It is possible.

[0284] Furthermore, the insulating layer 170 is an aluminum oxide film formed by sputtering. This is preferable. When forming an aluminum oxide film by sputtering, the following is used during film formation. It is desirable to have oxygen gas as the gas. Furthermore, the oxygen gas should be present in a concentration of 1% by volume or more (100% or more). The volume is less than or equal to %; preferably 4% to 100% by volume; more preferably 10% or more by volume. It is desirable to have 100% by volume or less of oxygen. By having 1% by volume or more of oxygen, the insulating layer It can supply excess oxygen to the insulating layer in the middle or in contact with it. Oxygen can be added to the layer.

[0285] For example, using aluminum oxide as the target for the insulating layer 170, sputtering Sometimes, oxygen gas is used as the gas during film formation, and the film thickness is 20 nm. It can be reduced to 40 nm.

[0286] Next, it is preferable to perform a heat treatment. Typically, this heat treatment is performed at a temperature of 150°C or higher on the substrate. Below the strain point, preferably 250°C to 500°C, more preferably 300°C to 450°C The temperature can be set to below °C. This heat treatment adds to the insulating layer (e.g., insulating layer 110). The oxygen 173 diffuses and moves to the oxide semiconductor layer 122, and in the oxide semiconductor layer 122 It can replenish oxygen in the presence of oxygen deficiency (see Figure 19).

[0287] For example, a heat treatment can be performed at 400°C for 1 hour under an oxygen atmosphere.

[0288] Furthermore, this heat treatment may be performed at any time during other processes. This allows for the repair of defects present in the film and reduces the interface state density. Cut.

[0289] <Oxygen addition> Furthermore, the oxygen addition process may be performed not only via the insulating layer 170. The additive treatment may be performed on the insulating layer 110, or on the first oxide insulating film, oxide insulating layer 1 This may be done on 23, or on other insulating layers. As the oxygen to be added, Use one or more of the following: radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, etc. Methods for adding oxygen include ion doping, ion implantation, and plasma immersion. Methods such as on-injection are available.

[0290] Furthermore, when using ion implantation as a method for adding oxygen, even if oxygen atomic ions are used... Yes, or you may use oxygen molecular ions. When oxygen molecular ions are used, the added film will Damage can be reduced. Oxygen molecular ions are added to the film surface to which the oxygen is added. It is separated and added as oxygen atom ions. Because energy is used, when oxygen molecular ions are added to the membrane to which the oxygen is added The energy per oxygen atom ion in is the energy of the oxygen atom ion when the oxygen is added. It is lower compared to when added to the membrane. Therefore, it reduces membrane damage when oxygen is added. Cut.

[0291] Furthermore, by using oxygen molecular ions, the oxygen atoms injected into the membrane to which the oxygen is added can be... Because the energy of each ON is reduced, the oxygen atom ion is implanted at a shallower position. Therefore, in subsequent heat treatment, oxygen atoms become more easily migrated, and in the oxide semiconductor film, It can supply more oxygen.

[0292] Furthermore, when implanting oxygen molecular ions, compared to when implanting oxygen atomic ions, the acid The energy per elementary atom ion is low. Therefore, it is implanted using oxygen molecular ions. and, it is possible to increase the acceleration voltage and increase the throughput. Also by injecting using oxygen molecular ions, compared with the case of using oxygen atomic ions, it is possible to halve the dose amount. As a result, the throughput can be increased .

[0293] When adding oxygen to the film to which the oxygen is added, using conditions such that the peak of the concentration profile of oxygen atomic ions is located in the film to which the oxygen is added, it is preferable to add oxygen to the film to which the oxygen is added. As a result, compared with the case of injecting oxygen atomic ions, [[ID=IS]]the acceleration voltage at the time of injection can be lowered, and damage to the film to which the oxygen is added can be reduced and it is possible to reduce the amount of defects in the film to which the oxygen is added, and suppress fluctuations in the electrical characteristics of the transistor. Furthermore, the amount of oxygen atoms added at the interface between the insulating layer 110 and the oxide insulating layer 121 is 1×10 21 atoms / cm 3 less than, or 1×10 20 atoms / cm 3 less than, or 1×10 19 atoms / cm 20 3 less than, or 1×10 19 atoms / cm 3 less than, by adding oxygen to the film to which the oxygen is added, the amount of oxygen added to the insulating layer 110 can be reduced. As a result, damage to the film to which the oxygen is added can be reduced 3

[0294] and fluctuations in the electrical characteristics of the transistor can be suppressed.

[0294] Also, by subjecting the film to which the oxygen is added to plasma treatment (plasma immersion ion implantation method) in plasma generated in an atmosphere containing oxygen, oxygen is added to the film to which the oxygen is added This is also acceptable. As an oxygen-containing atmosphere, oxygen, ozone, nitrous oxide, nitrogen dioxide, and other acids are also acceptable. There is an atmosphere containing chemical gases. This occurs when a bias is applied to the substrate 100 side. By exposing the film to which the oxygen is added to the plasma, the oxygen is added to the film. It is possible and preferable to increase the amount added. Examples of apparatus for such plasma processing are And there are abrasion control devices, etc.

[0295] For example, if the acceleration voltage is 60kV and the dose is 2 × 10⁻¹⁰ 16 / cm 2 The oxygen molecular ions It can be added to the insulating layer 110 by ion implantation.

[0296] The above process can be applied to transistor 10 and other transistors.

[0297] As a result, the localized energy level density of the oxide semiconductor film is reduced, and a transistor with excellent electrical properties is obtained. It is possible to fabricate a zista. Furthermore, it is possible to observe the changes in electrical properties due to aging and stress testing. It is possible to manufacture a small number of highly reliable transistors.

[0298] This embodiment can be appropriately combined with other embodiments shown herein. .

[0299] (Embodiment 2) <Oxide semiconductor structure> The structure of oxide semiconductors will be described below.

[0300] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (c-axis-aligned (crystalline oxide semiconductor), polycrystalline oxide Semiconductors, nc-OS (nanocrystalline oxide semiconductor) uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l Examples include oxide semiconductors and amorphous oxide semiconductors. ru.

[0301] From another perspective, oxide semiconductors include amorphous oxide semiconductors and other crystalline oxide semiconductors. It can be divided into conductors and crystalline oxide semiconductors. As for crystalline oxide semiconductors, there are single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductors, and nc-OS.

[0302] Amorphous structures are generally isotropic and lack heterogeneous structures, representing a metastable state of atomic arrangement. It is not fixed, the bonding angle is flexible, and it has short-range order but not long-range order. It is said that...

[0303] In other words, a stable oxide semiconductor is completely amorphous. ) It cannot be called an oxide semiconductor. Also, it is not isotropic (for example, periodic structure in a minute region). Oxide semiconductors (which have a structure) cannot be called perfectly amorphous oxide semiconductors. On the other hand, a-li ke OS is an unstable structure that is not isotropic but contains voids (also called porous structures). In terms of instability, a-like OSs are physically similar to amorphous oxide semiconductors. .

[0304] <caac-os> First, let me explain CAAC-OS.

[0305] CAAC-OS is an oxide semiconductor having multiple c-axis oriented crystalline portions (also called pellets). It is a type of conductor.

[0306] CAAC-OS can be analyzed by X-ray diffraction (XRD). Let's explain the case of analysis. For example, InGaZnO4, which is classified as space group R-3m Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in Figure 20(A), a peak appears near 31° at the diffraction angle (2θ). Since the 'k' is attributed to the (009) plane of the InGaZnO4 crystal, CAAC-OS The crystal has c-axis orientation, and the c-axis is the surface that forms the CAAC-OS film (also called the surface to be formed). It can be confirmed that it is facing in a direction approximately perpendicular to the top surface. Note that 2θ is 31° In addition to the nearby peak, a peak may also appear when 2θ is near 36°. The adjacent peak is due to a crystal structure classified as space group Fd-3m. Therefore, CAAC -OS preferably does not show the peak.

[0307] On the other hand, in CAAC-OS, X-rays are incident from a direction parallel to the surface being formed. Structural analysis using the ne method reveals a peak near 2θ = 56°. This peak corresponds to I It is attributed to the (110) plane of the nGaZnO4 crystal. Then, 2θ is fixed near 56°. The analysis (φ-scan) is performed while rotating the sample around the normal vector of the sample surface as the axis (φ-axis). Even when this is done, no clear peak appears, as shown in Figure 20(B). On the other hand, single crystal InGaZ When φ scanning is performed on nO4 with 2θ fixed near 56°, the result is shown in Figure 20(C). Six peaks are observed that belong to a crystal plane equivalent to the (110) plane. Therefore, X Structural analysis using RD revealed that CAAC-OS has irregular orientations in its a-axis and b-axis. This can be confirmed.

[0308] Next, we will explain CAAC-OS analyzed by electron diffraction. For example, InGaZ For CAAC-OS having nO4 crystals, a probe is applied parallel to the surface of the CAAC-OS being formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern like the one shown in Figure 20(D) (control) is observed. This is also called a limited-field electron diffraction pattern. A diffraction pattern may appear. This diffraction pattern includes In The spot contains a location originating from the (009) plane of the GaZnO4 crystal. Therefore, the electron rotation Depending on the circumstances, the pellets contained in CAAC-OS may have c-axis orientation, and the c-axis may be the surface to be formed. Alternatively, it can be seen that it is oriented in a direction approximately perpendicular to the upper surface. On the other hand, for the same sample, on the sample surface Figure 20(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly. As shown in Figure 20(E), a ring-shaped diffraction pattern can be observed. Therefore, the probe Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of peridotites in CAAC-OS. It can be seen that the a-axis and b-axis of the net do not have orientation. Note that in Figure 20(E) The ring is caused by the (010) and (100) planes of the InGaZnO4 crystal, among other things. It is thought that the second ring in Figure 20(E) is caused by the (110) plane, etc. It's possible.

[0309] Furthermore, a transmission electron microscope (TEM) A composite image of the bright-field image and diffraction pattern of CAAC-OS obtained by (croscope) analysis. When observing a high-resolution TEM image (also known as a TEM image), multiple pellets can be identified. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries, are not visible. Also called "Nandaly." ) There are cases where it is not possible to clearly confirm this. Therefore, CAAC -OS can be said to be less prone to the decrease in electron mobility caused by grain boundaries.

[0310] Figure 21(A) shows a high-resolution T of the cross-section of CAAC-OS observed from a direction approximately parallel to the sample surface. The EM image is shown. For observing high-resolution TEM images, spherical aberration correction is required. The aberration correction function was used. High-resolution analysis was performed using the spherical aberration correction function. High-resolution TEM images are specifically called Cs-corrected high-resolution TEM images. For example, using an atomic resolution analytical electron microscope such as the JEM-ARM200F manufactured by JEOL Ltd. This can be observed.

[0311] From Figure 21(A), we can see the pellet, which is a region in which metal atoms are arranged in layers. Yes, it is possible. It has been found that the size of a single pellet can be 1 nm or larger, or even 3 nm or larger. Therefore, pellets are called nanocrystals (nc). It is also possible to use CAAC-OS with CANC(C-Axis Aligned nan It can also be called an oxide semiconductor containing ocrystals. The pellet is CAAC -Reflects the unevenness of the surface or top surface of the OS, and the surface or top surface of the CAAC-OS It becomes parallel to the plane.

[0312] Furthermore, Figures 21(B) and 21(C) show CAAC observed from a direction approximately perpendicular to the sample surface. -Shows a Cs-corrected high-resolution TEM image of the OS plane. Figures 21(D) and 21(E) are shown. These are images obtained by image processing Figure 21(B) and Figure 21(C), respectively. The following describes the image processing. Let's explain the method. First, Figure 21(B) is converted to the Fast Fourier Transform (FFT). The FFT image is obtained by performing a Fourier Transform (FFT) process. Next, the acquisition In the resulting FFT image, with the origin as the reference point, 2.8 nm -1 from 5.0nm -1 Leave the range between Next, the masked FFT image is subjected to the inverse Fast Fourier Transform (IFFT: By processing the image (Inverse Fast Fourier Transform), The processed image is obtained. The image obtained in this way is called an FFT filtered image. The filtered image is an image obtained by extracting the periodic component from the Cs-corrected high-resolution TEM image, and is a grid image. This shows the array.

[0313] In Figure 21(D), areas where the grid arrangement is disordered are indicated by dashed lines. The area enclosed by the dashed lines is It is a single pellet. The dotted line indicates the connection point between the pellets. The dashed line indicates a hexagonal shape, showing that the pellet is hexagonal. The shape of the net is not always a regular hexagon; it is often a non-regular hexagon.

[0314] In Figure 21(E), a dotted line is drawn between one region with a aligned grid arrangement and another region with a aligned grid arrangement. As shown, even near the dotted line, a clear grain boundary cannot be confirmed. By connecting surrounding lattice points around a central lattice point, a distorted hexagon can be formed. That is, lattice arrangement It can be seen that the formation of grain boundaries is suppressed by distorting the material. This is CAAC -OS is characterized by a non-dense atomic arrangement in the ab-plane direction and the substitution of metallic elements. This is thought to be because the change in the bond distance between atoms allows for some degree of strain to be tolerated. It can be obtained.

[0315] As described above, CAAC-OS has c-axis orientation and multiple properties in the ab-plane direction. A number of pellets (nanocrystals) are linked together, forming a distorted crystalline structure. Therefore, CA AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an anchored crystal. ru.

[0316] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors depends on the presence of impurities. CAAC-OS may decrease due to impurities and defects ( It can be described as an oxide semiconductor with few oxygen vacancies, etc.

[0317] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metals. There are elements, for example. For instance, oxygen is more abundant than the metallic elements that make up oxide semiconductors such as silicon. Elements with strong bonding forces can alter the atomic arrangement of oxide semiconductors by removing oxygen from them. It disrupts the crystallinity and causes a decrease in its properties. Also, heavy metals such as iron and nickel, argon, and nickel... Because carbon oxides and other elements have a large atomic radius (or molecular radius), they affect the atomic arrangement of oxide semiconductors. This disrupts the crystallinity and reduces its properties.

[0318] When oxide semiconductors contain impurities or defects, their properties may change due to light, heat, etc. This is the case. For example, impurities contained in an oxide semiconductor may become carrier traps or carrier generation sources. For example, oxygen deficiencies in an oxide semiconductor may become carrier traps or carrier generation sources by capturing hydrogen. This is the case. For example, oxygen deficiencies in an oxide semiconductor may become carrier traps or carrier generation sources by capturing hydrogen.

[0319] CAAC-OS with few impurities and oxygen deficiencies is an oxide semiconductor with a low carrier density. Specifically, it is less than 8×10 11 / cm 3 Preferably, it is less than 1×10 11 / cm 3 More preferably, it is less than 1×10 / cm 10 / cm 3 and less than 1×10 -9 / cm 3 Carrier density of more than The oxide semiconductor can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics. The oxide semiconductor can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics. The oxide semiconductor can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

[0320] <nc-os> Next, I will explain nc-OS.

[0321] This section describes the case of analyzing nc-OS using XRD. For example, for nc-OS When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. In other words, nc-OS crystals do not have orientation.

[0322] Furthermore, for example, nc-OS having an InGaZnO4 crystal is thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, Figure 22 A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. Furthermore, the diffraction pattern when an electron beam with a probe diameter of 1 nm is incident on the same sample (na The beam electron diffraction pattern is shown in Figure 22(B). From Figure 22(B), a ring-shaped region is visible. Multiple spots are observed within. Therefore, nc-OS has a probe diameter of 50 nm. Order is not confirmed by irradiating with an electron beam, but when an electron beam with a probe diameter of 1 nm is irradiated... Order can be confirmed by having them shoot.

[0323] Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm, As shown in Figure 22(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. This may occur. Therefore, in the range of thickness less than 10 nm, nc-OS is ordered. It can be seen that there is a region with high fissure, i.e., a crystal. Furthermore, the crystals are oriented in various directions. Therefore, there are also regions where a regular electron diffraction pattern is not observed.

[0324] Figure 22(D) shows the Cs-corrected elevation of the cross-section of nc-OS observed from a direction approximately parallel to the surface being formed. High-resolution TEM images are shown. nc-OS refers to areas indicated by auxiliary lines in the high-resolution TEM image. As shown, there are regions where the crystalline structure can be observed and regions where the crystalline structure cannot be clearly observed. It has a region and a crystal portion contained in nc-OS, with a size of 1 nm to 10 nm. Yes, and they are often between 1 nm and 3 nm in size. Oxide semiconductors with a wavelength greater than 0 nm and less than or equal to 100 nm are called microcrystalline oxide semiconductors (micro It is sometimes called a crystalline oxide semiconductor. nc-OS may, for example, make it difficult to clearly identify grain boundaries in high-resolution TEM images. Yes. Furthermore, the nanocrystals may share the same origin as the pellets in CAAC-OS. Yes, it exists. Therefore, in the following, the crystalline portion of nc-OS may be referred to as a pellet.

[0325] Thus, nc-OS is suitable for minute regions (for example, regions between 1 nm and 10 nm, particularly The atomic arrangement has periodicity in the region between 1 nm and 3 nm. Furthermore, nc-OS is Furthermore, no regularity is observed in the crystal orientation between different pellets. Therefore, orientation is not observed throughout the entire film. Therefore, nc-OS can be analyzed using methods that produce a-like OS or amorphous OS. It can sometimes be indistinguishable from oxide semiconductors.

[0326] Furthermore, since there is no regularity in the crystal orientation between pellets (nanocrystals), nc-OS is used. Oxides containing RANC (Random Aligned nanocrystals) semiconductors, or containing NANC (Non-Aligned nanocrystals) It can also be called an oxide semiconductor.

[0327] nc-OS is an oxide semiconductor with higher orderliness than amorphous oxide semiconductors. Therefore, nc-OS has a lower defect level density than a-like OS and amorphous oxide semiconductors. However, nc-OS does not show any regularity in crystal orientation between different pellets. nc-OS has a higher defect level density compared to CAAC-OS.

[0328] <a-like OS> a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. It is a conductor.

[0329] Figure 23 shows a high-resolution cross-sectional TEM image of an a-like OS. Here, Figure 23(A) is This is a high-resolution cross-sectional TEM image of a-like OS at the start of electron irradiation. Figure 23(B ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation These are high-resolution cross-sectional TEM images. From Figures 23(A) and 23(B), a-like OS It can be seen that, from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. The bright regions show a change in shape after electron irradiation. Furthermore, the bright regions are either porous or low-density. It is presumed to be in the degree range.

[0330] Because it has porosity, a-like OS has an unstable structure. Below, a-like To demonstrate that the OS has a less stable structure compared to CAAC-OS and nc-OS. This shows the structural changes caused by electron irradiation.

[0331] As samples, prepare a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0332] First, high-resolution cross-sectional TEM images are obtained for each sample. All of them have a crystalline portion.

[0333] Furthermore, the unit cell of the InGaZnO4 crystal has three In-O layers, and Ga-Zn- It is known to have a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the spacing between the grid planes of the (009) plane (also called the d value). It is approximately [value], and from crystal structure analysis, its value has been determined to be 0.29 nm. Therefore, Below, areas where the spacing of the grid stripes is between 0.28 nm and 0.30 nm are represented as InGaZn. This was considered to be the crystalline portion of O4. Note that the lattice fringes correspond to the ab-plane of the InGaZnO4 crystal. ru.

[0334] Figure 24 shows an example of investigating the average size of the crystalline regions (22 to 30 locations) in each sample. The length of the lattice fringes mentioned above is used to define the size of the crystal portion. From Figure 24, a-like The crystalline portion of the OS grows larger in proportion to the cumulative amount of electrons irradiated during TEM image acquisition, etc. It can be seen that, as shown in Figure 24, the size is about 1.2 nm in the initial stages of TEM observation. The crystal region (also called the initial nucleus) is then transformed into an electron (e - The cumulative radiation dose was 4.2 × 10⁻⁶ 8 e - / nm 2 In this case, it can be seen that it has grown to a size of about 1.9 nm. On the other hand, nc -OS and CAAC-OS are defined as the cumulative electron dose from the start of electron irradiation being 4.2 × 10⁻⁶. 8 e - / nm 2 Within this range, it can be seen that there is no change in the size of the crystal portion. (Figure 24) Furthermore, regardless of the cumulative electron irradiation dose, the size of the crystal region in nc-OS and CAAC-OS is, It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. TEM observations were performed using a Hitachi transmission electron microscope H-9000NAR. Electron beam irradiation conditions The acceleration voltage is 300kV and the current density is 6.7 × 10⁻⁶. 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0335] Thus, in a-like OS, crystalline growth can sometimes be observed upon electron irradiation. On the other hand, nc-OS and CAAC-OS show almost no crystal growth due to electron irradiation. It cannot be seen. In other words, a-like OS is different from nc-OS and CAAC-OS. It is clear that the structure is unstable.

[0336] Furthermore, because it has porosity, a-like OS is superior to nc-OS and CAAC-OS. It has a low-density structure. Specifically, the density of a-like OS is the same as that of a single crystal of the same composition. The density is between 78.6% and 92.3%. Also, the density of nc-OS and CAAC - The density of OS is between 92.3% and 100% of the density of a single crystal of the same composition. Oxide semiconductors with a density of less than 78% are inherently difficult to deposit.

[0337] For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of single-crystal InGaZnO4 with a faceted crystal structure is 6.357 g / cm³. 3 That's right. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio] The density of a-like OS is 5.0 g / cm³. 3 More than 5.9g / cm 3 It is less than. For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], The density of nc-OS and CAAC-OS is 5.9 g / cm³. 3 More than 6.3g / cm 3 It is less than.

[0338] If single crystals with the same composition do not exist, single crystals with different compositions can be combined in any proportion. By doing so, the density equivalent to a single crystal at the desired composition can be estimated. The density corresponding to a single crystal of the desired composition is, with respect to the ratio of single crystals with different compositions combined, The density can be estimated using a weighted average. However, the density should be calculated using as few types of single crystals as possible. It is preferable to estimate by combining the costs.

[0339] As described above, oxide semiconductors can take on various structures, each possessing a variety of properties. Oxide semiconductors include, for example, amorphous oxide semiconductors, a-like OS, nc-OS, The multilayer film may have two or more types of CAAC-OS.

[0340] (Embodiment 3) In this embodiment, an example of a circuit utilizing a transistor according to one aspect of the present invention is shown in the drawings. Refer to the explanation.

[0341] <Cross-sectional structure> Figure 25(A) shows a cross-sectional view of a semiconductor device according to one embodiment of the present invention. In Figure 25(A), X The 1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. Figure 25(A) The semiconductor device shown has a transistor 2200 made of a first semiconductor material at the bottom, and above The part has a transistor 2100 using a second semiconductor material. In Figure 25(A), As a transistor 2100 using a second semiconductor material, the transistor exemplified in the previous embodiment is An example of applying a transistor is shown. Note that the part to the left of the dashed line is the transistor channel. The image shows a cross-section in the longitudinal direction, with the right side representing a cross-section in the channel width direction.

[0342] It is preferable that the first semiconductor material and the second semiconductor material have different band gaps. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (silicon (including strained silicon)). Germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum arsenide (e.g., gallium phosphate, indium phosphide, gallium nitride, organic semiconductors), and the second semiconductor The main material can be an oxide semiconductor. Other materials besides oxide semiconductors include single-crystal silicon Transistors using materials such as semiconductors are easy to operate at high speeds. On the other hand, transistors using oxide semiconductors By applying the transistor exemplified in the previous embodiment, the S value (sub The threshold value can be reduced, making it possible to create a miniaturized transistor. Furthermore, its fast switching speed enables high-speed operation, and its low off-current reduces leakage current. The flow is small.

[0343] Transistor 2200 is an n-channel type transistor or a p-channel type transistor. Either type of transistor is acceptable, and the appropriate transistor should be used depending on the circuit. Aside from using a transistor according to one embodiment of the present invention that uses a synthetic semiconductor, the materials and structure used are as follows: However, it is not necessary to limit the specific configuration of the semiconductor device shown here to what is presented.

[0344] In the configuration shown in Figure 25(A), an insulator 2201 and an insulator are placed on top of the transistor 2200. Transistor 2100 is provided via 2207. Also, transistor 2200 Multiple wires 2202 are provided between the transistor 2100 and the transistor. Multiple plugs 2203 embedded in the rim allow wiring to be provided in the upper and lower layers, respectively. The electrodes are electrically connected. Also, the insulator 2204 covering the transistor 2100 and Wiring 2205 and a sintered material are provided on the insulator 2204.

[0345] In this way, by stacking two types of transistors, the circuit footprint is reduced. Multiple circuits can be arranged at a higher density.

[0346] In this case, if a silicon-based semiconductor material is used for the transistor 2200 located in the lower layer, Hydrogen in the insulator placed near the semiconductor film of transistor 2200 is in the silicon dung. This terminates the ring bond and improves the reliability of transistor 2200. On the other hand, When an oxide semiconductor is used for the transistor 2100 located in the upper layer, transistor 21 Hydrogen in the insulator placed near the semiconductor film generates carriers in the oxide semiconductor. This can be one of the contributing factors, and therefore can reduce the reliability of transistor 2100. Therefore, an oxide layer is found on the upper layer of the transistor 2200 using silicon-based semiconductor material. When stacking transistors 2100 made of solid semiconductor material, hydrogen diffusion occurs between them. It is particularly effective to provide an insulator 2207 that has the function of preventing this. As a result of step 7, the reliability of transistor 2200 is improved by trapping hydrogen in the lower layer. In addition, the diffusion of hydrogen from the lower layer to the upper layer is suppressed, which affects transistor 2100. Reliability can also be improved at the same time.

[0347] Examples of insulators 2207 include aluminum oxide, aluminum oxide nitride, and gallium oxide. M, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, acid Hafnium nitride, yttria-stabilized zirconia (YSZ), etc., can be used.

[0348] Furthermore, the transistor 2100, which is composed of an oxide semiconductor film, is covered by the transistor It is preferable to form a blocking film on the sta 2100 that has the function of preventing hydrogen diffusion. i. The block film can be made of the same material as the insulator 2207, and is particularly acidic. It is preferable to apply aluminum oxide. The aluminum oxide film is resistant to hydrogen, moisture, and other impurities. It has a high blocking effect, preventing the permeation of both pure substances and oxygen. Therefore, an aluminum oxide film is used as the block film covering the transistor 2100. This prevents the desorption of oxygen from the oxide semiconductor film contained in transistor 2100. Both methods can prevent the ingress of water and hydrogen into the oxide semiconductor film. The lock film may be used by laminating the insulator 2204, or on the underside of the insulator 2204. It may be provided in [location].

[0349] Note that the 2200 transistor is not only a planar type transistor, but also various types It can be a transistor. For example, a FIN type, a TRI-GATE (transistor) It can be a transistor of the lygate type, etc. An example of a cross-sectional view in that case is shown below. As shown in FIG. 25(D). In FIG. 25(D), the X1-X2 direction indicates the channel length direction, and the Y1- Y2 direction indicates the channel width direction. An insulator 2212 is provided on the semiconductor substrate 2211. The semiconductor substrate 2211 has a thin convex portion (also referred to as a fin) at its tip. Note that an insulator may be provided on the convex portion. Note that the tip of the convex portion does not have to be thin, for example, it may be a substantially rectangular parallelepiped convex portion, or a convex portion with a thick tip. On the convex portion of the semiconductor substrate 2211, a gate insulator 2214 is provided, and a gate electrode 2213 is provided thereon. Source regions and drain regions 2 215 are formed in the semiconductor substrate 2211. Here, an example where the semiconductor substrate 2211 has a convex portion is shown, but the semiconductor device according to one aspect of the present invention is not limited to this. For example, an SOI substrate may be processed to form a semiconductor region having a convex portion.

[0350] <Circuit configuration example> In the above configuration, various circuits can be configured by appropriately connecting the electrodes of the transistor 2100 and the transistor 2200. Hereinafter, an example of a circuit configuration that can be realized by using the semiconductor device according to one aspect of the present invention will be described.

[0351] <CMOS inverter circuit> The circuit diagram shown in FIG. 25(B) shows the so-called CMO S inverter configuration in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their gates are connected.

[0352] <CMOS analog switch> Also, the circuit diagram shown in FIG. 25(C) shows the transistors 2100 and 2200 This shows a configuration where the source and drain are connected. With this configuration, It can function as a so-called CMOS analog switch.

[0353] <Example of a storage device> Using a transistor according to one aspect of the present invention, the stored contents can be preserved even when power is not supplied. Figure 26 shows an example of a semiconductor device (memory device) that can be stored and has no limit on the number of write cycles. This will be shown.

[0354] The semiconductor device shown in Figure 26(A) is a transistor 3200 using a first semiconductor material and a second It has a transistor 3300 and a capacitive element 3400 made of two semiconductor materials. Furthermore, the transistor 3300 is the transistor described in the previous embodiment. It is possible.

[0355] Figure 26(B) shows a cross-sectional view of the semiconductor device shown in Figure 26(A). In Figure 26(B), The X1-X2 direction indicates the channel length direction, and the Y1-Y2 direction indicates the channel width direction. (This is the cross-sectional view.) The semiconductor device shown has a configuration in which a back gate is provided for transistor 3300, A configuration without a back gate is also acceptable.

[0356] Transistor 3300 is a transistor in which a channel is formed in a semiconductor having an oxide semiconductor. It is a transistor. The 3300 transistor has a small off-current, so by using it... It is possible to retain memory content for a long period of time. In other words, it does not require a refresh operation. It is possible to create a semiconductor memory device that does not perform refresh operations, or one that performs refresh operations very infrequently. This allows for a significant reduction in power consumption.

[0357] In Figure 26(A), the first wiring 3001 is connected to the source electrode of transistor 3200 and electrical The second wire 3002 is electrically connected to the drain electrode of transistor 3200. It is continued. Also, the third wiring 3003 is the source electrode or of transistor 3300. Electrically connected to one of the rain electrodes, the fourth wire 3004 is connected to the gate of transistor 3300. It is electrically connected to the electrode. And the gate electrode of transistor 3200 is The source electrode or drain electrode of the transistor 3300, and the other of the capacitive element 3400 The first terminal is electrically connected, and the fifth wire 3005 is connected to the second terminal of the capacitive element 3400. They are electrically connected.

[0358] In the semiconductor device shown in Figure 26(A), the potential of the gate electrode of transistor 3200 can be maintained. By utilizing its unique characteristics, it is possible to write, retain, and read information in the following ways: ru.

[0359] This section will explain how to write and retain information. First, the potential of the fourth wiring 3004 is set to the traction control. The potential is set to the ON state for transistor 3300, thereby turning on transistor 3300. As a result, the potential of the third wiring 3003 is the same as the gate electrode of transistor 3200, and And is supplied to the capacitance element 3400. That is, the gate electrode of transistor 3200 is A predetermined charge is applied (written). Here, a charge that gives two different potential levels. (Hereafter referred to as Low-level charge and High-level charge) Then, the potential of the fourth wire 3004 is set to the potential at which transistor 3300 turns off. By doing so, and by turning off transistor 3300, the gate of transistor 3200 The charge applied to the electrode is retained (retained).

[0360] Because the off-current of transistor 3300 is extremely small, the gate current of transistor 3200 The charge at the poles is retained for a long period of time.

[0361] Next, we will explain how to read the information. A predetermined potential (constant potential) is applied to the first wiring 3001. In this state, when an appropriate potential (readout potential) is applied to the fifth wiring 3005, the transistor Depending on the amount of charge held at the gate electrode of terminal 3200, the second wiring 3002 will be at a different potential. Generally, if transistor 3200 is an n-channel type, then transistor 3200 The apparent threshold V when a high level charge is applied to the terminal terminal th_H This is the case when a low level charge is applied to the gate electrode of transistor 3200. The threshold V th_L This is because it becomes lower. Here, the apparent threshold voltage is, The potential of the fifth wire 3005, which is necessary to turn on transistor 3200, Therefore, the potential of the fifth wiring 3005 is set to V th_H and V th_L between By setting the potential to V0, the charge applied to the gate electrode of transistor 3200 can be determined. Yes, it is possible. For example, in writing, if a high-level charge is given, The potential of wiring 3005 is V0 (>V th_H ) If so, the transistor 3200 is "O The state becomes "N state". If a low-level charge is applied, the fifth wiring 3005 The rank is V0( <V th_L Even if this happens, transistor 3200 remains in the "off state". Therefore, by determining the potential of the second wiring 3002, the information being held can be read. It can be released.

[0362] When memory cells are arranged in an array, only the information of the desired memory cell is read. It is necessary to be able to output information. For example, in a memory cell that does not read information, Regardless of the potential applied to it, the potential such that transistor 3200 is in the "off state", In other words, V th_H By applying a smaller potential to the fifth wiring 3005, the desired memory setting is achieved. The configuration should allow only the information of the memory cell to be read. Alternatively, the memory cell should not be used to read information. In this case, regardless of the potential applied to the gate electrode, transistor 3200 is "on" A potential such that the state is "V th_L A higher potential is applied to the fifth wiring 3005. The system should be configured to allow reading only the desired information from the memory cell.

[0363] The semiconductor device shown in Figure 26(C) is different from the one shown in Figure 26(A) in that it does not have transistor 3200. ) is different. In this case as well, the information writing and retention operations are performed in the same manner as above. It is possible.

[0364] Next, we will explain how to read the information. When transistor 3300 is turned on, floating The third wiring 3003, which is in a free state, and the capacitive element 3400 are electrically connected, and the third wiring 3003 and Charge is redistributed among the capacitive elements 3400. As a result, the potential of the third wiring 3003 changes. The change in potential of the third wiring 3003 is the potential of the first terminal of the capacitive element 3400. Alternatively, it takes on different values ​​depending on the charge stored in the capacitive element 3400.

[0365] For example, let V be the potential of the first terminal of the capacitive element 3400, C be the capacitance of the capacitive element 3400, and the third terminal The capacitance component of wiring 3003 is CB, and the charge of the third wiring 3003 before redistribution is CB If the potential is VB0, then the potential of the third wiring 3003 after the charge has been redistributed is (CB × VB0 + C × V) / (CB + C). Therefore, the state of the memory cell is the capacity element If the potential of the first terminal of child 3400 takes two states, V1 and V0 (V1 > V0), then The potential of the third wiring 3003 when position V1 is maintained is (=(CB×VB0+C×V1)) / (CB+C)) is the potential of the third wiring 3003 when the potential V0 is maintained (=(C) It can be seen that this is higher than B × VB0 + C × V0) / (CB + C)).

[0366] Then, by comparing the potential of the third wiring 3003 with a predetermined potential, the information is read out. It is possible.

[0367] In this case, the first semiconductor material described above was applied to the drive circuit for driving the memory cell. A transistor is used, and a second semiconductor material is applied to transistor 3300. The zistas can be stacked on top of the drive circuit.

[0368] In the semiconductor device shown in this embodiment, an oxide semiconductor is used in the channel formation region for off-current By applying extremely small transistors, it is possible to retain memory contents for extremely long periods of time. This is possible. In other words, the refresh operation becomes unnecessary, or the refresh operation is eliminated. Because the frequency of operation can be made extremely low, power consumption can be significantly reduced. Furthermore, in the absence of power supply (however, it is desirable that the potential be fixed), However, it is possible to retain memory content over a long period of time.

[0369] Furthermore, the semiconductor device shown in this embodiment does not require a high voltage for writing information, and There are no issues with degradation of the child. For example, unlike conventional non-volatile memory, it does not use floating gates. Because there is no need to inject electrons into it or extract electrons from the floating gate, Problems such as deterioration of the gate insulating layer do not occur at all. In other words, the semiconductor according to the disclosed invention. The device does not have the limitations on the number of rewrite cycles that are a problem with conventional non-volatile memory, and Reliability improves dramatically. Furthermore, the on and off states of the transistors allow information to be transmitted. Because writing is performed, high-speed operation can be easily achieved.

[0370] By using the semiconductor device shown in this embodiment, low power consumption and high capacity (for example) are achieved. It is possible to create storage devices with a capacity of 1 terabit or more.

[0371] In this specification, active elements (transistors, diodes, etc.), passive elements ( For all terminals of capacitive elements, resistive elements, etc., the destination of their connection is not specified. However, a person skilled in the art may be able to constitute one aspect of the invention. In other words, connection Even without specifying the destination, one aspect of the invention can be said to be clear. And the connection destination is specified. If the content is described in this specification, etc., then one aspect of the invention that does not specify the connection destination is described in this specification. In some cases, it can be determined that this is stated in the document or other documentation. In particular, multiple terminals are used as connection destinations. When multiple cases are possible, it is not necessary to limit the connection destination of that terminal to a specific location. Therefore, active elements (transistors, diodes, etc.) and passive elements (capacitive elements, resistors) are distinct. By specifying the connection destination for only some of the terminals (such as those on an element), It may be possible to constitute one aspect of the invention.

[0372] Furthermore, in this specification, etc., if a certain circuit is specified, then at least the connection destination is identified, and this applies to our business. If you are an expert, you may be able to identify the invention. Or, regarding a certain circuit, However, if the function is specified, a person skilled in the art may be able to specify the invention. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in this specification, etc. Therefore, even without specifying the function of a certain circuit, if the connection destination is specified, it constitutes an invention. It is disclosed as such and can constitute one aspect of the invention. Regarding a certain circuit, even if the connection destination is not specified, if the function is specified, it can be considered as one aspect of the invention. This has been disclosed and can constitute one aspect of the invention.

[0373] In this specification, etc., the figures or text described in a particular embodiment may differ from the actual figures or text. Therefore, it is possible to take a part of it and constitute one aspect of the invention. If a diagram or text describing a part is included, remove a portion of that diagram or text. The information provided is disclosed as one aspect of the invention and constitutes one aspect of the invention. It is assumed that this is possible. For example, active elements (transistors, diodes) (etc.), wiring, passive elements (capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductors, organic materials Drawings that describe one or more materials, inorganic materials, parts, devices, operating methods, manufacturing methods, etc. Alternatively, in the description, it is possible to extract a part thereof to constitute an aspect of the invention. It is assumed that, for example, it has N (N is an integer) circuit elements (transistors, capacitor elements, etc.). From a circuit diagram constituted by, it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitors, etc.) to constitute an aspect of the invention. As another example, from a cross-sectional view constituted by having N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers to constitute an aspect of the invention. As yet another example, from a flowchart constituted by having N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention. Furthermore, as yet another example, from a flowchart constituted by having N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention. As yet another example, from a flowchart constituted by having N (N is an integer) elements, it is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention. It is possible to extract M (M is an integer, M < N) elements to constitute an aspect of the invention.

[0374] <Imaging device> Hereinafter, an imaging device according to an aspect of the present invention will be described.

[0375] FIG. 27(A) is a plan view showing an example of an imaging device 200 according to an aspect of the present invention. The imaging device 200 includes a pixel unit 210, a peripheral circuit 260 for driving the pixel unit 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification, etc., all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit". For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit. The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. The pixel unit 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 are each connected to a plurality of pixels 211 and have a function of supplying signals for driving the plurality of pixels 211. In this specification, etc., all of the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 may be referred to as "peripheral circuit" or "driving circuit". For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit. For example, the peripheral circuit 260 can be said to be a part of the peripheral circuit.

[0376] Furthermore, the peripheral circuits include at least logic circuits, switches, buffers, amplification circuits, or converters. It has one of the circuits. Furthermore, the peripheral circuits may be formed on the substrate forming the pixel section 210. Furthermore, semiconductor devices such as IC chips may be used in part or all of the peripheral circuits. The peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280 and peripheral circuit 290. You may omit one or more of the following:

[0377] Furthermore, as shown in Figure 27(B), in the pixel section 210 of the imaging device 200, Pixels 211 may be arranged at an angle. By arranging pixels 211 at an angle, the row direction and The pixel spacing (pitch) in the column direction can be shortened. This allows the imaging device 200 to This allows for a further improvement in the quality of the images being captured.

[0378] <Example of pixel configuration 1> The imaging device 200 has one pixel 211 which is composed of multiple sub-pixels 212, and each sub A filter (color filter) that transmits light in a specific wavelength range is combined with pixel 212. This allows us to obtain the information necessary to display color images.

[0379] Figure 28(A) is a plan view showing an example of pixels 211 for acquiring a color image. The pixel 211 shown in 28(A) is equipped with a color filter that transmits light in the red (R) wavelength band. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") emits light in the green (G) wavelength band. Sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. Sub-pixel 212 is provided with a color filter that transmits light in the wavelength bands of (u) and blue (B). It has (hereinafter also referred to as "sub-pixel 212B"). The sub-pixel 212 is a photosensor It can be made to work.

[0380] Sub-pixels 212 (sub-pixels 212R, 212G, and 212B) are connected to wiring 23 1. It is electrically connected to wires 247, 248, 249, and 250. Pixel 212R, sub-pixel 212G, and sub-pixel 212B are each connected by independent wiring 25 It is connected to 3. Also, in this specification, for example, the nth row (where n is an integer between 1 and p). Wirings 248 and 249 connected to pixel 211 of ) are respectively wired 248[n] And it is written as wiring 249[n]. Also, for example, the mth column (where m is an integer between 1 and q) The wiring 253 connected to pixel 211 is denoted as wiring 253[m]. Note that in Figure 28(A In this case, wiring 253 is connected to the sub-pixel 212R of the m-th pixel 211. Wiring 253[m]G connects to sub-pixel 212G, and sub-pixel 53[m]R, wiring 253[m]G, and sub-pixel The wiring 253 connected to element 212B is described as wiring 253[m]B. Sub-pixel 212 is It is electrically connected to the surrounding circuitry via the above wiring.

[0381] Furthermore, the imaging device 200 transmits light of the same wavelength band to adjacent pixels 211. The sub-pixels 212, each equipped with a filter, are electrically connected to each other via a switch. Figure 28(B) shows the sub-pixels 212 of the pixel 211 arranged in n rows and m columns, and the pixel 2 This shows an example of the connection of subpixels 212 of pixel 211, which is located in row n+1 and column m adjacent to pixel 11. In Figure 28(B), subpixels 212R are arranged in row n and column m, and subpixels 212R are arranged in row n+1 and column m. The sub-pixels 212R are connected via switch 201. Also, arranged in n rows and m columns The sub-pixel 212G placed and the sub-pixel 212G arranged in row n+1 and column m are switched 202 They are connected via [a certain method]. Also, the subpixels 212B are located in n rows and m columns, and the subpixels are located in n+1 rows and m columns. The sub-pixel 212B located there is connected via switch 203.

[0382] Furthermore, the color filters used for sub-pixel 212 are limited to red (R), green (G), and blue (B). Color film that transmits cyan (C), yellow (Y), and magenta (M) light respectively. A LUTA may be used. A sub-pixel detects light of three different wavelength bands in one pixel 211. By adding 212, it is possible to acquire a full-color image.

[0383] Alternatively, color filters that transmit red (R), green (G), and blue (B) light, respectively, are provided. In addition to the sub-pixels 212 that have been cut off, a sub-pixel with a color filter that transmits yellow (Y) light is provided. A pixel 211 having pixel 212 may be used. Alternatively, cyan (C) and yellow (Y) may be used, respectively. In addition to sub-pixels 212 equipped with a color filter that transmits ) and magenta (M) light, A pixel 21 has a sub-pixel 212 that is provided with a color filter that transmits blue (B) light. 1 may be used. Sub-pixels 2 detect light of four different wavelength bands in one pixel 211. By adding 12, the color reproduction accuracy of the acquired image can be further improved.

[0384] Furthermore, for example, in Figure 28(A), sub-pixel 212 detects light in the red wavelength band, and green Sub-pixel 212 for detecting light in a specific wavelength band, and sub-pixel 212 for detecting light in the blue wavelength band. The pixel ratio (or light-receiving area ratio) does not have to be 1:1:1. For example, the pixel ratio A Bayer array with a (light-receiving area ratio) of red:green:blue = 1:2:1 may also be used. Alternatively, The pixel ratio (light-receiving area ratio) may also be set to red:green:blue = 1:6:1.

[0385] Note that while one sub-pixel 212 may be provided in pixel 211, two or more are preferable. By providing two or more sub-pixels 212 that detect light in the same wavelength band, redundancy is increased, and This can improve the reliability of the imaging device 200.

[0386] Furthermore, IR (Infrared) absorbs or reflects visible light and transmits infrared light. By using a filter, an imaging device 200 that detects infrared light can be realized.

[0387] Also, an ND (Neutral Density) filter (light-reducing filter) is used. This is because when a large amount of light is incident on a photoelectric conversion element (light-receiving element), the output saturation occurs. This can prevent this. By using a combination of ND filters with different light reduction amounts, the imaging device This allows for a wider dynamic range in the image.

[0388] In addition to the filter mentioned above, a lens may also be provided at pixel 211. Here, Figure 29 An example of the arrangement of pixels 211, filter 254, and lens 255 will be explained using a cross-sectional diagram. By providing the 255 element, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in Figure 29(A), a lens 255 and a filter 25 are formed on the pixel 211. 4 (filters 254R, 254G, and 254B), and pixel circuit 2 The structure can be configured to allow light 256 to be incident on the photoelectric conversion element 220 through 30, etc.

[0389] However, as shown in the area enclosed by the dashed line, a portion of the light 256 indicated by the arrow is connected to wiring 257. It may be partially blocked by something. Therefore, as shown in Figure 29(B), the photoelectric The lens 255 and filter 254 are placed on the side of the conversion element 220, and the photoelectric conversion element 220 A structure that efficiently receives light 256 is preferred. Light 256 is received from the photoelectric conversion element 220 side. By injecting light into the photoelectric conversion element 220, an imaging device 200 with high detection sensitivity is provided. It is possible.

[0390] As shown in Figure 29, the photoelectric conversion element 220 has a pn-type junction or a pin-type junction formed on it. Photoelectric conversion elements may also be used.

[0391] Furthermore, the photoelectric conversion element 220 uses a material that has the function of absorbing radiation and generating electric charge. It may be formed by absorbing radiation and generating an electric charge. Len, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy These include:

[0392] For example, if selenium is used in the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 having an optical absorption coefficient across a wide wavelength range, including X-rays and gamma rays. We can achieve 20.

[0393] Here, one pixel 211 of the imaging device 200 is, in addition to the sub-pixel 212 shown in Figure 28, Furthermore, it may have a sub-pixel 212 having a first filter.

[0394] <Example of pixel configuration 2> Below, we will discuss transistors using silicon and transistors using oxide semiconductors. An example of how pixels are constructed using this method will be explained.

[0395] Figures 30(A) and 30(B) are cross-sectional views of the elements constituting the imaging device. Figure 30(A) In this diagram, the X1-X2 direction represents the channel length direction, and the Y1-Y2 direction represents the channel width direction. In Figure 30(B), the X1-X2 direction represents the channel length, and the Y1-Y2 direction represents the channel width. Indicates direction.

[0396] The imaging device shown in Figure 30(A) is a silicon-based transistor provided on a silicon substrate 300. Transistor 351, Transistor 351 with an oxide semiconductor stacked on top of it A diode 353 and a silicon substrate 300 are provided with an anode 361 and a cathode Includes a photodiode 360 ​​having 362. Each transistor and photodiode 360 is an electrical connection with various plugs 370 and wiring 371, wiring 372, wiring 373. It has a connection. Also, the anode 361 of the photodiode 360 ​​is connected via a low-resistance region 363. It has an electrical connection with plug 370.

[0397] The imaging device also includes a transistor 351 and a photodie provided on the silicon substrate 300. A layer 310 having an ore 360, and a layer 3 provided in contact with the layer 310 and having wiring 371 20 and layer 33 which is provided in contact with layer 320 and has a transistor 353 and an insulating layer 380 The set includes layer 0 and layer 340 which is provided in contact with layer 330 and has wiring 372 and wiring 373. It is.

[0398] In addition, in the example cross-sectional view in Figure 30(A), transistor 3 is located on the silicon substrate 300. The configuration includes a photodiode 360 ​​with a light-receiving surface on the side opposite to the surface where 51 is formed. This configuration ensures that the optical path is not affected by various transistors, wiring, etc. This allows for the formation of pixels with a high aperture ratio. The light-receiving surface of D360 can also be the same as the surface on which transistor 351 is formed.

[0399] Furthermore, when constructing pixels using only transistors made of oxide semiconductors, layer 31 Layer 0 can be a layer containing a transistor made of oxide semiconductor. Alternatively, layer 310 can be omitted. In short, pixels may be constructed using only transistors made of oxide semiconductors.

[0400] Furthermore, in the cross-sectional view of Figure 30(A), the photodiode 360 ​​provided in layer 310 and layer The transistors provided at 330 can be formed to overlap with the pixels. This allows for an increase in the integration density, that is, an increase in the resolution of the imaging device.

[0401] Furthermore, Figure 30(B) shows that the imaging device has a photodiode 365 on the layer 340 side and a transistor It can be a structure placed on top of. In Figure 30(B), for example, layer 310 is It has a silicon transistor 351, layer 320 has wiring 371, and layer 330 It has an oxide semiconductor transistor 353 and an insulating layer 380, and layer 340 has a It has a diode 365, wiring 373, and wiring 374 via plug 370 and electrical It is connected to the target.

[0402] The element configuration shown in Figure 30(B) can be used to improve the aperture ratio.

[0403] Furthermore, the photodiode 365 uses amorphous silicon film, microcrystalline silicon film, etc. A pin-type diode element may also be used. The photodiode 365 is an n-type semiconductor. The configuration has a stacked arrangement of semiconductor 368, i-type semiconductor 367, and p-type semiconductor 366 in that order. It is preferable to use amorphous silicon for the i-type semiconductor 367. Also, p-type semiconductor The conductor 366 and the n-type semiconductor 368 include dopants that impart their respective conductivity types. Amorphous silicon or microcrystalline silicon can be used. The photodiode 365, which serves as the power conversion layer, has high sensitivity in the visible light wavelength range, and is very sensitive to weak light. It can easily detect visible light.

[0404] This embodiment can be appropriately combined with other embodiments shown herein. .

[0405] (Embodiment 4) In this embodiment, a transistor having an oxide semiconductor layer as described in the above embodiment ( An example of a circuit configuration to which an OS transistor can be applied will be explained using Figures 31 to 34. do.

[0406] Figure 31(A) shows an inverter that can be applied to memory, FPGA, CPU, etc. The circuit diagram is shown. Inverter 2800 inverts the logic of the signal applied to the input terminal IN. It outputs to the output terminal OUT. The inverter 2800 has multiple OS transistors. . signal S BG This is a signal that can switch the electrical characteristics of an OS transistor.

[0407] Figure 31(B) is a circuit diagram of an example of inverter 2800. Inverter 2800 is It has OS transistor 2810 and OS transistor 2820. Inverter 2 The 800 can be fabricated as an n-channel type, and can be configured as a so-called unipolar circuit. Therefore, since inverters can be manufactured with a unipolar circuit configuration, CMOS (Complement Inverter (CMO) using a metal oxide semiconductor. It is possible to manufacture it at a lower cost compared to manufacturing an S-type inverter.

[0408] Furthermore, the inverter 2800, which has an OS transistor, is composed of C transistors. It can also be placed on top of a MOS. The inverter 2800 is superimposed on a CMOS circuit configuration. Because it can be positioned in this way, the increase in circuit area due to adding the inverter 2800 can be minimized. ru.

[0409] OS transistors 2810 and 2820 function as front gates. A first gate, a second gate that functions as a back gate, and one of the source or drain gates. It has a first terminal that functions as one side and a second terminal that functions as the other side of the source or drain. ru.

[0410] The first gate of OS transistor 2810 is connected to the second terminal. OS transistor 2 The second gate of 810 is signal S BG It is connected to the wiring that transmits the signal. OS Transistor 281 The first terminal of the 0 is connected to the wiring that provides the voltage VDD. The first terminal of the OS transistor 2810 Terminal 2 is connected to the output terminal OUT.

[0411] The first gate of the OS transistor 2820 is connected to the input terminal IN. The second gate of the 2820 is connected to the input terminal IN. Terminal 1 is connected to the output terminal OUT. Terminal 2 of the OS transistor 2820 is voltage Connect to the wiring that provides VSS.

[0412] Figure 31(C) is a timing chart illustrating the operation of inverter 2800. In the timing chart of Figure 31(C), the signal waveform of the input terminal IN and the output terminal OUT are shown. Signal waveform, signal S BG The signal waveform and the threshold voltage of the OS transistor 2810 change It indicates that.

[0413] signal S BG By applying this to the second gate of the OS transistor 2810, the OS transistor The threshold voltage of the 2810 can be controlled.

[0414] signal S BG This is the voltage V used to negatively shift the threshold voltage. BG_A , the threshold voltage Voltage V for shifting BG_B It has a voltage V applied to the second gate. BG_A to give Therefore, the OS transistor 2810 has a threshold voltage V TH_A It is possible to perform a negative shift. It can be done. Also, a voltage V is applied to the second gate. BG_B By providing this, the OS transistor 2810 Threshold voltage V TH_B It can be shifted to a positive value.

[0415] To visualize the above explanation, Figure 32(A) shows one of the electrical characteristics of a transistor. Next, a graph of the Vg-Id curve is shown.

[0416] The electrical characteristics of the OS transistor 2810 described above are such that the voltage at the second gate is V BG_A of By making it larger in this way, it shifts to the curve represented by the dashed line 2840 in Figure 32(A). It is possible. Furthermore, the electrical characteristics of the OS transistor 2810 described above are as follows: Voltage V BG_B By making it smaller as shown, it is represented by the solid line 2841 in Figure 32(A). It can be shifted to a curve. As shown in Figure 32(A), OS transistor 28 10 is signal S BG Voltage V BG_A Or voltage V BG_B Switching in this way This allows the threshold voltage to be shifted positively or negatively.

[0417] The threshold voltage is the threshold voltage V TH_B By shifting it to positive, the OS transistor 2810 This can create a state where current is difficult to flow. Figure 32(B) visualizes this state. As shown in Figure 32(B), the current I flowing through the OS transistor 2810 is shown. B to the extreme It can be made even smaller. Therefore, the signal applied to the input terminal IN is at a high level OS When transistor 2820 is ON, the voltage at the output terminal OUT drops sharply. It is possible to do so.

[0418] As shown in Figure 32(B), the current flowing through the OS transistor 2810 is difficult to control. Therefore, the output terminals in the timing chart shown in Figure 31(C) The signal waveform 2831 can be made to change sharply. The wiring that provides voltage VDD and voltage V Because the through-current flowing between the wiring that provides SS can be reduced, it consumes less power. It can perform the following actions.

[0419] Also, the threshold voltage is the threshold voltage V TH_A By shifting it to the negative, the OS transistor The 2810 can be made to a state where current flows easily. Figure 32(C) shows this state. Visualize and show. As shown in Figure 32(C), the current I flowing at this time A at least electricity Flow I B It can be made larger than that. Therefore, the signal applied to the input terminal IN is low level. When the OS transistor 2820 is in the OFF state, the voltage at the output terminal OUT is above It is possible to ascend steeply.

[0420] As shown in Figure 32(C), the current flowing through the OS transistor 2810 is in a state that allows current to flow easily. Therefore, the output terminals in the timing chart shown in Figure 31(C) The signal waveform 2832 can be made to change sharply.

[0421] Note that signal S BG The threshold voltage control of the OS transistor 2810 is performed by the OS transistor It is preferable to perform this before the state of the TA2820 switches, i.e., before time T1 or T2. For example, as shown in Figure 31(C), the signal applied to the input terminal IN is high level. Before the time T1 when the switch occurs, the threshold voltage V TH_A From threshold voltage V TH_B OS It is preferable to switch the threshold voltage of the transistor 2810. Also, as shown in Figure 31(C) Therefore, before the time T2 at which the signal applied to the input terminal IN switches to a low level, Threshold voltage V TH_B From threshold voltage V TH_A The threshold voltage of the OS transistor 2810 is switched It is preferable to replace it.

[0422] In the timing chart in Figure 31(C), the signal changes according to the signal applied to the input terminal IN. S BG The configuration shown involves switching between the two, but other configurations are also possible. For example, controlling the threshold voltage The voltage required for this is maintained at the second gate of the floating OS transistor 2810. A configuration that allows for this may also be used. An example of a circuit configuration that can realize this configuration is shown in Figure 33(A ) is shown.

[0423] Figure 33(A) shows the circuit configuration shown in Figure 31(B), plus an OS transistor 2850. It has the first terminal of OS transistor 2850 and the second terminal of OS transistor 2810. It is connected to the terminal. Also, the second terminal of the OS transistor 2850 is connected to the voltage V BG_B (be V is the voltage BG_A It is connected to the wiring that gives ) the first gate of the OS transistor 2850. The signal S F It is connected to the wiring that gives the signal. The second gate of the OS transistor 2850 is Voltage V BG_B (or voltage V) BG_A It is connected to the wiring that provides the following.

[0424] The operation shown in Figure 33(A) will be explained using the timing chart in Figure 33(B).

[0425] The voltage used to control the threshold voltage of the OS transistor 2810 is the signal applied to the input terminal IN. Before the time T3 when the signal switches to high level, the second gate of the OS transistor 2810 The configuration will be given to the signal S. F The OS transistor 2850 is turned ON as a high level State, node N BG A voltage V to control the threshold voltage. BG_B Give.

[0426] Node N BG Voltage V BG_B After that, the OS transistor 2850 is turned off. The OS transistor 2850 has an extremely low off-current, so it can be kept in the off state. And so, once node N BG The voltage V held at this position BG_B It can hold. A voltage V is applied to the second gate of the OS transistor 2850. BG_B The number of actions that give the result decreases. voltage V BG_B This reduces the power consumption required for rewriting the data.

[0427] Note that in the circuit configurations of Figures 31(B) and 33(A), the number of OS transistors 2810 We have shown a configuration in which the voltage applied to the two gates is supplied by external control, but another configuration This may also be done. For example, a voltage to control the threshold voltage is applied to the input terminal IN. It may also be configured to generate a base and apply it to the second gate of the OS transistor 2810. An example of a circuit configuration that can achieve this is shown in Figure 34(A).

[0428] In Figure 34(A), in the circuit configuration shown in Figure 31(B), the input terminal IN and OS transistor are shown. A CMOS inverter 2860 is located between the second gate of the zista 2810. The input terminal of inverter 2860 is connected to input terminal IN. CMOS inverter 286 The output terminal of 0 is connected to the second gate of the OS transistor 2810.

[0429] The operation shown in Figure 34(A) will be explained using the timing chart in Figure 34(B). In the timing chart 34(B), the signal waveform at the input terminal IN and the signal at the output terminal OUT are shown. Waveform, output waveform IN_B of CMOS inverter 2860, and OS transistor 281 This shows the change in the threshold voltage of 0.

[0430] The output waveform IN_B, which is the signal obtained by inverting the logic of the signal applied to the input terminal IN, is an OS transistor. This can be used as a signal to control the threshold voltage of the ZISTRA 2810. Therefore, Figure 32(A As explained in (C) or (F), the threshold voltage of the OS transistor 2810 can be controlled. For example, when time T4 occurs in Figure 34(B), the signal applied to the input terminal IN is high level. At this point, the OS transistor 2820 turns ON. At this time, the output waveform IN_B is low. It becomes a bell. Therefore, the OS transistor 2810 is designed to be in a state where current does not easily flow. This allows for a steep drop in the voltage at the output terminal OUT.

[0431] Furthermore, when time T5 occurs in Figure 34(B), the signal applied to the input terminal IN is low level. The OS transistor 2820 turns off. At this time, the output waveform IN_B is high-frequency. It becomes a bell. Therefore, the OS transistor 2810 is in a state where current flows easily. This allows for a steep increase in the voltage at the output terminal OUT.

[0432] As described above, in the configuration of this embodiment, the inverter having an OS transistor The back gate voltage is switched according to the logic of the signal applied to the input terminal IN. This configuration allows for control of the threshold voltage of the OS transistor. By controlling the threshold voltage of the inverter in accordance with the signal applied to the input terminal IN, the output terminal This allows for a steeper change in the voltage of the child OUT. It also allows for through-circuiting between wiring supplying power. The current can be reduced. Therefore, power consumption can be lowered.

[0433] (Embodiment 5) <RFタグ> In this embodiment, an RF including a transistor or memory device as described in the previous embodiment is used. Tags will be explained using Figure 35.

[0434] The RF tag in this embodiment has a memory circuit inside, and stores the necessary information in the memory circuit. Furthermore, it uses non-contact means, such as wireless communication, to exchange information with the outside world. Due to its characteristics, RF tags are used to identify items by reading individual information about those items. It can be used in body recognition systems, etc. However, in order to use it for these purposes, For the first time, a high level of reliability is required.

[0435] The configuration of an RF tag will be explained using Figure 35. Figure 35 shows an example of the configuration of an RF tag. This is a lock diagram.

[0436] As shown in Figure 35, the RF tag 800 is connected to the communicator 801 (also known as an interrogator, reader / writer, etc.). Antenna 8 receives a radio signal 803 transmitted from antenna 802 connected to ( It has 04. The RF tag 800 also has a rectifier circuit 805, a constant voltage circuit 806, and a demodulation circuit 8 It has a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Furthermore, the reverse current in the rectifying transistor included in the demodulation circuit 807 is sufficiently suppressed. A configuration may be made using a material capable of doing so, for example, an oxide semiconductor. This suppresses the decrease in rectification due to reverse current and prevents the output of the demodulation circuit from saturating. This can be prevented. In other words, the output of the demodulation circuit can be made more linear with respect to the input of the demodulation circuit. It is possible. Furthermore, the data transmission format involves a pair of coils positioned opposite each other and communicating through mutual induction. Electromagnetic coupling methods, electromagnetic induction methods that use induced electromagnetic fields for communication, and methods that use radio waves for communication. They can be broadly classified into three types of radio wave methods. The RF tag 800 shown in this embodiment uses any of these methods. It can also be used for this purpose.

[0437] Next, the configuration of each circuit will be explained. Antenna 804 is connected to the communication device 801. This is for transmitting and receiving wireless signals 803 with Tenor 802. Also, a rectifier circuit 8 05 rectifies the input AC signal generated by receiving a wireless signal with antenna 804. For example, half-wave voltage doubling rectification is performed, and the rectified signal is smoothed by a capacitive element provided in the subsequent stage. This is a circuit for generating input potential by converting it. Furthermore, the input side of the rectifier circuit 805 is also A limiter circuit may be provided on the output side. A limiter circuit is a circuit that limits the amplitude of the input AC signal. When the internally generated voltage is large, do not input power exceeding a certain level to the subsequent circuit. This is a circuit for controlling sea urchins.

[0438] The constant voltage circuit 806 generates a stable power supply voltage from the input potential and supplies it to each circuit. This is a circuit. Note that the constant voltage circuit 806 may also have an internal reset signal generation circuit. The reset signal generation circuit utilizes the stable rise of the power supply voltage to generate the logic circuit 80. This is a circuit for generating a reset signal for number 9.

[0439] The demodulation circuit 807 demodulates the input AC signal by detecting its envelope and generates a demodulated signal. This is a circuit for that purpose. Furthermore, the modulation circuit 808 responds to the data output from the antenna 804. This is a circuit for performing modulation.

[0440] Logic circuit 809 is a circuit for analyzing and processing demodulated signals. Memory circuit 810 is This is a circuit that holds the input information, and includes a row decoder, column decoder, memory area, etc. It has. Furthermore, ROM811 stores unique numbers (IDs), etc., and outputs them according to the processing. This is a circuit for that purpose.

[0441] Furthermore, the circuits described above can be selected or omitted as needed.

[0442] Here, the semiconductor device described in the previous embodiment can be used as the memory circuit 810. A memory circuit according to one aspect of the present invention can retain information even when the power supply is cut off. It can be suitably used in RF tags. Furthermore, a storage circuit according to one aspect of the present invention stores data Because the power (voltage) required for writing is significantly lower than that of conventional non-volatile memory, data It is also possible to eliminate the difference in the maximum communication distance between data reading and writing. This prevents malfunctions or incorrect data writing that may occur due to insufficient power during data writing. It is possible.

[0443] Furthermore, a memory circuit according to one aspect of the present invention can be used as a non-volatile memory. Therefore, it can also be applied to ROM811. In that case, the manufacturer will provide data to ROM811. A separate command is provided for writing the data, preventing users from freely rewriting it. It is preferable that the producer writes a unique number on the product before shipping it. Instead of assigning a unique number to every RF tag produced, only the good quality tags that are shipped will have a unique number assigned to them. It becomes possible to assign a unique number, and the unique numbers of products after shipment will not be discontinuous. Customer management corresponding to the shipped products becomes easy.

[0444] Note that this embodiment can be appropriately combined with other embodiments described in this specification. .

[0445] (Embodiment 6) In this embodiment, a CPU including the storage device described in the previous embodiment will be described.

[0446] FIG. 36 is a block diagram showing a configuration of an example of a CPU using at least a part of the transistors described in the previous embodiment. It is a block diagram showing a configuration of an example.

[0447] <Circuit diagram of CPU> The CPU shown in FIG. 36 has an ALU 1191 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface 1 198, a rewritable ROM 1199, and a ROM interface 1189 on a substrate 1190. The substrate 1190 uses a semiconductor substrate, an SOI substrate, a glass substrate, etc. The rewritable ROM 1199 and the ROM interface 1189 may be provided on a separate chip. Of course, the CPU shown in FIG. 36 is only an example showing a simplified configuration thereof, and an actual CPU has various configurations depending on its application. For example, the CPU shown in FIG. 36 or a configuration including an arithmetic circuit is regarded as one core, and a plurality of such cores are included, and each core operates in parallel as a configuration. Also, a CPU may be configured such that internal arithmetic circuits and data buses can handle it. or an arithmetic circuit as one core, and includes a plurality of such cores, and each core operates in parallel as a configuration. Also, a CPU may be configured such that internal arithmetic circuits and data buses can handle The number of bits can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc. can.

[0448] Instructions input to the CPU via the bus interface 1198 are instructions The signal is input to decoder 1193, decoded, and then processed by ALU controller 1192, interface Raptor controller 1194, register controller 1197, timing controller It is entered into 1195.

[0449] ALU controller 1192, interrupt controller 1194, register controller R1197 and timing controller 1195 control various commands based on the decoded instructions. To perform the operation. Specifically, the ALU controller 1192 controls the operation of the ALU 1191. It generates a signal. Also, the interrupt controller 1194 controls the CPU's program. During execution, interrupt requests from external input / output devices and peripheral circuits are processed based on their priority and masking. The system makes a judgment and processes based on the state. The register controller 1197 determines the address of register 1196. It generates a value and reads or writes to register 1196 depending on the CPU state.

[0450] Furthermore, the timing controller 1195 is connected to the ALU 1191 and the ALU controller 119 2. Instruction decoder 1193, interrupt controller 1194, and It generates signals to control the timing of the operation of the register controller 1197. For example, The timing controller 1195 generates an internal clock signal based on the reference clock signal. It is equipped with an internal clock generation unit that supplies the internal clock signal to the various circuits mentioned above.

[0451] In the CPU shown in Figure 36, a memory cell is located in register 1196. The transistors shown in the previous embodiment can be used as the 1196 memory cells. ru.

[0452] In the CPU shown in Figure 36, the register controller 1197 receives information from ALU 1191. Following the instructions, select the hold operation in register 1196. That is, register 11 In the memory cell of 96, data is retained by a flip-flop, or capacity Select whether to retain data using an element. Data retention using a flip-flop is If selected, power voltage is supplied to the memory cells in register 1196. If data retention in the capacitive element is selected, data rewriting to the capacitive element will not occur. This process can be performed to stop the supply of power voltage to the memory cells in register 1196. .

[0453] <Recording Circuit> Figure 37 is an example of a circuit diagram of a memory element that can be used as register 1196. The memory element 1200 has a circuit 1201 in which the stored data is lost when the power is cut off, and a memory element 1200 which loses stored data when the power is cut off. A circuit 1202 that prevents data from volatilizing, a switch 1203, a switch 1204, and a logic element It comprises a sub-element 1206, a capacitive element 1207, and a circuit 1220 having a selection function. 1202 consists of the capacitive element 1208, transistor 1209, and transistor 1210. It has a diode, a resistor, an inductor, etc., as needed. It may also have other elements such as a t-axis.

[0454] Here, the memory device described in the previous embodiment can be used in circuit 1202. When the power supply voltage to the memory element 1200 is stopped, the transistor 120 of circuit 1202 The gate of transistor 9 is input to ground potential (0V) or a potential that turns off transistor 1209. The configuration will continue to be such that the first gate of transistor 1209 is connected via a load such as a resistor. The configuration is such that it is grounded.

[0455] Switch 1203 uses a single-conductivity (e.g., n-channel) transistor 1213. The switch 1204 is configured to have a conductivity type opposite to that of a single-conductivity type (for example, a p-channel type). An example using transistor 1214 is shown. Here, the first terminal of switch 1203 The child corresponds to one of the source and drain of transistor 1213, and the second of switch 1203. The terminals correspond to the source and drain of transistor 1213, and switch 1203 is The control signal RD input to the gate of transistor 1213 controls the first terminal and the second terminal. Continuity or non-conductivity between terminals (i.e., the on or off state of transistor 1213) ) is selected. The first terminal of switch 1204 is the source and drain of transistor 1214. Corresponding to one side of the input, the second terminal of switch 1204 is the source of transistor 1214. Corresponding to the other side of the drain, switch 1204 is input to the gate of transistor 1214. The control signal RD determines whether the first terminal and the second terminal are conductive or non-conductive (i.e., The ON or OFF state of the Rangista 1214 is selected.

[0456] One of the sources and drains of transistor 1209 is connected to the pair of electrodes of capacitive element 1208. One side of this is electrically connected to the gate of transistor 1210. Here, the connection part Let the minute be node M2. One of the sources and drains of transistor 1210 is at a low power supply potential. It is electrically connected to a wire (e.g., a GND wire) that can supply power, and the other is a switch. The first terminal of 1203 (one of the source and drain of transistor 1213) is electrically connected. The second terminal of switch 1203 (source and drain of transistor 1213) On the other hand, the first terminal of switch 1204 (the source and drain of transistor 1214) is the first terminal of switch 1204. It is electrically connected to the second terminal of switch 1204 (the terminal of transistor 1214). The other end of the drain is electrically connected to wiring that can supply the power potential VDD. The second terminal of switch 1203 (the other terminal of the source and drain of transistor 1213) ) and the first terminal of switch 1204 (one of the source and drain of transistor 1214) ) and the input terminal of logic element 1206 and one of the pair of electrodes of capacitive element 1207, These are electrically connected. Here, the connection point is called node M1. A pair of capacitive elements 1207. The other electrode can be configured to receive a constant potential. For example, a low potential The system can be configured to receive either a source potential (such as GND) or a high power supply potential (such as VDD) as input. The other of the pair of electrodes of the capacitive element 1207 is a distribution capable of supplying a low power supply potential. It is electrically connected to a wire (for example, a GND wire). This configuration allows for a constant potential to be input. For example, a low power supply potential (such as GND). ) or a high power supply potential (VDD, etc.) can be input. Capacitive element 120 The other of the pair of electrodes (8) is connected to a wire capable of supplying a low power potential (e.g., GND). It is electrically connected to a wire.

[0457] Capacitive elements 1207 and 1208 are used to absorb parasitic capacitance from transistors and wiring. It was possible to omit it by actively using it.

[0458] The control signal WE is input to the first gate (first gate electrode) of transistor 1209. Switches 1203 and 1204 use a different control signal RD than control signal WE. The conduction or non-conduction state between the first terminal and the second terminal is selected by this, and one of the terminals When there is continuity between the first and second terminals of one switch, the first terminal of the other switch and the second terminal The area between terminals 2 becomes non-conductive.

[0459] Note that in transistor 1209 in Figure 37, the second gate (second gate electrode: buck) The diagram shows a configuration having gates. The first gate receives a control signal WE, and the second gate... The control signal WE2 can be input to the terminal. The control signal WE2 is a signal with a constant potential and This should be done. The constant potential can be, for example, the ground potential GND or the potential of transistor 1209. A potential smaller than the -potential is selected. At this time, the control signal WE2 is the transistor This is a potential signal used to control the threshold voltage of the 1209, and when the gate voltage VG is 0V... The current can be further reduced. Also, the control signal WE2 is the same potential signal as the control signal WE. This is also acceptable. Note that transistor 1209 is a transistor without a second gate. You can also use sta.

[0460] The source and drain of transistor 1209 are connected to the data held in circuit 1201. The corresponding signal is input. In Figure 37, the signal output from circuit 1201 is the transistor An example is shown where the source and drain of switch 1203 are input. The signal output from the second terminal (the other end of the source and drain of transistor 1213) is: The logic element 1206 inverts its logic value, resulting in an inverted signal, which is then transmitted via circuit 1220. This is then input to circuit 1201.

[0461] Note that in Figure 37, the second terminal of switch 1203 (source and terminal of transistor 1213) The signal output from the other side of Rain is routed through logic element 1206 and circuit 1220. An example of input to path 1201 is shown, but it is not limited to this. The second terminal of switch 1203 The signal output from (the other side of the source and drain of transistor 1213) is the inverse of the logic value. It may be input to circuit 1201 without being converted. For example, within circuit 1201, If there is a node that holds a signal that is the inverted logical value of the signal input from the input terminal The second terminal of switch 1203 (the other of the source and drain of transistor 1213) The signal output from this node can be input to the node in question.

[0462] Furthermore, in Figure 37, among the transistors used in the memory element 1200, Transistors other than TA1209 are made of a layer or substrate 119 made of a semiconductor other than an oxide semiconductor. A transistor can be formed where a channel is created at 0. For example, a silicon layer or It can be a transistor in which a channel is formed on a silicon substrate. Also, a memory element. All transistors used in the 1200 are transistors whose channels are formed from oxide semiconductors. It can also be a zista. Alternatively, the memory element 1200 may be a transistor other than the transistor 1209. However, it may also include a transistor whose channel is formed of an oxide semiconductor, and the remaining transistor The radiator has channels formed in a layer or substrate 1190 made of a semiconductor other than an oxide semiconductor. It can also be used as a transistor.

[0463] In Figure 37, circuit 1201 can be, for example, a flip-flop circuit. Furthermore, logic elements such as inverters and clocked inverters can be used as logic elements 1206. It is possible.

[0464] In one aspect of the present invention, in a semiconductor device, when the power supply voltage is not supplied to the memory element 1200 The data stored in circuit 1201 is transferred to the capacitive element 120 provided in circuit 1202. It can be held by 8.

[0465] Furthermore, transistors with channels formed in oxide semiconductors exhibit extremely low off-currents. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor is crystalline. It is significantly lower than the off-current of a transistor in which a channel is formed in silicon. By using the transistor as transistor 1209, the memory element 120 The signal held by the capacitive element 1208 is maintained for a long period of time even when no power supply voltage is supplied to 0. It drips. In this way, the memory element 1200 retains its stored contents (data) even when the power supply voltage is interrupted. It is possible to hold ).

[0466] Furthermore, by providing switches 1203 and 1204, pre-charge action Since it is a memory element characterized by performing an operation, after the power supply voltage is restored, the circuit 1201 This can shorten the time it takes to restore the original data.

[0467] Furthermore, in circuit 1202, the signal held by the capacitive element 1208 is transmitted to the transistor The signal is input to gate 1210. As a result, the power supply voltage to memory element 1200 is restored. After that, the state of transistor 1210 is determined according to the signal held by capacitive element 1208. The state (on or off) is determined and can be read from circuit 1202. Therefore, even if the potential corresponding to the signal held in the capacitive element 1208 fluctuates slightly, the original signal remains. It is possible to read the issue number accurately.

[0468] Such memory elements 1200 are stored in registers and cache memory of the processor. By using it in a storage device, it prevents the loss of data in the storage device due to a power supply interruption. This is possible. Furthermore, after the power supply voltage is restored, the system will quickly return to the state it was in before the power supply was interrupted. Therefore, the entire processor, or one of the components of the processor, This allows for power-off even for short periods in multiple logic circuits, thus reducing power consumption. It can be suppressed.

[0469] In this embodiment, although the memory element 1200 was described as an example of being used in a CPU, the memory element 1 200 is a DSP (Digital Signal Processor), custom L LSIs such as SIs and PLDs (Programmable Logic Devices), R This can also be applied to the F (Radio Frequency) tag.

[0470] This embodiment can be appropriately combined with other embodiments shown herein. .

[0471] (Embodiment 7) This embodiment describes an example of the configuration of a display device using a transistor according to one aspect of the present invention. explain.

[0472] <Display device circuit configuration example> Figure 38(A) is a top view of a display device according to one embodiment of the present invention, and Figure 38(B) is a top view of the present invention. This describes a pixel circuit that can be used when applying liquid crystal elements to the pixels of a display device in one embodiment. This is a circuit diagram for doing so. Also, Figure 38(C) shows the pixels of a display device according to one embodiment of the present invention. This is a circuit diagram illustrating a pixel circuit that can be used when applying an EL element. .

[0473] The transistors placed in the pixel area can be formed according to the previously described embodiment. Since the transistor can easily be made into an n-channel type, the n-channel transistor is used in the drive circuit. A portion of the drive circuit, which can be constructed using a single-type transistor, is identical to the transistors in the pixel section. It is formed on a substrate. In this way, the pixel portion and the driving circuit are formed with the transistors shown in the above embodiment. By using this, a highly reliable display device can be provided.

[0474] Figure 38(A) shows an example of a top view of an active-matrix display device. The circuit board of the display device. On 700 are a pixel section 701, a first scan line drive circuit 702, and a second scan line drive circuit 70 3. It has a signal line driving circuit 704. Multiple signal lines are connected to the signal line driving circuit in the pixel section 701. Extending from 704, multiple scan lines are arranged to drive the first scan line drive circuit 702 and the second It is arranged as an extension from the scan line drive circuit 703. Note the intersection region of the scan line and signal line. Each of these has pixels, each having a display element, arranged in a matrix. The board 700 is a connection part for FPC (Flexible Printed Circuit), etc. It is connected to the timing control circuit (also called a controller or control IC) via this.

[0475] Figure 38(A) shows the first scan line drive circuit 702, the second scan line drive circuit 703, and the signal line The drive circuit 704 is formed on the same substrate 700 as the pixel unit 701. Therefore, it is not externally installed. Since the number of components such as drive circuits is reduced, costs can be reduced. Also, the circuit board 7 If the drive circuit is located outside of 00, it becomes necessary to extend the wiring, increasing the number of connections between wires. It is possible to reduce the number of connections between the wiring when the drive circuit is placed on the same circuit board 700. This can improve reliability or yield. Circuit 702, the second scan line drive circuit 703, or the signal line drive circuit 704 are located on board 70 The configuration may be implemented on 0 or provided outside the circuit board 700.

[0476] <Liquid crystal display device> Furthermore, an example of the pixel circuit configuration is shown in Figure 38(B). Here, as an example, a VA-type liquid crystal display... This shows a pixel circuit that can be applied to the pixels of a display device.

[0477] This pixel circuit can be applied to configurations in which a single pixel has multiple pixel electrode layers. The pixel electrode layer is connected to different transistors, and each transistor is driven by a different gate signal. It is configured to allow this to happen. This allows for the individual pixels of a multi-domain designed pixel to be... The signals applied to the electrode layer can be controlled independently.

[0478] The scan line 712 of transistor 716 and the scan line 713 of transistor 717 are different. It is separated so that a gate signal can be applied. On the other hand, signal line 714 is a transistor It is used in common with the transistor 716 and the transistor 717. The transistor 717 can be any transistor as described in the previous embodiment. This makes it possible to provide a highly reliable liquid crystal display device.

[0479] Furthermore, the first pixel electrode layer is electrically connected to transistor 716, and transistor 7 17 is electrically connected to the second pixel electrode layer. The layers are separated from each other. Note the shape of the first pixel electrode layer and the second pixel electrode layer. There are no particular limitations. For example, the first pixel electrode layer can be V-shaped.

[0480] The gate electrode of transistor 716 is connected to scan line 712, and the gate electrode of transistor 717 The gate electrode is connected to scan line 713. Different gate signals are connected to scan line 712 and scan line 713. By assigning different numbers, the operating timings of transistors 716 and 717 are made different, and the liquid crystal The orientation can be controlled.

[0481] Furthermore, the capacitive wiring 710, the gate insulating layer which functions as a dielectric, and the first pixel electrode layer A retention capacitance may be formed by a capacitive electrode electrically connected to a second pixel electrode layer.

[0482] In a multi-domain design, each pixel is equipped with a first liquid crystal element 718 and a second liquid crystal element 719. The first liquid crystal element 718 is composed of a first pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. The second liquid crystal element 719 is composed of a second pixel electrode layer, a counter electrode layer, and a liquid crystal layer between them. It can be done.

[0483] Note that the pixel circuit shown in Figure 38(B) is not limited to this. For example, as shown in Figure 38(B) The pixel circuit now includes switches, resistors, capacitives, transistors, sensors, or logic You may add circuits or other components.

[0484] Figures 39(A) and 39(B) are examples of a top view and a cross-sectional view of a liquid crystal display device. Note that in Figure 39(A), the display device 20, display area 21, peripheral circuit 22, and FPC( A typical configuration having a flexible printed circuit board (42) is shown in Figure 39. The display device uses reflective liquid crystal elements.

[0485] Figure 39(B) shows the dashed lines A-A', B-B', C-C', and DD in Figure 39(A). The cross-sectional view between A and A' shows the peripheral circuitry, and between B and B' shows the display area. The sections between -C' and D-D' indicate connections to the FPC.

[0486] The display device 20 using liquid crystal elements includes transistors 50 and 52 (in its embodied form). In addition to the transistor 10) shown in state 1, there are conductive layer 165, conductive layer 197, insulating layer 420, liquid Crystalline layer 490, liquid crystal element 80, capacitive element 60, capacitive element 62, insulating layer 430, spacer 44 0, colored layer 460, adhesive layer 470, conductive layer 480, light shielding layer 418, substrate 400, adhesive layer 4 73, adhesive layer 474, adhesive layer 475, adhesive layer 476, polarizing plate 103, polarizing plate 403, protection The device comprises a substrate 105, a protective substrate 402, and an anisotropic conductive layer 510.

[0487] <Organic EL display device> Another example of a pixel circuit configuration is shown in Figure 38(C). Here, a display using an organic EL element is shown. The pixel structure of the device is shown.

[0488] Organic EL elements emit electrons from one of a pair of electrodes when a voltage is applied to the light-emitting element. On the other hand, holes are injected into layers containing luminescent organic compounds, and an electric current flows. Through the recombination of electrons and holes, the luminescent organic compound forms an excited state, It emits light when the excited state returns to the ground state. This mechanism explains why such light emission occurs. The device is called a current-excited light-emitting element.

[0489] Figure 38(C) shows an example of an applicable pixel circuit. Here, an n-channel type An example is shown where two transistors are used for one pixel. Furthermore, this pixel circuit is a digital time scale. A controlled drive can be applied.

[0490] Applicable pixel circuit configurations and pixel operation when digital time-gradation driving is applied. I will explain.

[0491] Pixel 720 consists of a switching transistor 721, a driving transistor 722, and a light-emitting element. It has a sub-element 724 and a capacitive element 723. The switching transistor 721 is a The source electrode layer is connected to scan line 726, and the first electrode (source electrode layer and drain electrode layer) One side is connected to signal line 725, and the second electrode (the other side of the source electrode layer and drain electrode layer) is connected to signal line 725. ) is connected to the gate electrode layer of the drive transistor 722. In 22, the gate electrode layer is connected to the power line 727 via the capacitive element 723, and the first electrode is electrically... The power line 727 is connected, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 724. The second electrode of the light-emitting element 724 corresponds to the common electrode 728. The common electrode 728 is identical. It is electrically connected to a common potential line formed on the substrate.

[0492] The switching transistor 721 and the driving transistor 722 are as described above. The transistors described below can be used as appropriate. This allows for highly reliable organic LEDs. A display device can be provided.

[0493] The potential of the second electrode (common electrode 728) of the light-emitting element 724 is set to the low power supply potential. The power supply potential is a potential lower than the high power supply potential supplied to power line 727, for example, GND. The forward threshold of the light-emitting element 724 The high and low power supply potentials are set so that they are equal to or greater than the value voltage, and the potential difference between them is used to power the light-emitting element 724 By applying a current to the light-emitting element 724, an electric current is passed through it, causing it to emit light. The forward voltage in 4 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is... Includes high-value voltage.

[0494] Furthermore, the capacitive element 723 is replaced by the gate capacitance of the drive transistor 722, thus saving space. It can be abbreviated.

[0495] Next, we will explain the signal input to the drive transistor 722. Voltage input Voltage drive method In this case, the driving transistor 722 is either fully on or completely off. A video signal like this is input to the drive transistor 722. To operate the 722 in the linear region, a voltage higher than the voltage of the power line 727 is used for the drive. It is applied to the gate electrode layer of transistor 722. Additionally, the signal line 725 is driven by the power line voltage. Apply a voltage greater than or equal to the threshold voltage Vth of transistor 722.

[0496] When performing analog grayscale driving, the gate electrode layer of the driving transistor 722 has an emissive element 72 A voltage greater than or equal to the sum of the forward voltage of transistor 4 and the threshold voltage Vth of the drive transistor 722. Apply the signal. Also, input the video signal so that the drive transistor 722 operates in the saturation region. This forces current to flow through the light-emitting element 724. Furthermore, the drive transistor 722 is operated in the saturation region. To achieve this, the potential of the power line 727 is set higher than the gate potential of the drive transistor 722. By converting the video signal to analog, the light-emitting element 724 receives a current corresponding to the video signal. It can perform flow and analog gradation driving.

[0497] Note that the pixel circuit configuration is not limited to the pixel configuration shown in Figure 38(C). For example, Figure 38 (C) The pixel circuit shown contains switches, resistors, capacitives, sensors, transistors or You can add circuits and other components.

[0498] When applying the transistor exemplified in the above embodiment to the circuit exemplified in Figure 38, the low potential The source electrode (first electrode) is on the side with the high potential, and the drain electrode (second electrode) is on the high potential side with the electrical currents. The configuration is designed to connect them precisely. Furthermore, the potential of the first gate electrode is controlled by a control circuit, etc. The second gate electrode is connected to a potential lower than the potential applied to the source electrode by wiring (not shown). The system should be configured to accept the potentials exemplified above, such as by applying them.

[0499] Figures 40(A) and 40(B) show a top view and a cross-sectional view of a display device using a light-emitting element. This is just one example. Note that in Figure 40(A), the display device 24, display area 21, peripheral circuit 22, and A typical configuration having an FPC (flexible printed circuit board) 42 is shown in the diagram.

[0500] Figure 40(B) shows cross-sectional views of the dashed lines A-A', B-B', and C-C' in Figure 40(A). The section between A and A' indicates the peripheral circuitry, the section between B and B' indicates the display area, and the section between C and C' indicates the FPC and This shows the connection point.

[0501] The display device 24 using a light-emitting element includes transistors 50 and 52 (in its embodiment) In addition to the transistor 10) shown in state 1, there is an insulating layer 420, a conductive layer 197, a conductive layer 410, and light Chemical adjustment layer 530, EL layer 450, conductive layer 415, light-emitting element 70, capacitive element 60, capacitive element 62, insulating layer 430, spacer 440, coloring layer 460, adhesive layer 470, partition wall 445, light shielding It has a layer 418, a substrate 400, and an anisotropic conductive layer 510.

[0502] In this specification, for example, a display element, a display device having a display element, and a light-emitting element. A light-emitting device, which is a device having a sub-element and a light-emitting element, can be used in various forms or It can have various elements. Display elements, display devices, light-emitting elements, or light-emitting devices are, for example, EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs) Examples include quantum dots, transistors (transistors that emit light in response to electric current), and electron-emitting elements. Children, liquid crystal elements, electronic ink, electrophoretic elements, grating light bulbs (GLV), RASMA display panels (PDPs), MEMS (Micro-Electro-Mechanical Systems) Systems), Digital Micromirror Devices (DMDs), DMS (Digital Micro • Shutter), MIRASOL (registered trademark), IMOD (interferometric) Modulation elements, electrowetting elements, piezoelectric ceramic displays These include at least one of the following: a display element using carbon nanotubes. In addition, electrical or magnetic effects can alter contrast, brightness, reflectivity, transmittance, etc. It may have a display medium that converts light. An example of a display device using an EL element is an EL display. Examples include displays. One example of a display device using electron emission elements is a field emitter. Surface-type display (FED) or SED flat-panel display (SED: Surf face-conduction electron-emitter display Examples include ) and others. An example of a display device using liquid crystal elements is a liquid crystal display (transmissive liquid crystal display). Crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays Examples include sprays and projection liquid crystal displays. They use electronic ink or electrophoretic elements. One example of such a display device is electronic paper.

[0503] This embodiment can be appropriately combined with other embodiments shown herein. .

[0504] (Embodiment 8) In this embodiment, a display module to which a semiconductor device according to one aspect of the present invention is applied is shown in Figure We will use 41 to explain.

[0505] <Display Module> The display module 6000 shown in Figure 41 consists of an upper cover 6001 and a lower cover 6002. In between, touch panel 6004 connected to FPC6003, and FPC6005 connected Display panel 6006, backlight unit 6007, frame 6009, printed circuit board It has 6010 and battery 6011. Furthermore, it has a backlight unit 6007 and battery Features such as the Lee 6011 and Touch Panel 6004 may not be available.

[0506] One embodiment of the present invention is, for example, a display panel 6006 or a printed circuit board. It can be used in integrated circuits that are implemented in [the device].

[0507] The upper cover 6001 and the lower cover 6002 are the touch panel 6004 and the display panel. The shape and dimensions can be appropriately modified to match the size of the 6006.

[0508] The touch panel 6004 is a resistive or capacitive touch panel. It can be used superimposed on 006. Also, the opposing substrate (encapsulation substrate) of the display panel 6006. It is also possible to give the display panel 6 a touch panel function. It is also possible to add an optical touch panel function by providing a light sensor within each pixel of 006. Yes. Alternatively, an electrode for a touch sensor can be provided within each pixel of the display panel 6006, and a capacitive method can be used. It is also possible to add a touch panel function to the model.

[0509] The backlight unit 6007 has a light source 6008. The light source 6008 is used as a backlight. A configuration using a light-diffusing plate, provided at the end of unit 6007, is also possible.

[0510] Frame 6009 provides protection for the display panel 6006, as well as generating signals from the printed circuit board 6010. It functions as an electromagnetic shield to block the generated electromagnetic waves. Also, the frame 600 9 may also function as a heat sink.

[0511] Printed circuit board 6010 is a power supply circuit and a signal for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. This is also fine, or a separate battery 6011 may be used. Battery 6011 can be omitted.

[0512] Furthermore, the display module 6000 includes additional components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided.

[0513] This embodiment can be appropriately combined with other embodiments shown herein. .

[0514] (Embodiment 9) This embodiment describes an example of the use of a semiconductor device according to one aspect of the present invention.

[0515] <Package using a lead frame type interposer> Figure 42(A) shows the cross-sectional structure of a package using a lead frame type interposer. A perspective view is shown. The package shown in Figure 42(A) is a semiconductor device according to one aspect of the present invention. The corresponding chip 1751 is bonded to the interposer 1750 by wire bonding. It is connected to terminal 1752. Terminal 1752 is connected to chip 17 of interposer 1750. 51 is positioned on the surface on which it is mounted. And tip 1751 is molded resin It may be sealed by 1753, but with a portion of each terminal 1752 exposed during sealing. Make it happen.

[0516] The configuration of an electronic device (mobile phone) module with a package mounted on a circuit board is shown in the diagram. This is shown in Figure 42(B). The mobile phone module shown in Figure 42(B) is a printed circuit board 18 Unit 01 contains package 1802 and battery 1804. Also, the display element A printed circuit board 1801 is mounted on panel 1800, which is provided with a child, by FPC1803. It is implemented.

[0517] This embodiment can be appropriately combined with other embodiments shown herein. .

[0518] (Embodiment 10) In this embodiment, an electronic device and a lighting device according to one aspect of the present invention will be described with reference to the drawings. do.

[0519] <Electronic equipment> Electronic devices and lighting devices can be manufactured using a semiconductor device according to one embodiment of the present invention. Using a semiconductor device of one embodiment, highly reliable electronic devices and lighting devices can be manufactured. Electronic devices and lighting with improved touch sensor detection sensitivity using a semiconductor device according to one aspect of the invention We can manufacture the device.

[0520] Examples of electronic devices include television equipment (also known as televisions or television receivers). (u) Monitors for computers, digital cameras, digital video cameras, digital Photo frames, mobile phones (also called mobile phones or mobile phone devices), portable game consoles, portable Examples include mobile information terminals, sound playback devices, and large game machines such as pachinko machines.

[0521] Furthermore, if an electronic device or lighting device according to one aspect of the present invention is flexible, it can be used on the interior walls of houses and buildings. Alternatively, it can be incorporated along the curved surfaces of exterior walls, or the interior or exterior of automobiles. ru.

[0522] Furthermore, an electronic device according to one aspect of the present invention may have a secondary battery and use contactless power transmission. It would be preferable if it could also charge a secondary battery.

[0523] Examples of secondary batteries include lithium polymer batteries (lithium iodine) which use a gel electrolyte. Lithium-ion secondary batteries (such as polymer batteries), lithium-ion batteries, nickel-metal hydride batteries Nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air-based rechargeable batteries, nickel-zinc batteries, silver-zinc batteries Examples include batteries.

[0524] An electronic device according to one aspect of the present invention may have an antenna. The antenna receives a signal. This allows the display unit to show images, information, etc. Also, electronic devices can use secondary batteries. If available, the antenna may be used for contactless power transmission.

[0525] Figure 43(A) shows a portable game console, comprising a casing 7101, casing 7102, display unit 7103, Display unit 7104, microphone 7105, speaker 7106, operation keys 7107, stylus It has 7108, etc. A semiconductor device according to one aspect of the present invention is built into a housing 7101 It can be used in integrated circuits, CPUs, etc. A normally-off type CPU is used for the CPU. This allows for lower power consumption, enabling you to enjoy games for longer periods than before. To do so, use a semiconductor device according to one aspect of the present invention in the display unit 7103 or the display unit 7104. This allows us to provide a portable game console that offers a superior user experience and is less prone to quality degradation. This is possible. Note that the portable game console shown in Figure 43(A) has two display units 7103 and Although it has a display unit 7104, the number of display units that a portable game console may have is not limited to this. I can't.

[0526] Figure 43(B) shows a smartwatch, consisting of a casing 7302, a display unit 7304, and operation buttons. It has 7311, 7312, connection terminal 7313, band 7321, clasp 7322, etc. A semiconductor device according to one aspect of the present invention includes a memory, CPU, etc., built into a housing 7302. It can be used for this purpose. Note that the display used in Figure 43(B) is a reflective liquid crystal panel. By using a normally-off type CPU, power consumption can be reduced. This reduces the number of times you need to charge your device on a daily basis.

[0527] Figure 43(C) shows a portable information terminal, which includes a display unit 7502 incorporated into the housing 7501, as well as Control buttons 7503, external connection port 7504, speaker 7505, microphone 7506 , and a display unit 7502, etc. A semiconductor device according to one aspect of the present invention is a housing 7501 It can be used for the mobile memory, CPU, etc. built into the device. By using an off-type CPU, the number of charging cycles can be reduced. Also, the display unit 7502 Because it can achieve extremely high resolution, it can display full HD and 4K even in a small to medium size. It can display various resolutions, such as 8K, and produce extremely sharp images. .

[0528] Figure 43(D) shows a video camera, consisting of a first housing 7701, a second housing 7702, and a display unit 77 03, it has an operation key 7704, a lens 7705, a connector 7706, etc. Operation key 770 4 and lens 7705 are provided in the first housing 7701, and the display unit 7703 is in the second housing It is located in body 7702. And the first housing 7701 and the second housing 7702 are connected. They are connected by part 7706, and the angle between the first housing 7701 and the second housing 7702 is, The connection part 7706 can be used to change the video displayed in the display unit 7703. A configuration that switches according to the angle between the first housing 7701 and the second housing 7702 in 6. It is permissible to do so. The position at the focal point of lens 7705 may be equipped with an imaging device according to one embodiment of the present invention. This is possible. A semiconductor device according to one aspect of the present invention is a cluster built into the first housing 7701 It can be used in integrated circuits, CPUs, and the like.

[0529] Figure 43(E) shows a digital signage display unit 7902 installed on a utility pole 7901. A semiconductor device according to one aspect of the present invention includes a display panel of the display unit 7902 and It can be used in the built-in control circuit.

[0530] Figure 44(A) shows a notebook personal computer, consisting of a casing 8121 and a display unit 8122 The present invention includes a keyboard 8123, a pointing device 8124, and the like. The semiconductor device in question is applicable to the CPU and memory built into the housing 8121. Yes, it is possible. Furthermore, the display unit 8122 can be made with very high resolution, and is suitable for medium-sized and compact devices. It can display 8K resolution while simultaneously producing extremely sharp images.

[0531] Figure 44(B) shows the exterior of the automobile 9700. Figure 44(C) shows the driver's seat of the automobile 9700. The car 9700 consists of a body 9701, wheels 9702, dashboard 9703, and lights. It has the T9704, etc. A semiconductor device according to one aspect of the present invention is a display unit of an automobile 9700, and It can be used in integrated circuits for control. For example, the display unit 9710 shown in Figure 44(C) Alternatively, a semiconductor device according to one aspect of the present invention can be provided in the display unit 9715.

[0532] Display units 9710 and 9711 are display devices installed on the windshield of an automobile, or is an input / output device. A display device or input / output device according to one aspect of the present invention is a display device, or Alternatively, by fabricating the electrodes of the input / output device from a light-transmitting conductive material, To create a display device or input / output device that is transparent, allowing the other side to be seen through, in other words, a see-through state. This is possible. If it is a see-through display device or input / output device, then the operation of the automobile 9700 It does not obstruct the view even when turning. Therefore, a display device or input / output display according to one aspect of the present invention The power device can be installed on the windshield of the automobile 9700. Furthermore, the display device, Alternatively, the input / output device may be equipped with a display device or a transistor for driving the input / output device. In such cases, organic transistors using organic semiconductor materials or transistors using oxide semiconductors are used. It is advisable to use a transmissive transistor, such as a light-transmitting transistor.

[0533] The display unit 9712 is a display device provided on the pillar portion. For example, a camera provided on the vehicle body By displaying the image from the imaging device on the display unit 9712, the field of view obstructed by the pillar is compensated for. It can be completed. The display unit 9713 is a display device provided on the dashboard. For example, by displaying images from an imaging device installed on the vehicle body on the display unit 9713, This allows you to compensate for the view obstructed by the dashboard. In other words, on the outside of the car By displaying images from the installed imaging device, blind spots are compensated for, and safety is enhanced. This is possible. Furthermore, by displaying images that fill in the gaps in the unseen areas, it becomes more natural and less jarring. Safety checks can be performed without any issues.

[0534] Furthermore, Figure 44(D) shows the interior of a car with bench seats for both the driver and passenger. The display unit 9721 is a display device or input / output device provided in the door section. By displaying the image from the imaging means installed on the vehicle body on the display unit 9721, It can compensate for the field of view obstructed by A. Also, the display unit 9722 is provided on the handle. This is a display device. The display unit 9723 is a display provided in the center of the seat surface of the bench seat. It is a device. Furthermore, the display device is installed on the seat or backrest, and the display device is... The heat generated by the display device can also be used as a seat heater.

[0535] Display unit 9714, display unit 9715, or display unit 9722 displays navigation information, speed The odometer, tachometer, mileage, fuel level, gear status, air conditioning settings, and other information are displayed. It can provide various kinds of information. Also, the display items and layout displayed on the display unit can be customized. These can be changed as needed to suit the user's preferences. Note that the above information is displayed on the display unit 9. It can also be displayed on display units 710 to 9713, display unit 9721, and display unit 9723. Furthermore, the display units 9710 to 9715 and 9721 to 9723 are illuminated. It can also be used as a device. In addition, display units 9710 to 9715, display unit Units 9721 through 9723 can also be used as heating devices.

[0536] Figure 45(A) also shows the external appearance of camera 8000. Camera 8000 is housed in housing 8001 , display unit 8002, operation button 8003, shutter button 8004, coupling unit 8005, etc. It has [a certain feature]. Furthermore, the camera 8000 can be fitted with a lens 8006.

[0537] The coupling portion 8005 has electrodes and, in addition to the viewfinder 8100 described later, also a strobe device, etc. It can be connected.

[0538] Here, we'll use camera 8000 and replace lens 8006 by removing it from housing 8001. Although this configuration allows for this, the lens 8006 and the housing 8001 may be integrated into a single unit.

[0539] By pressing the shutter button 8004, an image can be taken. Also, the display unit 80 Unit 02 functions as a touch panel, and by touching the display unit 8002, imaging is performed. It is also possible to do so.

[0540] A display device or input / output device according to one aspect of the present invention can be applied to the display unit 8002. ru.

[0541] Figure 45(B) shows an example of the camera 8000 with the viewfinder 8100 attached. It is.

[0542] The viewfinder 8100 includes a housing 8101, a display unit 8102, buttons 8103, etc.

[0543] The housing 8101 has a coupling portion that engages with the coupling portion 8005 of the camera 8000, The viewfinder 8100 can be attached to the camera 8000. Furthermore, the connection point is electrically powered. It has electrodes, and displays images and other data received from camera 8000 via these electrodes on display unit 8102. It can be made to happen.

[0544] Button 8103 functions as a power button. Button 8103 activates the display unit 8 You can switch the display of 102 on or off.

[0545] A semiconductor device according to one aspect of the present invention is applied to the integrated circuit and image sensor located inside the housing 8101. It can be used.

[0546] Note that in Figures 45(A) and 45(B), the camera 8000 and the viewfinder 8100 are connected to separate electronic devices. The container was designed to be detachable, but the housing 8001 of the camera 8000 is configured with the present invention. A viewfinder equipped with a display device or input / output device of one form may be incorporated.

[0547] Figure 45(C) also shows the external appearance of the head-mounted display 8200.

[0548] The head-mounted display 8200 consists of the mounting part 8201, the lens 8202, and the main body 820 3. It has a display unit 8204, a cable 8205, etc. Also, the mounting part 8201 has a battery It has a built-in Terry 8206.

[0549] Cable 8205 supplies power from battery 8206 to main unit 8203. Main unit 82 03 is equipped with a wireless receiver and displays video information such as received image data on the display unit 8204. It can also detect the movement of the user's eyeballs and eyelids using a camera located on the main unit 8203. By capturing the user's perspective and calculating the coordinates of their viewpoint based on that information, the user's viewpoint is determined. It can be used as an input method.

[0550] Furthermore, the attachment portion 8201 may be provided with multiple electrodes in positions that come into contact with the user. The main unit 8203 detects the current flowing through the electrodes in response to the user's eye movements, It may have a function of recognizing the user's perspective. Also, by detecting the current flowing through the electrode, it may have a function of monitoring the user's pulse. Further, the mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Also, it may detect the movement of the user's head or the like, and change the video displayed on the display portion 8204 according to the movement.

[0551] The semiconductor device according to an aspect of the present invention can be applied to an integrated circuit inside the main body 8203.

[0552] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0553] (Embodiment 11) In this embodiment, a usage example of an RF tag using the semiconductor device according to an aspect of the present invention will be described with reference to FIG. 46.

[0554] <Usage Example of RF Tag> The uses of RF tags are extensive. For example, banknotes, coins, securities, bearer bonds, certificates documents (such as driver's licenses and resident cards, see FIG. 46(A)), vehicles (such as bicycles, see FIG. 46(B) ), packaging containers (such as wrapping paper and bottles, see FIG. 46(C)), recording media (DVDs and video tapes, see FIG. 46(D)), personal items (such as bags and glasses), foods, plants, animals , the human body, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (liquid crystal display devices ), EL display devices, television devices, or mobile phones) and other articles, or attached to each article It can be attached to luggage tags (see Figures 46(E) and 46(F)) and used in this way.

[0555] An RF tag 4000 according to one aspect of the present invention can be attached to or embedded in the surface of an object. It is fixed to the product. For example, in the case of a book, it is embedded in the paper, and in the case of a package made of organic resin. The RF tag is embedded inside the organic resin and fixed to each article. The 4000 is designed to be small, thin, and lightweight, and even after being fixed to an object, it does not affect the design of the object itself. It does not impair the integrity of banknotes, coins, securities, bearer bonds, or certificates. By providing an RF tag 4000 according to one aspect of the present invention to the same type of object, an authentication function can be provided. This allows for counterfeiting to be prevented by utilizing this authentication function. Furthermore, packaging containers... The present invention applies to items such as recording media, personal belongings, food products, clothing, household goods, or electronic devices. By attaching RF tags related to the configuration, the efficiency of systems such as inspection systems can be improved. It is possible to attach an RF tag according to one aspect of the present invention to vehicles as well. This enhances security against theft and other crimes.

[0556] As described above, an RF tag using a semiconductor device according to one aspect of the present invention is provided in this embodiment. By using it for each of the listed applications, the operating power, including information writing and reading, can be reduced. Therefore, it becomes possible to extend the maximum communication range. Also, even when the power is cut off Because it can retain information for extremely long periods, it is also suitable for applications where the frequency of writing and reading is low. It can be used suitably.

[0557] This embodiment can be appropriately combined with other embodiments shown herein. . [Explanation of symbols]

[0558] 10 transistors 11 transistors 12 transistors 13 transistors 20 Display device 21 Display area 22 Peripheral Circuits 24 Display device 50 transistors 52 transistors 60 Capacitive elements 62 Capacitive elements 70 light-emitting elements 80 liquid crystal elements 100 circuit boards 103 Polarizing plate 105 Protective substrate 110 Insulating layer 121 Oxide insulating layer 122 Oxide semiconductor layer 123 Oxide insulating layer 125 Low resistance region 127 Low resistance region 150 Gate Insulation Layer 150a insulating film 160 Grid Unit Layer 160a conductive film 165 Conductive layer 167 Aeon 168 Conductive film 169 Aeon 170 Insulating layer 172 Insulating layer 173 Oxygen 176 Sidewall insulation layer 180 Insulating layer 190 conductive layer 195 Conductive layer 197 Conductive layer 200 Imaging device 201 Switch 202 Switch 203 Switch 210 pixel section 211 pixels 212 subpixels 212B subpixels...

Claims

1. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided, having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor. A first insulating layer is provided, having a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region for the second transistor is provided, A second conductive layer is provided, which functions as one electrode of the capacitive element. A third conductive layer is provided, having a region located above the second conductive layer and functioning as the other electrode of the capacitive element. A fourth conductive layer is provided, having a region located below the oxide semiconductor layer and having a region that functions as the first gate electrode of the second transistor. A fifth conductive layer is provided, having a region located above the oxide semiconductor layer and having a region that functions as the second gate electrode of the second transistor. A second insulating layer is provided, having a region in contact with the fifth conductive layer. The second conductive layer is located above the channel formation region of the first transistor and has a region that overlaps with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that overlaps with the channel formation region of the first transistor and a region that overlaps with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region that overlaps with the oxide semiconductor layer and a region that overlaps with the third conductive layer, and does not overlap with the first conductive layer. The second opening has a region that overlaps with the third conductive layer and does not overlap with the oxide semiconductor layer. The semiconductor device wherein the fourth conductive layer has a region located above the first insulating layer.

2. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided, having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor. A first insulating layer is provided, having a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region for the second transistor is provided, A second conductive layer is provided, which functions as one electrode of the capacitive element. A third conductive layer is provided, having a region located above the second conductive layer and functioning as the other electrode of the capacitive element. A fourth conductive layer is provided, having a region located below the oxide semiconductor layer and having a region that functions as the first gate electrode of the second transistor. A fifth conductive layer is provided, having a region located above the oxide semiconductor layer and having a region that functions as the second gate electrode of the second transistor. A second insulating layer is provided, having a region in contact with the fifth conductive layer. The second conductive layer is located above the channel formation region of the first transistor and has a region that overlaps with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that overlaps with the channel formation region of the first transistor and a region that overlaps with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region that overlaps with the oxide semiconductor layer and a region that overlaps with the third conductive layer, and does not overlap with the first conductive layer. The second opening has a region that overlaps with the third conductive layer and does not overlap with the oxide semiconductor layer. The fourth conductive layer has a region located above the first insulating layer, In a cross-sectional view of the second transistor in the channel width direction, a portion of the lower surface of the fifth conductive layer is located below the lower surface of the oxide semiconductor layer in the semiconductor device.

3. A first transistor having silicon in the channel formation region, A second transistor having an oxide semiconductor in the channel formation region, It has a capacitive element, The gate of the first transistor, one of the source and drain of the second transistor, and one electrode of the capacitive element are electrically connected. A first conductive layer is provided, having a region located above the channel formation region of the first transistor and functioning as the gate electrode of the first transistor. A first insulating layer is provided, having a region located above the first conductive layer and a region located below the channel formation region of the second transistor. An oxide semiconductor layer having a channel formation region for the second transistor is provided, A second conductive layer is provided, which functions as one electrode of the capacitive element. A third conductive layer is provided, having a region located above the second conductive layer and functioning as the other electrode of the capacitive element. A fourth conductive layer is provided, having a region located below the oxide semiconductor layer and having a region that functions as the first gate electrode of the second transistor. A fifth conductive layer is provided, having a region located above the oxide semiconductor layer and having a region that functions as the second gate electrode of the second transistor. A second insulating layer is provided, having a region in contact with the fifth conductive layer. The second conductive layer is located above the channel formation region of the first transistor and has a region that overlaps with the channel formation region of the first transistor. The second conductive layer is located above the oxide semiconductor layer and has a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that overlaps with the channel formation region of the first transistor and a region that overlaps with the channel formation region of the second transistor. The second insulating layer has a first opening and a second opening, The second conductive layer is electrically connected to the oxide semiconductor layer through the first opening. The second conductive layer is electrically connected to the first conductive layer through the second opening. The first opening has a region that overlaps with the oxide semiconductor layer and a region that overlaps with the third conductive layer, and does not overlap with the first conductive layer. The second opening has a region that overlaps with the third conductive layer and does not overlap with the oxide semiconductor layer. The fourth conductive layer has a region located above the first insulating layer, In a cross-sectional view of the second transistor in the channel width direction, a portion of the lower surface of the fifth conductive layer is located below the lower surface of the oxide semiconductor layer. A semiconductor device having a channel length direction of the first transistor that is aligned with the channel length direction of the second transistor.

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