Control and calibration of external oscillators

Abstract

To provide an apparatus and a method for external oscillator control and calibration.SOLUTION: In a particular embodiment, an electronic oscillator system includes a semiconductor die and a controllable oscillator external to the semiconductor die. The oscillation frequency of the controllable oscillator is adjusted by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] Embodiments of the invention relate to electronic systems, and more specifically, to the control and calibration of external oscillators. [Background technology]

[0002] Voltage-controlled oscillators (VCOs) are widely used in electronic and telecommunications applications such as clock generation and distribution, carrier synthesis, and data recovery. A VCO may include an oscillator core that generates an oscillating output signal, and a resonator (e.g., an inductor-capacitor tank) attached to the oscillator core that exhibits variable electrical properties such as capacitance and / or inductance. The oscillation frequency depends at least in part on the value of the variable electrical property, and therefore, tuning the resonator provides a method for controlling the oscillation frequency of the output signal.

[0003] A VCO can be included in a control loop such as a phase-locked loop (PLL). Such a control loop can use feedback to set the VCO's input control voltage to a desired value. [Overview of the project]

[0004] Apparatus and methods for controlling and calibrating an external oscillator are provided. In a particular embodiment, the electronic oscillator system includes a semiconductor die and a controllable oscillator located outside the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

[0005] In one embodiment, the electronic oscillator system includes a semiconductor die, a controllable oscillator located outside the semiconductor die, a first varactor configured to adjust the oscillation frequency of the controllable oscillator, and a second varactor configured to adjust the oscillation frequency of the controllable oscillator. The semiconductor die includes a phase-locked loop (PLL) configured to provide fine adjustment to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide coarse adjustment to the controllable oscillator by controlling the second varactor.

[0006] In another embodiment, a method for controlling an electronic oscillator is provided. The method includes adjusting the oscillation frequency of a controllable oscillator using a first varactor, the controllable oscillator being located outside a semiconductor die. The method further includes adjusting the oscillation frequency of a controllable oscillator using a second varactor, controlling the first varactor to provide fine adjustment to the controllable oscillator using a phase-locked loop (PLL) on a semiconductor die, and controlling the second varactor to provide coarse adjustment to the controllable oscillator using a calibration circuit on a semiconductor die.

[0007] In another embodiment, a radio frequency communication system is provided. The radio frequency communication system includes a mixer controlled by an oscillator signal, and a local oscillator which includes a semiconductor die, a controllable oscillator located outside the semiconductor die and configured to output an oscillator signal, a first varactor configured to adjust the oscillation frequency of the controllable oscillator, and a second varactor configured to adjust the oscillation frequency of the controllable oscillator. The semiconductor die includes a phase-locked loop (PLL) configured to provide fine adjustment to the controllable oscillator by controlling the first varactor, and a calibration circuit configured to provide coarse adjustment to the controllable oscillator by controlling the second varactor. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram of one embodiment of a radio frequency (RF) communication system. [Figure 2A] This is a schematic diagram of one embodiment of tuning an externally voltage controllable oscillator (VCO). [Figure 2B] This is a schematic diagram of another example of tuning an external VCO. [Figure 3A] This is a schematic diagram of an electronic oscillator system according to one embodiment. [Figure 3B] This is a schematic diagram of an electronic oscillator system according to another embodiment. [Figure 4] This is a schematic diagram of an external VCO tracking loop according to one embodiment. [Figure 5A] This is a schematic diagram of an external VCO tracking loop according to another embodiment. [Figure 5B] This is a schematic diagram of an external VCO tracking loop according to another embodiment. [Figure 6] This is a schematic diagram of an electronic oscillator system according to another embodiment. [Figure 7] This is a schematic diagram of another embodiment of an electronic oscillator system including a semiconductor die operating in a first coarse calibration mode. [Figure 8] This is a schematic diagram of another embodiment of an electronic oscillator system including a semiconductor die operating in a second coarse calibration mode. [Modes for carrying out the invention]

[0009] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be embodied in numerous different ways. Drawings are referenced in this description, where similar reference numerals may indicate identical or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that a particular embodiment may include more elements and / or subsets of elements shown in the drawings than those shown. Moreover, some embodiments may incorporate any preferred combination of features from two or more drawings.

[0010] Control and calibration of an externally controllable oscillator are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator (e.g., a VCO) located outside the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

[0011] Therefore, the controllable oscillator can be controlled using a first loop with low gain and a second loop with higher gain than the first. This, in turn, enables the implementation of a PLL on a semiconductor die while operating within the supply voltage limitations associated with typical semiconductor die manufacturing processes, with low noise and a wide adjustment range.

[0012] The teachings herein are applicable to a wide range of electronic systems and applications. For example, transceivers such as land vehicle radio transceivers can use an external VCO as the local oscillator (LO).

[0013] Figure 1 is a schematic diagram of one embodiment of an RF communication system 30. The RF communication system 30 includes a transceiver 1, a front-end system 2, and an antenna 3. The transceiver 1 in Figure 1 may include one or more local oscillators (LOs) implemented using adjustment and calibration loops as taught herein. However, the teaching herein is applicable to other configurations of electronic circuits.

[0014] In the embodiment shown, the transceiver 1 includes a transmitter 5 and a receiver 6. Although not shown in Figure 1, the transceiver 1 may also include other circuits, such as an observation receiver, a control circuit, and / or additional transmitters and / or receivers.

[0015] Figure 1 shows transceiver 1 as including one transmitter and one receiver, but the transceiver may include additional transmitters, receivers, and / or observation receivers.

[0016] In the shown embodiment, the transmitter 5 includes an I-pass DAC 11a, an I-pass amplifier 12a, an I-pass mixer 13a, a Q-pass DAC 11b, a Q-pass amplifier 12b, a Q-pass mixer 13b, and a transmit local oscillator (LO) 14. Although one embodiment of the transmitter circuitry is shown, the transmitter can be implemented in other ways.

[0017] Regarding signal transmission, the I-path DAC 11a converts the digital I signal to an analog I signal, and the analog I signal is amplified by the I-path amplifier 12a. In addition, the Q-path DAC 11b converts the digital Q signal to an analog Q signal, and the analog Q signal is amplified by the Q-path amplifier 12b. The transmit LO 14 provides the I-path clock signal to the I-path mixer 13a, which upconverts the amplified analog I signal. The transmit LO 14 further provides the Q-path clock signal to the Q-path mixer 13b, which upconverts the amplified analog Q signal. The outputs of the I-path mixer 13a and the Q-path mixer 13b are combined to generate the RF transmit signal TX provided to the front-end system 2.

[0018] Continuing to refer to Figure 1, the receiver 6 includes an I-pass ADC 21a, an I-pass amplifier 22a, an I-pass mixer 23a, a Q-pass ADC 21b, a Q-pass amplifier 22b, a Q-pass mixer 23b, and a receiver LO 24. Although one embodiment of the receiver circuit is shown, the receiver can be implemented in other ways.

[0019] Regarding signal reception, receiver 6 receives the RF received signal RX from the front-end system 2. Receiver LO 24 provides an I-pass clock signal to the I-pass mixer 23a and a Q-pass clock signal to the Q-pass mixer 23b. The I-pass mixer 23a uses the I-pass clock signal to downconvert the RF received signal RX to generate an analog I signal. The analog I signal is amplified by the I-pass amplifier 22a and digitized by the I-pass ADC 21a to generate a digital I signal. The Q-pass mixer 23b uses the Q-pass clock signal to downconvert the RF received signal RX to generate an analog Q signal. The analog Q signal is amplified by the Q-pass amplifier 22b and digitized by the Q-pass ADC 21b to generate a digital Q signal.

[0020] The transceiver 1 can be implemented according to any of the embodiments specified herein.

[0021] As shown in Figure 1, the front-end system 2 includes a power amplifier 27 that amplifies the RF transmit signal TX for transmission at antenna 3, and a low-noise amplifier 28 that generates the RF receive signal RX based on the amplification of the received signal from antenna 3. Although only the power amplifier 27 and the low-noise amplifier 28 are shown, the front-end system 2 may include other components, but is not limited to these, including filters, switches, duplexers, diplexers, couplers, and / or other components. Furthermore, the transmit channel and the receive channel do not need to share an antenna; rather, separate antennas can be used.

[0022] Transceiver 1 handles not only RF signals from 30MHz to 7GHz, but also the X band (approximately 7GHz to 12GHz) and K band. u Bandwidth (approx. 12GHz~18GHz), K band (approx. 18GHz~27GHz), K aIt is possible to handle signals of various frequencies, including higher frequency signals such as those in the V-band (approximately 27 GHz to 40 GHz), V-band (approximately 40 GHz to 75 GHz), and / or W-band (approximately 75 GHz to 110 GHz). Therefore, the teachings herein are applicable to a wide range of RF communication systems, including microwave systems.

[0023] Figure 2A is a schematic diagram of one embodiment of external VCO tuning. In this embodiment, the external VCO has a frequency-to-voltage gain (K) of 11 MHz / volt. VCO It is regulated using a single loop having ). When using a 9V adjustment range (0.5V to 9.5V), the external VCO has a frequency range of 100MHz to account for the desired adjustment range as well as process, voltage, and / or temperature (PVT) variations.

[0024] Figure 2B is a schematic diagram of another embodiment of external VCO tuning. In this embodiment, the external VCO is set to 1 MHz / volt K VCO1 A first loop for fine-tuning, and a K of 11MHz / volt VCO2 It is adjusted using a second loop for coarse adjustment. The first loop operates within a relatively small voltage adjustment range of 1V, allowing it to be mounted on a semiconductor die while operating within the typical supply voltage limitations associated with semiconductor die manufacturing processes. The first loop also has low gain, which is better for noise. The second loop operates within a wide voltage adjustment range of 9V (0.5V to 9.5V) and provides a wide frequency range of 100MHz to account for PVT.

[0025] K VCO Various examples of values, voltage ranges, and frequencies are shown in Figures 2A and 2B, but other values ​​are possible.

[0026] Figure 3A is a schematic diagram of an electronic oscillator system 50 according to one embodiment. The electronic oscillator system 50 includes a semiconductor die 41 and a controllable oscillator 42 located outside the semiconductor die 41. The electronic oscillator system 50 further includes a first varactor 43 controlled by a fine control signal FINE from the semiconductor die 41 and a second varactor 44 controlled by a coarse control signal COARSE from the semiconductor die 41.

[0027] As shown in Figure 3A, the controllable oscillator 42 outputs an oscillation signal OSC having an oscillation frequency controlled by a fine control signal FINE and a coarse control signal COARSE.

[0028] Therefore, the oscillation frequency of the controllable oscillator 42 is adjusted by the first varactor 43 and the second varactor 44.

[0029] Continuing to refer to Figure 3A, the semiconductor die 41 includes a phase-locked loop (PLL) 45 that provides fine adjustment to the controllable oscillator 42 by controlling a fine control signal FINE provided to a first varactor 43. In addition, the semiconductor die 41 further includes a calibration circuit 46 that provides coarse adjustment to the controllable oscillator 42 by controlling a coarse control signal COARSE provided to a second varactor 44. The oscillator signal OSC is provided to the semiconductor die 41 to provide feedback for adjusting the fine control signal FINE and the coarse control signal COARSE.

[0030] By implementing the electronic oscillator system 50 in this manner, the controllable oscillator 42 can be controlled using a first loop with low gain (LOW GAIN loop) and a second loop with higher gain (HIGH GAIN loop). This, in turn, enables the implementation of the PLL 45 on the semiconductor die 41 while operating with low noise, a wide adjustment range, and within the supply voltage limitations associated with typical semiconductor die manufacturing processes.

[0031] FIG. 3B is a schematic diagram of an electronic oscillator system 130 according to another embodiment. The electronic oscillator system 130 includes a semiconductor die 101 and various components external to the semiconductor die 101 on a circuit board.

[0032] In the illustrated embodiment, the external components include an external VCO 102, a first varactor 103, a second varactor 104, a first amplifier 105, a second amplifier 106, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a VCO bias inductor 110, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor bias inductor 112a, a second varactor bias inductor 112b, a coarse tuning resistor bypass switch 113a, a bias resistor bypass switch 113b, a coarse tuning resistor 114a, a bias resistor 114b, a first voltage divider resistor 115a / 115b, a second voltage divider resistor 116a / 116b, a first amplifier input resistor 117a, a second amplifier input resistor 117b, a bias capacitor 118, a fine tuning capacitor 119a, a sense capacitor 119b, and a coarse tuning capacitor 120.

[0033] The semiconductor die 101 of FIG. 3B includes a PLL 121, a coarse tuning and calibration circuit 122, an auxiliary analog-to-digital converter (ADC) 123, a PVT and coarse tuning digital-to-analog converter (DAC) 124, an amplitude DAC 125, and a switchable resistor network 126. The switchable resistor network 126 includes a fixed resistor 127, a switchable resistor 128, and a resistor bypass switch 129. The semiconductor die 101 also includes various pins or pads including a coarse tuning pin V coarse , a fine tuning pin V fine , a range sense pin V Z , a VCO sense pin V vco , and a VCO bias pin V bias .

[0034] The external VCO 102 is tuned by both the first varactor 103 and the second varactor 104. The first varactor 103 has a fine-tuning pin V set by a PLL 121 that can operate at low voltage (e.g., using a 1V charging pump 132). fine It is controlled by the voltage. As shown in Figure 3B, the PLL121 can be used to generate a feedback clock signal for the PLL detector, VCO sensing pin V vco The clock signal of the VCO above is received. For example, the PLL 121 may include a phase and / or frequency detector (PFD) 133 that compares the feedback clock signal with a reference clock signal, and the output of the PFD is used to control the PLL's charge pump 132.

[0035] The second varactor 104 is controlled by a coarse adjustment and calibration circuit 122 which may include an adjustment circuit 131 for PVT, temperature coefficient (TC), and / or amplitude control. The coarse adjustment and calibration circuit 122 provides a digital coarse control signal to the DAC 124, which controls the coarse adjustment pin V coarse It outputs current. Although shown as a single DAC124 for providing PVT and coarse adjustment, multiple DACs can be used.

[0036] Current flows from DAC124 through resistor 117a, generating a coarse adjustment voltage scaled by amplifier 105, which in turn generates a scaled coarse adjustment voltage that adjusts the second varactor 104. While this is one embodiment in which the coarse adjustment voltage is generated by the current flowing through the current DAC and the resistor, other implementations are possible, such as a configuration in which the voltage DAC generates the coarse adjustment voltage. The external amplifier 105 is V coarse The voltage is used to amplify the voltage to a suitable voltage level for varactor control, for example, up to about 20V. The external amplifier 105 is a varactor voltage source suitable for generating such a voltage level V VAR It is powered by [a specific component]. Noise from amplifier 105 is filtered by a low-frequency RC filter, which can be selectively bypassed (for example, during calibration).

[0037] In this embodiment, the coarse adjustment and calibration circuit 122 receives temperature information from the temperature sensor 107 via the ADC 123, as well as VCO sensing pin V vco From the VCO output clock signal, and the range sensing pin V Z Receive adjustment range information from [source].

[0038] In certain implementations, the coarse adjustment and calibration circuit 122 first controls the VCO bias pin V bias Using (and a bias supply voltage V to provide scaling) DDB VCO amplitude calibration is performed based on biasing the external VCO 102 (using a second amplifier 106 powered by the same device) and on observing the VCO output clock signal from the VCO sensing pin Vvco. After the initial amplitude calibration, the coarse adjustment and calibration circuit 122 can coarsely adjust the external VCO 102 using a second varactor 104.

[0039] During normal operation after amplitude calibration and coarse adjustment, the PLL 121 plays a role in providing fine adjustments to the external VCO 102 by controlling the first varactor 103. In addition, the coarse adjustment and calibration circuit 122 controls the range sensing pin V Z The adjustment voltage of the PLL121 can be monitored using this method, and coarse adjustment can be performed when the adjustment voltage exceeds the upper threshold or falls below the lower threshold. Thus, coarse adjustment can serve to maintain the adjustment voltage within the desired adjustment voltage range set by the upper and lower thresholds.

[0040] Although one embodiment involving VCO amplitude scaling has been described, such amplitude scaling can be omitted. For example, the amplitude DAC125 and the second amplifier106 do not need to be included to bring the external VCO102 to the desired target amplitude.

[0041] Figure 4 is a schematic diagram of an external VCO tracking loop 210 according to one embodiment. The external VCO tracking loop 210 includes a coarse control resistor 201 on a substrate, and a low-pass filter 202 and a control loop core 203 formed on a semiconductor die mounted on the substrate.

[0042] While specific components are shown as being located on a substrate or semiconductor die, other configurations are possible.

[0043] The control loop core 203 can be an analog loop or a digital loop. The control loop core 203 generates a range sensing signal V (generated by sensing the fine tuning voltage used to control the fine tuning varactor). z to signal V z The upper threshold (V tune_up ) and lower threshold (V tune_dn It monitors by comparing it with the signal V. The external VCO tracking loop 210 tracks the signal V. z The value of (therefore, the fine adjustment voltage V in Figure 3B) fine ) so that the signal V is held between two thresholds coarse Set the value of . In some implementations, the external VCO tracking loop uses temperature information 204(T BOARD ) can be received.

[0044] In the shown embodiment, the low-pass filter 202 receives the signal V z It is included to filter out the following. In this embodiment, the low-pass filter 202 includes a series resistor 207 and a shunt capacitor 208.

[0045] Figure 5A is a schematic diagram of an external VCO tracking loop 230 according to another embodiment. The external VCO tracking loop 230 includes a coarse control resistor 201 on a substrate, a low-pass filter 202 formed on a semiconductor die mounted on the board, a first comparator 211, a second comparator 212, a comparator processing circuit 213, an adder 219, and a PVT / TC DAC 220.

[0046] In this embodiment, analog hysteresis comparators 211 / 212 are used to measure the sensed voltage V (after low-pass filtering by low-pass filter 202). z upper threshold V tune_up and lower threshold V tune_dn This is compared with the following. In addition, the comparator output is processed by a comparator processing circuit 213 which includes an additive / subtractive counter 215, a flip-flop 216 (controlled by the clock signal CLK), an integrator 217, and a modulator 218. The output of the comparator processing circuit 213 is added in the digital domain to the PVT code 221 set by the PVT calibration loop, and then provided to the PVT / TC DAC 220.

[0047] Figure 5B is a schematic diagram of an external VCO tracking loop 240 according to another embodiment.

[0048] The external VCO tracking loop 240 in Figure 5B is similar to that of the external VCO tracking loop 230 in Figure 5A, except that separate DACs 231 are used for the PVT and TC. Therefore, the TC DAC 232 is included for temperature control, and the PVT DAC 233 is provided for PVT control, with the DAC outputs combined. Implementing the system in this way reduces the specifications for the DAC dynamic range.

[0049] Figure 6 is a schematic diagram of an electronic oscillator system 430 according to another embodiment. The electronic oscillator system 430 includes a semiconductor die 401 and various external components on a circuit board.

[0050] In the shown embodiment, the external component is (varactor supply voltage V CC_VCOThe system includes an external VCO 402 (powered by a VCO), a first varactor 103, a second varactor 104, a first amplifier 105, a second amplifier 106, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor bias inductor 112a, a second varactor bias inductor 112b, a coarse-adjusting resistor bypass switch 113a, a coarse-adjusting resistor 114a, a bias capacitor 118, a fine-adjusting capacitor 119a, a sensing capacitor 119b, a coarse-adjusting capacitor 120, a VCO clock buffer 403, and a coarse-adjusting voltage scaling circuit 404.

[0051] The semiconductor die 401 in Figure 6 includes a PLL 421, a coarse frequency adjustment and temperature compensation (TC) calibration circuit 422 (also called a coarse frequency adjustment and TC calibration loop), an auxiliary analog-to-digital converter (ADC) 123, a switchable resistor network 126, and an analog / digital interface 423. The switchable resistor network 126 includes a fixed resistor 127, a switchable resistor 128, and a resistor bypass switch 129. The semiconductor die 401 also includes a coarse adjustment pin V coarse , fine adjustment pin V fine Range sensing pin V Z , and also include various pins or pads, including the VCO sensing pin Vvco.

[0052] The external VCO402 is tuned by both a first varactor 103 (fine-tuning varactor) and a second varactor 104 (coarse-tuning varactor). The first varactor 103 is tuned by a fine-tuning pin V set by a PLL421 operated by a low-voltage (less than 1V in this embodiment) charge pump. fine It is controlled by the voltage. As shown in Figure 6, the PLL421 receives the VCO clock signal on the VCO sensing pin Vvco (through the clock driver 403 in this embodiment).

[0053] The second varactor 104 (coarse varactor) is controlled by the analog / digital interface 423 via the coarse voltage pin V coarseThe value is controlled by the coarse frequency adjustment and TC calibration loop 422. Coarse adjustment voltage pin V coarse The voltage level is increased by a coarse voltage scaling circuit 404 for setting the bias voltage of the second varactor 104 (coarse varactor). The coarse voltage scaling circuit 404 may include a level shifter, an amplifier, a charge pump, and / or other suitable circuits that play a role in increasing the bias voltage of the coarse varactor 104 from a low voltage domain associated with the semiconductor die 401 to a high voltage domain associated with the external VCO 402.

[0054] Figure 7 is a schematic diagram of another embodiment of the electronic oscillator system 460, which includes a semiconductor die 431 operating in a first coarse calibration mode.

[0055] The electronic oscillator system 460 includes a semiconductor die 431 and a circuit board including various external components for the semiconductor die 431. The external components include an external VCO 402 (powered in this embodiment by a 5V power supply), a first varactor 103, a second varactor 104, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor bias inductor 112a, a second varactor bias inductor 112b, a fine adjustment capacitor 119a, a sensing capacitor 119b, a VCO clock buffer 403, a first current mirror transistor 433, a second current mirror transistor 434, a current mirror load resistor 435 (coupled in this embodiment to a 20V power supply), a coarse adjustment bias resistor 436, a first current mirror load capacitor 437, a second current mirror load capacitor 438, and a first calibration switch S cal1 , Coarsely tuned integrated capacitor C i , and sensing resistor R z Includes.

[0056] The semiconductor die 431 in Figure 7 includes a PLL 451, a coarse frequency adjustment / switch control calibration circuit 452, an auxiliary ADC 123, and an auxiliary switch S aux Calibrated DAC453, Calibrated DAC reference current source Iref (In some implementations, to calibrate the DAC453, ref (Used in combination with) Calibration DAC reference current switch S ref , second calibration switch S cal2 , third calibration switch S cal3 Upward calibration switch S calup Downward calibration switch S caldn , current booster I up , current reduction source I dn , the first charging switch S chg1 , second charging switch S chg2 , third charging switch S chg3 , (S chg1 When it is closed 1 . Charging resistor R (connected between the 8V power supply and ground) chg , (reference voltage V ref (receives) First controllable transconductance circuit G m1 , and (reference voltage V ref (receives) Second controllable transconductance circuit G m2 The semiconductor die 431 also includes a coarse adjustment pin V coarse , fine adjustment pin V fine Range sensing pin V Z , coarsely adjusted integral pin V coarse_int VCO sensing pin V vco This also includes various pins or pads.

[0057] The external VCO 402 is tuned by both the first varactor 103 (fine-tuning varactor) and the second varactor 104 (coarse-tuning varactor). The first varactor 103 is tuned by the reference clock signal CLK. ref Fine-tuning pin V is set by the PLL451, which includes the PFD455 (which receives the feedback clock signal), the charging pump 456, and the feedback divider 457. fine It is controlled by the voltage.

[0058] The second varactor 104 (coarse-adjusting varactor) is controlled by the calibration DAC 453 and the coarse frequency adjustment / switch control calibration circuit 452, which controls the state of the indicated switches. The coarse frequency adjustment / switch control calibration circuit 452 receives the temperature signal D from the auxiliary ADC 123. temp Received and calibrated DAC code D cal Provides the calibration to DAC453.

[0059] The semiconductor die 431 has a coarse adjustment voltage pin V coarse It can operate in multiple modes to control the calibrated DAC453 and the transconductance circuit G. m1 and G m2 The first mode (DAC / G) is used for coarse calibration. m -C mode) and calibration charge pump (S calup , I up , I dn , and S caldn ) and the first transconductance circuit G m1 The second mode (charge pump / G) is used for coarse calibration. m -C mode) is included.

[0060] The electronic oscillator system can be implemented by selecting substrate components desired for a particular application, and the semiconductor die 431 operates in a first mode (DAC / G) based on the substrate components selected for that application. m -C mode) or second mode (charging pump / G m -C mode) can be used to provide coarse calibration. For example, the first mode (DAC / G m -C mode) can offer lower performance with lower board complexity, while the second mode (charge pump / G) m -C mode can offer higher performance at the expense of increased complexity of the board components.

[0061] The electronic oscillator system 460 in Figure 7 is implemented using external components suitable for operation in the first mode (DAC / Gm-C mode). Table 1 below shows the first mode (DAC / Gm -C mode), showing the operation of three states, where ON = 1 and OFF = 0. The states operate in the order of starting from the reset state, then transitioning to the calibration state, and ending in the tracking state. The reset state is used to reset the voltage level of the node, while the calibration state is used to calibrate the voltage level to a suitable value. Then, the mutual conductance circuit G m1 / G m2 coarse-tunes the voltage pin V coarse to enter the tracking state where it is controlled based on the ranging sensing pin V z . In this embodiment, current integration is provided by the integration capacitor C i . In the tracking mode, the second mutual conductance stage G m2 buffers the voltage of the integration capacitor for controlling the coarse-tune voltage pin V coarse . In this embodiment, the current mirror is controlled by the coarse-tune voltage pin V coarse , thereby controlling the bias of the coarse-tune varactor 104.

[0062] [Table 1]

[0063] Here, referring to FIG. 7, one embodiment of the first mode will be described. In this embodiment, the coarse frequency adjustment / switch control calibration circuit 452 operates as a finite state machine (FSM) starting from the reset state. In addition, during reset, the PLL block is powered on by a separate power-on signal from the local serial peripheral interface (SPI) present in the PLL (which can be started by firmware). In addition, the external VCO, synthesizer, and external circuits are powered on, and calibration is ready (which can be started by firmware).

[0064] When a new frequency is written to the semiconductor die 431, the FSM transitions from the reset state to the calibration state. In the calibration state, the PLL loop is opened and the PFD can be reset. In addition, the FSM sets the calibration DAC code D calA search (e.g., binary search or linear search) can be performed. For example, a binary search can start from the height of the most significant bit (MSB), and the current from the DAC is used to generate a coarse adjustment voltage for the external VCO using an external bipolar transistor and RC components. After each DAC bit trial, start the frequency measurement after a programmable time until the DAC settles. The measured frequency of the external VCO can be compared with the PLL reference frequency or a frequency derived from the PLL reference frequency, or a predetermined target value. Further, once all bits of the calibration DAC453 are used, the FSM transitions to a tracking state.

[0065] In the tracking state, a charge pump tri-state is issued (through the control of the PFD), and then the mutual conductance circuits G m1 and G m2 and the lock of the VCO calibration loop by the integrating capacitor Ci provide tracking. The first mutual conductance circuit G m1 senses the fine adjustment voltage, compares it with a reference value, and generates a current for driving the second mutual conductance circuit G m2 . In addition, the second mutual conductance compares the output with a reference value and further drives the coarse adjustment voltage pin V coarse .

[0066] FIG. 8 is a schematic diagram of another embodiment of an electronic oscillator system 470 including a semiconductor die operating in a second coarse calibration mode.

[0067] The electronic oscillator system 470 includes a semiconductor die 431 and a circuit board containing various external components for the semiconductor die 431. The external components include an external VCO 402 (powered in this embodiment by a 5V power supply), a first varactor 103, a second varactor 104, a temperature sensor 107, a VCO input capacitor 108, a VCO output capacitor 109, a first varactor series capacitor 111a, a second varactor series capacitor 111b, a first varactor bias inductor 112a, a second varactor bias inductor 112b, a fine-tuning capacitor 119a, a sensing capacitor 119b, a VCO clock buffer 403, an amplifier 461, a feedback integrating capacitor 462, and a sensing resistor R z Includes.

[0068] The semiconductor die 431 in Figure 8 includes a PLL 451, a coarse frequency adjustment / switch control calibration circuit 452, an auxiliary ADC 123, and an auxiliary switch S aux Calibrated DAC453, Calibrated DAC reference current source I ref Calibration DAC reference current switch S ref , second calibration switch S cal2 , third calibration switch S cal3 Upward calibration switch S calup Downward calibration switch S caldn , current booster I up , current reduction source I dn , the first charging switch S chg1 , second charging switch S chg2 , third charging switch S chg3 , (S chg1 When it is closed 1 . Charging resistor R (connected between the 8V power supply and ground) chg , (reference voltage V ref (receives) First controllable transconductance circuit G m1 , and (reference voltage V ref (receives) Second controllable transconductance circuit G m2 The semiconductor die 431 also includes a coarse adjustment pin V coarse , fine adjustment pin V fine Range sensing pin V Z , coarse adjustment integral pin Vcoarse_inVCO sensing pin V vco This also includes various pins or pads.

[0069] The external VCO 402 is tuned by both the first varactor 103 (fine-tuning varactor) and the second varactor 104 (coarse-tuning varactor). The first varactor 103 is tuned by the reference clock signal CLK. ref Fine-tuning pin V is set by the PLL451, which includes the PFD455 (which receives the feedback clock signal), the charging pump 456, and the feedback divider 457. fine It is controlled by the voltage.

[0070] As explained earlier with reference to Figure 7, the semiconductor die 431 has a rough adjustment voltage pin V coarse It can operate in multiple modes to control the calibrated DAC453 and the transconductance circuit G. m1 and G m2 The first mode (DAC / G) is used for coarse calibration. m -C mode) and calibration charge pump (S calup , I up , I dn , and S caldn ) and transconductance circuit G m1 The second mode (charge pump / G) is used for coarse calibration. m -C mode) is included.

[0071] The electronic oscillator system 470 in Figure 8 is in the second mode (charge pump / G m It is implemented using external components suitable for operation in the second mode (-C mode). Table 2 below shows the second mode (charge pump / G m The operation of the three states of the -C mode is shown, where ON=1 and OFF=0. The states operate in the order of starting from the reset state, then transitioning to the calibration state, and ending in the tracking state. The reset state is used to reset the voltage level of the node, and the calibration state is used to calibrate the voltage level to a suitable value. Subsequently, the transconductance stage G m1 The rangefinder transmission pin V zBased on the coarse adjustment voltage pin V coarse Enters a tracking state to control the coarseness. In this embodiment, the integral of the coarseness voltage is externally provided by amplifier 461 and feedback integrating capacitor 462. The output of amplifier 461 (in this embodiment, within the 20V domain) controls the bias of the coarseness varactor 104.

[0072] [Table 2]

[0073] Here, with reference to Figure 8, one embodiment of the second mode is described. In this embodiment, the coarse frequency adjustment / switch-controlled calibration circuit 452 operates as an FSM that starts in the reset state. In the reset state, the PLL block is powered on by a separate power-on signal from the local SPI located within the PLL (which can be started by the firmware). In addition, the external VCO, synth, and external circuitry are powered on and ready for calibration (which can be started by the firmware).

[0074] When a new frequency is written to the semiconductor die 431, the FSM transitions from the reset state to the calibration state. In the calibration state, the PLL loop is opened and the PFD can be reset. In addition, the FSM is a calibration charge pump (S calup and S caldn Upward and downward control of ) is set, and the current from the calibration charge pump is (S calup Source current (when ON), or (S caldn The current from the calibration charge pump, which is one of the sink currents (when the switch is ON), is integrated across the external capacitor 462 according to its polarity. After waiting for a programmable time for it to settle, the frequency of the external VCO 402 is measured. In addition, the measured VCO frequency relative to the PLL reference frequency is compared to a frequency derived from the PLL reference frequency or a predetermined target value.

[0075] Once the VCO frequency approaches the target frequency, the FSM enters a tracking state. In the tracking state, the charge pump tristate is emitted through the PFD, and then the tracking loop performs a lock, and the first transconductance circuit G m1 It senses the fine-tuning voltage, compares it to a reference value, and generates a current to drive the external amplifier and integrating capacitor.

[0076] conclusion The preceding description may refer to elements or features as being “connected” or “joined” together. As used herein, unless otherwise expressly stated, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically connected. Similarly, unless otherwise expressly stated, “joined” means that one element / feature is directly or indirectly joined to another element / feature, and not necessarily mechanically joined. Thus, while the various schematics shown in the figures depict exemplary configurations of elements and components, additional intervening elements, devices, features, or components may be present in actual embodiments (assuming that the functionality of the depicted circuit is not adversely affected).

[0077] While specific embodiments have been described, these embodiments are presented merely as examples and are not intended to limit the scope of the disclosure. In fact, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms, and furthermore, various omissions, substitutions, and modifications in the forms of methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given configuration, alternative embodiments may perform similar functionality using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Further embodiments can be provided by combining any preferred combination of elements and actions of the various embodiments described above. Accordingly, the scope of the invention is defined solely by reference to the appended claims.

[0078] The claims presented herein are in single dependent form for filing with the USPTO, but it should be understood that any claim may be dependent on any prior claim of the same type unless it is clearly not technically feasible. [Explanation of Symbols]

[0079] 1 Transmitter and receiver 2 Front-end system 3 Antennas 5 Transmitter 6 Receiver 12a I-pass amplifier 12b Q-pass amplifier 13a I-Pasmixer 13b Q Pass Mixer 14 Transmitting Local Oscillator (LO) 22a I-pass amplifier 22b Q-pass amplifier 23a I-Pasmixer 23b Q Pass Mixer 27 Power Amplifier 28 Low-noise amplifier 30 RF Communication Systems 41 Semiconductor Dies 42 Controllable Oscillators 43 The First Varactor 44 The Second Varactor 45. Phase-Locked Loop (PLL) 46 Calibration Circuit 50 Electronic Oscillator Systems 101 Semiconductor Die 103 The First Varactor 104 The Second Varactor 104 Coarse adjustment varactor 105 First Amplifier 106 Second Amplifier 107 Temperature Sensor 108 VCO input capacitors 109 VCO output capacitor 110 VCO bias inductor 111a First varactor series capacitor 111b Second varactor series capacitor 112a First varactor bias inductor 112b Second varactor bias inductor 113a Coarse-adjusting resistor bypass switch 113b Bias resistor bypass switch 114a coarse adjustment resistor 114b Bias resistor 115a First voltage divider resistor 116a Second voltage divider resistor 117a First amplifier input resistor 117a resistor 117b Second amplifier input resistor 118 Bias Capacitor 119a Fine-tuning capacitor 119b Sensing Capacitor 120 Coarse-adjusted capacitor 122 Calibration Circuit 123 Auxiliary Analog-to-Digital Converter (ADC) 124. Coarse-adjusted digital-to-analog converter (DAC) 126 Possible Resistor Network 127 Fixed resistor 128 possible resistor 129 Resistor Bypass Switch 130 Electronic Oscillator System 131 Adjustment Circuit 132 Rechargeable pump 132V rechargeable pump 133 Frequency Detector (PFD) 201 Coarse Control Resistor 202 Low-pass filter 203 Control Loop Core 204 Temperature information 207 Series resistors 208 Shunt Capacitors 210 External VCO tracking loop 211 First comparator 212 Second comparator 213 Comparator Processing Circuit 215 Subtractive Counter 216 (Flip-flops controlled by the clock signal CLK) 217 Integrator 218 Modulator 219 Adder 220 TC DAC 221 PVT code 230 External VCO tracking loop 232 TC DAC 233 PVT DAC 240 External VCO tracking loop 401 Semiconductor Die 403 VCO Clock Buffer 404 Coarse Voltage Scaling Circuit 422 Calibration Circuit 423 Digital Interface 430 Electronic Oscillator System 431 Semiconductor Die 433 First Current Mirror Transistor 434 Second Current Mirror Transistor 435 Current Miller load resistor (coupled to a 20V power supply in this embodiment) 436 Coarse-adjusted bias resistor 437 First current-mirror load capacitor 438 Second current Miller load capacitor 452 Switch Control Calibration Circuit 456 Rechargeable Pump 457 Feedback Divider 460 Electronic Oscillator System 461 Amplifier 462 Feedback Integrating Capacitor 470 Electronic Oscillator System

Claims

1. An electronic oscillator system, Semiconductor die and A controllable oscillator located outside the aforementioned semiconductor die, A first varactor configured to adjust the oscillation frequency of the controllable oscillator, The controllable oscillator comprises a second varactor configured to adjust the oscillation frequency of the controllable oscillator, The semiconductor die comprises a phase-locked loop (PLL) configured to provide fine adjustment to the controllable oscillator by controlling the first varactor, a calibration circuit configured to provide coarse adjustment to the controllable oscillator by controlling the second varactor, a coarse adjustment voltage pin configured to output a coarse control voltage from the calibration circuit, a calibration digital-to-analog converter (DAC), and a calibration charge pump, wherein the calibration circuit operates in a first mode in which the calibration DAC sets the voltage level of the coarse adjustment voltage pin, and a second mode in which the calibration charge pump sets the voltage level of the coarse control voltage, in an electronic oscillator system.

2. The electronic oscillator system according to claim 1, further comprising a coarse-tuned voltage scaling circuit configured to scale the coarse-tuned voltage to generate a varactor-tuned voltage for the second varactor.

3. The electronic oscillator system according to claim 1, wherein the semiconductor die further comprises a first transconductance stage and a second transconductance stage, wherein in the first mode, the first transconductance stage and the second transconductance stage operate in series to adjust the voltage level of the coarse adjustment voltage pin after it has been set by the calibration DAC, and in the second mode, the first transconductance stage adjusts the voltage level of the coarse adjustment voltage pin after it has been set by the calibration charge pump.

4. The electronic oscillator system according to claim 3, wherein in the first mode, the first transconductance stage generates a current based on comparing a reference signal with a sensed fine-tuning voltage in order to control the second varactor, and the second transconductance stage receives the current and drives the coarse-tuning voltage pin.

5. The electronic oscillator system according to claim 1, further comprising a digital-to-analog converter (DAC) having an input for receiving digital data from the calibration circuit and an output connected to the coarse adjustment voltage pin, wherein the coarse adjustment voltage pin is for controlling the second varactor.

6. The electronic oscillator system according to claim 1, wherein the coarse adjustment voltage pin is for controlling the second varactor, and further comprises a first DAC for controlling the coarse adjustment voltage pin based on a process voltage temperature (PVT) code, and a second DAC for controlling the coarse adjustment voltage pin based on an oscillator voltage range sensed by the calibration circuit.

7. The electronic oscillator system according to claim 1, wherein the calibration circuit is configured to calibrate the amplitude of the controllable oscillator based on controlling the bias of the controllable oscillator and observing the output oscillator signal of the controllable oscillator.

8. The electronic oscillator system according to claim 1, wherein the calibration circuit is configured to compare the adjustment voltage set by the PLL with an upper threshold signal and a lower threshold signal.

9. The electronic oscillator system according to claim 8, further comprising: a first comparator for comparing the adjustment voltage with the upper threshold signal; a second comparator for comparing the adjustment voltage with the lower threshold signal; a counter controlled based on the output of the first comparator and the output of the second comparator; and an integrator configured to integrate the output of the counter.

10. The electronic oscillator system according to claim 1, further comprising an external temperature sensor, wherein the calibration circuit operates based on temperature data received from the external temperature sensor.

11. The electronic oscillator system according to claim 1, wherein the second varactor provides a higher frequency-to-voltage gain than the first varactor.

12. A method for controlling an electronic oscillator, The adjustment involves using a first varactor to adjust the oscillation frequency of a controllable oscillator, wherein the controllable oscillator is located outside the semiconductor die. The oscillation frequency of the controllable oscillator is adjusted using a second varactor, Controlling the first varactor to provide fine-tuning to the controllable oscillator using a phase-locked loop (PLL) on the semiconductor die, The second varactor is controlled to provide coarse adjustment to the controllable oscillator using the calibration circuit of the semiconductor die by outputting a coarse control voltage through the coarse adjustment voltage pin of the semiconductor die, A method comprising operating the semiconductor die in either a first mode in which a calibration DAC sets the voltage level of the coarse adjustment voltage pin, or a second mode in which a calibration charge pump sets the voltage level of the coarse control voltage.

13. The method according to claim 12, further comprising outputting a coarse control voltage from a coarse adjustment voltage pin of the semiconductor die, and scaling the coarse control voltage using an amplifier to generate a varactor control voltage for the second varactor.

14. The method according to claim 12, further comprising receiving digital data from the calibration circuit as input to a digital-to-analog converter (DAC), and providing a coarse control voltage from the output of the DAC to the coarse adjustment voltage pin of the semiconductor die.

15. The method according to claim 12, further comprising comparing the adjustment voltage set by the PLL with an upper threshold signal and a lower threshold signal.

16. A radio frequency communication system, A mixer controlled by an oscillator signal, It is a local oscillator, Semiconductor die, A controllable oscillator located outside the semiconductor die and configured to output the oscillator signal, A first varactor configured to adjust the oscillation frequency of the controllable oscillator, and A local oscillator comprising a second varactor configured to adjust the oscillation frequency of the controllable oscillator, The semiconductor die comprises a phase-locked loop (PLL) configured to provide fine adjustment to the controllable oscillator by controlling the first varactor, a calibration circuit configured to provide coarse adjustment to the controllable oscillator by controlling the second varactor, a coarse adjustment voltage pin configured to output a coarse control voltage from the calibration circuit, a calibration digital-to-analog converter (DAC), and a calibration charge pump, wherein the calibration circuit operates in a first mode in which the calibration DAC sets the voltage level of the coarse adjustment voltage pin, and a second mode in which the calibration charge pump sets the voltage level of the coarse control voltage, in a radio frequency communication system.

17. The radio frequency communication system according to claim 16, wherein the calibration circuit is configured to compare the adjustment voltage set by the PLL with an upper threshold signal and a lower threshold signal.

18. The radio frequency communication system according to claim 16, wherein the second varactor provides a higher frequency-to-voltage gain than the first varactor.

Images