Fiber array, optical integrated circuit, and method for manufacturing an optical integrated circuit

Abstract

A fiber array for edge coupling of at least one optical fiber to at least one wafer substrate is provided, the fiber array including an optical fiber core, a cladding covering the optical fiber core, a V-groove mount on top of the cladding, and a polished tapered lid on the bottom of the cladding.

Description

Technical Field

[0001] Generally, this embodiment relates to an integrated optical circuit (PIC), and more particularly, to the coupling of optical fiber components and silicon photonics in a PIC.

Background Art

[0002] An integrated optical circuit (PIC), also called an integrated optical circuit or a planar lightwave circuit, is a device in which many optical and electronic components are integrated. PICs are manufactured using lithography on a substrate of a non-linear crystal material including silicon, silica, or lithium niobate. PICs mainly include arrays of a large number of the same components used in optical fiber communication, optical sensors, and measurement.

[0003] In most cases, the substrate material determines the characteristics and limitations of the PIC, for example, silica-on-silicon integrated optics built on a silicon wafer. Silica waveguides enable the realization of couplers, filters, splitters, and combiners. It can also include active elements with optical gain connected to optical fibers. One way to couple multiple waveguides is to use a fiber array. In some cases, photonic functions are implemented directly on the chip. The silicon nitride (Si3N4) platform is also used to manufacture photonic devices operating in the 1 μm spectral region or shorter wavelengths.

[0004] Waveguides are also manufactured on silica glass such as fused silica glass, and the waveguides are manufactured far below the surface to form embedded waveguides that enable three-dimensional circuit design. Further, another material used as a substrate is lithium niobate (LiNbO3) as a non-linear crystal material suitable for devices that perform non-linear functions such as electro-optic modulators or acousto-optic transducers.

[0005] In complex optical transmission systems, efficient fiber-to-chip coupling is crucial because optical interconnects between fibers and PICs occur frequently throughout the system. However, the dimensional difference between the substrate waveguide and the fiber diameter presents complex challenges. For example, the feature size of a silicon waveguide is small, around tens of nanometers, while the typical diameter of a single-mode fiber (SMF) is approximately 125 μm, with a core diameter of nearly 10 μm. This results in a large size mismatch between the fiber core and the Si waveguide, causing significant optical transmission loss when light emitted from the fiber core directly enters the Si waveguide. Fiber-to-chip couplers are a key optical component that addresses this problem in optical interconnects. Generally, fiber-to-chip coupling can be performed in two ways, depending on the relative position of the fiber and the photonic chip: vertical coupling (or off-plane coupling) and butt coupling (or edge coupling / in-plane coupling). In edge coupling, fibers are typically positioned in wafer facets and aligned horizontally with the Si waveguide, and edge couplers are commonly used. Edge couplers offer high coupling efficiency, wide bandwidth, and polarization independence, but they also have some limitations, including a relatively larger footprint than grating couplers, fixed coupling locations, and more stringent requirements for the coupling facets.

[0006] In telecom and datacom applications, some form of fiber-to-PIC coupling is required for the transfer of optical signals to and from a PIC. Edge coupling is one option that can provide low insertion loss (IL), wide spectral bandwidth (BW), and low sensitivity to polarization. However, current standard Si-PICs for edge coupling employ deep trench etching to form a high-quality optical interface for edge coupling, but this process creates protrusions that result in a 20-50 μm gap between the fiber core and the edge coupler. This gap causes high optical power loss. Several solutions have been proposed to avoid the effects of these protrusions. One solution involves longitudinally positioned fibers to extend from the V-groove. However, this is a complex process and, coupled with stability issues, does not provide any way to ensure fiber end roughness because fiber end polishing cannot be applied. Yet another solution involves removing the bottom fiber array lid for the fiber array assembly. However, removing the lid complicates the process and increases costs because it loosens control over fiber positioning and epoxy thickness. [Overview of the project] [Problems that the invention aims to solve]

[0007] As shown in Figure 1, a typical fiber array for optical alignment has a 20-50 μm gap between the fiber core and the PIC's edge coupler, resulting in high optical loss. For example, the edge coupler can include silicon oxide, a Si substrate, and a portion of the Si substrate extending toward the lid of the fiber array. However, increasing the trench depth for fiber movement makes the wafer fragile and prone to breakage.

[0008] Figure 2 shows a fiber array extending from a V-groove to reduce the aforementioned gap. However, extending fibers from a V-groove requires complex process control to form such a structure, and it is difficult to avoid damage to the fiber end faces or increased roughness during formation. The V-groove is monolithically integrated with the PIC and enables low-loss edge coupling with passive alignment to single fibers or fiber arrays.

[0009] Figure 3 shows a fiber array without a bottom lid for optical alignment of the fiber and waveguide. However, fiber arrays without a bottom lid are difficult to manufacture and complicate the process. This arrangement also makes it difficult to control the epoxy thickness because the positioning of the fibers without a bottom lid is looser.

[0010] Therefore, as the number of fiber ports per chip increases, it is crucial to find cost-effective solutions to address the fiber-to-chip optical interconnection problem in silicon photonics. As mentioned earlier, the challenge to be overcome is the mismatch in optical mode sizes between silicon photonics chip waveguides and optical fibers.

[0011] Therefore, solutions are still needed to mitigate the impact on the positioning of the fiber array and Si-PIC caused by protrusions from the etching process in the edge coupling region. [Means for solving the problem]

[0012] In a first embodiment, a fiber array is provided for edge coupling of at least one optical fiber to at least one wafer substrate. The fiber array comprises an optical fiber core, a fiber cladding covering the optical fiber core, a V-groove mount on the top of the fiber cladding, and a polished tapered fiber array lid at the bottom of the fiber cladding.

[0013] In one embodiment of the first aspect, the optical fiber core is single-mode.

[0014] In one embodiment of the first aspect, the optical fiber core is multimode.

[0015] In one embodiment of the first aspect, the fiber array lid is made of a polymer.

[0016] In a second embodiment, an optical integrated circuit comprising a wafer substrate is provided. The fiber array described herein is coupled in-plane to the wafer substrate.

[0017] In one embodiment of the second aspect, the optical fiber core is single-mode.

[0018] In one embodiment of the second aspect, the optical fiber core is multimode.

[0019] In one embodiment of the second aspect, the fiber array lid is made of a polymer.

[0020] In one embodiment of the second aspect, the V-groove array is manufactured on a separate silicon submount and edge-coupled to the wafer substrate by active alignment.

[0021] In one embodiment of the second aspect, the wafer substrate includes a deep trench structure, the fiber array is aligned on the deep trench structure, the alignment includes the angle and position of the fiber array lid, the angle of the fiber array lid is determined by the depth of the deep trench structure.

[0022] In a third embodiment, a method for manufacturing the optical integrated circuit described herein is provided. The method includes the following: a) The step of etching the silicon substrate of the wafer substrate to form a deep trench structure so that the deep trench structure forms an optical interface for edge coupling, b) Performing a first polishing of the fiber array lid to form a polished tapered fiber array lid aligned with the wafer substrate above the deep trench structure; c) Performing a second polishing of the polished tapered fiber array lid to place the polished tapered fiber array lid in proximity to the silicon oxide substrate; d) In a further step, the optical fiber core is adjusted in proximity to the silicon oxide substrate to achieve a good optical interconnect between the fiber array and the wafer substrate.

[0023] In one embodiment of the third aspect, the angle of the polished tapered fiber array lid is about 30° - 45°.

[0024] These and other aspects of the embodiments of the present invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. However, it should be understood that the following description, while showing preferred embodiments and many specific details thereof, is given by way of illustration only and is not limiting. Many changes and modifications can be made within the scope of the embodiments of the present invention without departing from the spirit of the embodiments of the present invention, and the embodiments herein include all such modifications.

Brief Description of the Drawings

[0025] The person skilled in the art will understand other objects, features and advantages from the following description of the preferred embodiments and the accompanying drawings.

[0026] [Figure 1] FIG. 1 shows a standard fiber array-based optical integrated circuit.

[0027] [Figure 2] FIG. 2 shows an extended fiber array-based optical integrated circuit.

[0028] [Figure 3] Figure 3 shows a fiber array-based optical integrated circuit without a bottom lid.

[0029] [Figure 4] Figure 4 shows a fiber array having polished tapered lids for bonding fibers to a wafer substrate to form an optical integrated circuit, according to one embodiment of the present invention. [Modes for carrying out the invention]

[0030] In the following detailed description, specific implementable embodiments will be described with reference to the accompanying drawings that form part of this specification. The embodiments are described in sufficient detail to be implementable by those skilled in the art, and it should be understood that logical, mechanical, and other modifications can be made without departing from the scope of the embodiments. Therefore, the following detailed description should not be construed as restrictive.

[0031] It should be understood that the expressions and terms used herein are for illustrative purposes only and not for limitation. Accordingly, while the embodiments described herein are described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments described herein can be modified and implemented within the spirit and scope of the claims.

[0032] As described above, standard fiber arrays for coupling optical fibers to wafer waveguides or substrate waveguides still have some limitations. The present invention and the disclosure herein overcome these limitations by providing a fiber array having polished tapered lids for coupling optical fibers to a wafer substrate or chip.

[0033] The fiber array 400 in Figure 4 includes a fiber core 402, fiber cladding 404, fiber array V-groove mount 406, and a tapered fiber array lid 408. The fiber core 402 is encased in fiber cladding 404 and held in three-point contact with the two V-groove sidewalls 406 and the tapered, angled fiber array lid 408. The bottom fiber array lid 408 can be made of polymer. The fiber core 402 is surrounded by fiber cladding 404, and the array consists of two layers of cladding 404 on both sides of the fiber core 402.

[0034] In one embodiment, the fiber core 402 may be a single-mode fiber. In another embodiment, the fiber core 402 may be a multimode fiber. In one embodiment, the fiber array lid 408 may have a thickness of at least about 200 μm and gradually taper towards the edge of the cladding layer 404 as it approaches the wafer substrate 410, as shown in Figure 4.

[0035] In one embodiment, the angle polishing of the fiber array lid 408 can be carried out based on a conventional method according to a standard fiber array shown in Figure 1. The angle α and the remainder of the front end lid need to be controlled so that the fiber core 402 is in close proximity to the silicon oxide 412 of the edge coupler. In one embodiment, “proximity” may mean that there is a space or gap between them. In one embodiment, the gap can be zero so that the fiber core and the silicon oxide are in contact with each other.

[0036] In one embodiment, the angle α can be approximately 45° and can be varied down to approximately 30°. Therefore, the angle α can be in the range of approximately 30° to 45° with respect to the plane and horizontal bottom surface of the cladding layer 404 at the bottom.

[0037] The taper of the fiber array lid 408 can be achieved by polishing the fiber array lid 408 to a specific angle that allows the fiber array to be positioned close to the edge coupler. The polishing angle is predetermined by the depth of the deep trench in layer 410, and thus the position of the fiber array is controlled by the deep trench bottom stage.

[0038] In one embodiment, the polishing can result in a taper angle of approximately 45°, which can be varied down to approximately 30° to allow for a certain degree of height tolerance.

[0039] The manufacturing of the fiber array 400 shown in Figure 4 is compatible with current mature fiber array assembly processes and associated controls, while simultaneously improving stability and alignment accuracy.

[0040] The wafer substrate 410 may consist of a silicon substrate layer 410 having deep trenches that leave portions 401 extending by distance or gap toward the fiber array lid. The substrate can form a deep trench structure based on the deep trenches and the extended portions. The deep trench structure forms an optical interface for edge coupling. The wafer substrate may also include a silicon oxide layer 412 disposed on top of the wafer substrate.

[0041] In one embodiment, the wafer substrate can be called an edge coupler. Thus, the edge coupler may include a silicon oxide layer 412, a silicon substrate layer 410, and a portion 401 of the silicon substrate layer that extends a certain distance toward the lid of the fiber array.

[0042] In one embodiment, the trench depth of layer 410 can be approximately 120 μm, and the gap distance of the portion 401 extending horizontally with respect to the front end of the fiber array can be approximately 20 to 40 μm, assuming that no lid remains at the front end. The silicon oxide layer 412 can have a thickness of approximately 5 to 6 μm.

[0043] In this regard, an edge-coupled optical integrated circuit (PIC) can be provided. The PIC may include a wafer substrate 410 and a fiber array 400 having optical fiber cores coupled in-plane to the wafer substrate and surrounded by a fiber cladding 404, wherein the fiber array V-groove 406 is mounted on the fiber cladding 404 and a polished tapered lid is attached to the bottom of the fiber cladding 404.

[0044] In one embodiment, a hybrid integration approach is preferred. Specifically, the V-groove array is fabricated on a separate silicon submount and edge-coupled to the wafer substrate by active alignment. The silicon V-grooves precisely position multiple fibers within the one-dimensional array with submicron precision, enabling simultaneous active alignment of multiple fibers.

[0045] In one embodiment, the concentricity of the core cladding can be less than 0.5 μm, and the thickness of the cladding 404 and fiber core 402 can be approximately 125 ± 0.7 μm.

[0046] In one embodiment, the thickness of the fiber core 402 can be approximately 8 to 10 μm, and the thickness of the fiber array V-groove 406 can be approximately 500 μm to 1 mm.

[0047] In one embodiment, the thickness of the fiber array lid 408 can be 200 to 300 μm, and polishing can be performed up to the edge of the cladding layer 404 on top of the lid.

[0048] In one embodiment, an integrated circuit structure is provided. The integrated circuit structure includes a substrate and a deep trench structure within the substrate, wherein a fiber array lid 408 is aligned on the deep trench structure, and this alignment includes the angle and position of the fiber array lid. The angle of the fiber array lid is determined by the depth of the deep trench structure, and the position of the fiber array lid is controlled by the horizontally extending bottom of the deep trench structure. The circuit further includes a fiber core disposed between two cladding structures, the cladding structures being disposed on the fiber array lid. The circuit further includes a fiber array groove 406 disposed on the cladding structure, the fiber array groove being V-shaped.

[0049] In one embodiment, a method for manufacturing an optical integrated circuit is provided. This method includes the steps of etching a silicon substrate of a wafer substrate to form a deep trench structure, the deep trench structure forming an optical interface for edge coupling, and performing a first polishing of a fiber array lid 408 to align the fiber array lid 408 with the silicon substrate, thereby aligning the fiber array lid 408 above the deep trench structure, the first polishing including the steps of forming a polished tapered fiber array lid aligned with the wafer substrate above the deep trench structure, and performing a second polishing of the polished tapered fiber array lid to position the polished tapered fiber array lid in close proximity to the silicon oxide substrate. The above steps are performed to control the angle of positioning of the polished tapered fiber array lid and the remainder of the lid at the front end. In one example, the fiber core 402 is in close proximity to the silicon oxide 412. "In close proximity" can refer to the space or gap between them. In one embodiment, the gap may be zero. The angle of the fiber array lid is between approximately 30° and 45°. The primary purpose of polishing the fiber array front end and lid is to bring the fiber core 402 closer to the silicon oxide 412, ensuring good optical interconnection between the fiber array and the PIC.

[0050] It will be understood that the modifications and other features and functions of the above disclosure, or alternatives thereof, can preferably be combined with many other different systems or applications. Furthermore, various alternatives, modifications, variations or improvements not currently anticipated or not anticipated may subsequently be made by those skilled in the art, and these are intended to be encompassed by the following claims.

[0051] While embodiments of this disclosure are described in considerable detail and comprehensively to cover possible aspects, those skilled in the art will recognize that other versions of this disclosure are also possible.

Claims

1. A fiber array for edge coupling at the edge of a fiber array, comprising at least one optical fiber and at least one wafer substrate, Optical fiber core and A fiber cladding having an edge, top, and bottom, covering the optical fiber core, The V-groove mount on the upper part of the fiber cladding, The fiber array lid at the bottom of the fiber cladding and Equipped with, The fiber cladding and the V-groove mount have a uniform cross-section perpendicular to the optical axis of the optical fiber at their edges, and the fiber array lid has a taper at its edges. Fiber array.

2. The fiber array according to claim 1, wherein the optical fiber core is single-mode, and the optical fiber core has a uniform cross-section perpendicular to the optical axis of the optical fiber at the edge of the fiber cladding.

3. The fiber array according to claim 1, wherein the fiber array lid is made of a polymer.

4. The fiber array according to claim 1, wherein the taper angle of the fiber array lid is 30° to 45°.

5. Wafer substrate and A fiber array according to claim 1, coupled in-plane to the wafer substrate, Equipped with, Optical integrated circuit.

6. The optical integrated circuit according to claim 5, wherein the optical fiber core is single-mode.

7. The optical integrated circuit according to claim 5, wherein the optical fiber core is multimode.

8. The optical integrated circuit according to claim 5, wherein the angle of the taper of the polished fiber array lid is 30° to 45°.

9. The wafer substrate includes a deep trench structure, The fiber array is aligned on the deep trench structure, The alignment includes the angle and position of the fiber array lid, The angle of the fiber array lid is determined by the depth of the deep trench structure. The optical integrated circuit according to claim 5.

10. A method for manufacturing an optical integrated circuit according to claim 9, a) The step of etching the silicon substrate of the wafer substrate to form a deep trench structure so that the deep trench structure forms an optical interface for edge coupling, b) A step of performing a first polishing of the fiber array lid to form a polished fiber array lid aligned with the wafer substrate above the deep trench structure, c) The step of performing a second polishing of the polished tapered fiber array lid and placing the further polished fiber array lid in close proximity to the silicon oxide substrate, d) The optical fiber core is positioned close to the silicon oxide substrate in order to achieve good optical interconnection between the fiber array and the wafer substrate. method.

11. The method according to claim 10, wherein the taper angle of the further polished fiber array lid is 30° to 45°.

12. The V-groove array is manufactured on a separate silicon submount, The wafer substrate is edge-coupled by active alignment. The method according to claim 10.

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