Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device with a mesa structure, the semiconductor device being reduced in electric field strength near an outer peripheral end of a field plate electrode while ensuring pressure resistance, and a manufacturing method of the same.SOLUTION: There is provided a semiconductor device including: a semiconductor layer 10 having a mesa portion 11 on a top face 10; a first insulating layer 20 that exists along a top face 11a and a side face 11b of the mesa portion 11 and along the top face 10a of the semiconductor layer 10 other than the mesa portion 11, and that has an opening 21 communicating with the top face 11a of the mesa portion 11; a second insulating layer 30 existing on a top face 22a of an outer peripheral edge 22 of the first insulating layer 20; and a field plate electrode 40 that has, inside the opening 21, a projection 41 ensuring electrical continuity with the mesa portion 11 and that exists from the projection 41 along a top face 20a and a side face 20b of the first insulating layer 20 and along an inner peripheral side face 30b of the second insulating layer 30. There is also provided a manufacturing method of the semiconductor device.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] When a semiconductor device is used as a power device, it is necessary to ensure the breakdown voltage when a reverse bias is applied.

[0003] When a reverse bias is applied to a semiconductor device, locally concentrated charge portions occur inside the semiconductor device, and so-called field concentration occurs. Then, dielectric breakdown occurs in the semiconductor device at a voltage much lower than the theoretical breakdown voltage. As a measure to avoid such dielectric breakdown, a field plate structure is well known.

[0004] The field plate structure has an insulating layer between a semiconductor layer and an electrode, an opening is provided in the insulating layer, a protruding portion is provided on the electrode, and the protruding portion of the electrode is inserted into the opening of the insulating layer to bring the semiconductor layer into contact with the protruding portion of the electrode, thereby ensuring electrical conduction between the semiconductor layer and the electrode. Such an electrode is called a field plate electrode. The field plate electrode extends in the circumferential direction around the protruding portion while contacting the upper surface of the insulating layer. The end position of such an extension is hereinafter referred to as the outer peripheral end of the field plate electrode.

[0005] In a semiconductor device having a field plate structure, the presence of an insulating layer between the semiconductor layer and the field plate electrode can ensure the breakdown voltage when a reverse bias is applied.

[0006] Semiconductor devices having a field plate structure are disclosed in, for example, Patent Documents 1 and 2.

[0007] Patent Document 1 discloses a semiconductor device having a field plate structure in which the thickness of the insulating layer is constant. Further, Patent Document 1 discloses that the semiconductor layer of this semiconductor device has a mesa structure.

[0008] A mesa structure refers to a structure in which a semiconductor layer, formed by joining multiple semiconductor films, has a trapezoidal region on its surface due to a slope or step. This trapezoidal region is called the mesa. Semiconductor devices with semiconductor layers that do not have a mesa structure experience electric field concentration near the edge of the semiconductor layer when a reverse bias is applied, which can cause dielectric breakdown. On the other hand, the presence of a mesa region in the semiconductor layer of a semiconductor device reduces electric field concentration near the edge of the semiconductor layer, thereby ensuring the breakdown voltage of the semiconductor device.

[0009] Patent Document 2 discloses a semiconductor device in which the thickness of the insulating layer gradually increases as it approaches the outer edge of the field plate. The insulating layer disclosed in Patent Document 2 is formed by etching the insulating layer in areas away from the outer edge of the field plate. Furthermore, Patent Document 2 discloses that the semiconductor layer of this semiconductor device does not have a mesa structure. [Prior art documents] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Publication No. 2018-137393 [Patent Document 2] Japanese Patent Publication No. 2019-57569 [Overview of the project] [Problems that the invention aims to solve]

[0011] In the semiconductor device disclosed in Patent Document 1, while voltage resistance can be ensured, the electric field strength is high near the outer edge of the field plate electrode.

[0012] The semiconductor layer of the semiconductor device disclosed in Patent Document 2 does not have a mesa structure. The semiconductor layer is composed of multiple semiconductor films. When all of the multiple semiconductor films constituting the semiconductor layer are n-type semiconductors, it is desirable for the semiconductor layer to have a mesa structure from the viewpoint of ensuring breakdown voltage. Therefore, when using a semiconductor material for the semiconductor layer of a semiconductor device where breakdown voltage is particularly required, and it is impossible or difficult to obtain a p-type semiconductor, such as gallium oxide, it is desirable for the semiconductor layer to have a mesa structure.

[0013] This disclosure aims to solve the above-mentioned problems. Specifically, this disclosure aims to provide a semiconductor device having a mesa structure that reduces the electric field strength near the outer edge of the field plate electrode while ensuring voltage resistance, and a method for manufacturing the same. [Means for solving the problem]

[0014] The Disclosers have diligently studied and completed the semiconductor device and its manufacturing method described herein in order to achieve the above objectives. The semiconductor device and its manufacturing method described herein include the following embodiments. <1> A semiconductor layer having a mesa portion on its upper surface, A first insulating layer having an opening that communicates with the upper surface of the mesa portion, and an opening that is located along the upper surface of the semiconductor layer other than the mesa portion, The second insulating layer located on the upper surface of the outer edge of the first insulating layer, The opening has a protrusion that ensures electrical conductivity with the mesa portion, and the field plate electrode is located along the upper surface and side surface of the first insulating layer and the inner circumferential side surface of the second insulating layer, A semiconductor device equipped with the following features. (2) The semiconductor device according to (1), wherein the field plate electrode is further located along at least a portion of the upper surface of the insulating layer that extends from the inner circumferential side surface of the second insulating layer. <3> When the thickness of the first insulating layer is t1 and the thickness of the second insulating layer is t2, The aforementioned t1 is 0.8 μm or more and 3.2 μm or less, and The aforementioned t2 is 0.8 μm or more and 10.0 μm or less. The semiconductor device described in (1) or (2). (4) The semiconductor device according to (1) or (2), wherein the semiconductor layer contains gallium oxide. A method for manufacturing a semiconductor device as described in <5> and <1>, The first insulating layer, the second insulating layer, and the field plate electrode are formed in this order on the semiconductor layer having the mesa portion. Before forming the first insulating layer, a first masking member is installed in the area where communication of the opening is planned. Before forming the second insulating layer, the second masking member is installed on a surface other than the upper surface of the outer edge of the first insulating layer, and Before forming the field plate electrode, remove the first masking member and the second masking member, and install the third masking member on the upper surface of the second insulating layer. A method for manufacturing a semiconductor device, including the method described above. A method for manufacturing a semiconductor device as described in <6> and <2>, The first insulating layer, the second insulating layer, and the field plate electrode are formed in this order on the semiconductor layer having the mesa portion. Before forming the first insulating layer, a first masking member is installed in the area where communication of the opening is planned. Before forming the second insulating layer, the second masking member is installed on a surface other than the upper surface of the outer edge of the first insulating layer, and Before forming the field plate electrode, remove the first masking member and the second masking member, and install a third masking member on the upper surface of the second insulating layer, excluding at least a portion of the upper surface of the second insulating layer that extends from the inner circumferential side surface of the second insulating layer. A method for manufacturing a semiconductor device, including the method described above. (7) The method for manufacturing a semiconductor device according to (5) or (6), wherein the semiconductor layer contains gallium oxide. [Effects of the Invention]

[0015] According to the present disclosure, by disposing a second insulating layer in addition to the first insulating layer near the outer peripheral end of the field plate electrode, it is possible to provide a semiconductor device having a mesa structure in which the electric field strength near the outer peripheral end of the field plate electrode is reduced while ensuring the breakdown voltage.

[0016] Further, according to the present disclosure, by using masking instead of etching to form the above structure, it is possible to provide a method for manufacturing a semiconductor device in which the mesa structure of the semiconductor layer is not damaged, the breakdown voltage is ensured, and the electric field strength near the outer peripheral end of the field plate electrode is reduced.

Brief Description of the Drawings

[0017] [Figure 1A] FIG. 1A is a top schematic view showing one aspect of the semiconductor device of the present disclosure. [Figure 1B] FIG. 1B is a longitudinal cross-sectional schematic view taken along line AA of FIG. 1A. [Figure 2A] FIG. 2A is a top schematic view showing another aspect of the semiconductor device of the present disclosure. <0000,104> [Figure 2B] FIG. 2B is a longitudinal cross-sectional schematic view taken along line AA of FIG. 2A. <, [Figure 3] FIG. 3 is a longitudinal cross-sectional schematic view showing the state before forming the first insulating layer. [Figure 4] FIG. 4 is a longitudinal cross-sectional schematic view showing the state before forming the second insulating layer. [Figure 5] FIG. 5 is a longitudinal cross-sectional schematic view showing one aspect of the state before forming the field plate electrode. [Figure 6] FIG. 6 is a longitudinal cross-sectional schematic view showing another aspect of the state before forming the field plate electrode. [Figure 7] FIG. 7 is a graph showing the relationship between the breakdown voltage and the electric field strength at the outer peripheral end of the field plate electrode for the semiconductor devices of each sample. [Figure 8]Figure 8 is a longitudinal cross-sectional view showing the results of numerical calculations of the electric field strength distribution for the semiconductor device of Reference Example 1. [Figure 9] Figure 9 is a longitudinal cross-sectional view showing the results of numerical calculations of the electric field strength distribution for the semiconductor device of Comparative Example 5. [Figure 10] Figure 10 is a longitudinal cross-sectional view showing the results of numerical calculation of the electric field strength distribution for the semiconductor device of Example 6. [Modes for carrying out the invention]

[0018] The following describes embodiments of the semiconductor device and its manufacturing method as disclosed herein. The semiconductor device and its manufacturing method as disclosed herein are not limited to the embodiments described below and can be implemented in various modifications within the scope of the spirit of this disclosure.

[0019] While not bound by theory, the present inventors will explain their findings regarding the reason why the semiconductor device of this disclosure reduces the electric field strength near the outer edge of the field plate electrode while ensuring voltage resistance, along with its manufacturing method.

[0020] In semiconductor devices having a field plate structure, electric field concentration occurs near the outer edge of the field plate electrode when a reverse bias is applied. To reduce electric field concentration near the outer edge of the field plate electrode, it is advantageous to make the insulating layer thicker near the outer edge of the field plate electrode.

[0021] As mentioned above, an insulating layer exists between the semiconductor layer and the field plate electrode. Such an insulating layer is typically formed by deposition. Therefore, in conventional semiconductor devices, the thickness of the insulating layer was generally almost constant throughout. Consequently, in conventional semiconductor devices, when the insulating layer was thickened near the outer edge of the field plate electrode to reduce electric field concentration near the outer edge, it was common to thicken the insulating layer throughout its entirety.

[0022] While increasing the thickness of the insulating layer throughout is advantageous in reducing electric field concentration near the outer edge of the field plate electrode, it can actually increase the likelihood of electric field concentration in other areas, particularly near openings in the insulating layer, leading to a decrease in breakdown voltage. This tendency becomes even stronger when the semiconductor layer has a mesa structure.

[0023] To reduce the electric field strength near the outer edge of the field plate electrode while ensuring voltage resistance, the thickness of the insulating layer should be increased at the outer edge of the field plate electrode compared to other areas. As an example of such an insulating layer, Patent Document 2 discloses an insulating layer that gradually increases in thickness as it approaches the outer edge of the field plate.

[0024] However, the semiconductor layer of the semiconductor device disclosed in Patent Document 2 does not have a mesa structure. If the semiconductor layer has a mesa structure, mesa portions exist on the surface of the semiconductor layer, and it is difficult to gradually change the thickness of the insulating layer when forming the insulating layer along these mesa portions. Furthermore, although the insulating layer in Patent Document 2 gradually changes the thickness of the insulating layer by etching the surface of the formed insulating layer, the etching solution may reach the mesa portions beneath the insulating layer, making it difficult to etch the insulating layer without damaging the mesa portions.

[0025] Therefore, the present disclosers have found that a first insulating layer can be formed in the area where an insulating layer is needed, and a second insulating layer can be formed near the outer edge of the field plate electrode, that is, on the upper surface of the outer edge of the first insulating layer. The first insulating layer has the necessary thickness to ensure withstand voltage except at the outer edge of the field plate electrode. The second insulating layer adds the necessary thickness to avoid electric field concentration near the outer edge of the field plate electrode. Furthermore, when forming the second insulating layer, a masking member can be placed on the upper surface of the first insulating layer other than the outer edge.

[0026] Next, we will describe the constituent elements of the semiconductor device and its manufacturing method as described herein, which have been completed based on the knowledge and other information explained so far.

[0027] Semiconductor equipment Figure 1A is a schematic top view showing one embodiment of the semiconductor device of the present disclosure. Figure 1B is a schematic longitudinal section along line AA in Figure 1A. Figure 2A is a schematic top view showing another embodiment of the semiconductor device of the present disclosure. Figure 2B is a schematic longitudinal section along line AA in Figure 2A. Figures 1A and 1B, and Figures 2A and 2B are schematic diagrams and therefore not to scale. Also, in Figures 1A and 1B, and Figures 2A and 2B, the corner and edge shapes are not to scale and may or may not be chamfered. Furthermore, for the sake of simplification, only the second insulating layer and field plate electrodes are described in Figures 1B and 2B.

[0028] As shown in Figures 1A and 1B and Figures 2A and 2B, the semiconductor device 100 comprises a semiconductor layer 10, a first insulating layer 20, a second insulating layer 30, a field plate electrode 40, and a bottom electrode 50. Hereinafter, the semiconductor layer 10, the first insulating layer 20, the second insulating layer 30, the field plate electrode 40, and the bottom electrode 50 will be explained mainly with reference to Figures 1A and 1B. The field plate electrode 40 will be explained using Figures 1A and 1B, as well as Figures 2A and 2B. The content explained using Figures 2A and 2B is the same as the content explained using Figures 1A and 1B, except for the content explained using Figures 2A and 2B.

[0029] <Semiconductor layer> The semiconductor layer 10 of the semiconductor device 100 of this disclosure has a mesa structure. Therefore, the upper surface 10a of the semiconductor layer 10 has a mesa portion 11. In the embodiments shown in Figures 1A and 1B, the mesa portion 11 is formed in a trapezoidal shape by a step, but is not limited to this. For example, the mesa portion 11 may be formed by connecting the upper surface 10a of the semiconductor layer 10 and the upper surface 11a of the mesa portion 11 with a straight or curved incline.

[0030] The semiconductor layer 10 and the mesa portion 11 are formed by joining multiple semiconductor films (not shown). As long as the semiconductor device 100 has a mesa portion 11 and can exhibit the desired performance, there are no particular restrictions on the method of joining the multiple semiconductor films. The multiple semiconductor films may, for example, be pn junctions, or multiple n-type semiconductor films with different carrier concentrations may be joined, or multiple p-type semiconductor films with different carrier concentrations may be joined.

[0031] Since the semiconductor layer 10 of the semiconductor device 100 of this disclosure has a mesa structure, it is particularly advantageous if it is formed by joining multiple semiconductor films with different carrier concentrations containing gallium oxide (Ga2O3), which is difficult to obtain as a p-type semiconductor. The reason for this is as described above.

[0032] <First insulating layer> The first insulating layer 20 has an opening 21. The opening 21 communicates with the upper surface 11a of the mesa portion 11. In the embodiments shown in Figures 1A and B, the opening 21 communicates with a part of the upper surface 11a of the mesa portion 11, but is not limited to this, and may communicate with the entire upper surface 11a of the mesa portion 11. That is, the opening 21 communicates with at least a part of the upper surface of the mesa portion 11. The opening 21 is usually one, but is not limited to this, and may be multiple.

[0033] Furthermore, the first insulating layer 20 exists along the upper surface 11a and side surface 11b of the mesa portion 11 and the upper surface 10a of the semiconductor layer 10 other than the mesa portion 11. "Existing" means that the first insulating layer 20 is in contact with or bonded to the mating surface in order for the semiconductor device 100 to function. "Along" means that, with respect to the first insulating layer 20, the shape of the contact surface with the mating surface is traced on the side opposite to the contact surface with the mating surface. That is, the corners and edges of the contact surface with the mating surface are also traced on the side opposite to the contact surface with the mating surface. In this specification, unless otherwise specified, "existing" and "along" are used interchangeably.

[0034] The material constituting the first insulating layer 20 is not particularly limited, as long as it does not hinder the securing of the dielectric strength of the semiconductor device 100 and does not hinder the normal functioning of the field plate electrode 40. As the material constituting the first insulating layer 20, well-known insulating materials used in conventional semiconductor devices having a field plate structure can be used. Examples of such insulating materials include silicon dioxide (SiO2) and aluminum oxide (Al2O3). These may be combined. From the viewpoint of securing dielectric strength, silicon dioxide (SiO2) is preferred, and when combined with insulating materials other than silicon dioxide (SiO2), a high proportion of silicon dioxide (SiO2) is preferred. In addition to the insulating material, the first insulating layer 20 may contain materials that improve properties other than dielectric strength, such as materials that improve heat resistance and / or corrosion resistance, as well as unavoidable impurities. From the viewpoint of securing dielectric strength, it is preferable that the first insulating layer 20 contains 85% by mass or more, 90% by mass or more, or 95% by mass or more of the insulating material.

[0035] The thickness t1 of the first insulating layer 20 can be appropriately determined so as not to cause electric field concentration and a decrease in breakdown voltage in areas other than the vicinity of the outer peripheral edge 45 of the field plate electrode 40, particularly near the base of the mesa portion 11 of the semiconductor layer 10. The thickness t1 of the first insulating layer 20 may be, for example, 0.8 μm or more, 1.0 μm or more, or 1.2 μm or more, and may be 3.2 μm or less, 2.4 μm or less, 2.0 μm or less, or 1.6 μm or less. The thickness t1 of the first insulating layer 20 is the distance between the contact surface of the first insulating layer 20 and the semiconductor layer 10 other than the mesa portion 11, and the surface opposite to that contact surface.

[0036] <Second insulating layer> The second insulating layer 30 is located on the upper surface 22a of the outer peripheral edge 22 of the first insulating layer 20. The outer peripheral edge 22 of the first insulating layer 20 is the edge opposite to the opening 21. Furthermore, "located" means that the first insulating layer 20 and the second insulating layer 30 function as a substantially integrated insulating layer, and that the second insulating layer 30 is in contact with or bonded to the other layer so that the semiconductor device 100 can function.

[0037] The second insulating layer 30 should be positioned such that the distance x1 (see Figures 1A and 1B) between the side surface 11b of the mesa portion 11 and the inner circumferential side surface 30b of the second insulating layer 30 is greater than the thickness t1 of the first insulating layer 20. The length of x1 may be, for example, 4 μm or more, 5 μm or more, 6 μm or more, 7 μm or more, or 8 μm or more, and may be 10 mm or less, 5 mm or less, 1 mm or less, 500 μm or less, 100 μm or less, 50 μm or less, 40 μm or less, 30 μm or less, 20 μm or less, or 10 μm or less.

[0038] The material constituting the second insulating layer 30 is similar to the material constituting the first insulating layer 20 described above, but the material constituting the second insulating layer 30 may be the same as the material constituting the first insulating layer 20, or it may be different from the material constituting the first insulating layer 20.

[0039] The thickness t2 of the second insulating layer 30 can be appropriately determined, taking into account the thickness t1 of the first insulating layer 20, so as to favorably reduce the electric field strength near the outer edge 45 of the field plate electrode 40. The thickness t2 of the second insulating layer 30 may be, for example, 0.8 μm or more, 1.0 μm or more, 1.2 μm or more, or 1.4 μm or more, and may be 10.0 μm or less, 5.0 μm or less, 3.2 μm or less, 2.4 μm or less, 2.0 μm or less, or 1.6 μm or less. The thickness t2 of the second insulating layer 30 is the distance between the contact surface of the first insulating layer 20 and the second insulating layer 30 and the surface opposite to that contact surface.

[0040] <Field plate electrode> The field plate electrode 40 has a protrusion 41 inside the opening 21 of the first insulating layer 20. The tip 41a of the protrusion 41 is in contact with the upper surface 11a of the mesa portion 11, ensuring electrical conductivity with the mesa portion 11. In the embodiments shown in Figures 1A and 1B, the field plate electrode 40 extends from the protrusion 41 along the upper surface 20a and side surface 20b of the first insulating layer 20, and along the inner circumferential side surface 30b of the second insulating layer 30.

[0041] The field plate electrode 40 is in contact with the inner circumferential surface 30b of the second insulating layer 30. This makes it possible to reduce the electric field strength near the outer circumferential edge 45 of the field plate electrode 40.

[0042] As shown in Figures 2A and 2B, the field plate electrode 40 may also be located along at least a portion of the upper surface 30a of the second insulating layer 30, which extends from the inner circumferential side surface 30b of the second insulating layer 30. In the embodiments shown in Figures 2A and 2B, the field plate electrode 40 is located along a portion of the upper surface 30a of the second insulating layer 30, which extends from the inner circumferential side surface 30b of the second insulating layer 30, but it may also be located along the entire upper surface 30a of the second insulating layer 30, which extends from the inner circumferential side surface 30b of the second insulating layer 30.

[0043] If the field plate electrode 40 is located along a portion of the upper surface 30a of the second insulating layer 30 that extends from the inner circumferential side surface 30b of the second insulating layer 30, then "along a portion of the upper surface 30a of the second insulating layer 30 that extends from the inner circumferential side surface 30b of the second insulating layer 30" means that the field plate electrode 40 is located on the inner circumferential side surface 30b of the upper surface 30a of the second insulating layer 30, and not on the outer circumferential side surface 30c. In this case as well, "along" means what was described above.

[0044] The degree of overlap between the field plate electrode 40 and the upper surface 30a of the second insulating layer 30 is expressed by the distance between the inner circumferential side surface 30b of the second insulating layer 30 and the outer circumferential end 45 of the field plate electrode 40 at the upper surface 30a of the second insulating layer 30 (the contact surface between the second insulating layer 30 and the field plate electrode 40). This distance is indicated by x2 in Figures 2A and 2B. x2 may also be referred to as the overlap length of the field plate electrode.

[0045] Even when the value of x2 increases, the increase in electric field strength near the outer edge 45 of the field plate electrode 40 is only slight. If x2 is 5.0 μm or less, 4.0 μm or less, 3.0 μm or less, or 2.0 μm or less, the increase in electric field strength is not a practical problem. If it is particularly desirable to reduce the electric field strength near the outer edge 45 of the field plate electrode 40, it is advantageous if x2 is 1.0 μm or less.

[0046] There are no particular restrictions on the materials that constitute the field plate electrode 40, as long as they do not impair its function as a field plate electrode 40. Examples of materials that constitute the field plate electrode include gold (Au), titanium (Ti), and nickel (Ni), and these may be combined. When combining these, each may be used as a separate layer, and these layers may be stacked. The field plate electrode 40 may contain materials that improve properties other than conductivity, such as heat resistance and / or corrosion resistance, as well as unavoidable impurities. From the viewpoint of ensuring conductivity, it is preferable that the field plate electrode 40 contains 85% by mass or more, 90% by mass or more, or 95% by mass or more of the electrode material.

[0047] <Bottom electrode> The semiconductor device 100 is provided with a bottom electrode 50 on the lower surface 10b of the semiconductor layer 10. There are no particular restrictions on the bottom electrode 50 as long as it does not impair the performance of the semiconductor device 100. A well-known bottom electrode used in conventional semiconductor devices having a field plate structure can be used.

[0048] 《Manufacturing method》 The semiconductor manufacturing method of this disclosure includes forming a first insulating layer, a second insulating layer, and a field plate electrode in the semiconductor layer having a mesa portion, in that order. The method for forming the semiconductor layer having a mesa portion can be a method used in a well-known method for manufacturing a semiconductor device having a mesa structure. For example, refer to Patent Document 1.

[0049] As mentioned in the section on "Semiconductor Layers" in "Semiconductor Devices," it is advantageous for semiconductor layers having a mesa structure to contain gallium oxide.

[0050] The formation of the first insulating layer, the second insulating layer, and the field plate electrode will be explained below with reference to the drawings.

[0051] <Formation of the first insulating layer> Figure 3 is a schematic longitudinal cross-sectional view showing one aspect of the state before the formation of the first insulating layer. For reference, the first insulating layer after formation is shown by a dashed line.

[0052] Before forming the first insulating layer 20, the first masking member 61 is placed in the area where communication of the opening 21 is planned. In this state, the first insulating layer 20 is formed.

[0053] There are no particular restrictions on the method for forming the first insulating layer 20, as long as it can be formed along the shape of the mesa portion 11. Examples of such formation methods include methods for forming the insulating layer of conventional semiconductor devices having a field plate structure, such as atomic deposition and CVD. From the viewpoint of forming the first insulating film along the shape of the mesa portion 11, the CVD method is preferred.

[0054] The first masking member 61 can mask areas where the first insulating layer 20 is not intended to be formed during the formation of the first insulating layer 20, and there are no particular limitations as long as the masked areas are not damaged when the first masking member 61 is removed. Areas where the first insulating layer 20 is not intended to be formed refer to areas where communication of the opening 21 is intended. Examples of the first masking member include members made of metal (including alloys), inorganic materials other than metal (including alloys), and / or resin materials. These may be combined.

[0055] <Formation of the second insulating layer> Figure 4 is a schematic longitudinal cross-sectional view showing one aspect of the state before the formation of the second insulating layer. For reference, the second insulating layer after formation is shown by a dashed line.

[0056] Before forming the second insulating layer 30, the second masking member 62 is installed on all surfaces except the upper surface 22a of the outer peripheral edge 22 of the first insulating layer 20. The upper surface 22a of the outer peripheral edge 22 of the first insulating layer 20 is the area where the second insulating layer 30 will be formed. In this state, the second insulating layer 30 is formed.

[0057] There are no particular restrictions on the method for forming the second insulating layer 30. Examples of methods for forming the second insulating layer 30 include conventional methods for forming the insulating layer of semiconductor devices having a field plate structure, such as atomic deposition and CVD.

[0058] The second masking member 62 can mask areas where the second insulating layer 30 is not intended to be formed during the formation of the second insulating layer 30, and there are no particular restrictions on the second masking member 62 as long as it does not damage the masked areas when it is removed. Areas where the second insulating layer 30 is not intended to be formed mean areas other than the upper surface 22a of the outer peripheral edge 22 of the first insulating layer 20. Examples of the second masking member 62 include members made of metal (including alloys), inorganic materials other than metal (including alloys), and / or resin materials. These may be combined.

[0059] <Formation of field plate electrodes> Figure 5 is a schematic longitudinal cross-sectional view showing one aspect of the state before the formation of the field plate electrode. For reference, the field plate electrode after formation is shown by a dashed line.

[0060] Before forming the field plate electrode 40, the first masking member 61 and the second masking member 62 are removed, and the third masking member 63 is placed on the upper surface 30a of the second insulating layer 30. In this state, the field plate electrode 40 is formed.

[0061] Before forming the field plate electrode 40, once the state shown in Figure 5 is reached, the first masking member 61 and the second masking member 62 may be removed and then the third masking member 63 may be installed on the upper surface 30a of the second insulating layer 30, or the third masking member 63 may be installed on the upper surface 30a of the second insulating layer 30 and then the first masking member 61 and the second masking member 62 may be removed.

[0062] There are no particular restrictions on the method of forming the field plate electrode 40, as long as the field plate electrode 40 can be formed along the upper surface 20a and side surface 20b of the first insulating layer 20 and along the inner circumferential side surface 30b of the second insulating layer. Since the first insulating layer 20 is very thin, when forming the field plate electrode 40 along the upper surface 20a and side surface 20b of the first insulating layer 20 and along the inner circumferential side surface 30b of the second insulating layer 30, the protrusion 41 can be formed at the same time, but the protrusion 41 may be formed separately.

[0063] Methods for forming the field plate electrode 40 include methods for forming the field plate electrode of a conventional semiconductor device having a field plate structure. Examples of such formation methods include electron beam deposition, resistance heating deposition, and sputtering.

[0064] The third masking member 63 can mask areas where the field plate electrode 40 is not intended to be formed during the formation of the field plate electrode 40, and there are no particular limitations as long as the masked area is not damaged when the third masking member is removed. The area where the field plate electrode 40 is not intended to be formed refers to the upper surface 30a of the second insulating layer 30. Examples of the third masking member 63 include members made of metal (including alloys), inorganic materials other than metal (including alloys), and / or resin materials. These may be combined.

[0065] In the embodiment shown in Figure 5, the semiconductor device shown in Figures 1A and 1B can be obtained.

[0066] Figure 6 is a schematic longitudinal cross-sectional view showing another aspect (different from Figure 5) of the state before the formation of the field plate electrode. For reference, the formed field plate electrode is shown by a dashed line. The following describes the aspects of the aspect shown in Figure 6 that differ from the aspect shown in Figure 5.

[0067] In the configuration shown in Figure 6, regarding the installation of the third masking member 63, the third masking member 63 is installed on the upper surface 30a of the second insulating layer 30, excluding at least a portion of the upper surface 30a of the second insulating layer 30 that extends from the inner circumferential side surface 30b of the second insulating layer 30. Then, in this state, the field plate electrode 40 is formed. As a result, the field plate electrode 40 is located along at least a portion of the upper surface 30a of the second insulating layer 30 that extends from the inner circumferential side surface 30b of the second insulating layer 30. That is, a semiconductor device in the configuration shown in Figures 2A and 2B can be obtained.

[0068] <Formation of the lower electrode> A bottom electrode 50 is formed on the bottom surface 10b of the semiconductor layer 10. The bottom electrode 50 may be formed before the formation of the first insulating layer 20, or it may be formed after the formation of the first insulating layer 20, the second insulating layer 30, and the field plate electrode 40. Alternatively, the bottom electrode 50 may be formed after the formation of the first insulating layer 20 but before the formation of the second insulating layer 30. Alternatively, the bottom electrode 50 may be formed after the formation of the second insulating layer 30 but before the formation of the field plate electrode.

[0069] Methods for forming the bottom electrode 50 include methods for forming the bottom electrode of a conventional semiconductor device having a field plate structure. Examples of such formation methods include electron beam deposition, resistance heating deposition, and sputtering.

[0070] 《Transformation》 On the surface of the semiconductor layer 10 (including the mesa portion 11), there may be localized areas where the first insulating layer 20 is not intended to be formed, as long as this does not significantly impair the function of the semiconductor device 100 of this disclosure. Similarly, on the surface of the first insulating layer 20, there may be localized areas where the second insulating layer 30 is not intended to be formed, as long as this does not significantly impair the function of the semiconductor device 100 of this disclosure. On the surface of the second insulating layer 30, in addition to the areas already described, there may be localized areas where the field plate electrodes are not intended to be formed, as long as this does not significantly impair the function of the semiconductor device 100 of this disclosure. Examples of such localized areas include areas where through holes for inserting electrical wiring members, etc. To provide such localized areas, the first insulating layer 20, the second insulating layer 30, and / or the field plate electrodes 40 are formed after installing additional masking members. [Examples]

[0071] The semiconductor device and its manufacturing method described herein will be further described in detail below with reference to examples and comparative examples. However, the semiconductor device and its manufacturing method described herein are not limited to the conditions used in the following examples.

[0072] Sample preparation A sample of semiconductor device 100 having the structure shown in Figures 2A and 2B was prepared. The semiconductor layer 10 having the mesa portion 11 is made of gallium oxide (Ga2O3) and has a doping density of 5 × 10⁻¹⁶. 16 cm -3 The height of the mesa portion 11 was 2.5 μm. The first insulating layer 20 and the second insulating layer 30 were formed by depositing silicon dioxide (SiO2) onto the semiconductor layer 10 having the mesa portion 11.

[0073] The t1 and t2 and x1 and x2 of each sample were as shown in Table 1. A t2 of 0 μm means that the semiconductor device 100 does not have a second insulating layer 30. Also, a x2 of 0 means that the field plate electrode 40 does not come into contact with the upper surface 30a of the second insulating layer 30, that is, the semiconductor device 100 has the structure shown in Figures 1A and 1B.

[0074] The sample in Reference Example 1 of Table 1 is a semiconductor device that does not have an insulating layer, i.e., does not have a field plate structure, and has an upper electrode positioned on the upper surface of the mesa portion.

[0075] Evaluation Method and Results The breakdown voltage was measured by applying a reverse bias to the semiconductor device 100 of each sample. Furthermore, the electric field strength at the outer edge 45 of the field plate electrode 40 was measured when the applied reverse bias was 1200V. For the semiconductor device of Reference Example 1, the electric field strength at the outer edge of the top electrode was measured when the applied reverse bias was 1200V. Additionally, the electric field strength distribution for each semiconductor device when the applied reverse bias was 1200V was numerically calculated.

[0076] The results are shown in Table 1 and Figures 7 to 10. Figure 7 is a graph showing the relationship between breakdown voltage and electric field strength at the outer edge of the field plate electrode for each semiconductor device sample. The electric field strength at the outer edge of the field plate electrode was measured when the applied reverse bias was 1200V. Figure 8 is a longitudinal cross-sectional view showing the results of numerical calculation of the electric field strength distribution for the semiconductor device of Reference Example 1. Figure 9 is a longitudinal cross-sectional view showing the results of numerical calculation of the electric field strength distribution for the semiconductor device of Comparative Example 5. Figure 10 is a longitudinal cross-sectional view showing the results of numerical calculation of the electric field strength distribution for the semiconductor device of Example 6.

[0077] [Table 1]

[0078] Table 1 and Figure 7 show that in the semiconductor devices 100 of Examples 1 to 7, which are equipped with a second insulating layer 30, the electric field strength near the outer peripheral edge 45 of the field plate electrode 40 can be reduced while maintaining voltage resistance. Furthermore, it was confirmed that increasing the thickness of the second insulating layer 30 can further reduce the electric field strength near the outer peripheral edge 45 of the field plate electrode 40 while maintaining voltage resistance.

[0079] On the other hand, in the semiconductor devices of Comparative Examples 1 to 5, which do not have a second insulating layer 30, it was confirmed that both the breakdown voltage and the electric field strength near the outer edge 45 of the field plate electrode 40 decreased with increasing thickness of the first insulating layer. Furthermore, it was confirmed that the semiconductor device of Reference Example 1 has very low breakdown voltage because it does not have a field plate structure.

[0080] From Figure 8, it can be seen that in the semiconductor device of Reference Example 1, there is no field plate structure, and electrodes are placed on the upper surface of the mesa portion. As a result, electric field concentration occurs near the base of the mesa portion, which significantly reduces the breakdown voltage.

[0081] From Figure 9, it can be seen that in the main conductor device of Comparative Example 5, although the field plate structure mitigates electric field concentration near the mesa, electric field concentration still occurs near the outer edge of the field plate electrode. From this, it can be seen that although the breakdown voltage of the semiconductor device of Comparative Example 5 is significantly improved compared to the semiconductor device of Reference Example 1, it does not quite reach the desired breakdown voltage.

[0082] In the semiconductor device of Example 6, it can be seen from Table 1 that the reduction in electric field strength at the outer edge of the field plate electrode is very good. Furthermore, referring to Figures 2B and 10, it can be seen that the electric field strength at the outer edge 45 of the field plate electrode 40 and the electric field strength at the side in contact with the inner side surface 30b of the second insulating layer 30 have equivalent electric field strengths. This is thought to be due to the small overlap distance x2 of the field plate electrode 40 being 1.0 μm in the semiconductor device of Example 6. From this, it is considered preferable to make x2 smaller if it is particularly desirable to reduce the electric field strength at the outer edge 45 of the field plate electrode 40.

[0083] Based on the above results, the effectiveness of the semiconductor device and its manufacturing method described herein was confirmed. [Explanation of Symbols]

[0084] 10 Semiconductor Layers 11 Mesa 20 First insulating layer 22 Outer edge 21 Opening 30 Second insulating layer 40 Field plate electrodes 45 Outer edge 50 Bottom electrode 100 Semiconductor Devices

Claims

1. A semiconductor layer having a mesa portion on its upper surface, A first insulating layer having an opening that communicates with the upper surface of the mesa portion, and an opening that is located along the upper surface of the semiconductor layer other than the mesa portion, The second insulating layer located on the upper surface of the outer edge of the first insulating layer, The opening has a protrusion that ensures electrical conductivity with the mesa portion, and the field plate electrode is located along the upper surface and side surface of the first insulating layer and the inner circumferential side surface of the second insulating layer, A method for manufacturing a semiconductor device, comprising: The first insulating layer, the second insulating layer, and the field plate electrode are formed in this order on the semiconductor layer having the mesa portion. Before forming the first insulating layer, a first masking member is installed in the area where communication of the opening is planned. Before forming the second insulating layer, the second masking member is installed on a surface other than the upper surface of the outer edge of the first insulating layer, and Before forming the field plate electrode, remove the first masking member and the second masking member, and install the third masking member on the upper surface of the second insulating layer. A method for manufacturing a semiconductor device, including the method described above.

2. A semiconductor layer having a mesa portion on its upper surface, A first insulating layer having an opening that communicates with the upper surface of the mesa portion, and an opening that is located along the upper surface of the semiconductor layer other than the mesa portion, The second insulating layer located on the upper surface of the outer edge of the first insulating layer, The opening has a protrusion that ensures electrical conductivity with the mesa portion, and the field plate electrode is located along the upper surface and side surface of the first insulating layer and the inner circumferential side surface of the second insulating layer, Equipped with, A method for manufacturing a semiconductor device, wherein the field plate electrode is further located along at least a portion of the upper surface of the second insulating layer, extending from the inner circumferential side surface of the second insulating layer, The first insulating layer, the second insulating layer, and the field plate electrode are formed in this order on the semiconductor layer having the mesa portion. Before forming the first insulating layer, a first masking member is installed in the area where communication of the opening is planned. Before forming the second insulating layer, the second masking member is installed on a surface other than the upper surface of the outer edge of the first insulating layer, and Before forming the field plate electrode, remove the first masking member and the second masking member, and install a third masking member on the upper surface of the second insulating layer, excluding at least a portion of the upper surface of the second insulating layer that extends from the inner circumferential side surface of the second insulating layer. A method for manufacturing a semiconductor device, including the method described above.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the semiconductor layer contains gallium oxide.

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