Multilayer ceramic electronic components

Abstract

Provided is a layered ceramic electronic component in which peeling between ceramic layers is prevented.　This layered ceramic electronic component 10 comprises: a layered body 12 comprising a plurality of layered ceramic layers 14 and a plurality of layered inner electrode layers 16, the layered body including a first main surface 12a and a second main surface 12b which face each other in a layering direction x, a first side surface 12c and a second side surface 12d which face each other in a width direction y that is orthogonal to the layering direction x, and a first end surface 12e and a second end surface 12f which face each other in a length direction z that is orthogonal to the layering direction x and the width direction y; and a plurality of outer electrodes 30. The layered ceramic electronic component is characterized in that: the plurality of inner electrode layers 16 include first inner electrode layers 16a that are layered alternately with the plurality of ceramic layers 14 and that are exposed to the first end surface 12e and the second end surface 12f, and second inner electrode layers 16b that are layered alternately with the plurality of ceramic layers 14 and that are exposed to the first side surface 12c and the second side surface 12d; the first inner electrode layers 16a and the second inner electrode layers 16b are disposed spaced apart from each other, and further include dummy electrodes 40 that are exposed from one of the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d; the plurality of outer electrodes 30 comprise a first outer electrode 30a and a second outer electrode 30b that are connected to the first inner electrode layers 16a, and a third outer electrode 30c and a fourth outer electrode 30d that are connected to the second inner electrode layers 16b; and in each of the dummy electrodes 40, a region 44 that is spaced apart from an exposed portion 42 of the dummy electrode 40 by at least 50% toward the center of the layered body 12 exhibits a conductive component wire coverage of less than 50%.

Description

[Technical Field]

[0001] This invention relates to multilayer ceramic electronic components. [Background technology]

[0002] In recent years, with the increasing performance of mobile phones and other devices such as smartphones, there has been a demand for miniaturization of multilayer ceramic electronic components. For example, a multilayer ceramic capacitor is a multilayer ceramic electronic component in which internal electrode layers and ceramic layers are alternately stacked, and the desired capacitance is obtained depending on the number of layers and the thickness of the ceramic layers.

[0003] Patent Document 1 discloses a multilayer ceramic capacitor having an element body (laminated structure) in which dielectric layers (ceramic layers) and internal electrode layers are alternately stacked.

[0004] However, in the structure of the multilayer ceramic capacitor described in Patent Document 1, the planar area of ​​the internal electrode layer is smaller than the planar area of ​​the ceramic layer, and a step is formed between the peripheral edge of the internal electrode layer and the ceramic layer, excluding the portion of the internal electrode layer that extends to the end face of the element body. This step causes the internal electrode layer to bend, which can lead to problems such as short circuits between the internal electrode layers and a decrease in high-temperature load reliability. In particular, the thinner the dielectric layer (ceramic layer) and the more layers of the internal electrode layer and dielectric layer (ceramic layer) there are, the more likely short circuits between the internal electrode layers are to occur, and the lower the reliability tends to be.

[0005] Therefore, in order to resolve the above problems, it is known that a dummy electrode having a thickness equal to the step formed between the peripheral edge of the internal electrode layer and the ceramic layer, excluding the portion that is pulled out to the end face of the laminate of the internal electrode layer, is placed in the outer layer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2006-73623 [Overview of the project] [Problems that the invention aims to solve]

[0007] However, since current also flows through the dummy electrode, there is a problem in that the current path becomes longer and ESR and ESL increase. In addition, the presence of the dummy electrode weakens the adhesion between the ceramic layer and the dummy electrode, which may cause delamination between the ceramic layers.

[0008] Therefore, the present invention aims to provide a multilayer ceramic electronic component that prevents delamination between ceramic layers. [Means for solving the problem]

[0009] The multilayer ceramic electronic component according to this invention comprises a laminate including a plurality of stacked ceramic layers and a plurality of stacked internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, and a plurality of external electrodes, wherein the plurality of internal electrode layers are alternately stacked with the plurality of ceramic layers, and a first internal electrode layer exposed on the first end surface and the second end surface is alternately stacked with the plurality of ceramic layers, and the first The external electrode comprises a second internal electrode layer exposed on the side and a second side, a dummy electrode positioned spaced apart from the first internal electrode layer and the second internal electrode layer, and exposed from one of the first end face, the second end face, the first side, and the second side, and the plurality of external electrodes comprises a first external electrode and a second external electrode connected to the first internal electrode layer, and a third external electrode and a fourth external electrode connected to the second internal electrode layer, wherein in the dummy electrode, the region spaced 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate has a linear coverage of the conductive component of less than 50%.

[0010] According to the multilayer ceramic electronic component of this invention, in the dummy electrode, the area separated by more than 50% from the exposed portion of the dummy electrode toward the center of the laminate has a linear coverage of less than 50% of the conductive component. This allows the ceramic layers to be joined through the void, leading to improved bonding strength between ceramic layers and improved moisture resistance reliability. Furthermore, the void makes it difficult for current to flow to the tip of the dummy electrode, shortening the current path and thus reducing the ESL (Electromagnetic Slip Level). [Effects of the Invention]

[0011] This invention provides a multilayer ceramic electronic component that prevents delamination between ceramic layers.

[0012] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is an external perspective view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to this invention. [Figure 2] This is a top view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to this invention. [Figure 3] This is a front view showing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to this invention. [Figure 4] This is a cross-sectional view along line IV-IV in Figure 1. [Figure 5] This is a cross-sectional view along line VV shown in Figure 1. [Figure 6] This is a cross-sectional view along line VI-VI in Figure 4. [Figure 7] This is a cross-sectional view along line VII-VII in Figure 4. [Figure 8](a) It is an enlarged view of part C shown in FIG. 6, and is a diagram showing the configuration of the dummy electrode on the side surface of the laminate. (b) It is an enlarged view of part D shown in FIG. 7, and is a diagram showing the configuration of the dummy electrode on the end surface side of the laminate. [Figure 9] It is a diagram for explaining the measurement region of line coverage in the dummy electrode. [Figure 10] It is an enlarged view of part A shown in FIG. 4. [Figure 11] It is an enlarged view of part B shown in FIG. 5. [Figure 12] It is an enlarged view of part C shown in FIG. 6. [Figure 13] It is an enlarged view of part D shown in FIG. 7. [Figure 14] It is a diagram showing the printing patterns of the internal electrode layer and the dummy electrode in the manufacturing method of a multilayer ceramic capacitor, which is an example of the multilayer ceramic electronic component according to this invention. (a) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface, the second side surface, the first end surface, and the second end surface. (b) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface and the second side surface. (c) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first end surface and the second end surface.

Mode for Carrying Out the Invention

[0014] 1. Multilayer Ceramic Electronic Component A multilayer ceramic capacitor 10, which is an example of the multilayer ceramic electronic component according to this invention, will be described. FIG. 1 is an external perspective view showing a multilayer ceramic capacitor, which is an example of the multilayer ceramic electronic component according to this invention. FIG. 2 is a top view showing a multilayer ceramic capacitor, which is an example of the multilayer ceramic electronic component according to this invention. FIG. 3 is a [description incomplete in the original, but left as is] showing a multilayer ceramic capacitor, which is an example of the multilayer ceramic electronic component according to this invention. frontThis is a diagram. Figure 4 is a cross-sectional view along line IV-IV in Figure 1. Figure 5 is a cross-sectional view along line VV in Figure 1. Figure 6 is a cross-sectional view along line VI-VI in Figure 4. Figure 7 is a cross-sectional view along line VII-VII in Figure 4. Figure 8(a) is an enlarged view of section C in Figure 6, showing the configuration of the dummy electrode on the side of the laminate. Figure 8(b) is an enlarged view of section D in Figure 7, showing the configuration of the dummy electrode on the end face of the laminate. Figure 9 is a diagram illustrating the measurement area of ​​line coverage in the dummy electrode. Figure 10 is an enlarged view of section A in Figure 4. Figure 11 is an enlarged view of section B in Figure 5. Figure 12 is an enlarged view of section C in Figure 6. Figure 13 is an enlarged view of section D in Figure 7. Figure 14 shows the printing patterns of the internal electrode layer and dummy electrodes in a method for manufacturing a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component according to the present invention. (a) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface, second side surface, first end surface and second end surface. (b) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first side surface and second side surface. (c) is the printing pattern when manufacturing a multilayer ceramic capacitor having dummy electrodes exposed on the first end surface and second end surface.

[0015] The multilayer ceramic capacitor 10 includes a laminate 12 comprising a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14, and a plurality of external electrodes 30 connected to the internal electrode layers 16. The laminate 12 includes a first main surface 12a and a second main surface 12b facing the stacking direction x, a first side surface 12c and a second side surface 12d facing the width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f facing the length direction z perpendicular to the stacking direction x and the width direction y.

[0016] The length z dimension of the multilayer ceramic capacitor 10, which includes the laminated body 12 and the external electrode 30, is L. M Let it be the dimension. L MThe dimensions are preferably 0.4 mm to 1.6 mm. The width direction y dimension of the multilayer ceramic capacitor 10, including the laminate 12 and the external electrode 30, is W. M Let W be the dimension. M The dimensions are preferably 0.2 mm or more and 1.0 mm or less. The dimension in the stacking direction x of the multilayer ceramic capacitor 10, which includes the laminate 12 and the external electrode 30, is T M Use as dimensions. M The dimensions are preferably between 0.2 mm and 1.0 mm.

[0017] (Laminated structure) The laminate 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to the stacking direction x, a first side surface 12c and a second side surface 12d opposite to the width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to the length direction z perpendicular to the stacking direction x and the width direction y.

[0018] The laminate 12 has a rectangular parallelepiped shape. Preferably, the corners and edges of the laminate 12 are rounded. The corners are the parts where three adjacent faces of the laminate 12 intersect, and the edges are the parts where two adjacent faces of the laminate 12 intersect. In addition, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may have irregularities or other features formed on them.

[0019] The laminate 12 has an effective layer portion 15a in which a plurality of internal electrode layers 16 are arranged facing each other via a ceramic layer 14 in the stacking direction x connecting the first main surface 12a and the second main surface 12b; a first outer layer portion 15b1 formed from a plurality of ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 that is closest to the first main surface 12a among the plurality of internal electrode layers 16; and a second outer layer portion 15b2 formed from a plurality of ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 that is closest to the second main surface 12b among the plurality of internal electrode layers 16.

[0020] The first outer layer 15b1 is located on the side of the first main surface 12a of the laminate 12 and is an aggregate of multiple ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a.

[0021] The second outer layer 15b2 is located on the second main surface 12b side of the laminate 12 and is an aggregate of multiple ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b.

[0022] The region sandwiched between the first outer layer 15b1 and the second outer layer 15b2 is the effective layer 15a.

[0023] The laminate 12 has side portions (W gaps) 22a, 22b located between one end in the width direction y of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b, which will be described later, and the first side surface 12c, and between one end in the width direction y of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b, which will be described later, and the second side surface 12d, and includes the third pull-out portion 20c and the fourth pull-out portion 20d of the second internal electrode layer 16b.

[0024] Furthermore, the laminate 12 has ends (L gaps) 24a, 24b of the laminate 12, which include the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b, located between one end in the longitudinal direction z of the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b, located between one end in the longitudinal direction z of the first opposing portion 18b of the second internal electrode layer 16b, and the second end face 12f, and which include the first pull-out portion 20a and the second pull-out portion 20b of the first internal electrode layer 16a.

[0025] The ceramic layer 14 can be formed from, for example, a dielectric material. Examples of dielectric materials include dielectric ceramics composed of main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3. Alternatively, materials containing minor components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components may also be used.

[0026] The number of stacked ceramic layers 14 is not particularly limited, but it is preferable that there are 4 to 1000 layers, including the first outer layer 15b1 and the second outer layer 15b2. Furthermore, the thickness of the ceramic layer 14 is preferably 0.4 μm to 1.0 μm.

[0027] The dimensions of the laminate 12 are not particularly limited. The dimension in the longitudinal direction z connecting the first end face 12e and the second end face 12f of the laminate 12 is defined as dimension L. Dimension L is preferably 0.4 mm or more and 1.6 mm or less. The dimension in the width direction y connecting the first side surface 12c and the second side surface 12d of the laminate 12 is defined as dimension W. Dimension W is preferably 0.2 mm or more and 1.0 mm or less. The dimension in the lamination direction x connecting the first main surface 12a and the second main surface 12b of the laminate 12 is defined as dimension T. Dimension T is preferably 0.2 mm or more and 1.0 mm or less.

[0028] (Internal electrode layer) The internal electrode layer 16 comprises a first internal electrode layer 16a and a second internal electrode layer 16b.

[0029] The first internal electrode layer 16a is arranged on a plurality of ceramic layers 14. The first internal electrode layer 16a is also drawn out to a first end face 12e and a second end face 12f. The first internal electrode layer 16a has a first opposing portion 18a located inside the laminate 12, a first drawn-out portion 20a connected to the first opposing portion 18a and drawn out to the first end face 12e, and a second drawn-out portion 20b drawn out to the second end face 12f.

[0030] The shape of the first opposing portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0031] The shape of the first lead portion 20a and the second lead portion 20b of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0032] The second internal electrode layer 16b is arranged on a plurality of ceramic layers 14. The second internal electrode layer 16b is also drawn out to the first side surface 12c and the second side surface 12d. The second internal electrode layer 16b has a second opposing portion 18b located inside the laminate 12, a third drawn-out portion 20c connected to the second opposing portion 18b and drawn out to the first side surface 12c, and a fourth drawn-out portion 20d drawn out to the second side surface 12d.

[0033] The shape of the second opposing portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0034] The shape of the third and fourth lead-out portions 20c and 20d of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded or formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0035] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0036] Furthermore, the number of first internal electrode layers 16a is not particularly limited, but is preferably, for example, 1 to 500. The number of second internal electrode layers 16b is not particularly limited, but is preferably, for example, 1 to 500. The total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 2 to 1000.

[0037] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.4 μm or more and 0.8 μm or less. Furthermore, the thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.4 μm or more and 0.8 μm or less.

[0038] In this embodiment, capacitance is formed when the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b face each other via the ceramic layer 14, thereby exhibiting capacitor characteristics.

[0039] Furthermore, when piezoelectric ceramics are used in the laminate 12, the multilayer ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include, for example, PZT (lead zirconate titanate) based ceramic materials.

[0040] Furthermore, when semiconductor ceramics are used in the laminate 12, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include, for example, spinel-based ceramic materials.

[0041] Furthermore, when magnetic ceramic material is used for the laminate 12, the multilayer ceramic electronic component functions as an inductor element. When functioning as an inductor element, the internal electrode layer becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include, for example, ferrite ceramic material.

[0042] In other words, by appropriately changing the material and structure of the laminate 12, the multilayer ceramic electronic component according to this embodiment can function suitably not only as a multilayer ceramic capacitor 10, but also as a ceramic piezoelectric element, a thermistor element, or an inductor element.

[0043] (Dummy electrode) The dummy electrode 40 is positioned spaced apart from the first internal electrode layer 16a and the second internal electrode layer 16b, and is exposed from one of the first end face 12e, the second end face 12f, the first side surface 12c, and the second side surface 12d. When the dummy electrode 40 is exposed from one of the first end face 12e, the second end face 12f, the first side surface 12c, or the second side surface 12d, the step difference between the first internal electrode layer 16a and the second internal electrode layer 16b can be filled by the dummy electrode 40, thereby reducing the distortion of the internal electrode layer 16 and the ceramic layer 14 during pressing, and ensuring compaction.

[0044] In this embodiment, the dummy electrode 40 includes a first dummy electrode 40a, a second dummy electrode 40b, a third dummy electrode 40c, and a fourth dummy electrode 40d.

[0045] A first dummy electrode 40a is positioned on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is located, spaced apart from the first internal electrode layer 16a and exposed on the first side surface 12c. The first dummy electrode 40a faces the third lead-out portion 20c of the second internal electrode layer 16b via the ceramic layer 14.

[0046] The shape of the first dummy electrode 40a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0047] A second dummy electrode 40b is positioned on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is located, spaced apart from the first internal electrode layer 16a and exposed on the second side surface 12d. The second dummy electrode 40b faces the fourth lead-out portion 20d of the second internal electrode layer 16b via the ceramic layer 14.

[0048] The shape of the second dummy electrode 40b is not particularly limited, but it is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0049] A third dummy electrode 40c is positioned on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is located, spaced apart from the second internal electrode layer 16b and exposed to the first end face 12e. The third dummy electrode 40c faces the first pull-out portion 20a of the first internal electrode layer 16a via the ceramic layer 14.

[0050] The shape of the third dummy electrode 40c is not particularly limited, but it is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0051] A fourth dummy electrode 40d is positioned on the same plane as the ceramic layer 14 on which the second internal electrode layer 16b is located, spaced apart from the second internal electrode layer 16b and exposed on the second end face 12f. The fourth dummy electrode 40d faces the second pull-out portion 20b of the second internal electrode layer 16b via the ceramic layer 14.

[0052] The shape of the fourth dummy electrode 40d is not particularly limited, but it is preferably rectangular in plan view. However, the corners in plan view may be rounded or formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0053] It is preferable that the first dummy electrode 40a and the second dummy electrode 40b are exposed on at least one of the first side surface 12c and the second side surface 12d, while being on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is located. Furthermore, it is even more preferable that both the first side surface 12c and the second side surface 12d of the first dummy electrode 40a and the second dummy electrode 40b are exposed while being on the same plane as the ceramic layer 14 on which the first internal electrode layer 16a is located. This configuration makes it possible to reduce the strain that occurs when pressing the laminate 12.

[0054] It is preferable that the third dummy electrode 40c and the fourth dummy electrode 40d are coplanar with the ceramic layer 14 on which the second internal electrode layer 16b is located, and are exposed on at least one of the first end face 12e and the second end face 12f. Furthermore, it is even more preferable that the third dummy electrode 40c and the fourth dummy electrode 40d are coplanar with the ceramic layer 14 on which the second internal electrode layer 16b is located, and are exposed on both the first end face 12e and the second end face 12f. This configuration makes it possible to reduce the strain that occurs when pressing the laminate 12.

[0055] The dummy electrode 40 contains a conductive material as a conductive component. The conductive material of the dummy electrode 40 can be made of an appropriate conductive material such as metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0056] The dummy electrode 40 has an end region 44 of the dummy electrode 40 that is spaced at least 50% away from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12, with a linear coverage of 50% or less. For example, as shown in Figure 8(a), the first dummy electrode 40a has an end region 44a of the first dummy electrode 40a with a linear coverage of 50% or less, spaced at least 50% away from the exposed portion 42a of the first dummy electrode 40a toward the center of the laminate 12. Similarly, the second dummy electrode 40b has an end region 44b of the second dummy electrode 40b with a linear coverage of 50% or less, spaced at least 50% away from the exposed portion 42b of the second dummy electrode 40b toward the center of the laminate 12. Furthermore, as shown in Figure 8(b), the third dummy electrode 40c has a linear coverage of 50% or less in a region that is 50% or more away from the exposed portion 42c of the third dummy electrode 40c toward the center of the laminate 12. 3 Dummy electrode 40 cAn end region 44c is provided. Similarly, the fourth dummy electrode 40d has an end region 44d of the fourth dummy electrode 40d with a line coverage of 50% or less in a region that is 50% or more away from the exposed portion 42d of the fourth dummy electrode 40d toward the center of the laminate 12.

[0057] Here, line coverage refers to the ratio of the total length over which the conductive component of the dummy electrode actually exists to the total length of the dummy electrode 40.

[0058] Next, the method for measuring line coverage will be explained. First, in the case of the first dummy electrode 40a and the second dummy electrode 40b, polishing is performed up to 1 / 2 of the length direction z of the laminate 12 to expose the WT cross section. In the case of the third dummy electrode 40c and the fourth dummy electrode 40d, polishing is performed up to 1 / 2 of the width direction y of the laminate 12 to expose the LT cross section. Next, the WT cross section or LT cross section is photographed with a digital microscope (VHX manufactured by Keyence Corporation). Next, each cross section image is performed using image processing software (HALCON manufactured by MVTec Corporation) for image recognition. In the case of the WT cross section, it is preferable that the measurement area F be a square region of 5 μm in the width direction y and 30 μm in the stacking direction x. In the case of the LT cross section, it is preferable that the measurement area F be a square region of 5 μm in the length direction z and 30 μm in the stacking direction x. The coverage is calculated by the ratio of the total length where the conductive component of the dummy electrode actually exists to the total length of the dummy electrode 40 within that region. Therefore, a region with line coverage of 50% or less is a region where the ratio of the total length where the conductive component of the dummy electrode actually exists to the total length of the dummy electrode 40 is 50% or less. For example, Figure 9 shows the measurement region F1 to F of the line coverage of the first dummy electrode 40a in the WT cross section. N This indicates the measurement range F1 to F N In this method, the line coverage is measured by calculating the total length of the first dummy electrode 40a and the total length over which the conductive component of the first dummy electrode 40a exists.

[0059] By providing a region with less than 50% line coverage in the end region 44 of the dummy electrode, the ceramic layers 14 can be joined together via the gap 46, which improves the bonding strength between the ceramic layers 14 and enhances moisture resistance reliability. Additionally, the gap 46 makes it more difficult for current to flow to the tip of the end region 44 of the dummy electrode 40, shortening the current path and thus reducing the ESL (Electrode Stabilization Level). Furthermore, if moisture enters from the outside, selectively concentrating the moisture in the end region 44 of the dummy electrode 40, where the line coverage is less than 50%, ensures the moisture resistance reliability of the effective layer 15a.

[0060] Furthermore, it is preferable that the ratio of the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 is 50% or more and 80% or less. A ratio of 50% or more for the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 allows the ceramic layer 14 to be bonded through the void 46, resulting in improved bonding strength between the ceramic layers 14 and improved moisture resistance reliability. Additionally, when moisture penetrates from the outside, selective concentration of the moisture in the end region 44 of the dummy electrode 40, where the wire coverage is 50% or less, ensures the moisture resistance reliability of the effective layer portion 15a. Moreover, a ratio of 80% or less for the area of ​​the void 46 to the area of ​​the end region 44 of the dummy electrode 40 allows the void 46 to reach the tip of the end region 44 of the dummy electrode 40. Flow This has the effect of reducing ESL because it eliminates current flow and shortens the current path. On the other hand, the ratio of the area of ​​the gap 46 to the area of ​​the end region 44 of the dummy electrode 40 is 80%. Larger As a result, the thickness of the internal electrode layer 16 and the thickness of the dummy electrode 40 differ, and the step difference between the internal electrode layer 16 and the dummy electrode 40 becomes large. During pressing, this step difference is pressed in, causing localized areas where the thickness of the laminate 12 in the lamination direction x is thinner, which increases the risk of reduced moisture resistance reliability.

[0061] Here, let t1 be the thickness of the first internal electrode layer 16a in the stacking direction x, and t2 be the thickness of the second internal electrode layer 16b in the stacking direction x. Also, let t3 be the thickness of the first dummy electrode 40a in the stacking direction x, t4 be the thickness of the second dummy electrode 40b in the stacking direction x, t5 be the thickness of the third dummy electrode 40c in the stacking direction x, and t6 be the thickness of the fourth dummy electrode 40d in the stacking direction x.

[0062] It is preferable that the thicknesses t3, t4, t5, and t6 of the dummy electrode 40 are formed to be thinner than the thicknesses t1 and t2 of the internal electrode layer 16. More specifically, it is preferable that the thicknesses t3, t4, t5, and t6 of the dummy electrode 40 are 75% to 95% of the thicknesses t1 and t2 of the internal electrode layer 16. By setting the thicknesses t3, t4, t5, and t6 of the dummy electrode 40 to 75% to 95% of the thicknesses t1 and t2 of the internal electrode layer 16, the step difference can be sufficiently filled, and the distortion of the internal electrode layer 16 and the ceramic layer 14 during pressing can be reduced.

[0063] Furthermore, it is preferable that the length w1 in the width direction y of the laminate 12 of the first dummy electrode 40a exposed on the first side surface 12c is 50% to 60% of the length w3 in the width direction y of the laminate 12 of the third pull-out portion 20c of the second internal electrode layer 16b. By making the length w1 in the width direction y of the laminate 12 of the first dummy electrode 40a exposed on the first side surface 12c 50% to 60% of the length w3 in the width direction y of the laminate 12 of the third pull-out portion 20c of the second internal electrode layer 16b, the current path can be kept at an appropriate distance while reducing the strain generated when pressing the laminate 12. Similarly, it is preferable that the length w2 in the width direction y of the laminate 12 of the second dummy electrode 40b exposed on the second side surface 12d is 50% to 60% of the length w4 in the width direction y of the laminate 12 of the fourth pull-out portion 20d of the second internal electrode layer 16b. By setting the length w2 in the width direction y of the laminate 12 of the second dummy electrode 40b exposed on the second side surface 12d to 50% to 60% of the length w4 in the width direction y of the laminate 12 of the fourth pull-out portion 20d of the second internal electrode layer 16b, the current path can be kept at an appropriate distance while reducing the strain generated when pressing the laminate 12.

[0064] Furthermore, it is preferable that the central part M1 in the longitudinal direction z of the laminate 12 of the first dummy electrode 40a exposed on the first side surface 12c is located within 3% of the central part M in the longitudinal direction z of the laminate 12 of the second internal electrode layer 16b. This arrangement ensures that the dummy electrode 40 and the second internal electrode layer 16b are uniformly pressed together, which reduces the likelihood of structural defects such as peeling between the ceramic layers 14. Similarly, it is preferable that the central part M2 in the longitudinal direction z of the laminate 12 of the second dummy electrode 40b exposed on the second side surface 12d is located within 3% of the central part M in the longitudinal direction z of the laminate 12 of the second internal electrode layer 16b. This arrangement ensures that the dummy electrode 40 and the second internal electrode layer 16b are uniformly pressed together, which reduces the likelihood of structural defects such as peeling between the ceramic layers 14.

[0065] Furthermore, it is preferable that the length l1 in the longitudinal direction z of the laminate 12 of the third dummy electrode 40c exposed on the first end face 12e is 50% to 60% of the length l3 in the longitudinal direction z of the laminate 12 of the first pull-out portion 20a of the first internal electrode layer 16a. By making the length l1 in the longitudinal direction z of the laminate 12 of the third dummy electrode 40c exposed on the first end face 12e 50% to 60% of the length l3 in the longitudinal direction z of the laminate 12 of the first pull-out portion 20a of the first internal electrode layer 16a, the strain generated when pressing the laminate 12 can be reduced while maintaining an appropriate distance for the current path. Similarly, it is preferable that the length l2 in the longitudinal direction z of the laminate 12 of the fourth dummy electrode 40d exposed on the second end face 12f is 50% to 60% of the length l4 in the longitudinal direction z of the laminate 12 of the second pull-out portion 20b of the first internal electrode layer 16a. By setting the length l2 in the longitudinal direction z of the laminate 12 of the fourth dummy electrode 40d exposed on the second end face 12f to 50% to 60% of the length l4 in the longitudinal direction z of the laminate 12 of the second pull-out portion 20b of the first internal electrode layer 16a, the current path can be kept at an appropriate distance while reducing the strain generated when pressing the laminate 12.

[0066] Furthermore, it is preferable that the central portion N1 in the width direction y of the laminate 12 of the third dummy electrode 40c exposed on the first end face 12e is located within 3% of the central portion N in the width direction y of the laminate 12 of the first internal electrode layer 16a. This arrangement ensures that the dummy electrode 40 and the first internal electrode layer 16a are uniformly pressed, which reduces the likelihood of structural defects such as peeling between the ceramic layers 14. Similarly, it is preferable that the central portion N2 in the width direction y of the laminate 12 of the fourth dummy electrode 40d exposed on the second end face 12f is located within 3% of the central portion N in the width direction y of the laminate 12 of the first internal electrode layer 16a. This arrangement ensures that the dummy electrode 40 and the first internal electrode layer 16a are uniformly pressed, which reduces the likelihood of structural defects such as peeling between the ceramic layers 14.

[0067] (external electrode) The external electrode 30 includes a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0068] The first external electrode 30a is positioned on the first end face 12e and connected to the first internal electrode layer 16a. The first external electrode 30a may also be positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c and a portion of the second side surface 12d.

[0069] The second external electrode 30b is positioned on the second end face 12f and connected to the first internal electrode layer 16a. The second external electrode 30b may also be positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c and a portion of the second side surface 12d.

[0070] The third external electrode 30c is positioned on the first side surface 12c and connected to the second internal electrode layer 16b. The third external electrode 30c may also be positioned on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0071] The fourth external electrode 30d is positioned on the second side surface 12d and connected to the second internal electrode layer 16b. The fourth external electrode 30d may also be positioned on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0072] It is preferable that the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d each have a base electrode layer 32 and a plating layer 34.

[0073] In other words, it is preferable that the first external electrode 30a has a first base electrode layer 32a and a first plating layer 34a. It is preferable that the second external electrode 30b has a second base electrode layer 32b and a second plating layer 34b. It is preferable that the third external electrode 30c has a third base electrode layer 32c and a third plating layer 34c. It is preferable that the fourth external electrode 30d has a fourth base electrode layer 32d and a fourth plating layer 34d.

[0074] The base electrode layer 32 comprises a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d. The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0075] First, we will explain the case where the base electrode layer 32 is formed by a baking layer. The baking layer contains a glass component and a metal component. The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baking layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. Furthermore, the baking layer may consist of multiple layers.

[0076] The baked layer is formed by applying a conductive paste containing glass and metal components to the laminate 12 and baking it. The baked layer may be formed by simultaneously firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminate chip, or by firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 to obtain the laminate 12, and then applying and baking the conductive paste. When simultaneously firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminate chip, it is preferable to bake a product with ceramic components added instead of glass components.

[0077] The thickness in the longitudinal direction z connecting the first end face 12e and the second end face 12f of the first and second baked layers (end face center thickness) in the central part of the stacking direction x connecting the first main surface 12a and the second main surface 12b of the first and second baked layers located at the first end face 12e and the second end face 12f is preferably, for example, 5 μm or more and 30 μm or less.

[0078] Furthermore, if a baking layer is also provided on a part of the first main surface 12a or a part of the second main surface 12b, the thickness in the stacking direction x connecting the first main surface 12a and the second main surface 12b of the first and second baking layers, at the center of the length direction z connecting the first end face 12e and the second end face 12f of the first and second baking layers located on the first main surface 12a or the second main surface 12b, is preferably, for example, 5 μm or more and 10 μm or less.

[0079] Next, we will describe the case where the base electrode layer 32 is formed by a conductive resin layer. The conductive resin layer may be arranged on top of the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 12 without a baking layer. Furthermore, the conductive resin layer may completely cover the baking layer, or it may cover only a part of the baking layer. In addition, there may be multiple conductive resin layers.

[0080] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer consisting of, for example, a plated film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the multilayer ceramic capacitor 10.

[0081] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Alternatively, metal powder with an Ag coating on its surface can be used. When using metal powder with an Ag coating, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder is that Ag has the lowest resistivity among metals, making it suitable for electrode materials; and because Ag is a noble metal, it does not oxidize and has high weather resistance. Furthermore, it allows for the use of less expensive base metals while maintaining the above-mentioned properties of Ag.

[0082] Furthermore, the metals included in the conductive resin layer can be Cu or Ni that have been treated to prevent oxidation. Additionally, metal powders coated with Sn, Ni, or Cu can be used as the metals included in the conductive resin layer. When using metal powders coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0083] The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0084] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0085] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins.

[0086] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0087] The thickest part of the conductive resin layer is preferably, for example, 5 μm to 30 μm.

[0088] Next, we will describe the case where the underlying electrode layer 32 is formed by a thin film layer. When a thin film layer is provided as the underlying electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. The thin film layer is a layer of 1 μm or less in thickness, on which metal particles are deposited.

[0089] (Plating layer) The plating layer 34 includes a first plating layer 34a arranged to cover the first underlay electrode layer 32a, a second plating layer 34b arranged to cover the second underlay electrode layer 32b, a third plating layer 34c arranged to cover the third underlay electrode layer 32c, and a fourth plating layer 34d arranged to cover the fourth underlay electrode layer 32d.

[0090] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0091] Furthermore, the plating layer 34 may be formed by multiple layers. teethPreferably, the structure consists of two layers: Ni plating followed by Sn plating. The Ni plating layer prevents the underlying electrode layer 32 from being corroded by the solder used when mounting the multilayer ceramic capacitor 10. The Sn plating layer improves the wettability of the solder used when mounting the multilayer ceramic capacitor 10, making mounting easier.

[0092] Furthermore, the thickness of each layer of the plating layer 34 is preferably 4 μm or more and 10 μm or less.

[0093] The first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d, or each of them, may have a plating layer 34 directly formed on the surface of the laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure that includes a first internal electrode layer 16a and a plating layer 34 that is directly electrically connected to the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed directly after a catalyst is placed on the surface of the laminate 12 as a pretreatment.

[0094] When the plating layer 34 is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be converted into a lower profile, i.e., a thinner design, or into the thickness of the laminate 12, i.e., the thickness of the effective layer portion 15a, thereby improving the design flexibility of the thin chip.

[0095] When a plating layer 34 is directly formed on the laminate 12, it is preferable that the plating layer 34 includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode.

[0096] The lower plated electrode and the upper plated electrode preferably each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal.

[0097] The lower layer plating electrode is preferably formed using Ni, which has solder barrier properties. Furthermore, the upper layer plating electrode is preferably formed using Sn or Au, which have good solder wettability.

[0098] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plated electrode be formed using Cu, which has good bonding properties with Ni. The upper plated electrode may be formed as needed, and the first external electrode and the second external electrode may each consist only of the lower plated electrode.

[0099] When a plating layer 34 is directly formed on the laminate 12, the upper plating electrode may be the outermost layer of the plating layer 34, or other plating electrodes may be formed on the surface of the upper plating electrode.

[0100] When a plating layer 34 is directly formed on the laminate 12, the thickness of each layer of the plating layer 34 is preferably 4 μm or more and 10 μm or less.

[0101] When a plating layer 34 is directly formed on the laminate 12, it is preferable that the plating layer 34 does not contain glass. Furthermore, it is preferable that the metal content per unit volume of the plating layer 34 is 99% by volume or more.

[0102] In the multilayer ceramic capacitor 10 shown in Figure 1, in the dummy electrode 40, the region 44 that is more than 50% away from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12 has a linear coverage of less than 50% of the conductive component. With this configuration, the ceramic layers 14 can be joined via the air gap 46, thereby improving the bonding strength between the ceramic layers 14 and improving moisture resistance reliability. In addition, the air gap 46 prevents current from flowing to the tip of the dummy electrode 40, shortening the current path and leading to a reduction in ESL. Furthermore, if moisture enters from the outside, selectively concentrating the moisture in the end region 44 of the dummy electrode 40 where the linear coverage is 50% or less ensures the moisture resistance reliability of the effective layer portion 15a.

[0103] Furthermore, it is preferable that the dummy electrodes 40 (40a, 40b) of the multilayer ceramic capacitor 10 shown in Figure 1 are exposed on at least one of the first side surface 12c and the second side surface 12d on the ceramic layer 14 on which the first internal electrode layer 16a is located. This reduces the strain that occurs when pressing the laminate 12.

[0104] Furthermore, it is preferable that the dummy electrodes 40 (40c, 40d) of the multilayer ceramic capacitor 10 shown in Figure 1 are exposed on at least one of the first end face 12e and the second end face 12f on the ceramic layer 14 where the second internal electrode layer 16b is located. This reduces the strain that occurs when pressing the laminate 12.

[0105] Furthermore, it is preferable that the thicknesses t3, t4, t5, t6 of the dummy electrode 40 in the stacking direction x of the multilayer ceramic capacitor 10 shown in Figure 1 are smaller than the thicknesses t1, t2 of the first internal electrode layer 16a and the second internal electrode layer 16b in the stacking direction x. Moreover, it is preferable that the thicknesses t3, t4, t5, t6 of the dummy electrode 40 in the stacking direction x of the multilayer ceramic capacitor 10 shown in Figure 1 are 75% to 95% of the thicknesses t1, t2 of the first internal electrode layer 16a and the second internal electrode layer 16b in the stacking direction x. This allows the step difference (the difference between the thicknesses t3, t4, t5, t6 of the dummy electrode 40 in the stacking direction x and the thicknesses t1, t2 of the first internal electrode layer 16a and the second internal electrode layer 16b in the stacking direction x) to be sufficiently filled, and the distortion of the internal electrode layer 16 and the ceramic layer 14 during pressing can be reduced.

[0106] Furthermore, it is preferable that the lengths w1 and w2 in the width direction y of the laminated body 12 of the dummy electrodes 40a and 40b exposed on the first side surface 12c or the second side surface 12d of the multilayer ceramic capacitor 10 shown in Figure 1 are 50% to 60% of the lengths w3 and w4 in the width direction y of the laminated body 12 of the third lead-out portion 20c and the fourth lead-out portion 20d of the second internal electrode layer 16b. This makes it possible to reduce the distortion that occurs when pressing the laminated body 12 while maintaining an appropriate distance for the current path.

[0107] Furthermore, it is preferable that the central portions M1 and M2 in the longitudinal direction z of the laminated body 12 of the dummy electrodes 40a and 40b exposed on the first side surface 12c or the second side surface 12d of the multilayer ceramic capacitor 10 shown in Figure 1 are located within 3% of the central portion M in the longitudinal direction z of the laminated body 12 of the second internal electrode layer 16b exposed on the first side surface 12c or the second side surface 12d. This ensures that the dummy electrodes 40a and 40b and the second internal electrode layer 16b are uniformly pressed together, which reduces the likelihood of structural defects such as peeling between the ceramic layers 14.

[0108] Furthermore, in the dummy electrode 40 of the multilayer ceramic capacitor 10 shown in Figure 1, it is preferable that the ratio of the area of ​​the void 46 to the area of ​​the region 44 that is 50% or more away from the exposed portion 42 of the dummy electrode 40 toward the center of the laminate 12 is 50% or more and 80% or less. This allows the ceramic layer 14 to be joined through the void 46, which has the effect of improving the bonding strength between the ceramic layers 14 and improving moisture resistance reliability. In addition, when moisture enters from the outside, it selectively concentrates the moisture in the end region 44 of the dummy electrode 40 where the line coverage is 50% or less, thereby ensuring the moisture resistance reliability of the effective layer portion 15a. The void 46 prevents the current path from flowing to the tip of the end region 44 of the dummy electrode 40, shortening the current path, which has the effect of reducing the ESL.

[0109] 2. Manufacturing method of multilayer ceramic electronic components The following describes a method for manufacturing a multilayer ceramic capacitor 10, which is an example of a multilayer ceramic electronic component according to this invention.

[0110] First, prepare the dielectric sheet and the conductive paste for the internal electrodes and dummy electrodes. The dielectric sheet and the conductive paste for the internal electrodes and dummy electrodes contain a binder and a solvent. Known binders and solvents can be used.

[0111] Next, a conductive paste for the internal electrodes and dummy electrodes is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the patterns for the internal electrode layer and dummy electrodes formed on it. More specifically, by separately preparing a screen plate for printing the first internal electrode layer 16a and the first dummy electrode 40a and second dummy electrode 40b, and a screen plate for printing the second internal electrode layer 16b and the third dummy electrode 40c and fourth dummy electrode 40d, and using a printing machine that can print the two types of screen plates separately, the internal electrode layer 16 and dummy electrode 40 of the present invention can be printed as shown in Figure 14(a). Figure 14(a) shows the printed patterns of the internal electrode layer and dummy electrodes in this embodiment. In other words, by printing the pattern 80 of the first internal electrode layer 16a and the first dummy electrode 40a and the second dummy electrode 40b, and the pattern 82 of the second internal electrode layer 16b and the third dummy electrode 40c and the fourth dummy electrode 40d, and then cutting the laminate in a subsequent process along the cut line 90 shown by the dashed line in Figure 14(a), a laminate 12 having the first internal electrode layer 16a, the second internal electrode layer 16b, the first dummy electrode 40a, the second dummy electrode 40b, the third dummy electrode 40c and the fourth dummy electrode 40d can be manufactured.

[0112] In this embodiment, a first dummy electrode 40a, a second dummy electrode 40b, a third dummy electrode 40c, and a fourth dummy electrode 40d are present, but the embodiment is not limited thereto. That is, for example, if a first dummy electrode 40a and a second dummy electrode 40b are present, but a third dummy electrode 40c and a fourth dummy electrode 40d are not, a portion of the effective layer 15a that has a first dummy electrode 40a and a second dummy electrode 40b, but does not have a third dummy electrode 40c and a fourth dummy electrode 40d, can be formed by printing a first internal electrode layer 16a, a second internal electrode layer 16b, a first dummy electrode 40a, and a second dummy electrode 40b as shown in Figure 14(b). Furthermore, for example, if the first dummy electrode 40a and the second dummy electrode 40b are not present, but the third dummy electrode 40c and the fourth dummy electrode 40d are present, a portion of the effective layer 15a can be formed by printing the first internal electrode layer 16a, the second internal electrode layer 16b, the third dummy electrode 40c and the fourth dummy electrode 40d as shown in Figure 14(c), thereby eliminating the first dummy electrode 40a and the second dummy electrode 40b but including the third dummy electrode 40c and the fourth dummy electrode 40d.

[0113] Here, to obtain the desired structure, sheets printed with the internal electrode layer 16 and dummy electrode 40 are laminated to form the effective layer portion 15a. In this embodiment, the patterns of the internal electrode and dummy electrode are printed by gravure printing.

[0114] Next, a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked to form the first outer layer portion 15b1 on the first main surface 12a side. Subsequently, the portion that will become the effective layer portion 15a prepared above is stacked, and a predetermined number of dielectric sheets without printed internal electrode layer patterns are stacked on top of this effective layer portion 15a to form the second outer layer portion 15b2 on the second main surface 12b side. This completes the production of the laminated sheet.

[0115] Next, the laminated sheets are pressed in the lamination direction using means such as a hydrostatic press to produce a laminated block.

[0116] Next, the laminated block is cut to the specified size, and the laminated chips are cut out. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or other methods.

[0117] Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the ceramic and internal electrode materials, but it is preferably between 900°C and 1400°C.

[0118] A first base electrode layer 32a for the first external electrode 30a and a second base electrode layer 32b for the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12 obtained by firing. In addition, a third base electrode layer 32c for the third external electrode 30c and a fourth base electrode layer 32d for the fourth external electrode 30d are formed on the first side surface 12c and the second side surface 12d of the laminate 12 obtained by firing.

[0119] When forming a baked layer as the base electrode layer 32, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the base electrode layer 32. The temperature of this baking process is preferably 700°C to 900°C. In this embodiment, the base electrode layer 32 is formed by a baked layer.

[0120] Here, various methods can be used to form the baked layer as the base electrode layer 32. For example, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed by a method in which conductive paste is extruded from a slit and applied. In this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0121] Furthermore, it can also be formed using a roller transfer method. In the case of the roller transfer method, when forming the base electrode layer 32 not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, it is possible to form a third base electrode layer 32c and a fourth base electrode layer 32d on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during roller transfer.

[0122] Next, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12 obtained by firing. When forming a baked layer as a base electrode layer 32, the first base electrode layer 32a and the second base electrode layer 32b are formed in the same way as the third base electrode layer 32c and the fourth base electrode layer 32d, a conductive paste containing glass and metal components is applied, and then a baking treatment is performed to form the base electrode layer 32. The temperature of the baking treatment at this time is preferably 700°C to 900°C.

[0123] Here, various methods can be used to form the first base electrode layer 32a and the second base electrode layer 32b. For example, by using a method such as dipping, they can be formed to extend not only to the first end face 12e and the second end face 12f, but also to a part of the first main surface 12a and a part of the second main surface 12b, a part of the first side surface 12c and a part of the second side surface 12d.

[0124] In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are formed using the DIP method so as to extend not only to the first end face 12e and the second end face 12f, but also to a part of the first main surface 12a and a part of the second main surface 12b, a part of the first side surface 12c and a part of the second side surface 12d.

[0125] Furthermore, in this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are fired after the third base electrode layer 32c and the fourth base electrode layer 32d have been fired. However, the first base electrode layer 32a and the second base electrode layer 32b, as well as the third base electrode layer 32c and the fourth base electrode layer 32d, may be fired simultaneously.

[0126] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate by itself without forming a baking layer.

[0127] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto a baked layer or laminate, and then heat-treating it at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0128] The conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, such as a method of applying the conductive paste by extruding it through a slit or a roller transfer method.

[0129] When forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer 32 can be formed in the desired location by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness, in which metal particles are deposited.

[0130] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or it may be formed directly on the laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electrolytic plating is usually preferred.

[0131] As described above, the multilayer ceramic capacitor 10 shown in Figure 1 can be manufactured.

[0132] As described above, embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. In other words, without departing from the scope of the technical idea and objectives of the present invention, various changes can be made to the embodiments and each of the modifications described above in terms of mechanism, shape, material, quantity, position or arrangement, etc., and these are included in the present invention.

[0133] Furthermore, although this embodiment describes a three-terminal multilayer ceramic capacitor, it can also be used for, for example, a two-terminal multilayer ceramic electronic component. That is, a multilayer ceramic electronic component comprising a laminate including a ceramic layer and a plurality of internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the lamination direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the lamination direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the lamination direction and the width direction, and a plurality of external electrodes, wherein the plurality of internal electrode layers are alternately laminated with the plurality of ceramic layers, and a first internal electrode layer exposed on the first end surface and the second end surface, and a plurality of internal electrode layers alternately laminated with the plurality of ceramic layers and exposed on the first side surface and the second side surface. The multilayer ceramic electronic component has a second internal electrode layer, and further has a dummy electrode that is spaced apart from the first and second internal electrode layers and exposed from either the first or second end face, and the plurality of external electrodes comprises a first external electrode that is placed on the first end face and connected to the first internal electrode layer, and a second external electrode that is placed on the second end face and connected to the second internal electrode layer, and in the dummy electrode, the region that is spaced 50% or more away from the exposed part of the dummy electrode toward the center of the laminate has a linear coverage of the conductive component of less than 50%. This configuration prevents delamination between ceramic layers.

[0134] <1> A multilayer ceramic electronic component comprising a laminate including a plurality of stacked ceramic layers and a plurality of stacked internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, and a plurality of external electrodes, The plurality of internal electrode layers are The plurality of ceramic layers are alternately laminated, and a first internal electrode layer is exposed on the first end face and the second end face, The plurality of ceramic layers are alternately laminated, and a second internal electrode layer is exposed on the first side and the second side, It has, The present invention further comprises a dummy electrode, which is spaced apart from the first internal electrode layer and the second internal electrode layer, and is exposed from any of the first end face, the second end face, the first side, and the second side. The aforementioned multiple external electrodes are A first external electrode and a second external electrode connected to the first internal electrode layer, A third external electrode and a fourth external electrode connected to the second internal electrode layer, Equipped with, In the dummy electrode, the region that is 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate has a linear coverage of less than 50% of the conductive component. Multilayer ceramic electronic components. <2> The dummy electrode is, On the ceramic layer on which the first internal electrode layer is arranged, at least one of the first side surface and the second side surface is exposed. <1> Multilayer ceramic electronic components as described above. <3> The dummy electrode is, On the ceramic layer on which the second internal electrode layer is arranged, at least one of the first end face and the second end face is exposed. <1> or <2> Multilayer ceramic electronic components as described above. <4> The thickness of the dummy electrode in the stacking direction is smaller than the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction. <1> or <3> A multilayer ceramic electronic component as described in any one of the following. <5> The thickness of the dummy electrode in the stacking direction is 75% or more and 95% or less of the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction. <1> or <4> A multilayer ceramic electronic component as described in any one of the following. <6> The second internal electrode layer has a second opposing portion facing the first internal electrode layer, a third leading portion extending from the second opposing portion and leading out to the first side surface, and a fourth leading portion extending from the second opposing portion and leading out to the second side surface. The widthwise length of the laminate of the dummy electrodes exposed on the first or second side surface is 50% or more and 60% or less of the widthwise length of the laminate of the third pull-out portion of the second internal electrode layer and the fourth pull-out portion of the second internal electrode layer. <3> Multilayer ceramic electronic components as described above. <7> The central portion of the dummy electrode exposed on the first or second side surface in the longitudinal direction of the laminate is located within 3% of the central portion of the second internal electrode layer exposed on the first or second side surface in the longitudinal direction of the laminate. <1> or <6> A multilayer ceramic electronic component as described in any one of the following. <8> In the dummy electrode, the ratio of the area of ​​the void to the area of ​​the region that is 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate is 50% or more and 80% or less. <1> or <7> A multilayer ceramic electronic component as described in any one of the following. [Industrial applicability]

[0135] This invention relates to multilayer ceramic electronic components and can be used as a multilayer ceramic electronic component that prevents delamination between ceramic layers. [Explanation of Symbols]

[0136] 10 Multilayer ceramic capacitors 12-layer structure 12a First main surface 12b Second main surface 12c First side 12d Second aspect 12e First end face 12f Second end face 14 Ceramic Layer 15a Effective layer 15b1 First outer layer 15b2 Second outer layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a First opposing part 18b Second opposing section 20a First drawer section 20b Second drawer section 20c Third drawer 20d Fourth drawer 22a, 22b Side of the laminate (W gap) 24a, 24b End of the laminate (L gap) 30 External electrode 30a First external electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode layer 32a First underlay electrode layer 32b Second base electrode layer 32c Third Underlay Electrode Layer 32d Fourth underlay electrode layer 34 Plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 40 Dummy electrodes 40a First dummy electrode 40b Second dummy electrode 40c Third dummy electrode 40d Fourth dummy electrode 42 Exposed portion of dummy electrode 42a Exposed portion of the first dummy electrode 42b Exposed portion of the second dummy electrode 42c Exposed portion of the third dummy electrode 42d Exposed portion of the fourth dummy electrode 44 End region of dummy electrode End region of the first dummy electrode 44a End region of the second dummy electrode 44b End region of the third dummy electrode 44c End region of the fourth dummy electrode 44d Gap 46 Stacking direction x Width direction y Length direction z L M Length dimension of the multilayer ceramic capacitor in the length direction W M Width dimension of the multilayer ceramic capacitor in the width direction T M Stacking dimension of the multilayer ceramic capacitor in the stacking direction Length dimension L of the laminate in the length direction Width dimension W of the laminate in the width direction Stacking dimension T of the laminate in the stacking direction F1 to F N Measurement region Center portion M in the length direction of the second internal electrode layer Center portion M1 in the length direction of the first dummy electrode Center portion M2 in the length direction of the second dummy electrode Center portion N in the width direction of the first internal electrode layer Center portion N1 in the width direction of the third dummy electrode Center portion N2 in the width direction of the fourth dummy electrode Thickness t1 of the first internal electrode layer in the stacking direction Thickness t2 of the second internal electrode layer in the stacking direction Thickness t3 of the first dummy electrode in the stacking direction Thickness t4 of the second dummy electrode in the stacking direction Thickness t5 of the third dummy electrode in the stacking direction Thickness t6 of the fourth dummy electrode in the stacking direction Length w1 of the first dummy electrode in the width direction Length w2 of the second dummy electrode in the width direction Length w3 of the third lead-out portion in the width direction Length w4 of the fourth lead-out portion in the width direction Length l1 of the third dummy electrode in the length direction Length l2 of the fourth dummy electrode in the length direction l3 Length in the longitudinal direction of the first drawer l4 Length in the longitudinal direction of the second drawer section

Claims

1. A multilayer ceramic electronic component comprising a laminate including a plurality of stacked ceramic layers and a plurality of stacked internal electrode layers, the laminate including a first main surface and a second main surface facing each other in the stacking direction, a first side surface and a second side surface facing each other in the width direction perpendicular to the stacking direction, and a first end surface and a second end surface facing each other in the length direction perpendicular to the stacking direction and the width direction, and a plurality of external electrodes, The plurality of internal electrode layers are The plurality of ceramic layers are alternately laminated, and a first internal electrode layer is exposed on the first end face and the second end face, A second internal electrode layer is alternately laminated with the plurality of ceramic layers and is exposed on the first side and the second side, It has, The present invention further comprises a dummy electrode that is spaced apart from the first internal electrode layer and the second internal electrode layer and is exposed from any of the first end face, the second end face, the first side, and the second side, The aforementioned multiple external electrodes are A first external electrode and a second external electrode connected to the first internal electrode layer, The third external electrode and the fourth external electrode are connected to the second internal electrode layer, Equipped with, In the dummy electrode, the region that is 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate has a linear coverage of less than 50% of the conductive component. In the dummy electrode, the region less than 50% away from the exposed portion of the dummy electrode toward the center of the laminate has greater linear coverage of the conductive component than the region more than 50% away. Multilayer ceramic electronic components.

2. The dummy electrode is, The multilayer ceramic electronic component according to claim 1, wherein the first internal electrode layer is exposed on at least one of the first side surface and the second side surface on the ceramic layer on which the first internal electrode layer is disposed.

3. The dummy electrode is, The multilayer ceramic electronic component according to claim 1 or claim 2, wherein the second internal electrode layer is exposed on at least one of the first end face and the second end face on the ceramic layer on which the second internal electrode layer is disposed.

4. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the dummy electrode in the stacking direction is smaller than the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction.

5. The multilayer ceramic electronic component according to claim 1, wherein the thickness of the dummy electrode in the stacking direction is 75% or more and 95% or less of the thickness of the first internal electrode layer and the second internal electrode layer in the stacking direction.

6. The second internal electrode layer has a second opposing portion facing the first internal electrode layer, a third leading portion extending from the second opposing portion and leading out to the first side surface, and a fourth leading portion extending from the second opposing portion and leading out to the second side surface. The multilayer ceramic electronic component according to claim 3, wherein the length in the width direction of the laminate of the dummy electrodes exposed on the first side surface or the second side surface is 50% or more and 60% or less of the length in the width direction of the laminate of the third pull-out portion of the second internal electrode layer and the fourth pull-out portion of the second internal electrode layer.

7. The multilayer ceramic electronic component according to claim 1, wherein the central portion of the dummy electrode exposed on the first side or the second side of the laminate in the longitudinal direction is located within 3% of the central portion of the second internal electrode layer exposed on the first side or the second side of the laminate in the longitudinal direction.

8. The multilayer ceramic electronic component according to claim 1, wherein in the dummy electrode, the ratio of the area of ​​the void to the area of ​​the region that is 50% or more away from the exposed portion of the dummy electrode toward the center of the laminate is 50% or more and 80% or less.

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