Multi-chip modules and control devices

Abstract

To prevent a bypass capacitor from coming into contact with a mother substrate when a support substrate is fixed to the mother substrate without curving the support substrate, in a multi-chip module.SOLUTION: A multi-chip module 2 includes: a plurality of semiconductor components 12 to 18; a plurality of bypass capacitors 20; a plurality of connection terminals 30; and a support substrate 10. A support substrate is a multi-layer wiring substrate, a semiconductor component is provided on an upper surface thereof, and a bypass capacitor and a connection terminal are provided on a lower surface thereof. As a plurality of connection terminals, a first terminal group 32 arranged in a ring shape along an outer periphery of the support substrate and a second terminal group 34 arranged inside the ring are provided. The bypass capacitors are lower in height from the lower surface than the connection terminals and are provided in opposite regions 12A to 18A to the semiconductor components. Spacers 36 are provided in the opposite regions.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a multi-chip module in which a plurality of semiconductor components are provided on the upper surface of a substrate, and a control device including the multi-chip module.

Background Art

[0002] Patent Document 1 describes that in a multi-chip module, by adjusting the copper foil remaining rate of two layers of a multi-chip module substrate (hereinafter, a support substrate) which is a multilayer substrate, the support substrate can be curved. This is for forming a region where the distance between the lower surface of the support substrate and the mother substrate increases when the support substrate is fixed to the mother substrate.

[0003] That is, in the multi-chip module described in Patent Document 1, by providing a bypass capacitor in the above region on the lower surface of the support substrate, it is possible to suppress the bypass capacitor from contacting the mother substrate when the support substrate is fixed to the mother substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, as a result of the inventors' detailed examination, it has been found that the curved shape of the support substrate is not determined only by the copper foil remaining rate, but also changes depending on the weight of the semiconductor components provided on the support substrate, the arrangement of connection terminals electrically connected to the mother substrate, and the like.

[0006] In other words, when the support substrate described in Patent Document 1, which is a multi-chip module with semiconductor components on its upper surface and bypass capacitors on its lower surface, is fixed to a motherboard, its curved shape changes, and the bypass capacitors may come into contact with the motherboard.

[0007] One aspect of this disclosure is to enable a multi-chip module to prevent the bypass capacitor from coming into contact with the motherboard when the support substrate is fixed to the motherboard without bending the motherboard. [Means for solving the problem]

[0008] A multichip module according to one aspect of the present disclosure comprises a plurality of semiconductor components (12-18) including a power supply circuit, a plurality of bypass capacitors (20), a plurality of connection terminals (30) electrically connected to a motherboard, and a support board (10).

[0009] The support substrate is a multilayer wiring board equipped with multiple semiconductor components, multiple bypass capacitors, and wiring patterns that are connected to multiple connection terminals to form an electrical circuit. Multiple semiconductor components are provided on the upper surface of the support substrate, and multiple bypass capacitors and multiple connection terminals are provided on the lower surface of the support substrate.

[0010] Furthermore, the support substrate is provided with multiple connection terminals: a first group of terminals (32) arranged in a ring along the outer circumference of the support substrate on its lower surface, and a second group of terminals (34) arranged inside the ring formed by the first group of terminals.

[0011] Multiple bypass capacitors are positioned so that their height from the underside of the support substrate is lower than that of the multiple connection terminals, and are located in the opposing region (12A~18A) on the underside of the support substrate, facing the semiconductor components on the upper surface across the support substrate.

[0012] In this opposing region, spacers (36, 38) are provided to restrict the distance between the support board and the motherboard so that the bypass capacitor does not come into contact with the motherboard when the support board is connected to the motherboard via multiple connection terminals.

[0013] Accordingly, according to the multi-chip module of this disclosure, when connected to a motherboard via multiple connection terminals, the distance between the lower surface of the support substrate and the motherboard is defined to be greater than the height of the bypass capacitor, due to the first group of terminals and the second group of terminals.

[0014] Furthermore, when the support board is connected to the motherboard, it may sink towards the motherboard due to the weight of the semiconductor components. However, spacers are provided on the underside of the support board in the area facing the semiconductor components where multiple bypass capacitors are located.

[0015] Therefore, when the multi-chip module of this disclosure is fixed to the motherboard, it is possible to suppress the bypass capacitor from coming into contact with the motherboard. [Brief explanation of the drawing]

[0016] [Figure 1] Figure 1A shows the configuration of the multi-chip module of the first embodiment, with Figure 1B being a plan view thereof, Figure 1B being a bottom view thereof, and Figure 1C being a cross-sectional view taken along line II shown in Figures 1A and 1B. [Figure 2] This is a bottom view of a multi-chip module, an example of a module with spacers distributed across it. [Figure 3] This is an explanatory diagram illustrating the length of the wiring connected to the bypass capacitor. Figure 3A shows the wiring length in the first embodiment, and Figure 3B shows the wiring length in the reference example. [Figure 4] Figure 4A shows the configuration of the multi-chip module of the second embodiment, with Figure 4B being a top view and Figure 4A being a bottom view. [Figure 5] Figure 5A shows a plan view of a modified multi-chip module of the second embodiment, and Figure 5B shows a bottom view thereof. [Figure 6] Shows the configuration of the multi-chip module of the third embodiment. FIG. 6A is a plan view thereof, FIG. 6B is a bottom view thereof, and FIG. 6C is a cross-sectional view taken along line VI-VI shown in FIGS. 6A and 6B.

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [First Embodiment] The multi-chip module 2 of this embodiment is an in-vehicle multi-chip module that is mounted and used on the mother board 50 of a vehicle control device, for example.

[0018] As shown in FIGS. 1A and 1B, the multi-chip module 2 includes a rectangular support substrate 10, a plurality of semiconductor components 12 to 18 provided on the upper surface of the support substrate 10, and a plurality of bypass capacitors 20 and connection terminals 30 provided on the lower surface of the support substrate 10.

[0019] Among the plurality of semiconductor components 12 to 18, for example, the semiconductor component 12 is a system-on-chip (hereinafter, SoC) configured to realize a predetermined function for vehicle control, and is mounted at the center of the upper surface of the support substrate 10.

[0020] Also, for example, the semiconductor component 14 is a power supply IC that functions as a power supply circuit that receives power supply from the mother board 50 and generates a power supply voltage, and the semiconductor components 16 and 18 are memories configured to store various information read and written by the SoC.

[0021] The semiconductor component 14 and the semiconductor component 16 are arranged in a row on the upper surface of the support substrate 10 with the semiconductor component 12, which is an SoC, sandwiched therebetween, and the other semiconductor component 18 is arranged beside the semiconductor component 12, deviating from the arrangement direction of the other semiconductor components 12 to 16.

[0022] The support substrate 10 is a multilayer wiring board equipped with a wiring pattern that constitutes a predetermined electrical circuit, connected to a plurality of semiconductor components 12 to 18 provided on its upper surface and a plurality of bypass capacitors 20 and connection terminals 30 provided on its lower surface.

[0023] The multiple bypass capacitors 20 are made up of chip components, and their thickness is thinner than the height of the multiple connection terminals 30 from the bottom surface of the support substrate 10, as shown in Figure 1C.

[0024] Furthermore, the multiple bypass capacitors 20 are capacitors that remove noise superimposed on the power lines of semiconductor components 12 to 18 and suppress fluctuations in the power supply voltage. For this reason, the multiple bypass capacitors 20 are provided in the opposing regions 12A to 18A on the upper surface of the support substrate 10, as shown in Figure 1B, with the support substrate 10 in between, so as to shorten the wiring length from the power supply terminals of semiconductor components 12 to 18.

[0025] On the other hand, the multiple connection terminals 30 include functional terminals for inputting and outputting various signals, power supply / GND terminals for power supply, and NC terminals that are not connected to the electrical circuit of the support board 10. The multi-chip module 2 is fixed to the motherboard 50 by electrically connecting these multiple connection terminals 30 to the terminals on the motherboard 50. GND represents ground, and NC represents non-connected.

[0026] Furthermore, as shown in Figure 1B, the multiple connection terminals 30 are divided into a first terminal group 32, which is arranged in a rectangular ring along the outer circumference of the support substrate 10 on the lower surface of the support substrate 10, and a second terminal group 34, which is arranged inside the ring formed by the first terminal group 32.

[0027] In the second terminal group 34, the multiple connection terminals 30 are arranged in a ring shape concentric with the first terminal group 32. Furthermore, the first terminal group 32 and the second terminal group 34 are arranged along the outer circumference of the support substrate 10, avoiding the opposing regions 12A to 18A that face the semiconductor components 12 to 18 on the upper surface of the support substrate 10.

[0028] Therefore, according to the multi-chip module 2 of this embodiment, the placement position of the bypass capacitor 20 within the opposing regions 12A to 18A can be arbitrarily set, thereby increasing the design flexibility when setting the placement position of the bypass capacitor 20.

[0029] Therefore, according to the multi-chip module 2 of this embodiment, the bypass capacitor 20 can be placed directly below the power supply terminals of the semiconductor components 12 to 18. As a result, the wiring length between the power supply terminals of the semiconductor components 12 to 18 and the bypass capacitor 20 can be shortened, thereby enhancing the noise suppression function of the bypass capacitor 20.

[0030] Furthermore, when the multi-chip module 2 is fixed to the motherboard 50, the distance between the lower surface of the support board 10 and the motherboard 50 is defined by the height of the connection terminals 30 that constitute the first terminal group 32 and the second terminal group 34.

[0031] Therefore, the distance between the lower surface of the support substrate 10 and the motherboard 50 is set to a constant distance higher than the height of the bypass capacitor 20, thereby preventing the bypass capacitor 20 from contacting the motherboard 50.

[0032] By the way, depending on the weight of the semiconductor components 12-18 located on the upper surface of the motherboard 50, the support board 10 may sink towards the motherboard 50, causing the bypass capacitor 20 to come into contact with the motherboard 50.

[0033] Therefore, as shown in Figure 1B, on the lower surface of the support substrate 10, within the regions 12A to 18A facing the semiconductor components 12 to 18, a third terminal group 36 consisting of multiple connection terminals 30 is provided in the empty region 40 where the bypass capacitor 20 is not located.

[0034] All of the connection terminals 30 constituting the third terminal group 36 are NC terminals that are not connected to the electrical circuits of the support board 10. Therefore, when the multi-chip module 2 is fixed to the motherboard 50, the third terminal group 36 comes into contact with the motherboard 50, but the electrical circuits of the support board 10 are not connected to the motherboard 50 via the third terminal group 36.

[0035] Furthermore, the connection terminals 30 constituting the third terminal group 36 are positioned similarly to the connection terminals 30 of the first terminal group 32 and the second terminal group 34, with a height from the lower surface of the support substrate 10 greater than that of the bypass capacitor 20.

[0036] Therefore, the third terminal group 36 can prevent the support substrate 10 from sinking towards the motherboard 50 due to the weight of the semiconductor components 12 to 18, and prevent the bypass capacitor 20 from coming into contact with the motherboard 50.

[0037] In other words, the connection terminals 30 constituting the third terminal group 36 function as spacers of this disclosure, constraining the distance between the support board 10 and the motherboard 50 so that the bypass capacitor 20 does not come into contact with the motherboard 50.

[0038] As described above, the multi-chip module 2 of this embodiment makes it possible to prevent the bypass capacitor 20 provided on the lower surface of the support substrate 10 from coming into contact with the motherboard 50 without bending the support substrate 10.

[0039] Therefore, by preventing the bypass capacitor 20 from contacting the motherboard 50, it is possible to suppress failure of the multi-chip module 2, or the control device including the multi-chip module 2 and the motherboard 50, thereby improving the reliability of the control device.

[0040] Furthermore, since the bypass capacitor 20 can be placed in areas other than the curved local region of the support substrate 10, the degree of freedom in placing the bypass capacitor is increased.

[0041] By the way, in order to prevent the bypass capacitor 20 provided on the lower surface of the support board 10 from coming into contact with the motherboard 50 without bending the support board 10, the connection terminals 30 may be distributed across the entire lower surface of the support board 10, as shown in the reference example in Figure 2.

[0042] However, doing so not only increases the number of connection terminals 30, but also makes it impossible to place the bypass capacitors 20 in the desired positions in the region 12A facing the semiconductor component (i.e., SoC) 12 where many bypass capacitors 20 are provided.

[0043] In other words, if the connection terminals 30 are distributed across the entire lower surface of the support substrate 10, the bypass capacitor 20 must be placed in the empty space between the connection terminals 30 within the region 12A facing the semiconductor component 12.

[0044] Therefore, in this case, the placement of the bypass capacitor 20 is restricted, and as shown in Figure 3B, it becomes impossible to place the bypass capacitor 20 directly below the power terminals 22 and 24 of the semiconductor component 12.

[0045] As a result, the wiring length of the wiring patterns 10A and vias 10B provided on the support substrate 10 to connect the power terminals 22 and 24 of the semiconductor component 12 to the bypass capacitor 20 becomes longer, and the noise suppression function of the bypass capacitor 20 is reduced.

[0046] Furthermore, in this case, more bypass capacitors 20 are needed to enhance the noise reduction function provided by the bypass capacitors 20, which leads to the problem of increasing the number of components in the multi-chip module 2.

[0047] In contrast, according to the multi-chip module 2 of this embodiment, as described above, the placement position of the bypass capacitor 20 within the region 12A facing the semiconductor component 12 can be arbitrarily set.

[0048] Therefore, as shown in Figure 3A, the bypass capacitor 20 can be placed directly below the power terminals 22 and 24 of the semiconductor component 12, thereby shortening the wiring length between the semiconductor component 12 and the bypass capacitor 20.

[0049] Therefore, according to this embodiment, not only can the bypass capacitor 20 be prevented from contacting the motherboard 50, but the noise reduction function of the bypass capacitor 20 can be enhanced without increasing the number of bypass capacitors 20.

[0050] Therefore, according to the multi-chip module 2 of this embodiment, the quality of the power supply voltage can be improved and the multi-chip module 2 can be miniaturized. Furthermore, according to the multi-chip module 2 of this embodiment, the position of the third terminal group 36, which acts as a spacer, can be determined after determining the placement of the bypass capacitors 20 relative to the semiconductor components 12 to 18 in order to ensure the quality of the power supply voltage. This makes the design process easier.

[0051] [Second Embodiment] As shown in Figure 4, the multi-chip module 2 of this embodiment has the same basic configuration as the first embodiment. The difference from the first embodiment lies in the arrangement of semiconductor components 12-18, bypass capacitors 20, and connection terminals 30 on the support substrate 10. Therefore, the differences from the first embodiment will be explained in this embodiment.

[0052] As shown in Figure 4A, the semiconductor components 12 to 18 are arranged on the upper surface of the support substrate 10, distributed in the upper, lower, left, and right directions so as to surround the central part of the support substrate 10. As shown in Figure 4B, on the lower surface of the support substrate 10, the multiple connection terminals 30 are divided into a first terminal group 32 arranged in a rectangular ring along the outer circumference of the support substrate 10, and a second terminal group 34 and a third terminal group 36 arranged inside the ring formed by the first terminal group 32.

[0053] The first terminal group 32 is configured in the same way as in the first embodiment, but the second terminal group 34 is configured by arranging a plurality of connection terminals 30 together in the central part of the support substrate 10 so as to be outside the areas 12A to 18A facing the semiconductor components 12 to 18 on the upper surface.

[0054] Furthermore, the third terminal group 36 is formed by arranging a plurality of connection terminals 30 in a ring-like arrangement between the first terminal group 32 and the second terminal group 34. All of the connection terminals 30 constituting the third terminal group 36 are NC terminals.

[0055] Furthermore, the multiple bypass capacitors 20 are positioned within the opposing regions 12A to 18A on the upper surface of the support substrate 10, facing the semiconductor components 12 to 18, in a location where they do not come into contact with the connection terminals 30 that constitute the third terminal group 36 or the second terminal group 34.

[0056] With the multi-chip module 2 of this embodiment configured in this way, the first terminal group 32 and the second terminal group 34 allow the distance between the lower surface of the support substrate 10 and the motherboard 50 to be set to a constant distance when fixed to the motherboard 50.

[0057] Furthermore, since the NC terminals constituting the third terminal group 36 are arranged to pass through opposing regions 12A to 18A that face the semiconductor components 12 to 18 on the upper surface of the support substrate 10, it is possible to suppress the support substrate 10 from sinking towards the motherboard 50 due to the weight of the semiconductor components 12 to 18.

[0058] Therefore, the same effects as in the first embodiment can be obtained with the multi-chip module 2 of this embodiment. In the above description, the third terminal group 36 is assumed to consist of multiple connection terminals 30 arranged in a ring shape on the lower surface of the support substrate 10, passing through opposing regions 12A to 18A that face the semiconductor components 12 to 18 on the upper surface.

[0059] In contrast, the third terminal group 36 may be configured, as shown in Figure 5, by providing connection terminals 30 consisting of NC terminals in the empty regions 40 where bypass capacitors 20 are not placed in the regions 12A to 18A facing the semiconductor components 12 to 18.

[0060] [Third Embodiment] As shown in Figure 6, the multi-chip module 2 of this embodiment has the same basic configuration as the first embodiment, and the difference from the first embodiment is that the spacer provided in the region 12A facing the semiconductor component 12 on the lower surface of the support substrate 10 is not a connection terminal 30.

[0061] In other words, in this embodiment, as shown in Figure 6B, in the region 12A facing the semiconductor component 12, a number of chip components 38 that are not connected to the electrical circuit of the multi-chip module 2 are provided as spacers in the empty region 40 where the bypass capacitor 20 is not placed. The chip components 38 may be chip capacitors, or other electronic components other than capacitors.

[0062] As shown in Figure 6C, the height of these multiple chip components 38 from the lower surface of the support substrate 10 is higher than that of the bypass capacitor 20, and is approximately the same height as the connection terminals 30 that constitute the first terminal group 32 and the second terminal group 34.

[0063] Therefore, according to the multi-chip module 2 of this embodiment, when fixed to the motherboard 50, the weight of the semiconductor components 12 causes the support substrate 10 to sink towards the motherboard 50, thereby preventing the bypass capacitor 20 from coming into contact with the motherboard 50.

[0064] The chip component 38 contacts the motherboard 50, but on the upper surface of the motherboard 50 on which the multi-chip module 2 is mounted, at least the surface facing the chip component 38 is either a solid ground or a solid hole.

[0065] Therefore, even if the chip component 38 comes into contact with the motherboard 50, the characteristics of the control device configured in the multi-chip module 2 and the motherboard 50 will not change. Therefore, the same effects as those of the first and second embodiments can be obtained with the multi-chip module 2 of this embodiment.

[0066] In Figure 6B, since the bypass capacitor 20 is not provided in the region 14A to 18A on the lower surface of the support substrate 10 that faces the semiconductor components 14 to 18, the connection terminal 30 or chip component 38 that would serve as a spacer is also not provided.

[0067] However, if a bypass capacitor 20 is provided in the region 14A to 18A facing the semiconductor components 14 to 18, then, as in the first and second embodiments, a connection terminal 30 or chip component 38 acting as a spacer may also be provided within that region 14A to 18A.

[0068] Although embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above and can be implemented in various modified forms. For example, in the above embodiment, it was described that a plurality of semiconductor components 12 to 18, namely an SoC, a power supply IC, and two memory chips, are mounted on the upper surface of the support substrate 10 of the multi-chip module 2. However, the number and types of semiconductor components provided on the upper surface of the support substrate 10 of the multi-chip module 2 can be appropriately set according to the application of the multi-chip module 2.

[0069] Furthermore, in the above embodiment, when a bypass capacitor 20 is provided on the lower surface of the support substrate 10 in the region 12A to 18A facing the semiconductor components 12 to 18, it is described that a connection terminal 30 or chip component 38 that serves as a spacer is provided.

[0070] However, even if a bypass capacitor 20 is provided in the region 12A to 18A facing the semiconductor components 12 to 18, there may be cases where the support substrate 10 sinks due to the weight of the semiconductor components 14 to 18, preventing the bypass capacitor 20 from making contact with the motherboard 50.

[0071] Therefore, in this case, on the lower surface of the support substrate 10, in the region 12A to 18A facing the semiconductor components 12 to 18 where there is no risk of the bypass capacitor 20 coming into contact with the motherboard 50, it is not necessary to provide a spacer connection terminal 30 or chip component 38.

[0072] Next, although the above embodiments mainly described the multi-chip module 2, the present disclosure may also describe a control device including the multi-chip module 2 and a motherboard 50. Furthermore, although the above embodiments described the control device as a control device for a vehicle and the multi-chip module 2 as an in-vehicle multi-chip module, the multi-chip module and control device of the present disclosure may not be mounted on a vehicle.

[0073] Furthermore, multiple functions of one component in the above embodiment may be realized by multiple components, or one function of one component may be realized by multiple components. Also, multiple functions of multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Furthermore, some parts of the configuration of the above embodiment may be omitted. Furthermore, at least some parts of the configuration of the above embodiment may be added to or replaced with the configuration of other above embodiments. [Explanation of Symbols]

[0074] 2...Multi-chip module, 10...Support substrate, 12~18...Semiconductor components, 12A~18A...Opposite region, 20...Bypass capacitor, 30...Connection terminal, 32...First terminal group, 34...Second terminal group, 36...Third terminal group, 38...Chip component, 50...Mother board.

Claims

1. Multiple semiconductor components (12-18) including a power supply circuit, Multiple bypass capacitors (20), Multiple connection terminals (30) connected to the motherboard (50), A multilayer wiring board comprising the plurality of semiconductor components, the plurality of bypass capacitors, and the wiring patterns connected to the plurality of connection terminals to constitute an electrical circuit, wherein the plurality of semiconductor components are provided on the upper surface and the plurality of bypass capacitors and the plurality of connection terminals are provided on the lower surface of the support substrate (10), Equipped with, The plurality of connection terminals include a first group of terminals (32) arranged in a ring along the outer circumference of the support substrate on the lower surface of the support substrate, and a second group of terminals (34) arranged inside the ring formed by the first group of terminals. The plurality of bypass capacitors are positioned such that their height from the lower surface of the support substrate is lower than the plurality of connection terminals, and are located on the lower surface of the support substrate in opposing regions (12A to 18A) that face the semiconductor components on the upper surface, with the support substrate in between. The opposing region is provided with a spacer (38) that restricts the distance between the support substrate and the motherboard so that the bypass capacitor does not come into contact with the motherboard when the support substrate is connected to the motherboard via the plurality of connection terminals. The spacer is made of a chip component that is not connected to the electrical circuit and whose height from the lower surface of the support substrate is greater than that of the bypass capacitor, and furthermore, the height of the chip component from the lower surface of the support substrate is approximately the same as that of the plurality of connection terminals, in a multi-chip module.

2. Multiple semiconductor components (12-18) including a power supply circuit, Multiple bypass capacitors (20), Multiple connection terminals (30) connected to the motherboard (50), A multilayer wiring board comprising the plurality of semiconductor components, the plurality of bypass capacitors, and the wiring patterns connected to the plurality of connection terminals to constitute an electrical circuit, wherein the plurality of semiconductor components are provided on the upper surface and the plurality of bypass capacitors and the plurality of connection terminals are provided on the lower surface of the support substrate (10), Equipped with, The plurality of connection terminals include a first group of terminals (32) arranged in a ring along the outer circumference of the support substrate on the lower surface of the support substrate, and a second group of terminals (34) arranged inside the ring formed by the first group of terminals. The plurality of bypass capacitors are positioned such that their height from the lower surface of the support substrate is lower than the plurality of connection terminals, and are located on the lower surface of the support substrate in opposing regions (12A to 18A) that face the semiconductor components on the upper surface, with the support substrate in between. The opposing region is provided with a spacer (38) that restricts the distance between the support substrate and the motherboard so that the bypass capacitor does not come into contact with the motherboard when the support substrate is connected to the motherboard via the plurality of connection terminals. The previous spacer is The height of the support substrate from the lower surface is greater than that of the bypass capacitor, and it is composed of chip components that are not connected to the electrical circuit. On the lower surface of the support substrate, facing the plurality of semiconductor components on the upper surface, in a plurality of opposing regions where the bypass capacitor is provided, it is provided so as not to be connected to the electrical circuit. Furthermore, the chip component is a multi-chip module in which the height from the lower surface of the support substrate is approximately the same as the height of the plurality of connection terminals.

3. A multichip module according to claim 1 or claim 2, The chip component constituting the spacer is a chip capacitor, in this multi-chip module.

4. A multichip module according to any one of claims 1 to 3, The aforementioned plurality of semiconductor components are a multi-chip module, which is a system-on-a-chip, memory, or power supply IC.

5. A multi-chip module (2) according to any one of Claims 1 to 4, The motherboard (50) to which the multichip module is electrically connected via a plurality of connection terminals, A control device equipped with, A control device wherein, on the surface of the motherboard facing the multi-chip module, the portion (50A) facing the chip component constituting the spacer is either a solid ground or a solid hole.

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