Current transformer fault detection circuit and power conversion system using the same

Abstract

The current transformer fault detection circuit (10U) includes a first comparator (31U) that compares the output of the current transformer with a first reference value, an on-delay timer (32U) that receives the output of the first comparator (31U), a second comparator (34U) that compares the command value of the DC current flowing through the DC reactor with a second reference value, and a logic circuit (33U) that receives the output of the on-delay timer (33U) and the output of the second comparator (34U).

Description

Technical Field

[0001] The present disclosure relates to a current transformer fault detection circuit and a power conversion system using the same.

Background Art

[0002] A power conversion device includes a converter that converts commercial frequency three-phase AC power into DC power, a DC reactor that smooths the DC power, and an inverter that converts the DC power supplied from the converter via the DC reactor into three-phase AC power of a desired frequency and supplies it to a synchronous motor via first to third AC lines. By controlling the three-phase AC power supplied to the synchronous motor, the synchronous motor in a stopped state can be started and rotationally driven at a predetermined rotational speed (see, for example, Japanese Patent Application Laid-Open No. 2003-61380 (Patent Document 1)).

[0003] Such a power conversion device is provided with a current transformer for detecting the magnitude of the flowing current. The control device controls the converter or the inverter according to the magnitude of the current detected by the current transformer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] ] When the current transformer fails, the magnitude of the current detected by the current transformer decreases. As a result, the control device determines that the current flowing through the power conversion device has decreased and executes control to increase the current. As a result, an overcurrent may flow through the power conversion device, and the power conversion device may fail.

[0006] Therefore, the object of this disclosure is to provide a current transformer fault detection circuit capable of detecting a fault in a current transformer, and a power conversion system using the same. [Means for solving the problem]

[0007] The current transformer fault detection circuit of this disclosure is a current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, the power converter includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter via the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the first to sixth AC lines. The current transformer fault detection circuit includes a first comparator that compares the output of the current transformer with a first reference value, an on-delay timer that receives the output of the first comparator, a second comparator that compares a command value of the DC current flowing through the DC reactor with a second reference value, and a logic circuit that receives the output of the on-delay timer and the output of the second comparator.

[0008] The current transformer fault detection circuit of this disclosure is a current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, the power converter includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter via the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the first to sixth AC lines. The current transformer fault detection circuit includes a multiplier that multiplies the command value of the DC current flowing through the DC reactor by a constant greater than 0 and less than 1, a comparator that compares the output of the current transformer with the output of the multiplier, and an on-delay timer that receives the output of the comparator.

[0009] The current transformer fault detection circuit of this disclosure is a current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, the power converter includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter via the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the first to sixth AC lines. The current transformer fault detection circuit includes a comparator that compares the output of the current transformer with a reference value, an on-delay timer that receives the output of the comparator, and a logic circuit that receives the output of the on-delay timer and a signal indicating the startup state of the power converter. [Effects of the Invention]

[0010] According to this disclosure, a fault in the current transformer can be detected. [Brief explanation of the drawing]

[0011] [Figure 1] This is a diagram showing the configuration of the power conversion system 1000 according to the first embodiment. [Figure 2] This is a circuit diagram showing the configuration of converter 3 and inverter 5. [Figure 3] This is a diagram showing the configuration of control circuit 7. [Figure 4] This diagram shows the configuration of the converter control unit 17. [Figure 5] This diagram shows the configuration of the current transformer fault detection circuit 10U according to the first embodiment. [Figure 6] This diagram shows the configuration of the current transformer fault detection circuit 10W according to the first embodiment. [Figure 7] This diagram shows the configuration of the current transformer fault detection circuit 10R according to the first embodiment. [Figure 8] This diagram shows the configuration of the current transformer fault detection circuit 10T according to the first embodiment. [Figure 9] This is a diagram showing the configuration of the power conversion system 1000 according to the second embodiment. [Figure 10] It is a diagram showing the configuration of the converter fault detection circuit 10U of the second embodiment. [Figure 11] It is a diagram showing the configuration of the converter fault detection circuit 10W of the second embodiment. [Figure 12] It is a diagram showing the configuration of the converter fault detection circuit 10R of the second embodiment. [Figure 13] It is a diagram showing the configuration of the converter fault detection circuit 10T of the second embodiment. [Figure 14] It is a diagram showing the configuration of the converter fault detection circuit 10U of the modified example of the second embodiment. [Figure 15] It is a diagram showing the configuration of the converter fault detection circuit 10W of the modified example of the second embodiment. [Figure 16] It is a diagram showing the configuration of the converter fault detection circuit 10R of the modified example of the second embodiment. [Figure 17] It is a diagram showing the configuration of the converter fault detection circuit 10T of the modified example of the second embodiment. [Figure 18] It is a diagram showing the configuration of the converter fault detection circuit 10U of the third embodiment. [Figure 19] It is a diagram showing the configuration of the converter fault detection circuit 10W of the third embodiment. [Figure 20] It is a diagram showing the configuration of the converter fault detection circuit 10R of the third embodiment. [Figure 21] It is a diagram showing the configuration of the converter fault detection circuit 10T of the third embodiment. [Figure 22] It is a diagram showing the configuration of the converter fault detection circuit 10U of the modified example of the third embodiment. [Figure 23] It is a diagram showing the configuration of the converter fault detection circuit 10W of the modified example of the third embodiment. [Figure 24] It is a diagram showing the configuration of the converter fault detection circuit 10R of the modified example of the third embodiment. [Figure 25] It is a diagram showing the configuration of the converter fault detection circuit 10T of the modified example of the third embodiment.

Embodiments for Carrying Out the Invention

[0012] The embodiments will be described below with reference to the drawings. (First Embodiment) Figure 1 is a diagram showing the configuration of the power conversion system 1000 according to the first embodiment. The power conversion system 1000 comprises an AC power supply 1, a power conversion device 100, a synchronous motor 8, a control circuit 7, and current transformer fault detection circuits 10U, 10W, 10T, and 10R.

[0013] The power converter 100 converts the first three-phase AC power supplied via the first to third AC lines into DC power, converts the DC power into second three-phase AC power, and supplies it to the load via the fourth to fifth AC lines. The power converter 100 receives three-phase AC power from the AC power source 1 and starts the synchronous motor 8, which is the load. The power converter 100 is used, for example, in a power plant as a thyristor starter to start a stopped synchronous generator as a synchronous motor 8. The power converter 100 comprises a three-phase transformer 2, a converter 3, a DC reactor 4, an inverter 5, current transformers 9U, 9W, 9R, 9T, and a voltage detector 6.

[0014] The three-phase transformer 2 converts the commercial frequency three-phase AC voltage from the AC power source (power system) 1 into a predetermined three-phase AC voltage. The three-phase AC voltage generated by the three-phase transformer 2 is supplied to the converter 3 via the U-phase line (first AC line) UL, the V-phase line (second AC line) VL, and the W-phase line (third AC line) WL.

[0015] Converter 3 converts the first three-phase AC power from the three-phase transformer 2 into DC power. DC reactor 4 is connected between the high-voltage output terminal 3a of converter 3 and the high-voltage input terminal 5a of inverter 5 to smooth the DC power generated by converter 3. The low-voltage output terminal 3b of converter 3 and the low-voltage input terminal 5b of inverter 5 are directly connected.

[0016] The DC reactor 4 may be connected between the low-voltage output terminal 3b of the converter 3 and the low-voltage input terminal 5b of the inverter 5. The DC reactor 4 may also be connected between the high-voltage output terminal 3a of the converter 3 and the high-voltage input terminal 5a of the inverter 5, and between the low-voltage output terminal 3b of the converter 3 and the low-voltage input terminal 5b of the inverter 5.

[0017] The inverter 5 converts the DC power supplied from the converter 3 via the DC reactor 4 into a second three-phase AC power of a desired frequency, and supplies this three-phase AC power to the synchronous motor 8 via the R-phase line (fourth AC line) RL, the S-phase line (fifth AC line) SL, and the T-phase line (sixth AC line) TL. The synchronous motor 8 is rotationally driven by the second three-phase AC power from the inverter 5. As the second three-phase AC power is gradually increased, the rotational speed (revolutions per minute) of the synchronous motor 8 gradually increases. The switching frequency fI of the inverter 5 is increased in accordance with the rotational speed of the synchronous motor 8. As a result, the rotational speed of the synchronous motor 8 gradually increases from 0 to a predetermined value, and the frequency of the second three-phase AC power gradually increases from 0 to a predetermined value.

[0018] Figure 2 is a circuit diagram showing the configuration of converter 3 and inverter 5. Converter 3 includes thyristors 11 to 16. The anodes of thyristors 11 to 13 are connected to the U-phase line UL, V-phase line VL, and W-phase line WL, respectively, and their cathodes are both connected to the high-voltage output terminal 3a. The cathodes of thyristors 14 to 16 are connected to the U-phase line UL, V-phase line VL, and W-phase line WL, respectively, and their anodes are both connected to the low-voltage output terminal 3b. Thyristors 11 to 16 are controlled by the control circuit 7. By turning on thyristors 11 to 16 at predetermined timings, the first three-phase AC power can be converted to DC power.

[0019] The inverter 5 includes thyristors 21-26. The anodes of thyristors 21-23 are all connected to the high-voltage input terminal 5a, and their cathodes are connected to the R-phase line RL, S-phase line SL, and T-phase line TL, respectively. The anodes of thyristors 24-26 are connected to the R-phase line RL, S-phase line SL, and T-phase line TL, respectively, and their cathodes are all connected to the low-voltage input terminal 5b. Thyristors 21-26 are controlled by the control circuit 7. By turning on thyristors 21-26 at predetermined timings, DC power can be converted into a second three-phase AC power of a desired frequency.

[0020] Current transformer 9U is installed in the U-phase line between the three-phase transformer 2 and the converter 3. Current transformer 9U detects the magnitude of the input current IU of the converter 3 in the U-phase line. Current transformer 9W is installed in the W-phase line between the three-phase transformer 2 and the converter 3. Current transformer 9W detects the magnitude of the input current IW of the converter 3 in the W-phase line. When current transformer 9U fails, the detected value of the U-phase output current IU of the converter 3 detected by current transformer 9U will continuously be "0" or close to "0". When current transformer 9W fails, the detected value of the W-phase input current IW of the converter 3 detected by current transformer 9W will continuously be "0" or close to "0".

[0021] Current transformer 9R is installed in the R-phase line between inverter 5 and synchronous motor 8. Current transformer 9R detects the magnitude of the output current IR of inverter 5 in the R-phase line. Current transformer 9T is installed in the T-phase line between inverter 5 and synchronous motor 8. Current transformer 9T detects the magnitude of the output current IT of inverter 5 in the T-phase line. When current transformer 9R fails, the detected value of the R-phase output current IR of inverter 5 detected by current transformer 9R will continuously be "0" or close to "0". When current transformer 9T fails, the detected value of the T-phase output current IT of inverter 5 detected by current transformer 9T will continuously be "0" or close to "0".

[0022] The voltage detector 6 detects the output voltage VR of the R-phase line, the output voltage VS of the S-phase line, and the output voltage VT of the T-phase line of the inverter 5.

[0023] The control circuit 7 receives signals indicating the input currents IU and IW of the converter 3 detected by the current transformers 9U and 9W, the output currents IR and IT of the inverter 5 detected by the current transformers 9R and 9T, the output voltages VR, VS, and VT of the inverter 5 detected by the voltage detector 6, and the rotational speed of the synchronous motor 8, and controls the converter 3 and inverter 5 based on the received signals.

[0024] When the control circuit 7 starts a synchronous motor 8 that is in a stopped state, it gradually increases the switching frequency fI of the inverter 5 from 0 to a predetermined value in accordance with the gradual increase in the rotational speed of the synchronous motor 8 from 0 to a predetermined value.

[0025] Figure 3 shows the configuration of the control circuit 7. The control circuit 7 comprises a converter control unit 17, an inverter control unit 18, a position detector 19, and a startup state management unit 71. The inverter control unit 18 comprises a control angle calculation unit 28 and a gate pulse generator 27.

[0026] The startup status management unit 71 outputs a startup status signal XT that indicates the startup status of the power converter 100. When the power converter 100 is running, that is, when the converter 3 and inverter 5 are operating, the startup status signal XT is at a high level. When the power converter 100 is not running, that is, when the converter 3 and inverter 5 are not operating, the startup status signal XT is at a low level.

[0027] The position detector 19 detects the rotor position of the synchronous motor 8 based on signals from the current transformers 9R and 9T and the voltage detector 6, and provides a signal indicating the detected value to the converter control unit 17 and the inverter control unit 18.

[0028] The converter control unit 17 controls the converter 3 based on signals from the current transformers 9U and 9W and the position detector 19. Specifically, the converter control unit 17 controls the current of the converter 3 so that the DC current Id output from the converter 3 and flowing through the DC reactor 4 matches a predetermined DC current command value Id*.

[0029] The inverter control unit 18 controls the firing phase of the inverter 5 based on the signal from the position detector 19. Specifically, the inverter control unit 18 includes a control angle calculation unit 28 and a gate pulse generator 27. The control angle calculation unit 28 calculates the phase control angle (firing angle) γ based on the detected rotor position of the synchronous motor 8 and provides the calculated phase control angle γ to the gate pulse generator 27. The gate pulse generator 27 generates a gate pulse (firing command) to be supplied to the gate of the thyristor of the inverter 5 based on the phase control angle γ received from the control angle calculation unit 28.

[0030] Figure 4 shows the configuration of the converter control unit 17. The converter control unit 17 comprises a current detector 92, a speed control unit 93, a current control unit 94, a control angle calculation unit 96, and a gate pulse generator 97.

[0031] The current detector 92 converts the three-phase alternating current detected by the current transformers 9U and 9W into a direct current Id output from the converter 3.

[0032] The current detector 92 includes a rectifier circuit 121 and a gain multiplier 122. The rectifier circuit 121 uses a full-wave rectifier type diode rectifier to rectify the three-phase AC current received from the current transformers 9U and 9W. The gain multiplier 122 calculates the DC current Id by multiplying the output signal from the rectifier circuit 121 by a gain.

[0033] The speed control unit 93 calculates the rotational speed of the synchronous motor 8 based on the detected rotor position of the synchronous motor 8. Based on the calculated rotational speed, the speed control unit 93 generates a DC current command value Id*, which is the target value of the DC current Id.

[0034] The current control unit 94 performs a control calculation to make the DC current Id follow the DC current command value Id* and generates the voltage command value VDC1* of the output voltage of the converter 3. Specifically, the current control unit 94 generates the voltage command value VDC1* by performing a control calculation using the integral element of the deviation ΔId of the DC current Id with respect to the DC current command value Id*.

[0035] The current control unit 94 includes a subtractor 141, a gain multiplier 142, an integrator 143, and an adder 144. The subtractor 141 calculates the deviation ΔId between the DC current command value Id* and the DC current Id, and outputs the calculated deviation ΔId to the gain multiplier 142 and the integrator 143. The gain multiplier 142 multiplies the deviation ΔId by a predetermined proportional gain KP. The integrator 143 integrates the deviation ΔId with a predetermined integral gain KI. The adder 144 adds the outputs from the gain multiplier 142 and the integrator 143 to generate a voltage command value VDC1*. The voltage command value VDC1* corresponds to a control command that defines the DC voltage VDC1 that the converter 3 should output. In this way, the current control unit 94 generates the voltage command value VDC1* by performing a proportional-integral (PI) operation. The current control unit 94 may be configured to perform proportional-integral-differential (PID) operations.

[0036] The converter control unit 17 controls the DC voltage VDC1 so that it is greater than the DC voltage VDC2 between the positive input terminal 5a and the negative input terminal 5b of the inverter 5 by the amount of the voltage drop due to the DC reactor 4. This controls the DC current Id.

[0037] The correction unit 95 corrects the voltage command value VDC1* generated by the current control unit 94 by adding a correction value to it. The correction unit 95 includes a correction value calculator 151 and an adder 152. The correction value calculator 151 calculates the rotational speed of the synchronous motor 8 based on the rotor position of the synchronous motor 8 detected by the position detector 19. The correction value calculator 151 calculates a correction value by inputting the rotational speed into a predetermined correction function F(x). The adder 152 adds the voltage command value VDC1* and the correction value.

[0038] The control angle calculation unit 96 calculates the phase control angle α of the thyristor in the converter 3 based on the voltage command value VDC1* to which the correction value has been added. The control angle calculation unit 96 provides the calculated phase control angle α to the gate pulse generator 97.

[0039] The gate pulse generator 97 generates gate pulses (firing commands) to be applied to the gates of the thyristors of the converter 3 based on the phase control angle α received from the control angle calculation unit 96. By switching the converter 3 according to the gate pulses generated by the gate pulse generator 97, a DC current Id according to the DC current command value Id* is output from the converter 3.

[0040] The current transformer fault detection circuit 10U detects a fault in the current transformer 9U. Figure 5 shows the configuration of the current transformer fault detection circuit 10U according to the first embodiment. The current transformer fault detection circuit 10U includes a comparator 31U, an on-delay timer 32U, and an AND circuit 33U.

[0041] Comparator 31U compares the detected value of the input current IU of the U phase of converter 3, output from current transformer 9U, with a reference value TH1. When the detected value of the input current IU of the U phase of converter 3, output from current transformer 9U, is less than or equal to the reference value TH1, comparator 31U outputs a high-level signal, and when the detected value of the input current IU of the U phase of converter 3, output from current transformer 9U, exceeds the reference value TH1, comparator 31U outputs a low-level signal. TH1 can be set using past data, etc.

[0042] The on-delay timer 32U receives the signal output from the comparator 31U. The on-delay timer 32U is activated when the signal output from the comparator 31U rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31U is at a high level is greater than or equal to ΔT, that is, when the detected value of the input current IU of the U phase of the converter 3 detected by the current transformer 9U is continuously "0" or close to "0" due to a failure of the current transformer 9U, the output signal of the on-delay timer 32U becomes high. When the period during which the signal output from the comparator 31U is at a high level is less than ΔT, that is, when the current transformer 9U is functioning normally and the detected value of the input current IU of the U phase of the converter 3 detected by the current transformer 9U is not continuously "0" or close to "0", the output signal of the on-delay timer 32U becomes low.

[0043] The AND circuit 33U receives the output signal of the on-delay timer 32U and the startup status signal XT, which indicates the startup status of the power converter 100 and is sent from the startup status management unit 71 of the control circuit 7, and outputs the logical AND of these signals as a fault detection signal CTU. When the power converter 100 is running, that is, when the converter 3 and inverter 5 are operating, the startup status signal XT is at a high level. When the power converter 100 is not running, that is, when the converter 3 and inverter 5 are not operating, the startup status signal XT is at a low level. When the fault detection signal CTU is at a high level, it indicates that the current transformer 9U is faulty. When the fault detection signal CTU is at a low level, it indicates that the current transformer 9U is functioning normally.

[0044] When the power converter 100 is not operating, the magnitude of the input current IU of the converter 3 becomes "0," so even if the current transformer 9U is functioning correctly, the output signal of the on-delay timer 32U becomes high level. By using the startup status signal XT, it is possible to avoid the false detection that the current transformer 9U is faulty when the power converter 100 is not operating.

[0045] The current transformer fault detection circuit 10W detects a fault in the current transformer 9W. Figure 6 shows the configuration of the current transformer fault detection circuit 10W in the first embodiment. The current transformer fault detection circuit 10W includes a comparator 31W, an on-delay timer 32W, and an AND circuit 33W.

[0046] Comparator 31W compares the detected input current IW of the W phase of converter 3, output from current transformer 9W, with a reference value TH1. Comparator 31W outputs a high-level signal when the detected input current IW of the W phase of converter 3, output from current transformer 9W, is less than or equal to the reference value TH1, and outputs a low-level signal when the detected input current IW of the W phase of converter 3, output from current transformer 9W, exceeds the reference value TH1. TH1 can be set using past data, etc.

[0047] The on-delay timer 32W receives the signal output from the comparator 31W. The on-delay timer 32W is activated when the signal output from the comparator 31W rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31W is at a high level is greater than or equal to ΔT, that is, when the detected value of the W-phase input current IW of the converter 3 detected by the current transformer 9W is continuously "0" or close to "0" due to a failure of the current transformer 9W, the output signal of the on-delay timer 32W becomes high. When the period during which the signal output from the comparator 31W is at a high level is less than ΔT, that is, when the current transformer 9W is functioning normally and the detected value of the W-phase input current IW of the converter 3 detected by the current transformer 9W is not continuously "0" or close to "0", the output signal of the on-delay timer 32W becomes low.

[0048] The AND circuit 33W receives the output signal of the on-delay timer 32W and the startup status signal XT, which indicates the startup status of the power converter 100 and is sent from the startup status management unit 71 of the control circuit 7, and outputs the logical AND of these signals as a fault detection signal CTW. When the fault detection signal CTW is at a high level, it indicates that the current transformer 9W is faulty. When the fault detection signal CTW is at a low level, it indicates that the current transformer 9W is functioning normally.

[0049] When the power converter 100 is not operating, the magnitude of the input current IW of the converter 3 becomes "0," so even if the current transformer 9W is functioning correctly, the output signal of the on-delay timer 32W becomes high level. By using the startup status signal XT, it is possible to avoid the false detection that the current transformer 9W is faulty when the power converter 100 is not operating.

[0050] The current transformer fault detection circuit 10R detects a fault in the current transformer 9R. Figure 7 shows the configuration of the current transformer fault detection circuit 10R in the first embodiment. The current transformer fault detection circuit 10R includes a comparator 31R, an on-delay timer 32R, and an AND circuit 33R.

[0051] Comparator 31R compares the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, with a reference value TH1. Comparator 31R outputs a high-level signal when the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, exceeds the reference value TH1. TH1 can be set using past data, etc.

[0052] The on-delay timer 32R receives the signal output from the comparator 31R. The on-delay timer 32R is activated when the signal output from the comparator 31R rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31R is at a high level is greater than or equal to ΔT, that is, when the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is continuously "0" or close to "0" due to a failure of the current transformer 9R, the output signal of the on-delay timer 32R becomes high. When the period during which the signal output from the comparator 31R is at a high level is less than ΔT, that is, when the current transformer 9R is functioning normally and the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is not continuously "0" or close to "0", the output signal of the on-delay timer 32R becomes low.

[0053] The AND circuit 33R receives the output signal of the on-delay timer 32R and the startup status signal XT, which indicates the status of the power converter 100 and is sent from the startup status management unit 71 of the control circuit 7, and outputs the logical AND of these signals as a fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0054] When the power converter 100 is not operating, the magnitude of the R-phase output current IR of the inverter 5 becomes "0," so even if the current transformer 9R is functioning correctly, the output signal of the on-delay timer 32R becomes high level. By using the startup status signal XT, it is possible to avoid the false detection that the current transformer 9R is faulty when the power converter 100 is not operating.

[0055] The current transformer fault detection circuit 10T detects a fault in the current transformer 9T. Figure 8 shows the configuration of the current transformer fault detection circuit 10T in the first embodiment. The current transformer fault detection circuit 10T includes a comparator 31T, an on-delay timer 32T, and an AND circuit 33T.

[0056] Comparator 31T compares the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T with a reference value TH1. Comparator 31T outputs a high-level signal when the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the T-phase output current IT of inverter 5 output from current transformer 9R exceeds the reference value TH1.

[0057] The on-delay timer 32T receives the signal output from the comparator 31T. The on-delay timer 32T is activated when the signal output from the comparator 31T rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31T is at a high level is greater than or equal to ΔT, that is, when the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is continuously "0" or close to "0" due to a failure of the current transformer 9T, the output signal of the on-delay timer 32T becomes high. When the period during which the signal output from the comparator 31T is at a high level is less than ΔT, that is, when the current transformer 9T is functioning normally and the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is not continuously "0" or close to "0", the output signal of the on-delay timer 32T becomes low.

[0058] The AND circuit 33T receives the output signal of the on-delay timer 32T and the startup status signal XT, which indicates the status of the power converter 100 and is sent from the startup status management unit 71 of the control circuit 7, and outputs the logical AND of these signals as a fault detection signal CTT. When the fault detection signal CTT is at a high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is at a low level, it indicates that the current transformer 9T is functioning normally.

[0059] When the power converter 100 is not operating, the magnitude of the T-phase output current IT of the inverter 5 becomes "0," so even if the current transformer 9T is functioning correctly, the output signal of the on-delay timer 32T becomes high level. By using the startup status signal XT, it is possible to avoid the false detection that the current transformer 9T is faulty when the power converter 100 is not operating.

[0060] As described above, according to this embodiment, it is possible to detect faults in the current transformers 9U, 9W, 9R, and 9T. If a fault is detected in any of the current transformers 9U, 9W, 9R, or 9T, the power converter 100 can be safely shut down. This eliminates the need to install three current transformers in case of a fault in one phase.

[0061] (Second embodiment) Figure 9 shows the configuration of the power conversion system 1000 according to the second embodiment. The difference between the power conversion system 1000 of the second embodiment and the power conversion system of the first embodiment is that the current transformer fault detection circuits 10U, 10W, 10T, and 10R receive a DC current command value Id* from the control circuit 7.

[0062] The current transformer fault detection circuit 10U detects a fault in the current transformer 9U. Figure 10 shows the configuration of the current transformer fault detection circuit 10U according to the second embodiment. The current transformer fault detection circuit 10U includes a comparator 31U, an on-delay timer 32U, a comparator 34U, and an AND circuit 33U.

[0063] Comparator 31U compares the detected value of the input current IU of the U phase of converter 3, output from current transformer 9U, with a reference value TH1. Comparator 31U outputs a high-level signal when the detected value of the input current IU of the U phase of converter 3, output from current transformer 9U, is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the input current IU of the U phase of converter 3, output from current transformer 9U, exceeds the reference value TH1.

[0064] The on-delay timer 32U receives the signal output from the comparator 31U. The on-delay timer 32U is activated when the signal output from the comparator 31U rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31U is at a high level is greater than or equal to ΔT, that is, when the detected value of the input current IU of the U phase of the converter 3 detected by the current transformer 9U is continuously "0" or close to "0" due to a failure of the current transformer 9U, the output signal of the on-delay timer 32U becomes high. When the period during which the signal output from the comparator 31U is at a high level is less than ΔT, that is, when the current transformer 9U is functioning normally and the detected value of the input current IU of the U phase of the converter 3 detected by the current transformer 9U is not continuously "0" or close to "0", the output signal of the on-delay timer 32U becomes low.

[0065] Comparator 34U compares the DC current command value Id* output from the converter control unit 17 in Figure 4 with the reference value TH2. Comparator 31U outputs a high-level signal when the magnitude of the DC current command value Id* is greater than or equal to the reference value TH2, and outputs a low-level signal when the magnitude of the DC current command value Id* is less than the reference value TH2. TH2 can be set using past data, etc.

[0066] The AND circuit 33U receives the output signal from the on-delay timer 32U and the output signal from the comparator 34, and outputs their logical AND as a fault detection signal CTU. When the fault detection signal CTU is at a high level, it indicates that the current transformer 9U is faulty. When the fault detection signal CTU is at a low level, it indicates that the current transformer 9U is functioning normally.

[0067] When the magnitude of the DC current command value Id* is small, the detected value of the U-phase input current IU of the converter 3 detected by the current transformer 9U will be small, even if the current transformer 9U is functioning correctly. In such cases, using the DC current command value Id* can prevent the system from mistakenly determining that the current transformer 9U is faulty.

[0068] The current transformer fault detection circuit 10W detects a fault in the current transformer 9W. Figure 11 shows the configuration of the current transformer fault detection circuit 10W in the second embodiment. The current transformer fault detection circuit 10W includes a comparator 31W, an on-delay timer 32W, a comparator 34W, and an AND circuit 33W.

[0069] Comparator 31W compares the detected value of the W-phase input current IW of converter 3, output from current transformer 9W, with a reference value TH1. Comparator 31W outputs a high-level signal when the detected value of the W-phase input current IW of converter 3, output from current transformer 9W, is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the W-phase input current IW of converter 3, output from current transformer 9W, exceeds the reference value TH1.

[0070] The on-delay timer 32W receives the signal output from the comparator 31W. The on-delay timer 32W is activated when the signal output from the comparator 31W rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31W is at a high level is greater than or equal to ΔT, that is, when the detected value of the W-phase input current IW of the converter 3 detected by the current transformer 9W is continuously "0" or close to "0" due to a failure of the current transformer 9W, the output signal of the on-delay timer 32W becomes high. When the period during which the signal output from the comparator 31W is at a high level is less than ΔT, that is, when the current transformer 9W is functioning normally and the detected value of the W-phase input current IW of the converter 3 detected by the current transformer 9W is not continuously "0" or close to "0", the output signal of the on-delay timer 32W becomes low.

[0071] Comparator 34W compares the DC current command value Id* output from the converter control unit 17 in Figure 4 with the reference value TH2. Comparator 31W outputs a high-level signal when the magnitude of the DC current command value Id* is greater than or equal to the reference value TH2, and outputs a low-level signal when the magnitude of the DC current command value Id* is less than the reference value TH2. TH2 can be set using past data, etc.

[0072] The AND circuit 33W receives the output signal from the on-delay timer 32W and the output signal from the comparator 34, and outputs the logical AND of these signals as a fault detection signal CTW. When the fault detection signal CTW is at a high level, it indicates that the current transformer 9W is faulty. When the fault detection signal CTW is at a low level, it indicates that the current transformer 9W is functioning normally.

[0073] When the magnitude of the DC current command value Id* is small, the detected value of the W-phase input current IW of converter 3, as detected by the current transformer 9W, will be small, even if the current transformer 9W is functioning correctly. In such cases, using the DC current command value Id* can prevent the system from mistakenly determining that the current transformer 9W is faulty.

[0074] The current transformer fault detection circuit 10R detects a fault in the current transformer 9R. Figure 12 shows the configuration of the current transformer fault detection circuit 10R in the second embodiment. The current transformer fault detection circuit 10R includes a comparator 31R, an on-delay timer 32R, a comparator 34R, and an AND circuit 33R.

[0075] Comparator 31R compares the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, with a reference value TH1. Comparator 31R outputs a high-level signal when the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, exceeds the reference value TH1.

[0076] The on-delay timer 32R receives the signal output from the comparator 31R. The on-delay timer 32R is activated when the signal output from the comparator 31R rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31R is at a high level is greater than or equal to ΔT, that is, when the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is continuously "0" or close to "0" due to a failure of the current transformer 9R, the output signal of the on-delay timer 32R becomes high. When the period during which the signal output from the comparator 31R is at a high level is less than ΔT, that is, when the current transformer 9R is functioning normally and the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is not continuously "0" or close to "0", the output signal of the on-delay timer 32R becomes low.

[0077] Comparator 34R compares the DC current command value Id* output from the converter control unit 17 in Figure 4 with the reference value TH2. Comparator 31R outputs a high-level signal when the magnitude of the DC current command value Id* is greater than or equal to the reference value TH2, and outputs a low-level signal when the magnitude of the DC current command value Id* is less than the reference value TH2.

[0078] The AND gate 33R receives the output signal from the on-delay timer 32R and the output signal from the comparator 34, and outputs their logical AND as the fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0079] When the magnitude of the DC current command value Id* is small, the detected value of the R-phase output current IR of the inverter 5, as detected by the current transformer 9R, will be small, even if the current transformer 9R is functioning correctly. In such cases, using the DC current command value Id* can prevent the system from mistakenly determining that the current transformer 9R is faulty.

[0080] The current transformer fault detection circuit 10T detects a fault in the current transformer 9T. Figure 13 shows the configuration of the current transformer fault detection circuit 10T in the second embodiment. The current transformer fault detection circuit 10T includes a comparator 31T, an on-delay timer 32T, a comparator 34T, and an AND circuit 33T.

[0081] Comparator 31T compares the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T with a reference value TH1. Comparator 31T outputs a high-level signal when the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T exceeds the reference value TH1.

[0082] The on-delay timer 32T receives the signal output from the comparator 31T. The on-delay timer 32T is activated when the signal output from the comparator 31T rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31T is at a high level is greater than or equal to ΔT, that is, when the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is continuously "0" or close to "0" due to a failure of the current transformer 9T, the output signal of the on-delay timer 32T becomes high. When the period during which the signal output from the comparator 31T is at a high level is less than ΔT, that is, when the current transformer 9T is functioning normally and the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is not continuously "0" or close to "0", the output signal of the on-delay timer 32T becomes low.

[0083] Comparator 34T compares the DC current command value Id* output from the converter control unit 17 in Figure 4 with the reference value TH2. Comparator 31T outputs a high-level signal when the magnitude of the DC current command value Id* is greater than or equal to the reference value TH2, and outputs a low-level signal when the magnitude of the DC current command value Id* is less than the reference value TH2.

[0084] The AND gate 33T receives the output signal from the on-delay timer 32T and the output signal from the comparator 34, and outputs their logical AND as the fault detection signal CTT. When the fault detection signal CTT is at a high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is at a low level, it indicates that the current transformer 9T is functioning normally.

[0085] When the magnitude of the DC current command value Id* is small, the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T will be small, even if the current transformer 9T is functioning correctly. In such cases, using the DC current command value Id* can prevent the system from mistakenly determining that the current transformer 9T is faulty.

[0086] As described above, according to this embodiment, similar to the first embodiment, it is possible to detect faults in the current transformers 9U, 9W, 9R, and 9T. If a fault is detected in any of the current transformers 9U, 9W, 9R, or 9T, the power converter 100 can be safely shut down. This eliminates the need to install three current transformers in case of a fault in one phase.

[0087] (Modified version of the second embodiment) Figure 14 shows the configuration of a modified current transformer fault detection circuit 10U of the second embodiment. The difference between the modified current transformer fault detection circuit 10U of the second embodiment and the current transformer fault detection circuit 10U of the second embodiment is the AND circuit 33U.

[0088] The AND circuit 33U receives the output signal of the on-delay timer 32U, the output signal of the comparator 34U, and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTU. When the fault detection signal CTU is at a high level, it indicates that the current transformer 9U is faulty. When the fault detection signal CTU is at a low level, it indicates that the current transformer 9U is functioning normally.

[0089] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9U due to some abnormality causing the output signal of the comparator 34U to become high level, even though the power converter 100 is not operating.

[0090] Figure 15 shows the configuration of a modified current transformer fault detection circuit 10W of the second embodiment. The difference between the modified current transformer fault detection circuit 10W of the second embodiment and the current transformer fault detection circuit 10W of the second embodiment is the AND circuit 33W.

[0091] The AND circuit 33W receives the output signal of the on-delay timer 32W, the output signal of the comparator 34W, and the startup status signal XT representing the status of the power converter 100, and outputs the logical AND of these signals as the fault detection signal CTW. When the fault detection signal CTW is at a high level, it indicates that the current transformer 9W is faulty. When the fault detection signal CTW is at a low level, it indicates that the current transformer 9W is functioning normally.

[0092] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9W due to some abnormality causing the output signal of the comparator 34W to become high level, even though the power converter 100 is not operating.

[0093] Figure 16 shows the configuration of a modified current transformer fault detection circuit 10R of the second embodiment. The difference between the modified current transformer fault detection circuit 10R of the second embodiment and the current transformer fault detection circuit 10R of the second embodiment is the AND circuit 33R.

[0094] The AND circuit 33R receives the output signal of the on-delay timer 32R, the output signal of the comparator 34R, and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0095] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9R due to some abnormality causing the output signal of the comparator 34R to become high level, even though the power converter 100 is not operating.

[0096] Figure 17 shows the configuration of a modified current transformer fault detection circuit 10T of the second embodiment. The difference between the modified current transformer fault detection circuit 10T of the second embodiment and the current transformer fault detection circuit 10T of the second embodiment is the AND circuit 33T.

[0097] The AND circuit 33T receives the output signal of the on-delay timer 32T, the output signal of the comparator 34T, and the startup status signal XT which indicates the state of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTT. When the fault detection signal CTT is at a high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is at a low level, it indicates that the current transformer 9T is functioning normally.

[0098] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9T due to some abnormality causing the output signal of the comparator 34T to become high level, even though the power converter 100 is not operating.

[0099] This modified example also provides the same effects as the second embodiment. (Third embodiment) Figure 18 shows the configuration of the current transformer fault detection circuit 10U according to the third embodiment. The current transformer fault detection circuit 10U comprises a multiplier 38U, a comparator 31U, and an on-delay timer 32U.

[0100] The multiplier 38U multiplies the DC current command value Id* output from the converter control unit 17 in Figure 4 by a predetermined coefficient K. K is a value greater than 0 and less than 1. For example, K is 0.1.

[0101] The comparator 31U compares the detected value of the input current IU of the U phase of converter 3, output from the current transformer 9U, with the magnitude of the output signal of the multiplier 38U. The comparator 31U outputs a high-level signal when the detected value of the input current IU of the U phase of converter 3, output from the current transformer 9U, is less than or equal to the magnitude of the output signal of the multiplier 38U, and outputs a low-level signal when the detected value of the input current IU of the U phase of converter 3, output from the current transformer 9U, exceeds the magnitude of the output signal of the multiplier 38U.

[0102] The on-delay timer 32U receives the signal output from the comparator 31U. The on-delay timer 32U is activated when the signal output from the comparator 31U rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31U is at a high level is greater than or equal to ΔT, that is, when the detected value of the input current IU of the U phase of the converter 3 detected by the current transformer 9U is continuously "0" or close to "0" due to a failure of the current transformer 9U, the output signal of the on-delay timer 32U becomes high. When the period during which the signal output from the comparator 31U is at a high level is less than ΔT, that is, when the current transformer 9U is functioning normally and the detected value of the input current IU of the U phase of the converter 3 detected by the current transformer 9U is not continuously "0" or close to "0", the output signal of the on-delay timer 32U becomes low.

[0103] The on-delay timer 32U outputs a fault detection signal CTU. When the fault detection signal CTU is at a high level, it indicates that the current transformer 9U is faulty. When the fault detection signal CTU is at a low level, it indicates that the current transformer 9U is functioning normally.

[0104] When the magnitude of the DC current command value Id* is small, the detected value of the input current IU of the U phase of converter 3 detected by the current transformer 9U will be small, even if the current transformer 9U is functioning correctly. By changing the reference value used for comparison of the input current IU in comparator 31U according to the magnitude of the DC current command value Id*, it is possible to avoid the current transformer 9U being mistakenly judged as faulty.

[0105] Figure 19 shows the configuration of the current transformer fault detection circuit 10W according to the third embodiment. The current transformer fault detection circuit 10W comprises a multiplier 38W, a comparator 31W, and an on-delay timer 32W.

[0106] The multiplier 38W multiplies the DC current command value Id* output from the converter control unit 17 in Figure 4 by a predetermined coefficient K. K is a value greater than 0 and less than 1. For example, K is 0.1.

[0107] Comparator 31W compares the detected value of the W-phase input current IW of converter 3 output from current transformer 9W with the magnitude of the output signal of multiplier 38W. Comparator 31W outputs a high-level signal when the detected value of the W-phase input current IW of converter 3 output from current transformer 9W is less than or equal to the magnitude of the output signal of multiplier 38W, and outputs a low-level signal when the detected value of the W-phase input current IW of converter 3 output from current transformer 9W exceeds the magnitude of the output signal of multiplier 38W.

[0108] The on-delay timer 32W receives the signal output from the comparator 31W. The on-delay timer 32W is activated when the signal output from the comparator 31W rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31W is at a high level is greater than or equal to ΔT, that is, when the detected value of the W-phase input current IW of the converter 3 detected by the current transformer 9W is continuously "0" or close to "0" due to a failure of the current transformer 9W, the output signal of the on-delay timer 32W becomes high. When the period during which the signal output from the comparator 31W is at a high level is less than ΔT, that is, when the current transformer 9W is functioning normally and the detected value of the W-phase input current IW of the converter 3 detected by the current transformer 9W is not continuously "0" or close to "0", the output signal of the on-delay timer 32W becomes low.

[0109] The on-delay timer 32W outputs a fault detection signal CTW. When the fault detection signal CTW is at a high level, it indicates that the current transformer 9W is faulty. When the fault detection signal CTW is at a low level, it indicates that the current transformer 9W is functioning normally.

[0110] When the magnitude of the DC current command value Id* is small, the detected value of the W-phase input current IW of converter 3 detected by the current transformer 9W will be small, even if the current transformer 9W is functioning correctly. By changing the reference value used for comparison of the input current IW in comparator 31W according to the magnitude of the DC current command value Id*, it is possible to avoid the current transformer 9W being mistakenly judged as faulty.

[0111] Figure 20 shows the configuration of the current transformer fault detection circuit 10R according to the third embodiment. The current transformer fault detection circuit 10R comprises a multiplier 38R, a comparator 31R, and an on-delay timer 32R.

[0112] The multiplier 38R multiplies the DC current command value Id* output from the converter control unit 17 in Figure 4 by a predetermined coefficient K. K is a value greater than 0 and less than 1. For example, K is 0.1.

[0113] Comparator 31R compares the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, with the magnitude of the output signal of multiplier 38R. Comparator 31R outputs a high-level signal when the magnitude of the R-phase output current IR of inverter 5, output from current transformer 9R, is less than or equal to the magnitude of the output signal of multiplier 38R, and outputs a low-level signal when the magnitude of the R-phase output current IR of inverter 5, output from current transformer 9R, exceeds the magnitude of the output signal of multiplier 38R.

[0114] The on-delay timer 32R receives the signal output from the comparator 31R. The on-delay timer 32R is activated when the signal output from the comparator 31R rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31R is at a high level is greater than or equal to ΔT, that is, when the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is continuously "0" or close to "0" due to a failure of the current transformer 9R, the output signal of the on-delay timer 32R becomes high. When the period during which the signal output from the comparator 31R is at a high level is less than ΔT, that is, when the current transformer 9R is functioning normally and the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is not continuously "0" or close to "0", the output signal of the on-delay timer 32R becomes low.

[0115] The on-delay timer 32R outputs a fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0116] When the magnitude of the DC current command value Id* is small, the magnitude of the R-phase output current IR of the inverter 5 detected by the current transformer 9R will be small, even if the current transformer 9R is functioning correctly. By changing the reference value used for comparison of the output current IR in the comparator 31R according to the magnitude of the DC current command value Id*, it is possible to avoid the current transformer 9R being mistakenly judged as faulty.

[0117] Figure 21 shows the configuration of the current transformer fault detection circuit 10T according to the third embodiment. The current transformer fault detection circuit 10T comprises a multiplier 38T, a comparator 31T, and an on-delay timer 32T.

[0118] The multiplier 38T multiplies the DC current command value Id* output from the converter control unit 17 in Figure 4 by a predetermined coefficient K. K is a value greater than 0 and less than 1. For example, K is 0.1.

[0119] Comparator 31T compares the magnitude of the T-phase output current IT of inverter 5 output from current transformer 9T with the magnitude of the output signal of multiplier 38T. Comparator 31T outputs a high-level signal when the magnitude of the T-phase output current IT of inverter 5 output from current transformer 9T is less than or equal to the magnitude of the output signal of multiplier 38T, and outputs a low-level signal when the magnitude of the T-phase output current IT of inverter 5 output from current transformer 9T exceeds the magnitude of the output signal of multiplier 38T.

[0120] The on-delay timer 32T receives the signal output from the comparator 31T. The on-delay timer 32T is activated when the signal output from the comparator 31T rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31T is at a high level is greater than or equal to ΔT, that is, when the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is continuously "0" or close to "0" due to a failure of the current transformer 9T, the output signal of the on-delay timer 32T becomes high. When the period during which the signal output from the comparator 31T is at a high level is less than ΔT, that is, when the current transformer 9T is functioning normally and the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is not continuously "0" or close to "0", the output signal of the on-delay timer 32T becomes low.

[0121] The on-delay timer 32T outputs a fault detection signal CTT. When the fault detection signal CTT is at a high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is at a low level, it indicates that the current transformer 9T is functioning normally.

[0122] When the magnitude of the DC current command value Id* is small, the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T will be small, even if the current transformer 9T is functioning correctly. By changing the reference value used for comparison of the output current IT in the comparator 31T according to the magnitude of the DC current command value Id*, it is possible to avoid the current transformer 9T being mistakenly judged as faulty.

[0123] As described above, according to this embodiment, a fault in the current transformers 9U, 9W, 9R, and 9T can be detected, similar to the first and second embodiments. If a fault is detected in any of the current transformers 9U, 9W, 9R, or 9T, the power converter 100 can be safely shut down. This eliminates the need to install three current transformers in case of a fault in one phase.

[0124] (Modified version of the third embodiment) Figure 22 shows the configuration of a modified current transformer fault detection circuit 10U of the third embodiment. The difference between the modified current transformer fault detection circuit 10U of the third embodiment and the current transformer fault detection circuit 10U of the third embodiment is the AND circuit 39U.

[0125] The AND circuit 39U receives the output signal of the on-delay timer 32U and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTU. When the fault detection signal CTU is at a high level, it indicates that the current transformer 9U is faulty. When the fault detection signal CTU is at a low level, it indicates that the current transformer 9U is functioning normally.

[0126] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9U due to some abnormality causing the output signal of the on-delay timer 32U to become high level, even though the power converter 100 is not operating.

[0127] Figure 23 shows the configuration of a modified current transformer fault detection circuit 10W of the third embodiment. The difference between the modified current transformer fault detection circuit 10W of the third embodiment and the current transformer fault detection circuit 10W of the third embodiment is the AND circuit 39W.

[0128] The AND circuit 39W receives the output signal of the on-delay timer 32W and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTW. When the fault detection signal CTW is at a high level, it indicates that the current transformer 9W is faulty. When the fault detection signal CTW is at a low level, it indicates that the current transformer 9W is functioning normally.

[0129] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9W due to some abnormality causing the output signal of the on-delay timer 32W to become high level, even though the power converter 100 is not operating.

[0130] Figure 24 shows the configuration of a modified current transformer fault detection circuit 10R of the third embodiment. The difference between the modified current transformer fault detection circuit 10R of the third embodiment and the current transformer fault detection circuit 10R of the third embodiment is the AND circuit 39R.

[0131] The AND gate 39R receives the output signal of the on-delay timer 32R and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0132] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9R due to some abnormality causing the output signal of the on-delay timer 32R to become high level, even though the power converter 100 is not operating.

[0133] Figure 25 shows the configuration of a modified current transformer fault detection circuit 10T of the third embodiment. The difference between the modified current transformer fault detection circuit 10T of the third embodiment and the current transformer fault detection circuit 10T of the third embodiment is the AND circuit 39T.

[0134] The AND gate 39T receives the output signal of the on-delay timer 32T and the status signal XT representing the state of the power converter 100, and outputs the logical AND of these as a fault detection signal CTT. When the fault detection signal CTT is high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is low level, it indicates that the current transformer 9T is functioning normally. By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9T due to some abnormality causing the output signal of the on-delay timer 32T to become high level even though the power converter 100 is not operating.

[0135] This modified example also provides the same effects as the second embodiment. (modified version) In the above embodiment, two current transformers are installed on the U-phase line and the W-phase line, but the invention is not limited to this. Current transformers may be installed on any two of the U-phase, V-phase, and W-phase lines. In the above embodiment, two current transformers are installed on the R-phase line and the T-phase line, but the invention is not limited to this. Current transformers may be installed on any two of the R-phase, S-phase, and T-phase lines.

[0136] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended to be included. [Explanation of Symbols]

[0137] 1 AC power supply, 2 Three-phase transformer, 3 Converter, 3a High-voltage output terminal, 3b Low-voltage output terminal, 4 DC reactor, 5 Inverter, 5a Positive input terminal, 5b Negative input terminal, 6 Voltage detector, 7 Control circuit, 8 Synchronous motor, 9R, 9T, 9U, 9W Current transformer, 10R, 10T, 10U, 10W Current transformer fault detection circuit, 11, 12, 13, 14, 15, 16, 21, 22, 23, 24, 25, 26 Thyristor, 17 Converter control unit, 18 Inverter control unit, 19 Position detector, 27, 97 Gate pulse generator, 28, 96 Control angle calculation unit, 31R, 31T, 31U, 31W, 34, 34R, 34T, 34U, 34W Comparator, 32R, 32T, 32U, 32W On-delay timer, 33R, 33T, 33U, 33W, 39R, 39T, 39U, 39W AND circuit, 38R, 38T, 38U, 38W Multiplier, 71 Startup state management unit, 92 Current detector, 93 Speed ​​control unit, 94 Current control unit, 95 Correction unit, 100 Power converter, 121 Rectifier circuit, 122, 142 Gain multiplier, 141 Subtractor, 143 Integrator, 144, 152 Adder, 151 Correction value calculator, 1000 Power conversion system.

Claims

1. A current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, The power conversion device includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter through the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the first to sixth AC lines. The current transformer fault detection circuit is, A first comparator that compares the output of the current transformer with a first reference value, An on-delay timer that receives the output of the first comparator, A second comparator that compares the command value of the DC current flowing through the DC reactor with a second reference value, A current transformer fault detection circuit comprising a logic circuit that receives the output of the on-delay timer and the output of the second comparator.

2. The current transformer fault detection circuit according to claim 1, further comprising the logic circuit receiving a signal indicating the startup status of the power converter.

3. The current transformer fault detection circuit according to claim 1, wherein the first comparator outputs a high-level signal when the output of the current transformer is less than or equal to the first reference value, and outputs a low-level signal when the output of the current transformer exceeds the reference value.

4. The current transformer fault detection circuit according to claim 1, wherein the second comparator outputs a high-level signal when the command value of the DC current is greater than or equal to a second reference value, and outputs a low-level signal when the command value of the DC current is less than the second reference value.

5. The current transformer fault detection circuit according to claim 1, wherein the logic circuit is an AND circuit.

6. A current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, The power conversion device includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter through the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the first to sixth AC lines. The current transformer fault detection circuit is, A multiplier that multiplies the command value of the DC current flowing through the DC reactor by a constant greater than 0 and less than 1, A comparator that compares the output of the current transformer with the output of the multiplier, A current transformer fault detection circuit comprising an on-delay timer that receives the output of the comparator.

7. The current transformer fault detection circuit according to claim 6, further comprising a logic circuit that receives the output of the on-delay timer and a signal indicating the startup status of the power converter.

8. The current transformer fault detection circuit according to claim 6, wherein the comparator outputs a high-level signal when the output of the current transformer is less than or equal to the output of the multiplier, and outputs a low-level signal when the output of the current transformer exceeds the output of the multiplier.

9. The current transformer fault detection circuit according to claim 7, wherein the logic circuit is an AND circuit.

10. A current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, The power conversion device includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter through the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the first to sixth AC lines. The current transformer fault detection circuit is, A comparator that compares the output of the current transformer with a reference value, An on-delay timer that receives the output of the comparator, A current transformer fault detection circuit comprising a logic circuit that receives the output of the on-delay timer and a signal indicating the startup status of the power converter.

11. The current transformer fault detection circuit according to claim 10, wherein the comparator outputs a high-level signal when the output of the current transformer is less than or equal to the reference value, and outputs a low-level signal when the output of the current transformer exceeds the reference value.

12. The current transformer fault detection circuit according to claim 10, wherein the logic circuit is an AND circuit.

13. The first current transformer fault detection circuit, The second current transformer fault detection circuit, The third current transformer fault detection circuit, The fourth current transformer fault detection circuit, The power converter comprises a power converter including a first current transformer installed on one of the two lines of the first to third AC lines, a second current transformer installed on the other of the first to third AC lines, a third current transformer installed on one of the two lines of the fourth to sixth AC lines, and a fourth current transformer installed on the other of the two lines of the fourth to sixth AC lines. The first current transformer fault detection circuit is a current transformer fault detection circuit according to any one of claims 1 to 12 that detects a fault in the first current transformer. The second current transformer fault detection circuit is a current transformer fault detection circuit according to any one of claims 1 to 12 that detects a fault in the second current transformer. The third current transformer fault detection circuit is a current transformer fault detection circuit according to any one of claims 1 to 12 that detects a fault in the third current transformer. The power conversion system wherein the fourth current transformer fault detection circuit is a current transformer fault detection circuit according to any one of claims 1 to 12 that detects a fault in the fourth current transformer.

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