Current transformer fault detection circuit and power conversion system using the same

Abstract

The current transformer fault detection circuit (10R) includes a comparator (31R) that compares the output of the current transformer with a reference value, an on-delay timer (32R) that receives the output of the comparator (31R), and a logic circuit (33R) that receives the output of the on-delay timer (32R) and a signal indicating whether the switching frequency of the inverter is above a specified frequency.

Description

Technical Field

[0001] The present disclosure relates to a current transformer fault detection circuit and a power conversion system using the same.

Background Art

[0002] A power conversion device includes a converter that converts commercial frequency three-phase AC power into DC power, a DC reactor that smooths the DC power, and an inverter that converts the DC power supplied from the converter via the DC reactor into three-phase AC power of a desired frequency and supplies it to a synchronous motor via first to third AC lines. By controlling the three-phase AC power supplied to the synchronous motor, the synchronous motor in a stopped state can be started and rotationally driven at a predetermined rotational speed (see, for example, Japanese Unexamined Patent Application Publication No. 2003-61380 (Patent Document 1)).

[0003] Such a power conversion device is provided with a current transformer for detecting the magnitude of the flowing current. The control device controls the converter or the inverter according to the magnitude of the current detected by the current transformer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When the current transformer fails, the magnitude of the current detected by the current transformer decreases. As a result, the control device determines that the current flowing through the power conversion device has decreased and executes control to increase the current. As a result, an overcurrent may flow through the power conversion device, and the power conversion device may fail.

[0006] Therefore, the object of this disclosure is to provide a current transformer fault detection circuit capable of detecting a fault in a current transformer, and a power conversion system using the same. [Means for solving the problem]

[0007] The current transformer fault detection circuit of this disclosure is a current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, the power converter includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter via the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the fourth to sixth AC lines. The current transformer fault detection circuit includes a comparator that compares the output of the current transformer with a reference value, an on-delay timer that receives the output of the comparator, and a logic circuit that receives the output of the on-delay timer and a signal indicating whether the switching frequency of the inverter is above a specified frequency. [Effects of the Invention]

[0008] According to this disclosure, a fault in the current transformer can be detected. [Brief explanation of the drawing]

[0009] [Figure 1] This is a diagram showing the configuration of the power conversion system 1000 according to the first embodiment. [Figure 2] This is a circuit diagram showing the configuration of converter 3 and inverter 5. [Figure 3] This diagram shows the configuration of the current transformer fault detection circuit 10R according to the first embodiment. [Figure 4] This diagram shows the configuration of the current transformer fault detection circuit 10T according to the first embodiment. [Figure 5] This is a diagram showing the configuration of the power conversion system 1000 according to the second embodiment. [Figure 6] This diagram shows the configuration of the current transformer fault detection circuit 10R according to the second embodiment. [Figure 7] This diagram shows the configuration of the current transformer fault detection circuit 10T according to the second embodiment. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. (First Embodiment) Figure 1 is a diagram showing the configuration of the power conversion system 1000 according to the first embodiment. The power conversion system 1000 comprises an AC power supply 1, a power conversion device 100, a synchronous motor 8, a control circuit 7, and current transformer fault detection circuits 10T and 10R.

[0011] The power converter 100 converts the first three-phase AC power supplied via the first to third AC lines into DC power, converts the DC power into second three-phase AC power, and supplies it to the load via the fourth to fifth AC lines. The power converter 100 receives three-phase AC power from the AC power source 1 and starts the synchronous motor 8, which is the load. The power converter 100 is used, for example, in a power plant as a thyristor starter to start a synchronous generator that is stopped as a synchronous motor 8. The power converter 100 comprises a three-phase transformer 2, a converter 3, a DC reactor 4, an inverter 5, current transformers 9U, 9W, 9R, 9T, and a voltage detector 19.

[0012] The three-phase transformer 2 converts the commercial frequency three-phase AC voltage from the AC power source (power system) 1 into a predetermined three-phase AC voltage. The three-phase AC voltage generated by the three-phase transformer 2 is supplied to the converter 3 via the U-phase line (first AC line) UL, the V-phase line (second AC line) VL, and the W-phase line (third AC line) WL.

[0013] Converter 3 converts the first three-phase AC power from the three-phase transformer 2 into DC power. DC reactor 4 is connected between the high-voltage output terminal 3a of converter 3 and the high-voltage input terminal 5a of inverter 5 to smooth the DC power generated by converter 3. The low-voltage output terminal 3b of converter 3 and the low-voltage input terminal 5b of inverter 5 are directly connected.

[0014] The DC reactor 4 may be connected between the low-voltage output terminal 3b of the converter 3 and the low-voltage input terminal 5b of the inverter 5. The DC reactor 4 may also be connected between the high-voltage output terminal 3a of the converter 3 and the high-voltage input terminal 5a of the inverter 5, and between the low-voltage output terminal 3b of the converter 3 and the low-voltage input terminal 5b of the inverter 5.

[0015] The inverter 5 converts the DC power supplied from the converter 3 via the DC reactor 4 into a second three-phase AC power of a desired frequency, and supplies this three-phase AC power to the synchronous motor 8 via the R-phase line (fourth AC line) RL, the S-phase line (fifth AC line) SL, and the T-phase line (sixth AC line) TL. The synchronous motor 8 is rotationally driven by the second three-phase AC power from the inverter 5. As the second three-phase AC power is gradually increased, the rotational speed (revolutions per minute) of the synchronous motor 8 gradually increases. The switching frequency fI of the inverter 5 is increased in accordance with the rotational speed of the synchronous motor 8. As a result, the rotational speed of the synchronous motor 8 gradually increases from 0 to a predetermined value, and the frequency of the second three-phase AC power gradually increases from 0 to a predetermined value.

[0016] Figure 2 is a circuit diagram showing the configurations of the converter 3 and the inverter 5. The converter 3 includes thyristors 11 to 16. The anodes of thyristors 11 to 13 are connected to the U-phase line UL, the V-phase line VL, and the W-phase line WL respectively, and their cathodes are both connected to the high-voltage side output terminal 3a. The cathodes of thyristors 14 to 16 are connected to the U-phase line UL, the V-phase line VL, and the W-phase line WL respectively, and their anodes are both connected to the low-voltage side output terminal 3b. The thyristors 11 to 16 are controlled by the control circuit 7. By turning on the thyristors 11 to 16 at a predetermined timing, the first three-phase AC power can be converted into DC power.

[0017] The inverter 5 includes thyristors 21 to 26. The anodes of thyristors 21 to 23 are all connected to the high-voltage side input terminal 5a, and their cathodes are connected to the R-phase line RL, the S-phase line SL, and the T-phase line TL respectively. The anodes of thyristors 24 to 26 are connected to the R-phase line RL, the S-phase line SL, and the T-phase line TL respectively, and their cathodes are all connected to the low-voltage side input terminal 5b. The thyristors 21 to 26 are controlled by the control circuit 7. By turning on the thyristors 21 to 26 at a predetermined timing, the DC power can be converted into the second three-phase AC power with a desired frequency.

[0018] The current converter 9U is installed on the U-phase line between the three-phase transformer 2 and the converter 3. The current converter 9U detects the magnitude of the input current IU of the converter 3 on the U-phase line. The current converter 9W is installed on the W-phase line between the three-phase transformer 2 and the converter 3. The current converter 9W detects the magnitude of the input current IW of the converter 3 on the W-phase line.

[0019] The converter 9R is installed in the R-phase line between the inverter 5 and the synchronous motor 8. The converter 9R detects the magnitude of the output current IR of the inverter 5 in the R-phase line. The converter 9T is installed in the T-phase line between the inverter 5 and the synchronous motor 8. The converter 9T detects the magnitude of the output current IT of the inverter 5 in the T-phase line. When the converter 9R fails, the detected value of the output current IR of the R-phase of the inverter 5 detected by the converter 9R continuously becomes "0" or a magnitude close to "0". When the converter 9T fails, the detected value of the output current IT of the T-phase of the inverter 5 detected by the converter 9T continuously becomes "0" or a magnitude close to "0".

[0020] The voltage detector 6 detects the output voltage VR of the R-phase line of the inverter 5, the output voltage VS of the S-phase line, and the output voltage VT of the T-phase line.

[0021] The control circuit 7 receives signals indicating the input currents IU, IW of the converter 3 detected by the converters 9U, 9W, the output currents IR, IT of the inverter 5 detected by the converters 9R, 9T, the output voltages VR, VS, VT of the inverter 5 detected by the voltage detector 6, and the rotational speed of the synchronous motor 8, etc., and controls the converter 3 and the inverter 5 based on the received signals.

[0022] When starting the synchronous motor 8 in a stopped state, the control circuit 7 gradually increases the switching frequency fI of the inverter 5 from 0 to a predetermined value as the rotational speed of the synchronous motor 8 gradually increases from 0 to a predetermined value.

[0023] The converter failure detection circuit 10R detects the failure of the converter 9R. FIG. 3 is a diagram showing the configuration of the converter failure detection circuit 10R of the first embodiment. The converter failure detection circuit 10R includes comparators 31R, 34R, an on-delay timer 32R, and an AND circuit 33R.

[0024] Comparator 31R compares the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, with a reference value TH1. Comparator 31R outputs a high-level signal when the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the R-phase output current IR of inverter 5, output from current transformer 9R, exceeds the reference value TH1. The reference value TH1 can be set using past data, etc.

[0025] The on-delay timer 32R receives the signal output from the comparator 31R. The on-delay timer 32R is activated when the signal output from the comparator 31R rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31R is at a high level is greater than or equal to ΔT, that is, when the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is continuously "0" or close to "0" due to a failure of the current transformer 9R, the output signal of the on-delay timer 32R becomes high. When the period during which the signal output from the comparator 31R is at a high level is less than ΔT, that is, when the current transformer 9R is functioning normally and the detected value of the R-phase output current IR of the inverter 5 detected by the current transformer 9R is not continuously "0" or close to "0", the output signal of the on-delay timer 32R becomes low.

[0026] Comparator 34R compares the magnitude of the switching frequency fI of inverter 5 with a reference value TF1. Comparator 34R outputs a high-level signal when the magnitude of the switching frequency fI of inverter 5 is greater than or equal to the reference value TF1, and outputs a low-level signal when the magnitude of the switching frequency fI of inverter 5 is less than the reference value TF1. The reason for using the switching frequency fI of inverter 5 to detect a fault in current transformer 9R is that when the switching frequency fI of inverter 5 is low, the fault in current transformer 9R cannot be accurately detected due to saturation of the current transformer 9R.

[0027] The AND gate 33R receives the output signal from the on-delay timer 32R and the output signal from the comparator 34R, and outputs their logical AND as the fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0028] The current transformer fault detection circuit 10T detects a fault in the current transformer 9T. Figure 4 shows the configuration of the current transformer fault detection circuit 10T in the first embodiment. The current transformer fault detection circuit 10T includes comparators 31T and 34T, an on-delay timer 32T, and an AND circuit 33T.

[0029] Comparator 31T compares the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T with a reference value TH1. Comparator 31T outputs a high-level signal when the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T is less than or equal to the reference value TH1, and outputs a low-level signal when the detected value of the T-phase output current IT of inverter 5 output from current transformer 9T exceeds the reference value TH1. TH1 can be set using past data, etc.

[0030] The on-delay timer 32T receives the signal output from the comparator 31T. The on-delay timer 32T is activated when the signal output from the comparator 31T rises to a high level, and outputs the input signal after a predetermined time ΔT has elapsed. The length of time ΔT can be set using past data, etc. When the period during which the signal output from the comparator 31T is at a high level is greater than or equal to ΔT, that is, when the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is continuously "0" or close to "0" due to a failure of the current transformer 9T, the output signal of the on-delay timer 32T becomes high. When the period during which the signal output from the comparator 31T is at a high level is less than ΔT, that is, when the current transformer 9T is functioning normally and the detected value of the T-phase output current IT of the inverter 5 detected by the current transformer 9T is not continuously "0" or close to "0", the output signal of the on-delay timer 32T becomes low.

[0031] Comparator 34T compares the magnitude of the switching frequency fI of inverter 5 with a reference value TF1. Comparator 34T outputs a high-level signal when the magnitude of the switching frequency fI of inverter 5 is greater than or equal to the reference value TF1, and outputs a low-level signal when the magnitude of the switching frequency fI of inverter 5 is less than the reference value TF1. The reason for using the switching frequency fI of inverter 5 to detect a fault in current transformer 9T is that when the switching frequency fI of inverter 5 is low, the fault in current transformer 9T cannot be accurately detected due to saturation of the current transformer 9T.

[0032] The AND gate 33T receives the output signal from the on-delay timer 32T and the output signal from the comparator 34T, and outputs their logical AND as the fault detection signal CTT. When the fault detection signal CTT is at a high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is at a low level, it indicates that the current transformer 9T is functioning normally.

[0033] As described above, according to this embodiment, it is possible to detect failures in the current transformers 9R and 9T. If a failure is detected in either of the current transformers 9R or 9T, the power converter 100 can be safely shut down. This eliminates the need to install three current transformers in case of a failure in one phase.

[0034] (Second embodiment) Figure 5 shows the configuration of the power conversion system 1000 according to the second embodiment. The difference between the power conversion system 1000 of the second embodiment and the power conversion system of the first embodiment is that the current transformer fault detection circuits 10T and 10R receive a startup status signal XT from the control circuit 7, which indicates the startup status of the power conversion device 100. When the power conversion device 100 is running, that is, when the converter 3 and inverter 5 are operating, the startup status signal XT is at a high level. When the power conversion device 100 is not running, that is, when the converter 3 and inverter 5 are not operating, the startup status signal XT is at a low level.

[0035] Figure 6 shows the configuration of the current transformer fault detection circuit 10R of the second embodiment. The difference between the current transformer fault detection circuit 10R of the second embodiment and the current transformer fault detection circuit 10R of the first embodiment is the AND circuit 33R.

[0036] The AND circuit 33R receives the output signal of the on-delay timer 32R, the output signal of the comparator 34R, and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTR. When the fault detection signal CTR is at a high level, it indicates that the current transformer 9R is faulty. When the fault detection signal CTR is at a low level, it indicates that the current transformer 9R is functioning normally.

[0037] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9R due to some abnormality causing the output signal of the comparator 34R to become high level, even though the power converter 100 is not operating.

[0038] The current transformer fault detection circuit 10T detects a fault in the current transformer 9T. Figure 7 shows the configuration of the current transformer fault detection circuit 10T in the second embodiment. The difference between the current transformer fault detection circuit 10T in the second embodiment and the current transformer fault detection circuit 10T in the first embodiment is the AND circuit 33T.

[0039] The AND circuit 33T receives the output signal of the on-delay timer 32T, the output signal of the comparator 34T, and the startup status signal XT, which indicates the startup status of the power converter 100, and outputs the logical AND of these signals as a fault detection signal CTT. When the fault detection signal CTT is at a high level, it indicates that the current transformer 9T is faulty. When the fault detection signal CTT is at a low level, it indicates that the current transformer 9T is functioning normally.

[0040] By using the startup status signal XT, it is possible to avoid the false detection of a fault in the current transformer 9T due to some abnormality causing the output signal of the comparator 34T to become high level, even though the power converter 100 is not operating.

[0041] As described above, according to this embodiment, a fault in the current transformers 9R and 9T can be detected, similar to the first embodiment. If a fault is detected in either of the current transformers 9R or 9T, the power converter 100 can be safely shut down. This eliminates the need to install three current transformers in case of a fault in one phase.

[0042] (modified version) In the above embodiment, two current transformers were installed on the R-phase line and the T-phase line, but the embodiment is not limited to this. Current transformers may be installed on any two of the R-phase, S-phase, and T-phase lines.

[0043] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended to be included. [Explanation of Symbols]

[0044] 1 AC power supply, 2 three-phase transformer, 3 converter, 3a high-voltage output terminal, 3b low-voltage output terminal, 4 DC reactor, 5 inverter, 5a high-voltage input terminal, 5b low-voltage input terminal, 6 voltage detector, 7 control circuit, 8 synchronous motor, 9R, 9T, 9U, 9W current transformer, 10R, 10T current transformer fault detection circuit, 11, 12, 13, 14, 15, 16, 21, 22, 23, 24, 25, 26 thyristor, 31R, 31T, 34R, 34T comparator, 32R, 32T on-delay timer, 33R, 33T AND circuit, 100 power converter, 1000 power conversion system.

Claims

1. A current transformer fault detection circuit for detecting a fault in a current transformer installed in a power converter, The power conversion device includes a converter that converts first three-phase AC power supplied via first to third AC lines into DC power, a DC reactor that smooths the DC power, an inverter that converts the DC power supplied from the converter through the DC reactor into second three-phase AC power and supplies it to a load via fourth to sixth AC lines, and a current transformer installed in any of the fourth to sixth AC lines. The current transformer fault detection circuit is, A comparator that compares the output of the current transformer with a reference value, An on-delay timer that receives the output of the comparator, A current transformer fault detection circuit comprising: a logic circuit that receives the output of the on-delay timer and a signal indicating whether the switching frequency of the inverter is above a specified frequency.

2. The current transformer fault detection circuit according to claim 1, further comprising the logic circuit receiving a signal indicating the startup status of the power converter.

3. The current transformer fault detection circuit according to claim 1, wherein the comparator outputs a high-level signal when the output of the current transformer is less than or equal to the reference value, and outputs a low-level signal when the output of the current transformer exceeds the reference value.

4. The current transformer fault detection circuit according to claim 1, wherein the logic circuit is an AND circuit.

5. The first current transformer fault detection circuit, The second current transformer fault detection circuit, The system comprises a power converter, the power converter including a first current transformer installed on one of the two lines of the fourth to sixth AC lines, and a second current transformer installed on the other of the two lines. The first current transformer fault detection circuit is a current transformer fault detection circuit according to any one of claims 1 to 4 that detects a fault in the first current transformer. The power conversion system wherein the second current transformer fault detection circuit is a current transformer fault detection circuit according to any one of claims 1 to 4 for detecting a fault in the second current transformer.

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