Semiconductor equipment
The semiconductor device addresses miniaturization and noise interference by using a clock generation circuit to generate lower-frequency clock signals for the last stage capacitor, enhancing A/D conversion accuracy and reducing circuit area in charge pump circuits.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2023-01-11
- Publication Date
- 2026-05-19
AI Technical Summary
Conventional charge pump circuits in semiconductor devices face challenges in miniaturization due to the need for increased capacitor capacitance to maintain desired current capacity, while high clock signal frequencies interfere with A/D conversion accuracy, leading to noise mixing and increased circuit area.
A semiconductor device with a charge pump circuit and A/D conversion unit uses a clock generation circuit to generate two clock signals, where one clock signal with a lower frequency is applied to the last stage capacitor, reducing noise impact on A/D conversion and allowing smaller capacitors, thus minimizing circuit area.
This configuration effectively suppresses noise from affecting A/D conversion while maintaining a compact circuit size by ensuring the clock signal edges do not coincide with sampling timings and allowing higher frequencies for other capacitors, thus reducing the overall circuit area.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device including a charge pump circuit and an A / D conversion unit.
Background Art
[0002] In a conventional charge pump circuit, it is common to apply the same clock signal to each terminal of a plurality of capacitors. When configuring a semiconductor device including such a conventional charge pump circuit and an A / D conversion unit that samples an input signal and performs A / D conversion, the following problems may occur. That is, for the charge pump circuit, in order to ensure the desired current capacity while reducing the size, it is conceivable to increase the frequency of the clock signal.
[0003] However, if the frequency of the clock signal is higher than the sampling frequency in the A / D converter, the possibility that the rising edge or falling edge of the clock signal coincides with or is close to the sampling timing by the A / D conversion unit increases. Then, noise caused by the edge of the clock signal is mixed into the input signal of the A / D conversion unit, and the accuracy of the operation of the A / D conversion unit, and thus the accuracy of various processes performed using the digital signal output from the A / D conversion unit, decreases.
[0004] Due to such circumstances, in a semiconductor device including a conventional charge pump circuit and an A / D conversion unit, it was necessary to set the frequency of the clock signal lower than the sampling frequency in the A / D conversion unit. Since there is a restriction on the frequency of the clock signal in this way, in the conventional configuration, for the charge pump circuit, in order to ensure the desired current capacity, the capacitance of the capacitor has to be increased, and as a result, there is a problem that the circuit area becomes large.
[0005] On the other hand, Patent Document 1 discloses a technique for suppressing the effect of the switching operation of the charge pump circuit on the sample-and-hold circuit in a semiconductor device equipped with a sample-and-hold circuit and a charge pump circuit. Hereinafter, the prior art described in Patent Document 1 will be referred to as the first prior art. In the first prior art, two clock signals, a first delayed clock signal and a second delayed clock signal, are used as the operating clock for the charge pump circuit.
[0006] The first and second delayed clock signals are both synchronized with the operating clock signal of the sample-and-hold circuit and are delayed by the same amount of time relative to the operating clock signal. Furthermore, the first delayed clock signal has the same frequency as the operating clock signal, and the second delayed clock signal has a frequency that is n times that of the operating clock signal. According to this configuration of the first prior art, there is a discrepancy between the timing of noise generation caused by the edges of the clock signal of the charge pump circuit and the operating timing of the sample-and-hold circuit, so sampling can be performed without being affected by noise. [Prior art documents] [Non-patent literature]
[0007] [Patent Document 1] Japanese Patent Publication No. 2017-41922 [Overview of the project] [Problems that the invention aims to solve]
[0008] In the first prior art, a first delayed clock signal having the same frequency as the sample-and-hold circuit's operating clock is used as the normal operating clock for the charge pump circuit. Therefore, in the first prior art, while noise caused by the edges of the clock signal can be suppressed from affecting the operation of the sample-and-hold circuit, it was difficult to miniaturize the charge pump circuit.
[0009] The present invention has been made in view of the above circumstances, and its purpose is to provide a semiconductor device that can reduce the circuit area of the charge pump circuit while suppressing noise caused by the edges of the clock signal from affecting the operation of the A / D conversion unit. [Means for solving the problem]
[0010] The semiconductor device according to claim 1 comprises a charge pump circuit (9), an A / D conversion unit (7), and a clock generation circuit (8). The charge pump circuit generates a boosted voltage by increasing the input voltage input via an input node (Ni) and outputs the boosted voltage via an output node (No). The charge pump circuit comprises a plurality of switching elements (D1 to D6) connected in series between the input node and the output node, and a plurality of capacitors (C1 to C6) to which one terminal is connected to each connection node (N1 to N5) to which the switching elements are connected, and to which a binary clock signal is supplied to the other terminal. The A / D conversion unit samples the input signal and performs A / D conversion. The clock generation circuit generates the clock signal.
[0011] Here, of the plurality of capacitors, the capacitor (C6) located closest to the output node is designated as the last stage capacitor, and the capacitors other than the last stage capacitor (C1 to C5) are designated as other capacitors. In this case, the clock generation circuit uses the other capacitors as the clock signal. Ta The first clock signal to be given and ,before The A / D converter generates a second clock signal which is supplied to the capacitor at the last stage and has a lower frequency than the first clock signal. The A / D converter terminates its sampling operation of the input signal at a timing after the second clock signal has changed from the first level to the second level and before the second clock signal subsequently changes from the second level to the first level.
[0012] With the above configuration ,blood The possibility of the edge of the second clock signal supplied to the final stage capacitor of the charge pump circuit coinciding with or being close to the sampling timing of the A / D converter can be kept low. As a result, the impact of noise caused by the edge of the second clock signal, in other words, noise caused by the switching of the final stage of the charge pump circuit, on the operation of the A / D converter is reduced.
[0013] Furthermore, in this case, the frequency of the first clock signal supplied to the other capacitors in the charge pump circuit can be increased compared to the frequency of the second clock signal. As a result, the capacitance of the capacitors can be kept smaller, and consequently, the circuit area of the charge pump circuit is reduced. Thus, the above configuration provides the excellent effect of suppressing noise caused by the edges of the clock signal from affecting the operation of the A / D conversion section while keeping the circuit area of the charge pump circuit small. [Brief explanation of the drawing]
[0014] [Figure 1] A schematic diagram showing the configuration of a battery monitoring device according to one embodiment. [Figure 2] A diagram showing a specific configuration example of a charge pump circuit according to one embodiment. [Figure 3] Timing chart showing specific examples of the operating timing of each part according to one embodiment. [Figure 4] This diagram schematically shows the operating waveforms of each part when noise caused by the edge of the clock signal is superimposed during the first half of the sampling period according to one embodiment. [Figure 5] This diagram schematically shows the operating waveforms of each part when noise caused by the edge of the clock signal is superimposed at the timing of the latter half of the sampling period according to one embodiment. [Modes for carrying out the invention]
[0015] Hereinafter, an embodiment of a semiconductor device including a charge pump circuit and an A / D conversion unit will be described with reference to the drawings. <Overall Configuration> As shown in FIG. 1, the battery monitoring device 1 of this embodiment is mounted on a vehicle such as an automobile, and is a device that detects various states such as the voltage of the battery pack 2 and monitors the state of the battery pack 2.
[0016] The battery monitoring device 1 includes a battery monitoring IC 3 which is an integrated circuit in which circuits performing various operations for battery monitoring are integrated, and a plurality of externally attached elements provided outside the battery monitoring IC 3. Here, IC is an abbreviation for Integrated Circuit. In this embodiment, the battery monitoring IC 3 is an example of a semiconductor device.
[0017] The battery pack 2 is mounted on a vehicle such as an automobile, and has a configuration in which a plurality of, for example, 24 battery cells Cb are connected in series in multiple stages between a pair of DC power lines L1 and L2. In this case, the battery cell Cb is a secondary battery such as a lithium ion battery, a fuel cell, or the like. In FIG. 1, 4 of the 24 battery cells Cb are shown, and in order to distinguish these 4 battery cells Cb, numbers are attached to the ends of the reference signs.
[0018] This number corresponds to the arrangement of the battery cells Cb in the battery pack 2. The battery cell Cb arranged on the lowest potential side is given 1, and as it progresses to the higher potential side, the numbers 2, 3, 4,... increase, and the battery cell Cb arranged on the highest potential side is given 24. Therefore, in FIG. 1, the battery cell Cb1 arranged on the lowest potential side, the battery cell Cb2 arranged on the second lowest potential side, the battery cell Cb23 arranged on the second highest potential side, and the battery cell Cb24 arranged on the highest potential side are shown.
[0019] Regarding each of the above-described battery cells Cb, for each of the configurations provided in the battery monitoring device 1 corresponding to the battery cells Cb1, Cb2, Cb23, and Cb24, the same number may be appended to the end of the reference numeral for distinction. However, when there is no need to distinguish these configurations, the reference numeral at the end may be omitted and they may be collectively referred to. In the above configuration, a common mode voltage is superimposed on the battery cell Cb. This common mode voltage becomes higher for the battery cells Cb connected to the upper stage side, that is, the high potential side of the assembled battery 2, and its maximum value is a relatively high voltage of, for example, about several hundred volts.
[0020] <Configuration of External Elements> First, the configuration of the external elements provided outside the battery monitoring IC 3 will be described. The high potential side terminal of the battery cell Cb24 is connected to the connection terminal BLK via the resistor RB and is also connected to the connection terminal PS25 via the resistor RB. The connection terminal BLK is a terminal to which the voltage Va of the assembled battery 2 having a configuration in which a plurality of battery cells Cb to be monitored by the battery monitoring IC 3 are connected in series is applied.
[0021] A resistor RS and a capacitor CS are connected in series between the high potential side terminal and the low potential side terminal of the battery cell Cb24. The node Na, which is the interconnection node of the resistor RS and the capacitor CS, is connected to the connection terminal PV24. The low potential side terminal of the battery cell Cb24 and the high potential side terminal of the battery cell Cb23 are connected to the connection terminal PS24 via the resistor RB.
[0022] Although some illustrations are omitted, a resistor RS and a capacitor CS are connected in series between the high potential side terminal and the low potential side terminal of the battery cell Cb23. The node Na, which is the interconnection node of the resistor RS and the capacitor CS, is connected to the connection terminal PV23. Although the illustration is omitted, the low potential side terminal of the battery cell Cb23 and the high potential side terminal of a battery cell Cb22 not shown are connected to the connection terminal PS23 via the resistor RB.
[0023] The low-potential terminal of battery cell Cb3 (not shown) and the high-potential terminal of battery cell Cb2 are connected to connection terminal PS3 via resistor RB. A resistor RS and a capacitor CS are connected in series between the high-potential and low-potential terminals of battery cell Cb2. Node Na, which is the interconnection node of resistor RS and capacitor CS, is connected to connection terminal PV2.
[0024] The low-potential terminal of battery cell Cb2 and the high-potential terminal of battery cell Cb1 are connected to connection terminal PS2 via resistor RB. A resistor RS and a capacitor CS are connected in series between the high-potential and low-potential terminals of battery cell Cb1. Node Na, which is the interconnection node of resistor RS and capacitor CS, is connected to connection terminal PV1. The low-potential terminal of battery cell Cb1 is connected to connection terminal PS1 via resistor RB.
[0025] In the above configuration, a low-pass filter 4 is formed by resistors RS and capacitors CS, each corresponding to a battery cell Cb. In other words, in the above configuration, a filter 4 is provided to correspond to each battery cell Cb. Resistor RB is a discharge resistor used to discharge the battery cell Cb during equalization. Since resistor RB functions as a current limiting resistor during equalization, its resistance value is very small compared to the resistance value of resistor RS that makes up the filter 4, specifically, for example, around several tens of ohms.
[0026] <Internal Configuration of Battery Monitoring IC> Next, the internal configuration of the battery monitoring IC3 will be described. The battery monitoring IC3 includes equalization switches (not shown) and a control unit 5 that controls the overall operation of the battery monitoring IC3. The equalization switches described above are provided corresponding to each of the multiple battery cells Cb. The equalization switches are made up of, for example, MOS transistors and, together with resistors RB, form a discharge circuit. The on / off state of the equalization switches is controlled by the control unit 5. In the battery equalization process, the operation of each discharge circuit is controlled so that the voltage of each battery cell Cb becomes approximately the same as the voltage of the lowest battery cell Cb.
[0027] The battery monitoring IC3 includes a multiplexer 6, an analog front-end 7, a clock generation circuit 8, and a charge pump circuit 9. In the following description and Figure 1, the multiplexer may be referred to as MUX, and the analog front-end as AFE. MUX6 includes multiple switches SV corresponding to each of the connection terminals PV1 to PV24, and multiple switches SS corresponding to each of the connection terminals PS1 to PS25. Switches SV and SS are composed of, for example, MOS transistors.
[0028] Each terminal on one side of multiple switches SV is connected to the corresponding connection terminal PV. Specifically, each terminal on switches SV24, SV23, SV2, and SV1 is connected to connection terminals PV24, PV23, PV2, and PV1, respectively. Each other terminal on multiple switches SV is connected to the first output line Lo1. Specifically, each other terminal on switches SV24, SV23, SV2, and SV1 is connected to the first output line Lo1.
[0029] Each terminal on one side of multiple switches SS is connected to the corresponding connection terminal PS. Specifically, each terminal on switches SS25, SS24, SS3, SS2, and SS1 is connected to connection terminals PS25, PS24, PS3, PS2, and PS1, respectively. Each other terminal on multiple switches SS is connected to the second output line Lo2. Specifically, each other terminal on switches SS25, SS24, SS3, SS2, and SS1 is connected to the second output line Lo2.
[0030] MUX6 receives the voltages from connection terminals PV1-PV24 and PS1-PS25, and selectively outputs two voltages necessary to detect the voltage of the target battery cell Cb by switching switches SV and SS on and off. In other words, MUX6 receives the voltages of multiple battery cells Cb and selects one of those input voltages to output. This selection operation by MUX6, i.e., switching switches SV and SS on and off, is controlled by control unit 5. MUX6 operates by receiving the voltage Vb output from the charge pump circuit 9.
[0031] AFE7 is an example of an A / D conversion unit that samples an input signal and performs A / D conversion. AFE7 includes a differential sample-and-hold circuit 10 and a differential input A / D converter 11. In the following description and Figure 1, the sample-and-hold circuit may be referred to as S / H, and the A / D converter may be referred to as ADC. The S / H circuit 10 receives the voltage output from MUX6 as an input signal and samples that input signal. The ADC 11 performs A / D conversion on the signal sampled and held by the S / H circuit 10.
[0032] In this configuration, the AFE7 receives the voltage output from the MUX6 as an input signal and samples the input signal for A / D conversion. The AFE7 operates using the third clock signal CLK3 output from the clock generation circuit 8 as its clock. The AFE7 outputs the digital signal obtained as a result of the A / D conversion to the control unit 5. The control unit 5 controls the operation of the MUX6, AFE7, etc., and also detects the voltage of each of the multiple battery cells Cb in a time-division manner based on the digital signal output from the AFE7.
[0033] The clock generation circuit 8 generates three binary clock signals: the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3. In the following description, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 may be abbreviated as signal CLK1, signal CLK2, and signal CLK3. Signals CLK1 and CLK2 are supplied to the charge pump circuit 9, and signal CLK3 is supplied to the AFE7.
[0034] In this case, signal CLK2 has a lower frequency than signal CLK1. Also, signal CLK3 has the same frequency as signal CLK2. In other words, in this case, the frequencies f1, f2, and f3 of signals CLK1, CLK2, and CLK3 have the relationship shown in equation (1) below. f1 > f2 = f3 …(1)
[0035] The charge pump circuit 9 generates a boosted voltage Vb by increasing the input voltage input via the input node, and outputs the voltage Vb via the output node. In this case, the input voltage is the voltage Va of the battery pack 2. The charge pump circuit 9 operates using the first clock signal CLK1 and the second clock signal CLK2 output from the clock generation circuit 8 as its clock.
[0036] <Specific example of charge pump circuit configuration> A specific configuration of the charge pump circuit 9 is shown in Figure 2, for example. As shown in Figure 2, the charge pump circuit 9 in this example configuration includes diodes D1 to D6, capacitors C1 to C7, inverter 21, buffers 22 and 23, etc. In this case, the charge pump circuit 9 is configured to receive a voltage Va via the input node Ni and output a voltage Vb via the output node No.
[0037] Inverter 21 receives signal CLK1 as input and outputs a signal with the opposite logic to signal CLK1, that is, a signal that is the inverted version of signal CLK1. Buffer 22 receives signal CLK1 as input and outputs a signal with the same logic as signal CLK1. Buffer 23 receives signal CLK2 as input and outputs a signal with the same logic as signal CLK2.
[0038] Diodes D1, D2, D3, D4, D5, and D6 are connected in series in the forward direction between node Ni and node No in this order. In this configuration example, diodes D1 to D6 are an example of multiple switching elements connected in series between the input node and the output node. One terminal of capacitor C1 is connected to node Ni, and the other terminal is connected to the output terminal of inverter 21. One terminal of capacitor C2 is connected to node N1, which is a connection node where diodes D1 and D2 are connected, and the other terminal is connected to the output terminal of buffer 22. One terminal of capacitor C3 is connected to node N2, which is a connection node where diodes D2 and D3 are connected, and the other terminal is connected to the output terminal of inverter 21.
[0039] One terminal of capacitor C4 is connected to node N3, which is the connection node where diodes D3 and D4 are connected, and the other terminal is connected to the output terminal of buffer 22. One terminal of capacitor C5 is connected to node N4, which is the connection node where diodes D4 and D5 are connected, and the other terminal is connected to the output terminal of inverter 21. One terminal of capacitor C6 is connected to node N5, which is the connection node where diodes D5 and D6 are connected, and the other terminal is connected to the output terminal of buffer 23. One terminal of capacitor C7 is connected to node No, and the other terminal is connected to ground, to which the circuit's reference potential is supplied.
[0040] In this configuration example, capacitors C1 to C6 are examples of multiple capacitors, one terminal of which is connected to each connection node where switching elements are connected, and a binary clock signal is applied to the other terminal. In the above configuration, capacitors C1 to C5 are supplied with signal CLK1 or an inverted signal of signal CLK1, and capacitor C6 is supplied with signal CLK2. Capacitor C7 is provided for purposes such as smoothing the voltage Vb output from node No.
[0041] Of the capacitors C1 to C6, capacitor C6, which is located closest to node No., is designated as the final stage capacitor, while capacitors C1 to C5 other than the final stage capacitor are designated as other capacitors. In this configuration, the other capacitors are supplied with signal CLK1 or an inverted signal of signal CLK1, while the final stage capacitor is supplied with signal CLK2. In other words, the clock generation circuit 8 generates signal CLK1, which is supplied to the other capacitors, and signal CLK2, which is supplied to the last stage capacitor, as the clock signals for the charge pump circuit 9.
[0042] Next, the operating timing of each part in the above configuration will be explained. In the following explanation, for binary signals such as signals CLK1 and CLK2, a relatively high level will be referred to as the high level, and a relatively low level will be referred to as the low level. In this embodiment, for binary signals such as signals CLK1 and CLK2, one of the high level and the low level corresponds to the first level, and the other of the high level and the low level corresponds to the second level.
[0043] AFE7 is configured to terminate the sampling operation of the input signal after the signal CLK2 has changed from the first level to the second level, and before the signal CLK2 subsequently changes from the second level to the first level. In other words, AFE7 performs the sampling operation in such a way that the level of the signal CLK2 does not change during the change-prevention period from a predetermined timing in the latter half of the sampling period until the end timing of the sampling operation.
[0044] <Specific examples of the timing of each part's operation> A concrete example of the timing of the operation of each part is the timing example shown in Figure 3. In timing charts such as Figure 3, the sampling period during which sampling is performed in AFE7 is represented as "Sample," and the hold period during which hold is performed in AFE7 is represented as "Hold." AFE7 alternates between sampling and holding operations for each cycle of signal CLK3. In other words, the length of the sampling period and the hold period are the same as the length of one cycle of signal CLK3. In AFE7, the sampling period and the hold period are repeated alternately for each cycle of signal CLK3.
[0045] As shown in Figure 3, in this timing example, AFE7 terminates the sampling operation after the signal CLK2 has changed from a high level to a low level, and before the signal CLK2 subsequently changes from a low level to a high level. In other words, AFE7 performs the sampling operation so that the level of the signal CLK2 does not change during the change-prohibition period Ta, from a predetermined timing ta to the termination timing tb when the sampling operation ends, in the latter half of the sampling period.
[0046] The timing ta can be set based on the following concept. In the following explanation, the timing at which a binary signal such as signal CLK2 changes from a low level to a high level may be referred to as the rising edge, and the timing at which it changes from a high level to a low level may be referred to as the falling edge. Also, in the following explanation, the rising edge and falling edge may be collectively referred to as the edge.
[0047] The voltage Vb output from the charge pump circuit 9 is superimposed with noise caused by the rising and falling edges of the signal CLK2 that controls the switching in its final stage; in other words, noise originating from the edges of signal CLK2. The noise superimposed on voltage Vb directly affects the operation of MUX6, but indirectly affects the operation of AFE7 as well. The reason for this is as follows:
[0048] First, in the above configuration, the voltage of the battery cell Cb is input to the AFE7 via MUX6. Therefore, there is a possibility that noise may be superimposed on the voltage of the battery cell Cb when passing through MUX6, and if so, the operation of the AFE7 may also be affected by the noise. Furthermore, in the above configuration, the AFE7 is mounted on the same battery monitoring IC3 as the charge pump circuit 9, etc. Therefore, there is a possibility that noise superimposed on the voltage Vb may propagate to the AFE7 via the semiconductor substrate, and if so, the operation of the AFE7 may also be affected by the noise.
[0049] If noise superimposed on the voltage Vb affects the sampling operation by AFE7, the accuracy of voltage detection of the battery cell Cb may decrease. Therefore, in this embodiment, the timing ta is set so that noise caused by the edges of the signal CLK2 superimposed on the voltage Vb does not affect the sampling operation by AFE7. First, as shown in Figures 4 and 5, in the sampling operation by AFE7, the sampled value converges to the expected value, that is, the value corresponding to the voltage of the battery cell Cb to be detected, at a time tc that is a predetermined time before the end timing tb.
[0050] Therefore, as shown in Figure 4, if noise originating from the edge of the signal CLK2 is superimposed at a timing well before time tc, for example, in the first half of the sampling period, that noise will not affect the sampling operation, and consequently the sampled value. In this case, the sampled value in AFE7 will converge to the expected value, and the voltage of the battery cell Cb will be detected with high accuracy.
[0051] On the other hand, as shown in Figure 5, if noise originating from the edge of the signal CLK2 is superimposed at a timing close to time tc, for example, immediately after time tc, that noise will affect the sampling operation and, consequently, the sampled value. Therefore, in this case, the sampled value in AFE7 may not converge to the expected value, and as a result, errors may occur in the detection result of the voltage of the battery cell Cb.
[0052] For these reasons, the timing ta needs to be set so that even if noise is superimposed on the voltage Vb at that point, the sampled value in AFE7 can correctly converge to the expected value. In other words, the timing ta can be set to a point a predetermined margin time before time tc in the latter half of the sampling period, for example, immediately after the start of the latter half of the sampling period. In this case, the period from immediately after the start of the latter half of the sampling period to the end timing tb becomes the aforementioned change-prohibition period Ta.
[0053] According to the embodiment described above, the following effects can be obtained. The battery monitoring IC3 comprises an AFE7, a clock generation circuit 8, and a charge pump circuit 9. The clock generation circuit 8 generates two signals as the clock signal for the charge pump circuit 9: CLK1, which is supplied to other capacitors, and CLK2, which is supplied to the last stage capacitor and has a lower frequency than CLK1. The AFE7 is configured to terminate its sampling operation after CLK2 has changed from a high level to a low level, and before CLK2 subsequently changes from a low level to a high level.
[0054] In other words, the AFE7 is configured to perform sampling operations so that the level of the signal CLK2 does not change during the change-prohibition period Ta, from a predetermined timing ta in the latter half of the sampling period when the sampling operation is performed until the end timing tb when the sampling operation ends. With the above configuration, the possibility that the edge of the signal CLK2 supplied to the final stage capacitor of the charge pump circuit 9 coincides with or is close to the timing of sampling by the AFE7 can be kept low. As a result, the influence of noise caused by the edge of the signal CLK2, in other words, noise caused by the switching of the final stage of the charge pump circuit 9, on the operation of the AFE7 can be suppressed.
[0055] Furthermore, in this case, the frequency of the signal CLK1 supplied to capacitors C1 to C5, which are other capacitors in the charge pump circuit 9, can be increased compared to the frequency of the signal CLK2 supplied to capacitor C6, which is the final stage capacitor. As a result, the capacitance of capacitors C1 to C5 can be kept small, and consequently, the circuit area of the charge pump circuit 9 is reduced. Thus, according to this embodiment, an excellent effect can be obtained in which the circuit area of the charge pump circuit 9 can be kept small while suppressing the effect of noise caused by the edges of the clock signal CLK2 on the operation of the AFE7.
[0056] (Other embodiments) It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, and can be arbitrarily modified, combined, or expanded without departing from its essence. The numerical values and other figures shown in the above embodiments are illustrative and not limiting.
[0057] The charge pump circuit 9 was configured to use diodes D1 to D6 as multiple switching elements, but various semiconductor switching elements such as MOS transistors can also be used as multiple switching elements. The number of stages in the charge pump circuit 9, that is, the number of switching elements and capacitors, is not limited to those shown in the above embodiment, and can be two or more.
[0058] In other words, the charge pump circuit 9 can be configured to include a plurality of switching elements connected in series between node Ni and output node No, and a plurality of capacitors, one terminal of which is connected to each connection node where the switching elements are connected, and to which a binary clock signal is supplied to the other terminal. With such a configuration, the same operation and effects as in the above embodiment can be obtained.
[0061] This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of symbols]
[0062] 1...Battery monitoring device, 2...Battery pack, 3...Battery monitoring IC, 6...Multiplexer, 7...Analog front end, 8...Clock generation circuit, 9...Charge pump circuit, C1~C6...Capacitors, Cb...Battery cell, D1~D6...Diodes, N1~N5...Nodes, Ni...Node, No...Node.
Claims
1. A charge pump circuit (9) that generates a boosted voltage by increasing the input voltage input via an input node (Ni) and outputs the boosted voltage via an output node (No), comprising: a plurality of switching elements (D1 to D6) connected in series between the input node and the output node; and a plurality of capacitors (C1 to C6) to which one terminal is connected to each connection node (N1 to N5) to which the switching elements are connected, and a binary clock signal is supplied to the other terminal, An A / D conversion unit (7) samples the input signal and performs A / D conversion, A clock generation circuit (8) that generates the aforementioned clock signal, Equipped with, If, among the plurality of capacitors, the capacitor (C6) located closest to the output node is designated as the last stage capacitor, and the other capacitors (C1 to C5) are designated as other capacitors, The clock generation circuit generates a first clock signal to be supplied to the other capacitors and a second clock signal to be supplied to the last stage capacitor, which has a lower frequency than the first clock signal. The A / D conversion unit is configured to terminate the sampling operation of the input signal after the second clock signal has changed from the first level to the second level, and before the second clock signal subsequently changes from the second level to the first level.
2. The semiconductor device according to claim 1, wherein the A / D conversion unit performs the sampling operation so that the level of the second clock signal does not change during a change-prohibition period from a predetermined timing in the latter half of the sampling period in which the sampling operation is performed until the end timing when the sampling operation is completed.
3. Furthermore, the system includes a multiplexer (6) that operates by receiving the boosted voltage output from the charge pump circuit, The input voltage is the voltage of a battery pack (2) configured in which multiple battery cells (Cb) are connected in series. The multiplexer takes the voltages of the multiple battery cells as input and selects one of the input voltages to output. The semiconductor device according to claim 1 or 2, wherein the A / D conversion unit receives the voltage output from the multiplexer as the input signal and samples the input signal to perform A / D conversion.
4. The semiconductor device according to claim 3, used for detecting various states of the battery pack and monitoring the state of the battery pack.