Single-sensor digital control method for three-level flying capacitor buck converter

Abstract

The application discloses a single-sensor digital control method of a three-level flying capacitor step-down converter, and comprises the following steps: analyzing the working mechanism of the three-level flying capacitor step-down converter circuit, including the on-off logic of each switching device during normal operation of the circuit, four static working modes and two dynamic working switching modes; taking a static working mode point (1, 0) as an example to analyze the influence of flying capacitor voltage balance on the normal operation of the circuit; aiming at the flying capacitor voltage balance problem of the three-level flying capacitor step-down converter circuit, a single-sensor digital control strategy is provided; an improved digital control strategy is provided; then, stability analysis is carried out on the algorithm; aiming at the digital control algorithm with subharmonic oscillation, a solution strategy is provided, a digital slope compensation technology is introduced, and the subharmonic oscillation problem existing in the algorithm is eliminated; based on the deduction of the digital valley voltage control technology, the digital peak voltage control technology is summarized and extended.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a single-sensor digital control method for a three-level flying capacitor buck converter. Background Technology

[0002] Compared to traditional two-level buck converters, three-level flying capacitor buck converters offer direct advantages such as halved stress on switching devices, halved voltage swing of the filter inductor, frequency doubling of the output voltage, and reduced size of magnetic components. However, the voltage imbalance problem of the flying capacitor is a major challenge in the topology design of three-level flying capacitor buck converters. Existing research on this problem mostly focuses on relying on multi-sensor control or using analog control methods. However, a large number of sensors is detrimental to the miniaturization of the device; furthermore, analog control suffers from poor stability and limited flexibility. Summary of the Invention

[0003] In view of the problem that the existing flying capacitor voltage balancing requires too many sensors, the present invention provides a single-sensor digital control method for a three-level flying capacitor buck converter, providing a more convenient solution to the flying capacitor voltage balancing problem in a three-level flying capacitor buck circuit.

[0004] The technical solution of this invention is as follows:

[0005] A single-sensor digital control method for a three-level flying capacitor buck converter includes the following steps:

[0006] The working mechanism of a three-level flying capacitor buck converter circuit is analyzed, including the on / off logic of each switching device during normal operation, four static operating modes, and two dynamic switching modes. The on / off logic of each switching device during normal operation includes: the first switching device Q1 and the fourth switching device Q4 are complementary in conduction; the second switching device Q2 and the third switching device Q3 are complementary in conduction; and the first switching device Q1 and the second switching device Q2 exhibit a 180° phase difference staggered conduction characteristic. The four static operating modes are described by the coordinate sequence (Q1, Q2) formed by the first and second switching devices, denoted as State I, State II, State III, and State IV, respectively. The coordinate sequence (Q1, Q2) corresponds to (1,0), (0,0), (0,1), and (1,1), respectively. The two dynamic switching modes are divided into two operating modes based on the range of the voltage conversion ratio G, where the voltage conversion ratio G is the output voltage V. o With input voltage V g The ratios are as follows: In Mode 1 (G < 0.5), the circuit's static operating modes switch sequentially in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; In Mode 2 (G > 0.5), the circuit's static operating modes switch sequentially in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ.

[0007] Taking one of the static operating mode points (1,0) as an example, we analyze the impact of the flying capacitor voltage balance on the normal operation of the circuit.

[0008] To address the voltage balance problem across the flying capacitor in a three-level flying capacitor buck converter circuit, a single-sensor digital control strategy is proposed, namely, a single-sensor digital voltage dual-loop feedback V. 2 Control technologies include digital valley voltage control and digital peak voltage control;

[0009] To overcome the delay of one output change cycle, an improved digital control strategy is proposed; then, the stability of the algorithm is analyzed.

[0010] For digital control algorithms that suffer from subharmonic oscillations, a solution strategy is proposed, which introduces digital slope compensation technology to eliminate the subharmonic oscillation problem in the algorithm.

[0011] Next, based on the derivation of digital valley voltage control technology, the process is summarized and extended to digital peak voltage control technology;

[0012] Further analysis is needed to determine whether digital valleys and peak values ​​possess the characteristic of self-balancing across capacitors after the elimination of subharmonic oscillations.

[0013] In one possible implementation, the three-level flying capacitor buck converter includes a DC input voltage source V. g Flying capacitor C fly Bridge arms composed of switching devices, and filter inductor L o Output capacitor C o And the DC output terminal, DC input voltage source V g It is connected in parallel with a bridge arm consisting of four switching devices (Q1, Q2, Q3, Q4) connected in series, and a flying capacitor C fly The filter inductor L is connected in parallel across the series branch consisting of Q2 and Q3. o and output capacitor C o The series branch consisting of Q3 and Q4 is connected in parallel with the series branch consisting of Q3 and Q4, and the output capacitor C o Connected in parallel with the DC output terminal. Attached Figure Description

[0014] Figure 1 This is the basic circuit architecture of a three-level flying capacitor buck converter.

[0015] Figure 2 The four static operating modes of a three-level flying capacitor buck converter and their corresponding equivalent circuit diagrams are shown.

[0016] Figure 3Output waveforms of a three-level flying capacitor buck converter under two dynamic operating switching modes;

[0017] Figure 4 This is the digital control system architecture for the three-level flying capacitor buck converter described in this invention;

[0018] Figure 5 The waveform diagram of digital valley voltage control under leading-edge modulation mode when G<0.5;

[0019] Figure 6 The waveform diagram of digital valley voltage control under trailing edge modulation mode when G<0.5;

[0020] Figure 7 The waveform diagram of digital valley voltage control under the triangular leading edge modulation mode when G<0.5;

[0021] Figure 8 The waveform diagram of digital valley voltage control under triangular trailing edge modulation mode when G<0.5;

[0022] Figure 9 This is a timing diagram of a leading-edge modulation digital circuit;

[0023] Figure 10 The waveform diagram shows the improved digital valley voltage control under the leading-edge modulation method when G < 0.5.

[0024] Figure 11 The waveform diagram shows the improved digital valley voltage control under trailing edge modulation when G < 0.5.

[0025] Figure 12 Waveform of improved digital valley voltage control with leading edge modulation after slope compensation when G<0.5;

[0026] Figure 13 The output waveform diagram of the improved digital valley voltage control with small disturbance of flying capacitor voltage under the leading edge modulation method after slope compensation when G<0.5 is shown. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] A single-sensor digital control method for a three-level flying capacitor buck converter according to an embodiment of the present invention includes the following steps:

[0029] The working mechanism of a three-level flying capacitor buck converter circuit is analyzed, including the on / off logic of each switching device during normal operation, four static operating modes, and two dynamic switching modes. The on / off logic of each switching device during normal operation is characterized by the complementary conduction of the first switching device Q1 and the fourth switching device Q4, the complementary conduction of the second switching device Q2 and the third switching device Q3, and the staggered conduction characteristic of the first switching device Q1 and the second switching device Q2 with a 180° phase difference. The four static operating modes are characterized by being described by the coordinate sequence (Q1, Q2) formed by the first and second switching devices, respectively denoted as State I, State II, State III, and State IV, with the coordinate sequence (Q1, Q2) corresponding to (1,0), (0,0), (0,1), and (1,1), respectively. The two dynamic switching modes are characterized by dividing the dynamic switching process of the circuit into two operating modes according to the range of the voltage conversion ratio G, where the voltage conversion ratio G is the output voltage V. o With input voltage V g The ratios are as follows: In Mode 1 (G < 0.5), the circuit's static operating modes switch sequentially in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; In Mode 2 (G > 0.5), the circuit's static operating modes switch sequentially in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ.

[0030] Taking one of the static operating mode points (1,0) as an example, we analyze the impact of the flying capacitor voltage balance on the normal operation of the circuit. If the voltage across the flying capacitor cannot reach the steady-state value, the voltage imbalance problem of the series devices will be highlighted.

[0031] To address the voltage balance problem across the flying capacitor in a three-level flying capacitor buck converter circuit, a single-sensor digital control strategy is proposed, namely, a single-sensor digital voltage dual-loop feedback V. 2 Control technologies include digital valley voltage control technology and digital peak voltage control technology;

[0032] To overcome the delay of one output change cycle, an improved digital control strategy is proposed; then, the stability of the algorithm is analyzed.

[0033] For digital control algorithms that suffer from subharmonic oscillations, a solution strategy is proposed, which introduces digital slope compensation technology to eliminate the subharmonic oscillation problem in the algorithm.

[0034] Next, based on the derivation of digital valley voltage control technology, a table is given to summarize the extension to digital peak voltage control technology;

[0035] Further analysis is needed to determine whether digital valleys and peak values ​​possess the characteristic of self-balancing across capacitors after the elimination of subharmonic oscillations.

[0036] In one specific embodiment of the present invention, such as Figure 1As shown, the basic circuit structure of a three-level flying capacitor buck converter is proposed. This circuit mainly includes a DC input voltage source V... g Flying capacitor C fly Bridge arms composed of switching devices, and filter inductor L o Output capacitor C o And the DC output terminal. DC input voltage source V g It is connected in parallel with a bridge arm consisting of four switching devices (Q1, Q2, Q3, Q4) connected in series. Flying capacitor C fly It is connected in parallel across the series branch consisting of Q2 and Q3. The filter inductor L o and output capacitor C o The series branch formed by Q3 and Q4 is connected in parallel with the series branch formed by Q3 and Q4. Output capacitor C o It is connected in parallel with the DC output terminal. In an exemplary embodiment of the present invention, the DC output terminal is taken as an example of a purely resistive load R connected in parallel, and the voltage across the purely resistive load R is denoted as the output voltage v. o For ease of subsequent description, Figure 1 The key measurement points are marked: the voltage across the series branch consisting of switching devices Q3 and Q4 is defined as the switching node voltage V. sw At the same time, the flying capacitor C is set. fly and filter inductor L o The direction of the reference current is as follows Figure 1 The diagram is shown to illustrate the circuit's operating principle and dynamic behavior.

[0037] In a specific application example, the working mechanism of the aforementioned three-level flying capacitor buck converter circuit can be analyzed as follows: the conduction logic of each switching device during normal operation; the four static operating modes; and the two dynamic switching modes. Specifically, the conduction logic of each switching device during normal operation includes: the first switching device Q1 and the fourth switching device Q4 are complementary in conduction; the second switching device Q2 and the third switching device Q3 are complementary in conduction. Complementary conduction means that when one device in a pair is on, the other is off, and vice versa. Furthermore, when the three-level flying capacitor buck converter circuit reaches a steady state, the first switching device Q1 and the second switching device Q2 exhibit a 180° phase difference staggered conduction characteristic.

[0038] Further analysis Figure 1The three-level flying capacitor buck converter circuit shown has four static operating modes. Due to the complementary conduction characteristics of the switching devices in the three-level flying capacitor buck converter, there are two degrees of freedom in controlling the on / off state of the four switching devices. For example, when the on / off state of the first switching device Q1 and the second switching device Q2 is determined, the on / off state of the third switching device Q3 and the fourth switching device Q4 is also determined. If a certain switching device is on, it is denoted as Q. n =1 (where n = 1, 2, 3, 4); if a certain switching device is turned off, it is denoted as Q. n =0 (where n = 1, 2, 3, 4). In this embodiment of the invention, the first switching device Q1 and the second switching device Q2 are used as examples for explanation, but the embodiments of the invention are not limited to this. Q1 has two on / off states, namely Q1 = 1 or Q1 = 0, and Q2 also has two on / off states, namely Q2 = 1 or Q2 = 0. If the on state of the first switching device Q1 is used as the horizontal axis and the on state of the second switching device Q2 is used as the vertical axis to form a coordinate sequence (Q1, Q2), and the circuit is described by this coordinate sequence, there are 4 static operating modes, which are denoted as state I, state II, state III, and state IV, respectively. The coordinate sequence (Q1, Q2) corresponds to (1, 0), (0, 0), (0, 1), and (1, 1), respectively. The equivalent circuit diagrams corresponding to the 4 static operating modes are as follows. Figure 2 As shown.

[0039] Further analysis Figure 1 The three-level flying capacitor buck converter circuit shown has two dynamic operating switching modes, specifically including the defined output voltage V. o With input voltage V g The ratio is the voltage conversion ratio G, that is Ideally, the duty cycles D1 and D2 of G, Q1, and Q2 are equal. Due to the interleaved conduction characteristics of the switching devices in the three-level flying capacitor buck converter, the circuit will experience variations in voltage conversion ratio G within one switching cycle (T). s This presents two different dynamic work switching modes. For example... Figure 3 As shown, the two dynamic working switching modes are: Mode 1: when G < 0.5, Figure 2 The static operating modes of the circuit are switched sequentially in the order of I→II→III→II; Mode 2: When G>0.5, Figure 2 The circuit's static operating modes switch sequentially in the order of IV→I→IV→III. In both modes, the output voltage will remain constant within one switching cycle (T). s The output voltage changes twice within a given period, and the period of this change is denoted as T. sw .

[0040] In a specific application example, taking one of the static operating mode points (1,0) as an example, the impact of the flying capacitor voltage balance on the normal operation of the circuit is analyzed. This analysis includes a detailed explanation using the circuit operating mode (Q1,Q2)=(1,0) as an example, but the embodiments of the present invention are not limited thereto. For Figure 1 The three-level flying capacitor buck converter circuit has an input voltage V. g With the first switching device Q1 and the flying capacitor C fly The first switching circuit is formed by the fourth switching device Q4; simultaneously, the flying capacitor C... fly Together with the second switching device Q2 and the third switching device Q3, they form a second switching circuit. (Reference) Figure 2 In the static operating state at coordinate point (1,0), that is, when the first switching device Q1 is turned on and the second switching device Q2 is turned off, the fourth switching device Q4 is turned off and the third switching device Q3 is turned on accordingly. The equivalent circuit is as follows: Figure 2 As shown in State I. In the first switching circuit, the voltage relationship holds as follows, denoted by the flying capacitor C. fly The voltage across the terminals is v fly The voltage across the fourth switching device Q4 is

[0041]

[0042] In the second switching circuit, the voltage relationship exists as follows, denoted as: [Equation omitted for brevity].

[0043]

[0044] From equations (1) and (2), it can be seen that if the flying capacitor C fly Voltage v at both ends fly Able to reach steady-state value, that is Then the voltage drops of the second switching device Q2 and the fourth switching device Q4 are equal and are only equal to the input voltage V. g Half of it. Conversely, if the capacitor C flies across... fly Voltage v at both ends fly Unable to reach steady-state value, i.e., exhibiting or All of these situations will lead to and The unequal voltage distribution in series components, if persisting for a long time, will not only exacerbate the voltage instability of the flying capacitor and cause charging and discharging imbalances, but will ultimately lead to the imbalance of the three-level flying capacitor buck converter system and the loss of its circuit function. Therefore, regarding... Figure 1 The three-level flying capacitor buck converter circuit shown controls the flying capacitor C. fly Voltage v at both ends flyAchieving balance is particularly important for the normal operation of the circuit and for leveraging the key advantages of this topology.

[0045] In a specific application example, for Figure 1 the voltage balance problem across the flying capacitors of the three-level flying-capacitor buck converter circuit shown, a digital control strategy based on a single sensor is proposed, namely, a digital voltage dual-loop feedback V 2 control technology, including digital valley voltage control technology and digital peak voltage control technology, specifically including the control system architecture, control principle, control process, and control algorithm.

[0046] Furthermore, the present invention proposes a digital control system architecture for a three-level flying-capacitor buck converter, which is characterized in that as Figure 4 shown, it consists of a three-level flying-capacitor buck converter circuit and a digital controller. The digital controller integrates an analog-to-digital converter (ADC), a discrete proportional-integral-derivative (D-PID) compensator, and a digital pulse-width modulator (DPWM). Specifically, the output voltage port of the three-level flying-capacitor buck converter circuit and the drive signal port for controlling the states of four switching devices are respectively connected to the digital controller.

[0047] Furthermore, the control principle of the present invention is based on Figure 4 the analysis shown in this figure, which is an extension of the basic circuit of the three-level flying-capacitor buck converter shown in Figure 1 . Specifically, when the equivalent series resistance R o on the output capacitor C e branch is significantly smaller than the load resistance R, i.e., R e <<R, then the high-frequency varying inductor current ripple Δi L in the inductor completely flows through the output capacitor C o and discharges the output capacitor C e through the series resistance R o , thereby generating a voltage drop Δi e R L on R e that is the same as the slope of the inductor current. When the capacitance of C o is very large, its voltage V cap can be considered constant, and the output voltage consists of a constant quantity and a ripple quantity, i.e., V o = V cap + Di L R e , and the ripple change trend of the output voltage V o will change with the change of the inductor current ripple Δi L . The digital controller senses the output voltage V oThe ripple changes, and based on this, the algorithm proposed in this invention reacts to generate corresponding drive signals, control the switching devices in the circuit to turn on and off, and thus achieve the target output.

[0048] Furthermore, the control process of the present invention specifically includes the following steps: the analog-to-digital converter (ADC) module in the digital controller processes the output voltage V. o Sampling is performed to obtain digitized sampled values ​​v. o The system has a preset reference voltage V stored in digital form. ref The reference voltage is compared with the sampled output voltage v. o The comparison generates an error signal. This error signal is then fed into the Discrete Proportional-Integral-Derivative (D-PID) control module to generate the corresponding voltage control signal v. pi Next, the digital pulse width modulation (DPWM) module calculates the current output voltage sample value v. o and the voltage control signal v generated by the D-PID module pi By combining the specific algorithm proposed in this invention, the required switching duty cycle of the circuit is calculated. Based on this calculation result, the DPWM module outputs high and low level drive signals at different time intervals to precisely control the on and off states of the four switching devices, thereby achieving effective regulation of the output voltage.

[0049] Furthermore, the present invention provides a detailed description of the control algorithm, specifically including the implementation of the digital valley voltage control algorithm under leading edge, trailing edge, triangular leading edge, and triangular trailing edge modulation, and the three-level flying capacitor buck converter operating in mode one, i.e., G<0.5, as an example. However, the embodiments of the present invention are not limited to this.

[0050] like Figure 5 The figure shows the control waveform of a three-level flying capacitor buck converter with digital valley voltage control operating under the condition G < 0.5, when the inductor current is in continuous conduction mode (the inductor current never reaches 0 within one switching cycle). Here, m1 and m2 are the output voltage ripple detected by the digital controller, respectively. o Based on the working principle of the three-level flying capacitor buck converter, the rising and falling slopes of m1 and m2 are respectively within the range of G < 0.5, where m1 and m2 are:

[0051]

[0052] d n-1 d n These are the duty cycles of the switching devices corresponding to two adjacent output voltage changes, V oThe output voltage is the average value in steady state. The solid line represents the steady-state waveform, and the dotted line represents the trend of output voltage change after a disturbance occurs. The output voltage is sampled once at the beginning of each output voltage change cycle to obtain the sampled value v. o The values ​​of two consecutive samples are defined as v. o (n-1), v o (n). The digital controller generates the valley voltage control signal v through its built-in discrete proportional-integral-derivative (D-PID) controller. pi Since the system's natural frequency is much lower than the switching frequency, the valley voltage control signal v can be considered to be within two adjacent output voltage variation cycles. pi No significant changes occurred, i.e., v pi (n)=v pi (n-1). The voltage disturbance that occurs at the beginning of the (n-1)th cycle. Reflected in v o In (n-1), if no other disturbances occur in the current period, then... DPWM according to v o (n-1), v pi Duty cycle d n-1 The circuit parameters pre-stored within the digital controller, and the duty cycle d calculated for different modulation methods. n This ensures that during the nth period, the valley of the output voltage ripple is detected and v pi Equal. According to... Figure 5 The principle of digital valley voltage control under leading-edge modulation when G < 0.5 is as follows: at the beginning of the nth switching cycle, both Q1 and Q2 are turned off, and v o The descent occurred over a time period of 0.5 days. n-1 )T s After that, Q1 is turned on, v o Rise, conduction d n-1 T s After a certain time, Q1 is turned off again, maintaining the current switching cycle (T) indefinitely. s End, Q1 and Q2 are staggered. The circuit is always on. Let the ripple voltage valley value in the nth switching cycle be v. ovy (n), by Figure 5 have to:

[0053] v pi =v ovy (n)=v o (n-1)-m2d' n-1 T s +m1d n-1 T s -m2d' n T s (4)

[0054] Among them, d' n =0.5-d n ,d' n-1 =0.5-d n-1 From equation (4), we can further obtain the duty cycle algorithm for the digital valley control three-level flying capacitor buck converter under leading-edge modulation mode when the voltage conversion ratio G < 0.5:

[0055]

[0056] Similarly, refer to Figure 6 The waveform of digital valley voltage control under trailing edge modulation is given when G < 0.5. In trailing edge modulation, the sampling point of each output change cycle appears at the valley position of the ripple. Figure 6 We can obtain:

[0057] v pi =v ovy (n)=v o (n-1)+m1d n-1 T s -m2d' n-1 T s +m1d n T s -m2d' n T s (6)

[0058] From equation (6), we can further obtain the duty cycle algorithm for the digital valley control three-level flying capacitor buck converter under trailing edge modulation mode when the voltage conversion ratio G < 0.5:

[0059]

[0060] Similarly, refer to Figure 7 The digital valley voltage control with triangular leading edge modulation when G < 0.5 is given. At the beginning of the nth cycle, Q1 and Q2 are turned off, and v o Descending, after time Q1 is on, v o Ascend, after d n-1 T s In time, Q1 will shut down again until the end of the current cycle, and Q2 will overlap with Q1. Time-based conduction. In triangular leading-edge modulation, the sampling point of each switching cycle appears in the middle of the output voltage ripple decline phase; switching transistors Q2 and Q1 in each output voltage change cycle (T in the figure) sw The start and end segments of the sequence have equal shutdown times. Figure 7 We can obtain:

[0061]

[0062] From equation (8), we can further obtain the duty cycle algorithm for the digital valley control three-level flying capacitor buck converter under the triangular leading edge modulation mode when G < 0.5:

[0063]

[0064] Similarly, refer to Figure 8 The digital valley voltage control with triangular trailing edge modulation when G < 0.5 is given, by... Figure 8 We can obtain:

[0065]

[0066] From equation (10), we can further obtain the duty cycle algorithm for the digital valley control three-level flying capacitor buck converter under the triangular trailing edge modulation mode when G < 0.5:

[0067]

[0068] In a specific application example, since the above derivations are all within the range of G<0.5, this invention extends the applicability of digital control to the range of G>0.5. Its characteristic is that, as can be seen from the above analysis, equations (5), (7), (9), and (11) respectively give the duty cycle algorithms for the three-level flying capacitor buck converter under digital valley control modulation of the leading edge, trailing edge, symmetrical triangle leading edge, and symmetrical triangle trailing edge when G<0.5. When G>0.5, the above algorithms are still applicable, the difference being that the rising and falling slopes of the output voltage ripple are different in the two operating modes. Equation (12) gives the expressions for m1 and m2 when G>0.5:

[0069]

[0070] Observe the duty cycles of equations (5), (7), (9), and (11). The duty cycles obtained by the above algorithms are all calculated based on the quantities in the previous output change cycle. There is a delay of one output change cycle. If the delay of one output change cycle can be overcome, the duty cycle required for the current switch can be calculated based on the state quantity of the current output change cycle.

[0071] In a specific application example, this invention overcomes the delay of one output change cycle and proposes an improved digital control strategy. Specifically, for digital control circuits, the following time interval typically exists: sampling time and circuit delay interval t. s The algorithm calculates the time interval t. c (Including D-PID and DPWM times), duty cycle update time t r For the digital valley voltage controlled three-level flying capacitor buck converter described in this invention, there are... The key to overcoming the switching cycle delay is to maximize t. r This allows sufficient time to update the duty cycle, while t s Typically determined by the circuit hardware structure, it remains largely unchanged; therefore, minimizing t is crucial. c This increases the feasibility of overcoming switching cycle delay. Taking the timing diagram of a leading-edge modulated digital circuit as an example, such as... Figure 9 If the timing t can be satisfied r >dT s This allows for the implementation of an improved leading-edge modulation digital valley control algorithm. For example... Figure 10 As shown, the control waveform of the improved digital valley control three-level flying capacitor buck converter under leading-edge modulation is presented. According to... Figure 10 We can obtain:

[0072] v pi =v ovy (n-1)=v o (n-1)-m2(0.5-d n-1 )T s (13)

[0073] From equation (13), we can further obtain the duty cycle algorithm for the improved digital valley control three-level flying capacitor buck converter under the leading edge modulation mode as follows:

[0074]

[0075] Depend on Figure 10 It can be seen that after a disturbance occurs at the beginning of the (n-1)th cycle, the valley of the output voltage ripple can reach the control target v in the (n-1)th cycle. pi .

[0076] Similarly, equations (15), (16), and (17) respectively give the duty cycle calculation algorithms for the improved digital valley voltage-controlled three-level flying capacitor buck converter under trailing edge modulation, triangular leading edge modulation, and triangular trailing edge modulation modes:

[0077]

[0078] In a specific application example, this invention performs stability analysis on the algorithm. Specifically, the improved digital control algorithm overcomes the delay in the output change cycle present in the traditional digital control algorithm, and both have the same stability. Taking the improved digital control algorithm as an example, stability analysis is performed using a ratio... Conduct research. According to... Figure 10 The improved digital valley voltage control waveform under leading-edge modulation can be obtained from the geometric relationship of the triangle and parallelogram in the figure:

[0079]

[0080] The stable region needs to satisfy |K| < 1. Substituting m1 and m2 when G < 0.5 and G > 0.5 respectively, the stable region of the improved digital valley voltage control three-level flying capacitor buck converter under the leading-edge modulation method is obtained:

[0081]

[0082] Similarly, from Figure 11 the control waveforms of the improved digital valley voltage control three-level flying capacitor buck converter under the trailing-edge modulation method shown, it can be seen that the output voltage disturbance that appears at the beginning of the previous output voltage change cycle disappears at the end of the next output voltage change cycle. Therefore, the trailing-edge modulation eliminates the possible subharmonic oscillation problem in the improved digital valley voltage control three-level flying capacitor buck converter from the modulation principle. Therefore, the stable region of the improved digital valley voltage control three-level flying capacitor buck converter under the trailing-edge modulation method is 0 < G < 1; in addition, similar to the principle of deriving the stable region of the leading-edge modulation, it can be obtained that the improved digital valley voltage control three-level flying capacitor buck converter under the triangular leading-edge modulation method will generate subharmonic oscillations in the entire voltage conversion ratio range, that is, 0 < G < 1; the stable range of the improved digital valley voltage control three-level flying capacitor buck converter under the triangular trailing-edge modulation method is the same as that of the trailing-edge modulation, which is 0 < G < 1.

[0083] In a specific application example, for the digital control algorithm with subharmonic oscillations, a solution strategy is proposed, and the digital ramp compensation technology is introduced to eliminate the subharmonic oscillation problem existing in the algorithm. It is characterized in that the control waveforms of the leading-edge modulation improved digital valley control three-level flying capacitor buck converter using the digital ramp compensation technology are as Figure 12 shown, and k comp is the slope of the digital ramp compensation. It can be obtained that:

[0084]

[0085] Substituting m1 and m2 when G < 0.5 and G > 1 respectively, we get:

[0086]

[0087] Therefore, the minimum ramp slope required for the algorithm of the leading-edge modulation improved digital valley control three-level flying capacitor buck converter using the digital ramp compensation technology is Similarly, the minimum ramp slope required for the algorithm of the triangular leading-edge modulation improved digital valley control three-level flying capacitor buck converter using the digital ramp compensation technology is

[0088] Furthermore, the above derivations for the single-sensor digital voltage dual-loop feedback control technology proposed in this invention are all based on digital valley voltage control technology. A similar derivation process and conclusion exist for digital peak voltage control technology. Specifically, Table 1 summarizes the duty cycle calculation methods for the single-sensor digital voltage dual-loop feedback control technology under different modulation schemes, including leading-edge modulation, trailing-edge modulation, triangular leading-edge modulation, and triangular trailing-edge modulation, applicable to both digital valley voltage control and digital peak voltage control technologies. In addition, this invention also proposes improved digital valley voltage control and improved digital peak voltage control technologies, and Table 1 lists the corresponding duty cycle algorithm expressions for these two improved technologies.

[0089]

[0090] Meanwhile, since the improved digital control algorithm has the same stability as the traditional digital control algorithm, Table 2 details the stability regions of the single-sensor digital voltage dual-loop feedback control technology under different modulation methods, applicable to (improved) digital valley voltage control technology and (improved) digital peak voltage control technology. Specifically, the digital valley voltage control technology is stable across the entire range under trailing-edge modulation and triangular trailing-edge modulation methods, unstable across the entire range under triangular leading-edge modulation method, and stable in a partial range under leading-edge modulation method; similar conclusions are reached for the digital peak voltage control technology. Furthermore, regarding the case of subharmonic oscillations, the original control voltage signal (v... pi Based on the above, slope compensation is superimposed. The minimum slope that can be compensated varies depending on whether it is single-edge modulation (leading edge modulation, trailing edge modulation) or double-edge modulation (triangular leading edge modulation, triangular trailing edge modulation). Whether to compensate for positive or negative slopes also varies depending on whether valley control or peak control is used.

[0091]

[0092] Furthermore, regarding the impact of eliminating subharmonic oscillations in the output voltage using digital slope compensation technology on the stability of the flying capacitor voltage, the analysis includes, for example... Figure 13 Taking a three-level flying capacitor buck converter with digital valley control under front-edge modulation and operating in G<0.5 mode as an example, assuming there is a disturbance V on the flying capacitor. fly That is, the voltage across the capacitor Due to the disturbance V on the flying capacitor fly The existence of this will inevitably result in an imbalance in the charging and discharging of the flying capacitor, and will also cause the duty cycles of the two switching devices to be different, denoted as D1 and D2 respectively. Based on the geometric relationship of the waveforms, the following can be obtained:

[0093]

[0094] The formula for the average current flowing through the flying capacitor is:

[0095]

[0096] Among them, A pos and A neg Let the positive and negative areas of the current curve of the flying capacitor be respectively. By solving the geometric relationship and substituting equations (24) and (25) into equation (26), we obtain the formula for the average current of the flying capacitor in the range of G < 0.5:

[0097]

[0098] From equation (27), it can be seen that within the range of G < 0.5, when the slope of the compensation slope satisfies This will cause the average current I across the capacitor to... fly The positive and negative values ​​of the voltage disturbance V fly The positive and negative signs are opposite. Therefore, we can conclude that in a three-level flying capacitor buck converter with digital valley control under leading-edge modulation, once the subharmonic oscillation of the converter output voltage is suppressed, this technique will inherently stabilize the flying capacitor voltage, eventually bringing it to a balanced state. Similarly, the digital valley control method under triangular leading-edge modulation can also reach a similar conclusion. Therefore, digital valley control possesses the characteristic of self-balancing of the flying capacitor voltage after the subharmonic oscillation is eliminated.

[0099] Unlike other methods, digital peak control does not possess the self-balancing characteristic of the flying capacitor voltage after the subharmonic oscillation is eliminated. The flying capacitor voltage will only stabilize when the peak-to-peak ripple is sufficiently large.

[0100] It should be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A single-sensor digital control method for a three-level flying capacitor buck converter, characterized in that, Includes the following steps: Four switching devices Q1, Q2, Q3, and Q4 are connected in series to form a bridge arm; The working mechanism of a three-level flying capacitor buck converter circuit is analyzed, including the on / off logic of each switching device during normal operation, four static operating modes, and two dynamic switching modes. The on / off logic of each switching device during normal operation includes: the first switching device Q1 and the fourth switching device Q4 are complementary in conduction; the second switching device Q2 and the third switching device Q3 are complementary in conduction; and the first switching device Q1 and the second switching device Q2 exhibit a 180° phase difference staggered conduction characteristic. The four static operating modes are described by the coordinate sequence (Q1, Q2) formed by the first and second switching devices, denoted as State I, State II, State III, and State IV, respectively. The coordinate sequence (Q1, Q2) corresponds to (1,0), (0,0), (0,1), and (1,1), respectively. The two dynamic switching modes are divided into two operating modes based on the range of the voltage conversion ratio G, where the voltage conversion ratio G is the output voltage V. o With input voltage V g The ratios are as follows: In Mode 1 (G < 0.5), the circuit's static operating modes switch sequentially in the order of Ⅰ→Ⅱ→Ⅲ→Ⅱ; In Mode 2 (G > 0.5), the circuit's static operating modes switch sequentially in the order of Ⅳ→Ⅰ→Ⅳ→Ⅲ. The impact of the flying capacitor voltage balance on the normal operation of the circuit is analyzed using one of the static operating mode points (1,0). A digital voltage dual-loop feedback V² control based on a single sensor is executed by a digital controller. The digital controller is configured to sample the output voltage at a single point, generate a control voltage signal through discrete proportional-integral regulation, and adjust the duty cycle of the switching device based on digital pulse width modulation. The digital voltage dual-loop feedback V² control includes digital valley voltage control and digital peak voltage control, as detailed below: ； Where d n-1 This represents the duty cycle of switching device Q1 or Q2 during the (n-1)th output voltage change cycle; v o (n-1) represents the output voltage sample value during the (n-1)th output voltage change cycle; v pi This represents the voltage control signal generated by the D-PID module from the error signal obtained by comparing the reference voltage and the sampled output voltage; m1 represents the magnitude of the rising slope of the output voltage ripple detected by the digital controller; m2 represents the magnitude of the falling slope of the output voltage ripple detected by the digital controller; T s This represents the switching cycles of switching devices Q1, Q2, Q3, and Q4; the duty cycle update time t is maximized. r Minimize the algorithm to calculate the time interval t c This eliminates the delay; Digital slope compensation technology is introduced to eliminate subharmonic oscillations in the algorithm.

2. The single-sensor digital control method for a three-level flying capacitor buck converter as described in claim 1, characterized in that, The three-level flying capacitor buck converter includes a DC input voltage source V. g Flying capacitor C fly Bridge arms composed of switching devices, and filter inductor L o Output capacitor C o And the DC output terminal, DC input voltage source V g It is connected in parallel with a bridge arm consisting of four switching devices Q1, Q2, Q3, and Q4 connected in series, and a flying capacitor C fly The filter inductor L is connected in parallel across the series branch consisting of Q2 and Q3. o and output capacitor C o The series branch consisting of Q3 and Q4 is connected in parallel with the series branch consisting of Q3 and Q4, and the output capacitor C o Connected in parallel with the DC output terminal.

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