rectifier

Abstract

This rectifier firstly comprises a semiconductor layer (101) that is configured in a column shape that extends in a predetermined direction, and has a channel formed therein. The rectifier also comprises a first gate (102) that is disposed spaced away from one end (111) of the semiconductor layer (101) and applies a gate voltage to the semiconductor layer (101), and a second gate (103) that is disposed spaced away from the first gate (102) on the other end (112) side of the semiconductor layer (101) and applies a gate voltage to the semiconductor layer (101). The first gate (102) and the second gate (103) are formed on the semiconductor layer (101) with a gate insulating layer 121 interposed therebetween. The rectifier also comprises a charge accumulation region (104) that is formed in the semiconductor layer (101) between the first gate (102) and the second gate (103). An alternating current signal is inputted to the one end (111) of the semiconductor layer (101) and a direct current signal is outputted from the other end (112) of the semiconductor layer (101).

Description

[Technical Field]

[0001] This invention relates to a rectifier that converts AC signals into DC signals. [Background technology]

[0002] Wireless communication and microwave power transmission require receiving AC signals using antennas and rectifying them into DC signals, necessitating the use of various rectifiers. When using diodes as rectifiers, the capacitance component formed by the pn junction causes the impedance to drop at high frequencies. Furthermore, the rectification characteristics cannot be maintained due to factors such as the recovery characteristics when switching from forward bias to reverse bias of the diode, thus limiting the usable frequency bandwidth. Additionally, because AC signals must be transmitted, the usable frequency bandwidth is also limited by the RC time constant due to parasitic components of the diode and wiring.

[0003] On the other hand, devices using low-dimensional materials such as carbon nanotubes and semiconductor quantum dots have also been reported for rectifying high-frequency signals such as THz (Non-Patent Literature 1). In this device, a THz signal with an energy corresponding to the energy level of the low-dimensional material is input, exciting electrons at the energy level of the input signal and monitoring it as a DC current. This device has the advantage that the RC time constant problem is easier to solve because it does not transmit the THz signal itself and convert it to DC. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Y. Kawano, "Terahertz Response of Carbon Nanotubes and Graphene", Journal of the Physical Society of Japan, vol. 84, 121010, 2015. [Overview of the project] [Problems that the invention aims to solve]

[0005] However, the aforementioned technology utilizes electron excitation by THz signals, making room-temperature operation difficult in principle. Furthermore, its strong dependence on energy levels limits material selection and makes device fabrication challenging. Thus, conventional rectifiers have found it difficult to convert high-frequency signals from 100 GHz to THz into DC at room temperature due to the device's operating principle and RC time constant.

[0006] This invention was made to solve the above-mentioned problems and aims to provide a rectifier that can convert high-frequency signals of 100 GHz to THz into DC at room temperature. [Means for solving the problem]

[0007] The rectifier according to the present invention comprises a semiconductor layer that is columnar in shape and extends in a predetermined direction to form a channel, a first gate that is spaced apart from one end of the semiconductor layer and applies a gate voltage to the semiconductor layer, a second gate that is spaced apart from the first gate on the other end of the semiconductor layer and applies a gate voltage to the semiconductor layer, and a charge storage region formed in the semiconductor layer between the first gate and the second gate, wherein an AC signal is input to one end of the semiconductor layer and a DC signal is output from the other end of the semiconductor layer.

[0008] Furthermore, the rectifier according to the present invention comprises a first semiconductor layer which is columnar in shape and has a channel formed thereon extending in a predetermined first direction; a first gate which is spaced apart from one end of the first semiconductor layer and applies a gate voltage to the first semiconductor layer; a second semiconductor layer which is columnar in shape and extends in a second direction intersecting the first direction, with the other end of the first semiconductor layer being the second gate; and a charge storage region which is formed in the first semiconductor layer between the first gate and the second gate, wherein an AC signal is input to one end of the first semiconductor layer and a DC signal flows through the second semiconductor layer. [Effects of the Invention]

[0009] As described above, according to the present invention, a first gate and a second gate are provided in a columnar semiconductor layer, a charge storage region is formed in the semiconductor layer between the first gate and the second gate, and an AC signal is input to one end of the semiconductor layer on the first gate side. As a result, a rectifier capable of converting high-frequency signals of 100 GHz to THz into DC at room temperature can be provided. [Brief explanation of the drawing]

[0010] [Figure 1A] Figure 1A is a cross-sectional view showing the basic configuration of a rectifier for illustrating the principle of the present invention. [Figure 1B] Figure 1B is a plan view showing the basic configuration of a rectifier for explaining the principle of the present invention. [Figure 1C] Figure 1C is a circuit diagram showing the equivalent circuit of the basic configuration of a rectifier to explain the principle of the present invention. [Figure 2A] Figure 2A is a band diagram showing the energy band structure of the semiconductor layer 101 of the rectifier to illustrate the principle of the present invention. [Figure 2B] Figure 2B is a band diagram showing the energy band structure of the semiconductor layer 101 of the rectifier to illustrate the principle of the present invention. [Figure 2C] Figure 2C is a band diagram showing the energy band structure of the semiconductor layer 101 of the rectifier to illustrate the principle of the present invention. [Figure 3A] Figure 3A is a characteristic diagram showing the relationship between the frequency of the AC signal applied to one end 111 and the rise in potential of the charge storage region 104. [Figure 3B] Figure 3B is a characteristic diagram showing the results of monitoring the state in which the number of electrons in the charge storage region 104 changes depending on the presence or absence of an AC signal when Telectron = 3 seconds. [Figure 4A] Figure 4A is a cross-sectional view showing the configuration of a rectifier according to Embodiment 1 of the present invention. [Figure 4B] Figure 4B is a plan view showing the configuration of a rectifier according to Embodiment 1 of the present invention. [Figure 4C] Figure 4C is a cross-sectional view showing the configuration of a rectifier according to Embodiment 1 of the present invention. [Figure 4D] FIG. 4D is a circuit diagram showing an equivalent circuit of the configuration of the rectifier according to Embodiment 1 of the present invention. [Figure 5A] FIG. 5A is an energy band diagram representing the operating principle of the rectifier according to Embodiment 1 of the present invention. [Figure 5B] FIG. 5B is an energy band diagram representing the operating principle of the rectifier according to Embodiment 1 of the present invention. [Figure 6A] FIG. 6A is a cross-sectional view showing the configuration of the rectifier according to Embodiment 2 of the present invention. [Figure 6B] FIG. 6B is a plan view showing the configuration of the rectifier according to Embodiment 2 of the present invention. [Figure 6C] FIG. 6C is a circuit diagram showing an equivalent circuit of the configuration of the rectifier according to Embodiment 2 of the present invention. [Figure 7A] FIG. 7A is a cross-sectional view showing the configuration of the rectifier according to Embodiment 3 of the present invention. [Figure 7B] FIG. 7B is a plan view showing the configuration of the rectifier according to Embodiment 3 of the present invention. [Figure 8A] FIG. 8A is a cross-sectional view showing the configuration of the rectifier according to Embodiment 4 of the present invention. [Figure 8B] FIG. 8B is a plan view showing the configuration of the rectifier according to Embodiment ...............

Embodiments for Carrying Out the Invention

[0011] The following describes a rectifier according to an embodiment of the present invention. First, the principle of the present invention will be explained with reference to Figures 1A, 1B, and 1C. Figure 1A is a cross-sectional view showing the basic configuration of the rectifier, Figure 1B is a plan view showing the basic configuration of the rectifier, and Figure 1C is an equivalent circuit of the basic configuration of the rectifier. This rectifier has a semiconductor layer 101 and a first gate 102 as its basic configuration. The semiconductor layer 101 is columnar in shape extending in a predetermined direction, forming a channel through which carriers flow. The first gate 102 is positioned spaced apart from one end of the semiconductor layer 101 and applies a gate voltage to the semiconductor layer 101. The first gate 102 is provided with respect to the semiconductor layer 101 via a gate insulating layer 121.

[0012] An AC signal is input to one end 111 of the semiconductor layer 101, relative to the formation position of the first gate 102. A charge storage region 104 is also positioned on the other end of the semiconductor layer 101, relative to the formation position of the first gate 102.

[0013] An input terminal is connected to one end 111 of the field-effect transistor formed by the semiconductor layer 101 and the first gate 102, and nothing is connected to the other end 112. However, because it has a capacitive component, it can be considered as an equivalent circuit with a capacitor 122 connected, as shown in Figure 1C.

[0014] Figures 2A, 2B, and 2C show the energy band structure of the semiconductor layer 101. Here, we consider the case where an energy barrier is formed by the first gate 102, and the charge storage region 104 connected to the capacitor is electrically disconnected from one end 111 (input terminal). The electrons on the one end 111 side and the electrons in the charge storage region 104 have energy due to heat (thermal energy) and move randomly. Therefore, the energy possessed by electrons varies from electron to electron for each Fermi level, and the probability of possessing that energy follows a Boltzmann distribution with respect to the Fermi level.

[0015] Since the Boltzmann distribution is uniquely determined by thermal energy, i.e., temperature, when no signal is input to one end 111, the electron energy distribution in the semiconductor layer 101 on the side of one end 111 (a) and the electron energy distribution in the charge storage region 104 (b) have the same shape (Figure 2A). For this reason, an equilibrium state is maintained in which the flow of electrons entering the charge storage region 104 from the side of one end 111 via the first gate 102 is equal to the flow of electrons entering the side of one end 111 from the charge storage region 104.

[0016] Next, when an AC signal is applied to one end 111, the energy of the electrons changes by the amount of this AC signal. As shown in Figure 2B, the electron energy distribution (a) in the semiconductor layer 101 on the side of the one end 111 widens the range of electron energy that electrons can possess. As a result, a difference in electron energy distribution occurs between the charge storage region 104, which is unaffected by the AC signal, and the semiconductor layer 101 on the side of the one end 111 to which the AC signal is applied, resulting in an energetically non-equilibrium state. Therefore, electrons with high energy flow from the side of the one end 111 over the energy barrier created by the gate voltage of the first gate 102 into the charge storage region 104. As a result, as shown in Figure 2C, the potential of the charge storage region 104 rises.

[0017] When the flow of electrons entering the charge storage region 104 from end 111 equals the flow of electrons entering the charge storage region 104 from end 111, the potential rise in the charge storage region 104 stops, and a steady state is reached. In this way, by applying an AC signal to end 111, the potential of the charge storage region 104 rises and energy is stored.

[0018] To achieve this energy storage, without applying an AC signal, the electrons in the semiconductor layer 101 on one end 111 must exceed the energy barrier for a time T. electron (This corresponds to the time constant of the current path composed of an FET and a capacitor) and the period T of the AC signal. ac It must be at least one order of magnitude longer than T. ac is T electron Longer than (T electron is Tac If it is shorter (than...), electrons will enter and leave the charge storage region 104 in response to the change in the AC signal. As a result, the electron energy distribution on the side of one end 111 and the electron energy distribution in the charge storage region 104 will become uniform, and a non-equilibrium state will not occur.

[0019] Therefore, the frequency of the AC signal required to store energy in the charge storage region 104 is 10 / T electron or higher. In other words, the time constant T electron must be an AC signal faster than... This is contrary to the normal concept that for a circuit or device to operate, the input signal must not be slower than the time constant.

[0020] FIG. 3A shows the simulation results. As the frequency of the AC signal applied to one end 111 increases, the potential of the charge storage region 104 rises, and it can be seen that the potential rise saturates when the frequency becomes 10 / T electron or higher. FIG. 3B shows the current that monitors how the number of electrons in the charge storage region 104 changes depending on the presence or absence of the AC signal when T electron = 3 seconds. By applying the AC signal, the electron count current has decreased overall compared to when no signal is applied, indicating that the potential of the charge storage region 104 has risen.

[0021] The upper limit of the frequency of the AC signal for which this operating principle holds is determined by the time required for electrons to cross the energy barrier formed in the semiconductor layer 110 by the gate voltage of the first gate 102. Therefore, the shorter the distance, the higher the upper limit of the frequency of the AC signal can be increased.

[0022] The above description states that electrons move in and out of the semiconductor layer 101 between the side of one end 111 and the charge storage region 104. This movement must be due to crossing an energy barrier. Therefore, if leakage current occurs in the FET made of the semiconductor layer 101 with the first gate 102, the operating principle of the present invention is not satisfied. Furthermore, when electrons move in and out of the side of one end 111 and the charge storage region 104, their energy must not be lost due to scattering or other reasons.

[0023] [Embodiment 1] Based on the principles described above, the rectifier according to Embodiment 1 of the present invention will be described with reference to Figures 4A, 4B, 4C, and 4D. Figure 4D shows the equivalent circuit of the rectifier according to Embodiment 1.

[0024] This rectifier first includes a semiconductor layer 101 that is columnar in shape and extends in a predetermined direction to form a channel. It also includes a first gate 102 positioned spaced apart from one end 111 of the semiconductor layer 101 to apply a gate voltage to the semiconductor layer 101, and a second gate 103 positioned spaced apart from the first gate 102 on the other end 112 of the semiconductor layer 101 to apply a gate voltage to the semiconductor layer 101. The first gate 102 and the second gate 103 are formed on the semiconductor layer 101 via a gate insulating layer 121. It also includes a charge storage region 104 formed in the semiconductor layer 101 between the first gate 102 and the second gate 103. An AC signal is input to one end 111 of the semiconductor layer 101, and a DC signal is output from the other end 112 of the semiconductor layer 101.

[0025] Figures 5A and 5B are energy band diagrams illustrating the operating principle. Energy barriers are formed on both sides of the charge storage region 104 using the first gate 102 and the second gate 103. In this example, the gate voltage from the second gate 103 is made smaller than the gate voltage from the first gate 102, so that the energy barrier on the other end 112 of the charge storage region 104 is smaller than the energy barrier on the one end 111.

[0026] When an AC signal is applied to one end 111, as described above, electrons 131 are transferred to the charge storage region 104, causing the potential of the charge storage region 104 to rise. As a result, the potential of the charge storage region 104 becomes higher than that of the other end 112 to which the output terminal is connected, so the electrons 131 from the charge storage region 104 are transferred to the other end 112, and the electrons 131 flow out from one end 111 to the other end 112, becoming an electric current. The frequency of the AC signal is 10 / T electron When the voltage is higher than the specified voltage, the potential rise in the charge storage region 104 is constant, so the flow of electrons 131 transferred from the charge storage region 104 to the other end 112 is also a direct current. In other words, it functions as a rectifier that converts the alternating current applied to one end 111 into a direct current and outputs it to the other end 112.

[0027] Next, the structure for realizing the rectifier according to Embodiment 1 will be described. In order to realize this rectifier, there must be no leakage current in the FET with the first gate 102 and the FET with the second gate 103. For this reason, the gate insulating layer 121 must suppress the tunnel current flowing between the first gate 102, the second gate 103 and the semiconductor layer 101.

[0028] The gate insulating layer of a typical FET uses materials such as silicon oxide or hafnium oxide. In the case of silicon oxide (SiO2), the gate insulating layer 121 only needs to be about 10 nm thick. A thickness greater than 10 nm is also acceptable, but a thinner layer is preferable to improve controllability through the gate voltage from the first gate 102 and the second gate 103.

[0029] Furthermore, gate-induced drain leakage (GIDL) is a current that flows through the FET in the off state. Since this is caused by crystalline defects in the semiconductor layer 101, it is important that the semiconductor layer 101 is made of high-quality, defect-free crystals. However, defects occur probabilistically in actual FET structures, so to avoid this, it is desirable for the columnar semiconductor layer 101 to be narrow and have a short gate length. A short gate length is also desirable to increase the upper limit of the frequency of the AC signal that can be rectified.

[0030] For example, the width of the columnar semiconductor layer 101 is preferably 100 nm or less. The gate length of the first gate 102 and the second gate 103 is preferably 100 nm or less, and it can be expected that AC signals of about 1 THz can be rectified. In addition, the thickness of the columnar semiconductor layer 101 is preferably 100 nm or less, but it can be thicker. The narrower the gap between the first gate 102 and the second gate 103, the less susceptible it is to the effects of defects, so a gap of 100 nm or less is also preferable.

[0031] [Embodiment 2] Next, a rectifier according to Embodiment 2 of the present invention will be described with reference to Figures 6A, 6B, and 6C. Figure 6C shows the equivalent circuit of the rectifier according to Embodiment 2.

[0032] This rectifier, in addition to the rectifier according to Embodiment 1 described above, first includes a third gate 105 positioned between the first gate 102 and the second gate 103 to apply a gate voltage to the semiconductor layer 101. It also includes a back gate 106 positioned in the region where the first gate 102, the second gate 103, and the third gate 105 are formed, sandwiching the semiconductor layer 101, and applying a gate voltage to the semiconductor layer 101. The back gate 106 is formed on the back side of the semiconductor layer 101 via a back gate insulating layer 107.

[0033] According to Embodiment 2, the potential of the charge storage region 104 formed in the semiconductor layer 101 between the first gate 102 and the second gate 103 can be precisely controlled by the first gate 102 and the back gate 106. Furthermore, when an AC signal input to one end 111 propagates through space, the third gate 105 can act as a shield electrode to prevent this propagating signal from affecting the charge storage region 104. In addition, by inducing carriers in the semiconductor layer 101 using the back gate 106, carriers can be conducted without introducing impurities into the semiconductor layer 101. For example, if a positive voltage is applied to the semiconductor layer 101 using the back gate 106, electrons in the semiconductor layer 101 are induced.

[0034] Generally, in FETs, impurities are introduced into the source and drain to conduct carriers between them. However, during this impurity introduction process, crystalline defects occur in the semiconductor layer (channel), resulting in leakage currents such as GIDL. By using a back gate 106, it is possible to suppress these leakage currents.

[0035] As mentioned above, the thickness of the back gate insulating layer 107 is preferably 10 nm or more in order to suppress leakage current due to tunnel current from the back gate 106. Also, by making the back gate insulating layer 107 thinner, the controllability of the back gate 106 is improved and it can be driven at a lower voltage, but a thickness of several hundred nm is not a problem. The third gate 105 only needs to be sized to fit between the first gate 102 and the second gate 103, and although a longer gate length is desirable as it improves the controllability of the gate voltage of the third gate 105, it is not essential.

[0036] [Embodiment 3] Next, a rectifier according to Embodiment 3 of the present invention will be described with reference to Figures 7A and 7B.

[0037] This rectifier first includes a first semiconductor layer 201 which is columnar in shape and extends in a predetermined first direction, forming a channel. The first direction is the left-right direction in the plane of Figure 7B. It also includes a first gate 202 which is spaced apart from one end 211 of the first semiconductor layer 201 and applies a gate voltage to the first semiconductor layer 201. In the third embodiment, it also includes a columnar second semiconductor layer 205 which extends in a second direction intersecting the first direction, with the other end of the first semiconductor layer 201 serving as a second gate 203. The second direction is the up-down direction in the plane of Figure 7B.

[0038] In this example, the first semiconductor layer 201 and the second semiconductor layer 205 are embedded in an insulating layer 221. A portion of the insulating layer 221 above the first semiconductor layer 201 functions as a gate insulating layer for the first gate 202. The rectifier also includes a charge storage region 204 formed in the first semiconductor layer 201 between the first gate 202 and the second gate 203. An AC signal is input to one end 211 of the first semiconductor layer 201, and a DC signal flows through the second semiconductor layer 205.

[0039] Since the other end of the region where the charge storage region 204 of the first semiconductor layer 201 is formed is capacitively coupled with the second semiconductor layer 205, the charge storage region 204 functions as a second gate 203 with respect to the second semiconductor layer 205. Therefore, if the potential of the charge storage region 204 changes when an AC signal is applied to one end 111, this change in potential is applied to the second semiconductor layer 205 as the gate voltage of the second gate 203, so that the DC current 212 flowing through the second semiconductor layer 205 changes. In other words, the AC signal applied to one end 111 is read out by the DC current 212 of the second semiconductor layer 205, thus functioning as a rectifier.

[0040] According to Embodiment 3, even when the strength of the AC signal applied to one end 111 is weak, and the rectified current obtained by the configurations of Embodiments 1 and 2 is small and difficult to measure, it is possible to read out the AC signal with high sensitivity by changing the DC current 212 of the second semiconductor layer 205.

[0041] To realize the rectifier according to Embodiment 3, the shorter the distance between the second gate 203 and the second semiconductor layer 205 due to the charge storage region 204, the more accurately the AC signal can be read out. Furthermore, it is desirable that the width and thickness of the columnar first semiconductor layer 201 and second semiconductor layer 205 be small.

[0042] For example, the distance between the second gate 203 and the second semiconductor layer 205 due to the charge storage region 204 is set to 50 nm or less. Also, the width and thickness of the first semiconductor layer 201 and the second semiconductor layer 205 are set to 10 nm or less. Furthermore, the length of the charge storage region 204 (the distance between the first gate 202 and the other end of the first semiconductor layer 201) is set to 100 nm or less. With these configurations, even a change of just one electron in the charge storage region 204 can be detected as a change in the DC current 212 of the second semiconductor layer 205 (Reference 1).

[0043] As a result, as shown in Figure 3B, electrons entering and leaving the charge storage region 204 can be monitored at the single-electron level with high sensitivity. Although the current changes in a stepwise manner in Figure 3B, the amount of potential change in the charge storage region 204 can be obtained by taking a time average.

[0044] [Embodiment 4] Next, a rectifier according to Embodiment 4 of the present invention will be described with reference to Figures 8A and 8B. In addition to the rectifier according to Embodiment 3 described above, this rectifier includes a third gate 206 positioned between the first gate 202 and the second gate 203, which applies a gate voltage to the first semiconductor layer 201. Furthermore, it includes a back gate 207 positioned in the region where the first gate 202 and the third gate 206 are formed, sandwiching the first semiconductor layer 201, which applies a gate voltage to the first semiconductor layer 201.

[0045] In this example as well, the first semiconductor layer 201 and the second semiconductor layer 205 are formed embedded in the insulating layer 221. A portion of the insulating layer 221 above the first semiconductor layer 201 functions as the gate insulating layer for the first gate 202. In addition, the insulating layer 221 below the first semiconductor layer 201 and the second semiconductor layer 205 functions as the gate insulating layer for the back gate 207.

[0046] According to Embodiment 4, the potential of the charge storage region 204 formed in the first semiconductor layer 201 between the first gate 202 and the second gate 203 can be precisely controlled by the third gate 206 and the back gate 207. Furthermore, when an AC signal input to one end 211 propagates through space, the third gate 206 can act as a shielding electrode to prevent this propagating signal from affecting the charge storage region 204. In addition, by inducing carriers in the first semiconductor layer 201 using the back gate 207, carriers can be conducted without introducing impurities into the first semiconductor layer 201. For example, if a positive voltage is applied to the first semiconductor layer 201 using the back gate 207, electrons in the first semiconductor layer 201 are induced.

[0047] Generally, in FETs, impurities are introduced into the source and drain to conduct carriers between them. However, during this impurity introduction process, crystalline defects occur in the semiconductor layer (channel), resulting in leakage currents such as GIDL. By using a back gate 207, it is possible to suppress these leakage currents.

[0048] The thickness of the insulating layer 221, which functions as a gate insulating layer for the back gate 207, should preferably be 10 nm or more, as mentioned above, in order to suppress leakage current due to tunnel current from the back gate 207. Furthermore, by making the insulating layer 221 thinner, the controllability of the back gate 207 is improved and it can be driven at a lower voltage, but a thickness of several hundred nm is not a problem. The third gate 206 only needs to be sized to fit between the first gate 202 and the second gate 203, and a longer gate length is desirable because it improves the controllability of the gate voltage of the third gate 206, but it is not essential.

[0049] As described above, according to the present invention, a first gate and a second gate are provided in a columnar semiconductor layer, a charge storage region is formed in the semiconductor layer between the first gate and the second gate, and an AC signal is input to one end of the semiconductor layer on the first gate side. As a result, a rectifier capable of converting high-frequency signals of 100 GHz to THz into DC at room temperature can be provided.

[0050] The rectifier according to the present invention is characterized by utilizing a steady-state process that is generated by inducing a non-equilibrium state using a FET with no leakage current, which is constructed by providing a first gate and a second gate in a columnar semiconductor layer. Furthermore, the rectifier according to the present invention is characterized by accumulating a low-intensity AC signal in a capacitor between a columnar first semiconductor layer and a columnar second semiconductor layer, and reading it out with the FET. According to the present invention, the frequency of the AC signal that can be rectified is not restricted by the RC time constant, and high-frequency signals can be handled. Furthermore, AC signals with low intensity can also be handled.

[0051] [Reference 1] K. Nishiguchi et al., "Single-Electron-Resolution Electrometer Based on Field-Effect Transistor", Japanese Journal of Applied Physics, vol. 47, no. 11, pp. 8305-8310, 2008. [Explanation of symbols]

[0052] 101... Semiconductor layer, 102... First gate, 103... Second gate, 104... Charge storage region, 111... One end, 112... Other end, 121... Gate insulating layer.

Claims

1. A semiconductor layer that is columnar in shape and extends in a predetermined direction to form a channel, A first gate is positioned spaced apart from one end of the semiconductor layer and applies a gate voltage to the semiconductor layer, A second gate is positioned at the other end of the semiconductor layer, spaced apart from the first gate, and applies a gate voltage to the semiconductor layer. A charge storage region formed in the semiconductor layer between the first gate and the second gate and Equipped with, An AC signal is input to one end of the semiconductor layer. A DC signal is output from the other end of the semiconductor layer. A rectifier characterized by the following features.

2. In the rectifier according to claim 1, A third gate is positioned between the first gate and the second gate and applies a gate voltage to the semiconductor layer, A back gate is positioned in the region where the first gate, second gate, and third gate are formed, sandwiching the semiconductor layer, and applies a gate voltage to the semiconductor layer. A rectifier characterized by having the following features.

3. A first semiconductor layer that is columnar in shape and extends in a predetermined first direction, and in which a channel is formed, A first gate is positioned spaced apart from one end of the first semiconductor layer and applies a gate voltage to the first semiconductor layer, A columnar second semiconductor layer extending in a second direction intersecting the first direction, with the other end of the first semiconductor layer serving as a second gate, A charge storage region formed in the first semiconductor layer between the first gate and the second gate and Equipped with, An AC signal is input to one end of the first semiconductor layer. A DC signal flows through the second semiconductor layer. A rectifier characterized by the following features.

4. In the rectifier according to claim 3, A third gate is positioned between the first gate and the second gate and applies a gate voltage to the first semiconductor layer, A back gate is positioned in the region where the first gate and the third gate are formed, sandwiching the first semiconductor layer, and applying a gate voltage to the first semiconductor layer. A rectifier characterized by having the following features.

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