Overcurrent protection circuit

Abstract

To provide an overcurrent protection circuit with suppressed malfunctions at activation.SOLUTION: An on-drive circuit 4 has a current source 42 that supplies a constant current I1, and turns on a transistor MSW by supplying the constant current I1 to a gate of the transistor MSW. An overcurrent control circuit 5, when a load current becomes larger than a first reference current, sinks an amount of a current corresponding to a difference between the load current and the first reference current from the current supplied to the gate of the transistor MSW to control the transistor MSW so that the load current becomes constant at the first reference current. A delay circuit 6, in a case where the control of the transistor MSW by the overcurrent control circuit 5 continues for a certain period, turns on a transistor M4 to forcibly turn off the transistor MSW.SELECTED DRAWING: Figure 1

Description

Technical Field

[0006] , , , , ,

[0001] The present invention relates to an overcurrent protection circuit.

Background Art

[0002] As an overcurrent protection circuit, it is known to provide a transistor between a load and a power supply to turn off the transistor when an overcurrent flows through the load to protect the load and the like from the overcurrent. However, a capacitive load is connected in parallel to the load. When the capacitance of the capacitive load is large, the capacitive load is charged at startup, causing a rush current to flow through the load. The conventional overcurrent protection circuit may misdetect this rush current as an overcurrent and cause a malfunction in which the transistor turns off.

[0003] Therefore, it is conceivable to suppress the slew rate when the gate rises and suppress the rush current by adding a capacitor to the gate of the transistor, but this causes a problem that the startup time of the transistor becomes slower due to the added capacitor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide an overcurrent protection circuit that suppresses malfunction at startup.

Means for Solving the Problems

[0006] To achieve the above object, the overcurrent protection circuit according to the present invention is as described in the following [1] to6 It is characterized by [...]. [1] In an overcurrent protection circuit that controls a first transistor connected between a load and a power supply to protect the load from overcurrent, An ON drive circuit having a first current source that supplies a first constant current, and which turns on the first transistor by supplying the first constant current to the gate or base of the first transistor, An overcurrent control circuit controls the first transistor so that the load current flowing through the load exceeds the first reference current, by sinking a current portion from the current supplied to the gate or base of the first transistor corresponding to the difference between the load current and the first reference current, so that the load current remains constant at the first reference current. The present invention has a second transistor connected between the gate or base of the first transistor and ground. ,before The device comprises a delay circuit that turns on the second transistor and forcibly turns off the first transistor. 、 The side of the load opposite to the side connected to the first transistor is connected to the ground. The delay circuit includes a determination circuit that determines whether the capacitive load connected in parallel to the load is charging during startup or whether the startup has ended after charging of the capacitive load. If it is determined that startup is in progress, the circuit waits for the control of the first transistor by the overcurrent control circuit to continue for a certain period of time before turning on the second transistor. If it is determined that startup has ended, the circuit turns on the second transistor as soon as the load current exceeds the first reference current. Overcurrent protection circuit. [2] In the overcurrent protection circuit described in [1], The overcurrent control circuit includes a sense resistor for detecting the load current, a differential amplifier that outputs a voltage corresponding to the potential difference between the voltage across the sense resistor and a first reference voltage corresponding to the first reference current, and a third transistor connected between the gate or base and ground of the first transistor. A voltage corresponding to the potential difference, which is the output of the differential amplifier, is supplied to the gate or base of the third transistor. Overcurrent protection circuit. [3] In the overcurrent protection circuit described in [1], The delay circuit includes a second current source that supplies a second constant current, a first capacitor to which the second constant current is supplied while the first transistor is being controlled by the overcurrent control circuit, and a first comparator that compares the voltage across the first capacitor with a second reference voltage and outputs the comparison result. The second transistor is controlled to turn on or off according to the output of the first comparator. Overcurrent protection circuit. [4] [ 1 In the overcurrent protection circuit described in [ ], The determination circuit includes a second comparator that compares the gate or base voltage of the first transistor with a third reference voltage and outputs the comparison result as a determination result. Overcurrent protection circuit. [5] [ 1 In the overcurrent protection circuit described in [ ], The delay circuit includes a slew rate detection circuit that detects when the slew rate of the gate-source voltage or base-emitter voltage of the first transistor exceeds a certain value, and when it is detected that the slew rate exceeds a certain value, it turns on the second transistor. Overcurrent protection circuit. [6] [ 5 In the overcurrent protection circuit described in [ ], The slew rate detection circuit includes a detection resistor connected in series between the gate and source or between the base and emitter of the first transistor, a second capacitor, and a third comparator that outputs the result of comparing the voltage across the detection resistor with a fourth reference voltage as the detection result. Overcurrent protection circuit. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide an overcurrent protection circuit that suppresses malfunctions during startup.

[0008] The above is a brief description of the present invention. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the attached drawings.

Brief Description of the Drawings

[0009] [Figure 1] FIG. 1 is a circuit diagram showing a power supply device incorporating the overcurrent protection circuit of the present invention in the first embodiment. [Figure 2] FIG. 2 is a time chart showing the constant current I1 shown in FIG. 1, the source potential of the transistor MSW, the gate-source voltage of the transistor MSW, the voltage across both ends of the sense resistor Rs, and the voltage across both ends of the capacitor CT. [Figure 3] FIG. 3 is a circuit diagram showing a power supply device incorporating the overcurrent protection circuit of the present invention in the second embodiment. [Figure 4] FIG. 4 is a time chart showing the constant current I1 shown in FIG. 3, the source potential of the transistor MSW, the gate-source voltage of the transistor MSW, the voltage across both ends of the sense resistor Rs, and the voltage across both ends of the capacitor CT. [Figure 5] FIG. 5 is a circuit diagram showing a power supply device incorporating the overcurrent protection circuit of the present invention in the third embodiment.

Embodiments for Carrying out the Invention

[0010] (First Embodiment) The first embodiment of the present invention will be described below with reference to each figure.

[0011] Figure 1 is a circuit diagram showing a power supply unit 1 incorporating the overcurrent protection circuit 3 of the present invention in a first embodiment. As shown in the figure, the power supply unit 1 is a device that supplies a DC voltage V1 output from a power supply 2 to a load RL. A capacitive load CL1 is connected in parallel to the load RL. The power supply unit 1 includes a transistor MSW (first transistor) connected between the power supply 2, the load RL, and the capacitive load CL1, and an overcurrent protection circuit 3 that controls the on / off state of the transistor MSW to protect the power supply 2 and the load RL from overcurrent.

[0012] The MSW transistor is composed of N-channel field-effect transistors. The MSW transistor is connected to the positive terminal side of power supply 2, relative to the load RL and capacitive load CL1. The source of the MSW transistor is connected to the load RL and capacitive load CL1, and its drain is connected to the positive terminal of power supply 2 via a sense resistor Rs, which will be described later.

[0013] The overcurrent protection circuit 3 includes an ON drive circuit 4, an overcurrent control circuit 5, and a delay circuit 6. The ON drive circuit 4 has a current source 42 (first current source) that supplies a constant current I1 (first constant current), and is a circuit that turns on the transistor MSW by supplying the constant current I1 to the gate of the transistor MSW.

[0014] The overcurrent control circuit 5 is a circuit that, when the load current flowing through the load RL exceeds the first reference current, sinks (sucks out) a current from the current supplied to the gate of transistor MSW corresponding to the difference between the load current and the first reference current, and controls transistor MSW so that the load current remains constant at the first reference current. The delay circuit 6 is a circuit that, if the control by the overcurrent control circuit 5 continues for a certain period of time, turns on transistor M4 (the second transistor) and forcibly turns off transistor MSW.

[0015] Next, the details of the ON drive circuit 4 will be described. The ON drive circuit 4 includes a charge pump circuit 41, a current source 42, a resistor RG, and a Zener diode DZ1. The charge pump circuit 41 is a circuit that boosts the DC voltage V1 and supplies it to the current source 42. The current source 42 is a circuit that receives power from the charge pump circuit 41 and outputs a constant current I1. This constant current I1 charges the gate capacitance of transistor MSW, allowing transistor MSW to be turned on. The resistor RG is connected between the gate and source of transistor MSW and discharges the charge of the gate capacitance when the constant current I1 is not supplied to the gate capacitance. When the gate capacitance is discharged by resistor RG, transistor MSW is turned off.

[0016] Zener diode DZ1 has its cathode connected to the gate of transistor MSW and its anode connected to the source of transistor MSW. Zener diode DZ1 can clamp the gate-source voltage of transistor MSW to the Zener voltage.

[0017] Next, the details of the overcurrent control circuit 5 will be explained. The overcurrent control circuit 5 includes a sense resistor Rs, a differential amplifier 51, a transistor M1 (the third transistor), and a resistor R1. The sense resistor Rs is provided to detect the load current. One end of the sense resistor Rs is connected to the positive terminal of the power supply 2, and the other end is connected to the drain of the transistor MSW. The voltage across the sense resistor Rs is a voltage corresponding to the drain current (= load current) of the transistor MSW.

[0018] The differential amplifier 51 has the connection point between the sense resistor Rs and the drain of the transistor MSW connected to its inverting input, and the negative terminal of the reference power supply 52 connected to its non-inverting input. The reference power supply 52 outputs a reference voltage Vref1 (first reference voltage), and its positive terminal is connected to the positive terminal of power supply 2. The reference voltage Vref1 is set to the voltage across the sense resistor Rs when a first reference current is flowing through the sense resistor Rs. The differential amplifier 51 outputs a voltage corresponding to the potential difference between the voltage across the sense resistor Rs and the reference voltage Vref1.

[0019] Transistor M1 is an N-channel field-effect transistor, with its drain connected to the gate of transistor MSW, its source connected to resistor R1, and its gate connected to the output of differential amplifier 51. Resistor R1 is connected between transistor M1 and ground. When the voltage across the sense resistor Rs exceeds the reference voltage Vref1, differential amplifier 51 outputs a voltage to the gate of transistor M1 corresponding to the potential difference between the voltage across the sense resistor Rs and the reference voltage Vref1.

[0020] As a result, transistor M1 sinks a portion of the current supplied to the gate of transistor MSW that corresponds to the potential difference between the voltage across the sense resistor Rs and the reference voltage Vref1 (= the difference between the load current and the first reference current). Due to the current sunk by transistor M1, the current supplied from the current source 42 to the gate of transistor MSW decreases. When the sink current by transistor M1 becomes greater than or equal to the constant current I1, the gate-source voltage of transistor MSW decreases, reducing the load current. This negative feedback operation allows the overcurrent control circuit 5 to control the load current so that it remains constant at the first reference current.

[0021] Next, the delay circuit 6 will be described. The delay circuit 6 has a power supply 601. The power supply 601 outputs a DC voltage V2. The delay circuit 6 also includes a current source 602 (second constant current source) for counting a certain amount of time, a capacitor CT (first capacitor), and a comparator 603 (first comparator). The current source 602 receives the DC voltage V2 supplied from the power supply 601 and outputs a constant current I2 (second constant current). The current source 602 and the capacitor CT are connected in series, and the current source 602 charges the capacitor CT with the constant current I2.

[0022] Comparator 603 has the connection point between the current source 602 and the capacitor CT connected to its non-inverting input, and the positive terminal of the reference power supply 604 connected to its inverting input. The reference power supply 604 outputs a reference voltage Vref2 (second reference voltage), and its negative terminal is connected to ground. Comparator 603 compares the voltage across the capacitor CT with the reference voltage Vref2 and inputs the comparison result to the AND circuit 605. That is, comparator 603 outputs an L level when the voltage across the capacitor CT is less than or equal to the reference voltage Vref2. Also, comparator 603 inverts its output from an L level to an H level when a certain amount of time has elapsed since charging the capacitor CT began and the voltage across the capacitor CT exceeds the reference voltage Vref2.

[0023] The delay circuit 6 includes a resistor R2, a transistor M2, and a transistor M3 for detecting the control by the overcurrent control circuit 5 and starting the charging of the capacitor CT. One end of the resistor R2 is connected to the positive terminal of the power supply 601. Transistor M2 is an N-channel field-effect transistor, with its drain connected to the other end of the resistor R2 and its source connected to ground. The gate of transistor M2 is connected to the output of the differential amplifier 51. Transistor M3 has its drain connected to one end of the capacitor CT and its source connected to the other end of the capacitor CT. The gate of transistor M3 is connected to the connection point between the resistor R2 and the drain of transistor M2.

[0024] As long as the voltage across the sense resistor Rs is less than or equal to the reference voltage Vref1 and the differential amplifier 51 outputs an L level, transistors M1 and M2 are turned off. When transistor M2 is turned off, the drain voltage of transistor M2 becomes H level (DC voltage V2), and transistor M3 turns on. When transistor M3 is turned on, the terminals of capacitor CT are short-circuited, and capacitor CT is not charged by the current source 602.

[0025] On the other hand, when the voltage across the sense resistor Rs exceeds the reference voltage Vref1, the differential amplifier 51 outputs a voltage corresponding to the potential difference between the voltage across the sense resistor Rs and the reference voltage Vref1, and transistors M1 and M2 turn on. When transistor M2 turns on, the drain voltage of transistor M2 becomes L level (ground potential), and transistor M3 turns off. When transistor M3 turns off, charging of capacitor CT from current source 602 begins.

[0026] The delay circuit 6 further includes an AND circuit 605, an inverter circuit 606, a flip-flop circuit 607, and transistors M4 and M5. The AND circuit 605 receives the output of the comparator 603 and the output of the inverter circuit 606 as inputs, and its output is connected to the S input of the flip-flop circuit 607. The inverter circuit 606 receives the drain voltage of transistor M2 as input, and its output is connected to the input of the AND circuit 605. The Q output of the flip-flop circuit 607 is connected to the gates of transistors M4 and M5.

[0027] Transistor M4 (the second transistor) is composed of an N-channel field-effect transistor, with its drain connected to the gate of transistor MSW and its source connected to ground. Transistor M5 is composed of an N-channel field-effect transistor, with its drain connected to one end of capacitor CT and its source connected to the other end of capacitor CT.

[0028] When the voltage across the sense resistor Rs is less than or equal to the reference voltage Vref1 and transistor M2 is off, the drain voltage of transistor M2 is at a high level, and the inverter circuit 606 outputs a low level. At this time, the capacitor CT is also not charged, so the output of the comparator 603 is also at a low level, and the AND circuit 605 outputs a low level. When the AND circuit 605 outputs a low level, the Q output of the flip-flop circuit 607 outputs a low level, and transistors M4 and M5 are turned off.

[0029] On the other hand, when the voltage across the sense resistor Rs exceeds the reference voltage Vref1, transistor M2 turns on, the drain voltage of transistor M2 becomes low, and inverter circuit 606 outputs a high level. Also, when the capacitor CT starts charging and a certain amount of time has passed and the output of comparator 603 becomes high, the output of AND circuit 605 inverts from low to high. When AND circuit 605 outputs a high level, the Q output of flip-flop circuit 607 outputs a high level, and transistors M4 and M5 turn on.

[0030] When transistor M4 is turned on, transistor MSW is turned off. When transistor MSW is turned off, the output of differential amplifier 51 becomes low, transistor M2 is turned off, and the output of inverter circuit 606 is inverted to low. Also, when transistor M5 is turned on, the terminals of capacitor CT are short-circuited, and the charge stored in capacitor CT is discharged. As a result, the voltage across capacitor CT falls below the reference voltage Vref2, and the output of comparator 603 is inverted to low.

[0031] When the output of the inverter circuit 606 and the output of the comparator 603 are inverted to a low level, the output of the AND circuit 605 is also inverted to a low level. However, the flip-flop circuit 607 keeps the Q output at a high level until a reset signal is input to the R input, thus allowing transistors M4 and M5 to remain on.

[0032] The operation of the power supply unit 1 with the above configuration will be explained below with reference to the time chart shown in Figure 2. Figure 2 shows the voltages at various points as the current source 42 begins to supply a constant current I1 and the gate voltage of transistor MSW gradually rises. In Figure 2, for the purpose of explaining the operation, it is assumed that the capacitance of the capacitive load CL1 is set to be sufficient for the overcurrent control circuit 5 to operate when the gate voltage rises.

[0033] When the current source 42 starts supplying a constant current I1 during startup, the gate-source voltage of transistor MSW increases, and transistor MSW turns on. When transistor MSW turns on, the source potential rises. Also, when transistor MSW turns on, current is supplied to the load RL and the capacitive load CL1, and charging of the capacitive load CL1 begins.

[0034] When charging of the capacitive load CL1 begins, an inrush current flows, increasing the voltage across the sense resistor Rs and exceeding the reference voltage Vref1. Once the voltage exceeds Vref1, the overcurrent control circuit 5 controls the current flowing through the transistor MSW to a constant value at the first reference current, and the voltage across the sense resistor Rs becomes constant at the reference voltage Vref1. When the overcurrent control circuit 5 starts its control, the delay circuit 6 begins charging the capacitor CT.

[0035] In this example, before the voltage across capacitor CT reaches the reference voltage Vref2, the capacitive load CL1 finishes charging, and the source voltage of transistor MSW rises to the output voltage of charge pump circuit 41. As a result, the voltage across sense resistor Rs falls below the reference voltage Vref1, and charging of capacitor CT stops. Subsequently, if an overcurrent occurs due to a short circuit or the like, the load current is first controlled by the overcurrent control circuit 5 to keep it constant. This initiates charging of capacitor CT, and the voltage across capacitor CT rises. If the overcurrent is not resolved and a certain period of time has elapsed, the voltage across capacitor CT exceeds the reference voltage Vref2, and the delay circuit 6 turns on transistors M4 and M5, turning off transistor MSW.

[0036] According to the embodiment described above, the overcurrent control circuit 5 controls the transistor MSW so that the load current remains constant at the first reference current, and the delay circuit 6 turns on the transistor M4 to forcibly turn off the transistor MSW if the control of the transistor MSW by the overcurrent control circuit 5 continues for a certain period of time. As a result, even if the capacitance of the capacitive load CL1 is large, the inrush current at startup can be suppressed and kept constant, and malfunctions in which the transistor MSW is turned off due to the inrush current can be prevented.

[0037] Furthermore, since there is no need to add capacitance to the gate of the MSW transistor, a faster startup time can be set. In addition, by changing the capacitance of the CT capacitor, the time for constant current operation can be set according to the gate capacitance and allowable power dissipation of the MSW transistor.

[0038] (Second Embodiment) Next, the power supply unit 1B of the second embodiment will be described below with reference to Figure 3. In Figure 3, parts equivalent to those of the power supply unit 1 shown in Figure 1 described in the first embodiment above are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0039] The main difference between the first and second embodiments lies in the configuration of the delay circuit 6B. In addition to the components described in the first embodiment, the delay circuit 6B of the second embodiment includes a comparator 608 (second comparator) that functions as a decision circuit and a reference power supply 609. The comparator 608 has the positive terminal of power supply 2 connected to its inverting input and the negative terminal of reference power supply 609 connected to its non-inverting input. The reference power supply 609 outputs a reference voltage Vref3, and its positive terminal is connected to the gate of transistor MSW.

[0040] As a result, comparator 608 compares the gate voltage of transistor MSW with the voltage obtained by adding the DC voltage V1 output by power supply 2 and the reference voltage Vref3 (V1+Vref3) (third reference voltage), and outputs the comparison result to the S input of flip-flop circuit 610. That is, comparator 608 outputs an L level while it is starting up (capacitive load CL1 is charging) and the gate voltage of transistor MSW is low (below (V1+Vref3)). Comparator 608 outputs an H level when it has finished starting up (capacitive load CL1 has finished charging) and the gate voltage of transistor MSW has risen (i.e., when it exceeds (V1+Vref3)).

[0041] The delay circuit 6B further includes a flip-flop circuit 610 and an OR circuit 611. The Q output of the flip-flop circuit 610 is connected to the input of the OR circuit 611. The output of the comparator 603 is further connected to the input of the OR circuit 611. The output of the OR circuit 611 is connected to the input of the AND circuit 605.

[0042] The operation of power supply unit 1B with the above configuration will be explained below with reference to the timing chart shown in Figure 4. During startup, the gate voltage of transistor MSW is low, so the output of comparator 608 becomes L level, and the Q output of flip-flop circuit 610 becomes L level. Therefore, the output of OR circuit 611 becomes H level if the output of comparator 603 is H level, and L level if the output of comparator 603 is L level. For this reason, power supply unit 1B operates in the same manner as in the first embodiment during startup.

[0043] Once the startup is complete and the gate voltage of transistor MSW becomes high, the output of comparator 608 becomes high, and the Q output of flip-flop circuit 610 inverts to high. When the Q output of flip-flop circuit 610 becomes high, the output of OR circuit 611 becomes high.

[0044] Therefore, after startup is complete, the AND gate 605 outputs according to the output of the inverter gate 606. As a result, if an overcurrent flows and the voltage across the sense resistor Rs exceeds the reference voltage Vref1, transistors M4 and M5 can be turned off immediately, and transistor MSW can be turned off, without waiting for the voltage across the capacitor CT to exceed the reference voltage Vref2.

[0045] (Third embodiment) Next, the power supply unit 1C of the third embodiment will be described below with reference to Figure 5. In Figure 5, parts equivalent to those of the power supply unit 1 shown in Figure 3 described in the second embodiment above are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0046] Another major difference between the second and third embodiments is the configuration of the delay circuit 6C. In addition to the components described in the second embodiment, the delay circuit 6C of the third embodiment includes a resistor RDET (detection resistor) that functions as a slew rate detection circuit, a capacitor C1 (second capacitor), a comparator 613 (third comparator), and a reference power supply 614. The resistor RDET and capacitor C1 are connected in series and connected between the gate and source of the transistor MSW. The resistor RDET converts the current flowing through the parasitic capacitance Cgd between the drain and gate of the transistor MSW (described later) into a voltage and inputs it as a detection voltage to the inverting input of the comparator 613. Capacitor C1 is charged by the current flowing through the parasitic capacitance Cgd and holds the detection voltage.

[0047] Comparator 613 has the connection point of resistor RDET and capacitor C1 connected to its inverting input, the negative terminal of reference power supply 614 connected to its non-inverting input, and its output connected to the input of OR circuit 611. Reference power supply 614 outputs a reference voltage Vref4, and its positive terminal is connected to the gate of transistor MSW.

[0048] In the first and second embodiments, if a short circuit occurs in the load RL during startup, the current of the transistor MSW is controlled to a constant current. However, the transistor MSW could not be turned off unless this condition continued for a certain period of time or longer and the voltage across the capacitor CT exceeded the reference voltage Vref2. The third embodiment improves upon this point by providing a configuration that allows the transistor MSW to be turned off immediately if a short circuit occurs in the load RL during startup.

[0049] During startup, when the gate and source voltages of transistor MSW have risen to a certain extent, and the load RL is short-circuited, the gate and source voltages are rapidly reduced. At this time, the potential difference between the drain and gate of transistor MSW increases rapidly, causing current to flow to the gate of transistor MSW through the parasitic capacitance Cgd, and the gate-source voltage increases more rapidly compared to when it is raised by the current source 42. The increased current charges capacitor C1 and increases the voltage across resistor RDET. When the voltage across resistor RDET exceeds the reference voltage Vref4, the output of comparator 613 switches from L level to H level, and even if the voltage across capacitor CT is below the reference voltage Vref2, the Q output of flip-flop circuit 607 becomes H level, allowing transistor MSW to be immediately turned off.

[0050] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.

[0051] In the embodiments described above, the transistors MSW, M1 to M5 were composed of field-effect transistors, but this is not limited to them. The transistor MSW may be composed of a bipolar transistor. [Explanation of symbols]

[0052] 2 Power supply 3 Overcurrent protection circuit 4 ON drive circuit 5. Overcurrent control circuit 6. Delay Circuit 42 Current source (first current source) 51 Differential Amplifier (First Differential Amplifier) 602 Current source (second current source) 603 Comparator (First comparator) 608 Comparator (Second comparator, decision circuit) 609 Reference power supply (judgment circuit) 613 Comparator (Third comparator, slew rate detection circuit) 614 Reference power supply (slew rate detection circuit) I1 Constant current (first constant current) I2 Constant current (second constant current) C1 Capacitor (Second capacitor, slew rate detection circuit) CL1 capacitive load CT Capacitor (First Capacitor) M1 transistor (third transistor) M4 transistor (second transistor) MSW transistor (first transistor) RDET resistor (sensing resistor, slew rate sensing circuit) RL load Rs Sense Resistance Vref1 Reference voltage (first reference voltage) Vref2 Reference voltage (second reference voltage) V1 + Vref3 Voltage (Third reference voltage) Vref4 Reference voltage (fourth reference voltage)

Claims

1. In an overcurrent protection circuit that controls a first transistor connected between a load and a power supply to protect the load from overcurrent, An ON drive circuit having a first current source that supplies a first constant current, which turns on the first transistor by supplying the first constant current to the gate or base of the first transistor, An overcurrent control circuit controls the first transistor so that the load current flowing through the load exceeds the first reference current, by sinking a current portion corresponding to the difference between the load current and the first reference current from the current supplied to the gate or base of the first transistor, so that the load current remains constant at the first reference current. The device comprises a delay circuit that has a second transistor connected between the gate or base and ground of the first transistor, and turns on the second transistor to forcibly turn off the first transistor, The side of the load opposite to the side connected to the first transistor is connected to the ground. The delay circuit includes a determination circuit that determines whether the capacitive load connected in parallel to the load is charging during startup or whether the startup has ended after charging of the capacitive load. If it is determined that startup is in progress, the circuit waits for a certain period of time for the control of the first transistor by the overcurrent control circuit to continue before turning on the second transistor. If it is determined that startup has ended, the circuit turns on the second transistor as soon as the load current exceeds the first reference current. Overcurrent protection circuit.

2. In the overcurrent protection circuit described in claim 1, The overcurrent control circuit includes a sense resistor for detecting the load current, a differential amplifier that outputs a voltage corresponding to the potential difference between the voltage across the sense resistor and a first reference voltage corresponding to the first reference current, and a third transistor connected between the gate or base and ground of the first transistor. A voltage corresponding to the potential difference which is the output of the differential amplifier is supplied to the gate or base of the third transistor. Overcurrent protection circuit.

3. In the overcurrent protection circuit described in claim 1, The delay circuit includes a second current source that supplies a second constant current, a first capacitor to which the second constant current is supplied while the first transistor is being controlled by the overcurrent control circuit, and a first comparator that compares the voltage across the first capacitor with a second reference voltage and outputs the comparison result. The second transistor is controlled to turn on or off according to the output of the first comparator. Overcurrent protection circuit.

4. In the overcurrent protection circuit described in claim 1, The determination circuit includes a second comparator that compares the gate or base voltage of the first transistor with a third reference voltage and outputs the comparison result as a determination result. Overcurrent protection circuit.

5. In the overcurrent protection circuit described in claim 1, The delay circuit includes a slew rate detection circuit that detects when the slew rate of the gate-source voltage or base-emitter voltage of the first transistor exceeds a certain value, and when it is detected that the slew rate exceeds a certain value, it turns on the second transistor. Overcurrent protection circuit.

6. In the overcurrent protection circuit described in claim 5, The slew rate detection circuit includes a detection resistor connected in series between the gate and source or between the base and emitter of the first transistor, a second capacitor, and a third comparator that outputs the result of comparing the voltage across the detection resistor with a fourth reference voltage as the detection result. Overcurrent protection circuit.

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