High-sensitivity depth sensor with non-avalanche photodetector

Abstract

To provide a high-sensitivity depth sensor with a non-avalanche photodetector.SOLUTION: A sensing device (100) includes a light source (101) to emit light, a light sensor (105) to detect reflection of the emitted light, and a distance determination circuit responsive to reflected-light detection within the light sensor. The light sensor includes a photodetector (115) having a photocharge storage capacity in excess of one electron and an output circuit (117) which generates an output signal responsive to light detection within the photodetector with latency of less than 100 nanoseconds. The distance determination circuit (119) measures an elapsed time on the basis of transition of the output signal in response to photonic detection within the photodetector and determines a distance between the sensing device and a surface which yielded the reflection of the emitted light on the basis of the elapsed time.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims the benefit of U.S. Provisional Application No. 62 / 698,805, filed Jul. 16, 2018, which is incorporated herein by reference. This application also incorporates by reference U.S. Application No. 15 / 301,267 (35 USC 371(c) filed Sep. 30, 2016, now U.S. Patent No. 10,319,776), No. 15 / 555,911 (35 USC 371(c) filed Sep. 5, 2017, now U.S. Patent No. 10,283,539), and No. 62 / 676,266 (filed May 24, 2018), and International Applications No. PCT / US17 / 22607 (International filing date Sep. 15, 2018) and No. PCT / US19 / 34036 (International filing date May 24, 2019).

Background Art

[0002] (Introduction) A three - dimensional imaging device or depth sensor generally measures the time required for a light pulse (emitted from a light source near the sensor) to reflect off the surface of an object and return for detection by the sensor, or measures the envelope attenuation in the reflection of a carrier wave used to modulate a continuous light source (the attenuation indicates a phase shift of the modulated carrier wave) to determine the depth of the object or the distance between the sensor and the object. In both pulse - based and phase - based detection systems, the optical sensor needs to detect the reflected light and record its magnitude and / or arrival time with a resolution sufficient to meet the accuracy requirements of the application. For example, an optical sensor in a pulse - based system aimed at measuring distance / depth with an accuracy of 5 mm needs to have a low light sensitivity sufficient to detect weak pulses of reflection and resolve the round - trip flight time of the light pulse to within about 33 picoseconds (ps).

Summary of the Invention

[0003] Conventional 3D imaging devices and depth sensors typically employ solid-state photodetectors with electron avalanche gain, such as single-photon avalanche diodes (SPADs) and silicon photon multipliers (SiPMs). While fast and highly sensitive to single photons, avalanche-gain photodetectors have several drawbacks, including high dark current (i.e., high noise), single-electron well capacitance, low quantum efficiency (QE), low spatial resolution, and low manufacturing yield. Other more robust photodetectors (i.e., with deeper photowells and / or higher QE, spatial resolution, and manufacturing yield) have generally been avoided due to impractically long readout latencies. For example, in sensors with pin photodiodes (PPDs) readout by photocharge transfer to floating-diffuse nodes (e.g., in conventional 4-transistor imaging pixels), the charge transfer time alone is typically around several hundred nanoseconds (corresponding to a distance measurement resolution of several hundred meters), and therefore impractical latency for many depth sensing applications.

[0004] The disclosure herein relates to a solid-state optical sensor that may be deployed in a three-dimensional imaging device or depth sensor.

[0005] The various embodiments described herein are shown in the figures of the accompanying drawings as examples, not as limitations, and similar reference numerals in the figures refer to similar elements. [Brief explanation of the drawing]

[0006] [Figure 1] An embodiment of a depth sensor (or 3D sensor) having a light source and a low-latency multi-photowell optical sensor is shown. [Figure 2] Figure 1 shows one embodiment of a low-latency multi-photowell photodetector. [Figure 3] Figure 2 shows an exemplary detection cycle within a low-latency multi-well photodetector. [Figure 4]Figure 2 shows a photodiode reset sequence that can be performed after each detection cycle or every few detection cycles in a low-latency multiwell photodetector. [Figure 5] This document describes one embodiment of a low-latency multi-photowell photodetector having a JFET-based device that serves as both a multi-well photodiode and an output transistor. [Figure 6] Figure 5 shows an exemplary operating sequence within a JFET-based photodetector. [Figure 7] Figure 5 shows an exemplary top view and cross-sectional view of a p-type JFET transistor stacked vertically on a photodiode, as in the detector shown. [Figure 8] An alternative JFET-based photodetector circuit is shown. [Figure 9] An alternative JFET-based photodetector circuit is shown. [Figure 10] One embodiment of an analog front-end / time-to-digital converter (AFE / TDC) is shown, having a parallel amplification path with decreasing gain to trigger count-latch operation in each register with each photon detection count. [Figure 11] An alternative AFE / TDC embodiment is shown in which a single amplifier stage outputs the amplified photodetector output signal to the latch inputs of registers, each having a progressively increasing latch threshold. [Modes for carrying out the invention]

[0007] Optical sensors having multi-carrier photowell depth and sub-nanosecond readout latency (or latency of a few nanoseconds or less) are disclosed in various embodiments herein, along with corresponding embodiments of analog front-ends (AFEs) and time-to-digital converters (TDCs) that provide rapid and / or robust signal digitization. When deployed in depth sensors or 3D sensors, the low-latency readout and multiphoton sensitivity (i.e., multi-electron or multi-hole well depth) combined with the improved AFE / TDC enable dramatically improved depth sensing (higher sensitivity, finer resolution) compared to conventional avalanche gain sensors.

[0008] Figure 1 shows one embodiment of a depth sensor (or 3D sensor) 100, which includes a light source 101 and a low-latency multi-photowell photosensor 105, i.e., a photosensor having photowells capable of storing multiple photocarriers (in contrast to a single-photocarrier avalanche gain sensor), and which generates a sensor output indicating the accumulation of photocarriers (and thus the incident photon collision) either immediately upon incident photon collision or within a few nanoseconds (or less than 1 nanosecond) from the readout pulse. Referring to detail Figure 110, for example, the photosensor 105 includes an optional photodetector optics element for focusing inbound (reflected) light to a low-latency readout (LLR) multi-well photodetector 115, which then outputs the detection signal to a time-to-digital converter (TDC) 119 via an analog front-end (AFE) 117. The TDC output is fed to back-end processing logic (not shown in particular) within the depth sensor 100, which finalizes and outputs the measurement data.

[0009] Figure 2 shows an embodiment of the low-latency multi-photowell photodetector of Figure 1, in which case it has a pin photodiode (PPD) 121 and a pin floating-spread node (PFD) 123 interconnected by a gated channel (i.e., opened and closed by a transfer gate 125). A readout controller 140 asserts a transfer gate (TG) pulse at the transfer gate 125 to form a charge transfer channel between the PPD and the PFD, and thus transfers the photocharge accumulated in the photodiode to the pin floating-spread node for readout via a source follower transistor 127. The pin region within the floating-spread cancels out the TG pulse feedthrough to the floating-spread node, avoiding the relatively long floating-spread stabilization time (pre-readout delay) that plagues non-pinned floating-spread structures, and thus dramatically reduces the time between TG pulse assertion and output signal stabilization. In some embodiments, for example, the delay between TG pulse assertion (at the source terminal of transistor 127) and output signal stabilization is reduced from several hundred nanoseconds to less than 100 nanoseconds, more commonly less than 10 nanoseconds, or less than 5 nanoseconds (e.g., 3, 2, or 1 nanosecond, or even sub-nanosecond intervals), thereby reducing the photodetector readout latency by more than two orders of magnitude. The pin photodiode can be designed to have a photowell (multi-photocarrier storage well, SW) of any practical size, and the floating-diffuse node can similarly be sized to enable photon count sensitivity, resulting in a sufficiently high conversion gain (depending on the capacitance ratio of the PPD and PFD) and low input-referred readout noise. The source follower transistor 127 is named after its configuration in a source follower circuit, which is implemented by voltage-following operation between the gate terminal (to which the pin floating-diffuse node 123 is coupled) and the source terminal of the transistor.More specifically, the current source 131 establishes a constant bias current through transistor 127, resulting in a steady-state gate-source voltage that causes the photodetector output at the source terminal of transistor 127 to follow the potential of the pin floating-diffuse node (at the gate of transistor 127), i.e., any change in the PFD potential appears at the source of the SF transistor and therefore at the signal output AFE. A reset transistor 129 is provided to enable resetting of the PFD and PPD, returning the PFD node to VDD (in this example) when the read controller asserts a reset pulse (RST), and returning both the PFD and PPD storage nodes to VDD when the read controller generates both the RST and TG signals simultaneously.

[0010] Continuing to refer to Figure 2, the p+pin region within the n+ floating diffusion can be sized as needed to mitigate TG pulse feedthrough caused by TG-FD capacitive coupling. Referring to the physical cross-section 150 (showing the pin layer and storage well (SW) components of the pin photodiode along with the pin region and capacitive storage (FD) region of the pin floating diffusion node), the transfer gate 125 (implemented, for example, by doped polysilicon) is disposed on the surface oxide to enable the formation of an augmentation channel in the substrate 153 between the PPD and PFD.

[0011] Figure 3 shows an exemplary detection cycle within the low-latency multi-well photodetector of Figure 2. At the start of the detection cycle (150), the readout controller asserts a reset pulse to reset the floating-spread node (to VDD in this example), and then outputs a series of TG pulses to repeatedly sample the charge accumulation level in the pin photodiode. Each TG pulse allows the transfer of collected (generated) photocharge from the photodiode's storage well to the pin floating-spread node (i.e., the charge collected by the PPD since the previous TG pulse assertion is transferred to the PFD, thereby changing the PFD potential), and such charge transfer results in an output voltage step having a magnitude (dV1, dV2, dV3) corresponding to the number of photocarriers transferred. Note that, in contrast to conventional CMOS image sensors that reset floating-spread (assert an RST pulse) before all charge transfer events (i.e., before all TG pulses), the floating-spread reset operation is performed only at the start of the photodetection cycle to restore the output voltage to a relatively high value (reset value).

[0012] Within a depth sensor or 3D sensor, the AFE and TDC may record the magnitude and timing of the photodetector output signal following each TG pulse, allowing backend logic / computation circuitry to generate time-of-flight dependent depth measurements (e.g., determining the time when the output signal falls below the detection threshold and applying that time to depth measurement calculations). Generally, detection resolution is constrained by the TG pulse cycle time (tcyc), but measurement generation logic may interpolate between voltage reduction events in consecutive pulse cycles to achieve measurements with resolutions less than tcyc (e.g., modeling a linear photon collision profile over the duration of the detection cycle and using the coefficients of that linear profile to estimate the threshold crossover within a given tcyc interval).

[0013] Figure 4 shows the simultaneous assertion of the RST and TG signals during a photodiode reset sequence, i.e., a "blind phase" being adjusted, which can be performed after each detection cycle or every few detection cycles. The latter approach allows for averaging of measurements captured along different photowell filling points (i.e., potentially correcting the nonlinearity of the charge transfer operation) and amortizes the overhead of the blind phase over multiple detection cycles. In the illustrated example, immediately after the end of the photodiode reset operation (which can actually be an electric shutter used to clear thermally generated carriers and / or charges generated by ambient light), a light pulse is emitted, and the output of the TG pulse train begins shortly thereafter or immediately (i.e., depending on the minimum depth measurement).

[0014] In an alternative embodiment, the transfer gate 125 and the PIN floating diffusion node 123 may be omitted from the low-latency photodetector shown in Figure 2, in which case the PIN photodiode 121 continuously drives the gate of the source follower transistor 127. Such a configuration, since charge transfer operation is unnecessary, yields a relatively instantaneous output in response to photon detection and can therefore be applied to time-critical systems where sensitivity requirements are relaxed.

[0015] Figure 5 shows an alternative embodiment of the low-latency multi-photowell photodetector shown in Figure 1, in which case the JFET-based device 201 also serves as a multi-well photodiode (PD) 203 and a source follower transistor 205 for driving downstream signal processing logic. As shown in the cross-sectional view 220, the source and channel of the depletion-mode JFET are mounted on a dual-region n-doped storage well (i.e., having an n-doped region 221 and a less densely doped n-doped region 223), while the transistor drain is mounted on a p-type substrate on which the dual-region storage well is formed. The pn junction between the p-type substrate and the n-type storage well effectively constitutes the placement of the photodiode below the JFET (i.e., a stacked JFET / PD structure). From a functional standpoint, the drain of the JFET is internally connected to the substrate and biased to VSS (connection not shown), while the source of the JFET is coupled to a constant current source 215 (which itself is coupled between VDD and the JFET source terminal). When a photon collision brings electron-hole pairs into silicon, the electrons (photocharges) are collected by the storage well and accumulated in a more densely n-doped region (221) surrounding the JFET channel, modulating the electrostatic potential of the storage well and thus modulating the width of the depletion region within the channel, as shown by the dashed depletion profile in 230, effectively changing the channel resistance. Since the current flowing through the channel is kept constant by the current source 215, the voltage at the source of the JFET follows the potential of the storage well (i.e., when the detector is biased within the saturation range) and therefore changes in proportion to the number of absorbed photons.

[0016] The JFET-based detector shown in Figure 5 offers several advantages over the pin photodiode detection method. Firstly, since absorbed photons result in instantaneous voltage changes at the detector output, charge transfer operation is unnecessary, enabling higher time resolution and therefore more accurate depth measurements. Additionally, because parasitic capacitance and voltage noise from the source follower are further reduced, the JFET-based detector exhibits higher conversion gain and lower input-referred readout noise than MOSFET-based detectors (e.g., pin photodiode-based detectors), potentially enabling single-photon sensitivity.

[0017] Figure 6 shows an exemplary operating sequence within the JFET-based photodetector of Figure 5. First, during the blind phase, an electric shutter is applied by positively biasing the reset gate, i.e., element 211 in Figure 5 (i.e., asserting RST and switching it on), thereby clearing (resetting to VDD) the photodiode's storage well. At the end of the blind phase, a light pulse is emitted to initiate the depth sensing (and / or 3D imaging) operation. Subsequently, each photon collision results in photoelectron capture in the storage well, and therefore a decrease in the output voltage, as shown in 251. The timing and magnitude of the output voltage change are recorded by subsequent readout electronics (AFE / TDC circuitry), enabling the generation of depth / distance / proximity measurements within the backend processing logic.

[0018] FIG. 7 shows an exemplary top view and cross-sectional view of a p-type JFET transistor stacked vertically on a photodiode, as in the detector of FIG. 5. In the illustrated embodiment, the JFET-based detector includes a pair of (p+) type highly doped source and drain regions, an n-type doped storage well (SW) for collecting and storing photoelectrons, a p-type doped channel interconnecting the source and drain regions, and an oxide-filled isolation trench (implemented using, for example, shallow trench isolation (STI) technology, implantation-based isolation, etc.) for separating the source region from the p-type substrate. The reset transistor is physically coupled to the n-type region of the storage well to cause a reset operation to be performed on the storage well, the reset drain is always biased at a positive voltage higher than the threshold voltage of the transistor (e.g., VDD), and the reset operation can be asserted by applying a positive bias to the reset gate. In an alternative embodiment, the JFET-based detector is implemented with an n-type channel while reversing the doping polarity of each region while maintaining the relative doping concentration.

[0019] Figures 8 and 9 show alternative JFET-based photodetector circuits. In the embodiment of Figure 8, gateless reset is achieved using punch-through diodes 281, 283. The punch-through diodes form an npn junction with the n-type doping well of the photodiode. It performs the reset operation of the photodiode by making the reset drain n-well positively pulsed. Compared to the conventional reset transistor approach, there is less parasitic capacitance between the reset gate and the voltage output node (e.g., photodiode or floating-diffuse), resulting in a higher conversion gain and lower input-referred readout noise. In the embodiment of Figure 9 (which can be implemented using gateless reset or with the gated reset configuration shown in Figure 5), the JFET is biased to act as a common-source amplifier (instead of the common-drain-source follower configuration shown in Figure 5) to boost the detector gain. More specifically, a constant current source is coupled between the drain and VSS (which may be grounded) to bias the JFET drain potential, while a resistance-controlled transistor 291 (RES) is coupled between the JFET source and VDD to bias the JFET source terminal.

[0020] As described above, avalanche-gain photodetectors such as SPADs and SiPMs have only single-electron (photon) well capacitance and therefore saturate after each detected photon, requiring a reset before the next detection. This limited capacitance restricts the functionality of the detector. For example, if the full-well capacitance (FWC) is greater than that of a single electron, as in the case of the pin photodiode and JFET-based photodetectors described above, light intensity information can be acquired during the detection cycle and used to detect more informative / descriptive measurements, such as the reflectivity coefficient and texture of the detected object. More specifically, the pin photodiode and JFET-based photodetectors described herein are implemented with well capacitances far exceeding that of a single photoelectron, e.g., 2, 3, 5, 10, 100, 1000, or more photoelectron well depths or greater (or any well depth between these limits), and therefore can result in an output signal that changes gradually throughout / within a given photodetection cycle (as shown, e.g., in Figures 3 and 6). In some embodiments, AFEs and TDCs capable of capturing in-cycle arrival time and intensity information corresponding to continuous photon reception events occurring before photodetector saturation (including events or sub-intervals in which two or more photoelectrons are captured) are coupled with such multi-well low-latency photodetectors to enable high-speed readout of such in-cycle information.

[0021] In some embodiments of the sensor system, a high-bandwidth and low-noise gain stage is implemented within an analog front end (AFE) that amplifies the low-latency photodetector output signal and prepares a signal for high-speed digitization, enabling high-sensitivity / high-resolution depth measurements that utilize additional detection data made available by a multi-carrier photowell. Generally, the required AFE gain is application-specific and depends on the detector's conversion gain and the depth of the photowell. For applications that require relatively low time resolution and high sensitivity (i.e., long-distance / high-spatial-resolution depth measurements), for example, a low-latency CMOS photodetector with very low readout noise (e.g., a CMOS photodetector having a pin region within a floating diffusion as described above) and a pump gate jot (i.e., as described in U.S. Application No. 15 / 301,267) can be used. A charge transfer amplifier (CTA) can be used to read out these photodetectors (pixels). The bandwidth of the in-pixel amplifier can also be increased using a stack structure. For example, a cluster parallel architecture can be implemented as described in International Application PCT / US17 / 22607. In any case, after amplification by the analog front end, the output signal of the photodetector can be buffered (if necessary) by one or more inverters and applied to a TDC (e.g., a counter and circuitry for latching the counter output when an AFE output exceeding a predetermined or programmed threshold is detected).

[0022] Figure 10 shows one embodiment of an AFE / TDC having a parallel amplification path with decreasing gain to trigger a latch operation in each register for each photon detection count, i.e., to latch the output of the global counter 310, and thus the measured time of occurrence. For example, when a photodetector with a 1mV / e conversion gain is coupled to registers 311, 313, and 315 having a trigger threshold of 300mV (i.e., a latch signal of 300mV or more triggers a latch operation in the register, thereby recording the global count at the time of trigger), the gains of amplifiers 321, 323, and 325 are set to 300x (300 volts per volt or 300V / V), 150x, and 100x, respectively. This operation causes single-photon detection (collection of a single photoelectron in the photodiode storage well) to generate a latch trigger signal (300mV) at the latch input 311 via amplifier stage 321 to capture the time of the detection event (i.e., latch the output of the global counter in response to the first photon detection). The lower gain levels in amplifier stages 323 and 325 result in output signals (150mV and 100mV) below the threshold at the latch inputs of registers 313 and 315, so that these registers remain ready and available to latch subsequent global count values. Thus, when a second photon is detected, the output signal of the photodetector doubles from 1mV to 2mV, thus resulting in a 300mV output from amplifier stage 323, triggering a count-latch operation in register 313 to capture the time of the second photon detection event (global count). When a third photon is detected, the photodetector increments by another 1mV (to 3mV), resulting in a 300mV output from the amplifier stage 325, and thus latches the global count (and the time of detection of the third photon) in register 315. In an alternative embodiment, an additional AFE gain stage and TDC register may be provided to generate a TDC output for subsequent photon detection events up to the well depth (saturation level) of the photodetector (capturing the global count value).Furthermore, an optical sensor having an array of photodetectors (pixels within the array) may include the corresponding array of the AFE / TDC unit shown in Figure 10 (a single global counter may be provided to provide an elapsed time count for the entire array).

[0023] Figure 11 shows an alternative AFE / TDC embodiment in which a single amplifier stage outputs the amplified photodetector output signal to the latch inputs of registers, each having progressively increasing latch thresholds. Subsequently, in the exemplary 1mV / e conversion gain photodetector, amplifier stage 325 with a 100V / V gain drives the latch inputs of registers 341, 343, and 345, which have latch trigger thresholds of 50mV, 150mV, and 250mV, respectively. In this configuration, single-photon detection generates a 100mV amplifier output and thus triggers a count-latch operation in register 341 (i.e., the 100mV output from amplifier 325 exceeds the 50mV latch threshold of register 341, but does not exceed the 150mV and 250mV thresholds of registers 343 and 345). The detection of a second photon latches the output of the global counter 311 in register 343 (i.e., amplifier 325 generates a 200mV output exceeding the 150mV latch threshold of register 343), and the detection of a third photon latches the global count in register 345 (i.e., 300mV output from amplifier > 250mV latch threshold of register 345). Similar to the embodiment in Figure 10, alternative embodiments may include an additional TDC register with a progressively increasing latch threshold to generate a TDC output for subsequent photon detection events up to the well depth (saturation level) of the photodetector (global count value capture). The photosensor having an array of photodetectors may also include a corresponding array of AFE / TDC units shown in Figure 11 (however, a single global counter may be provided to provide the elapsed time count for the entire AFE / TDC array).

[0024] The AFE / TDC circuits, particularly the amplifier stage(s) shown in Figures 10 and 11, may be implemented in a stacking process to increase the bandwidth of the AFE / TDC circuit by increasing the curve factor of the photodetector IC and / or decreasing the length (and therefore parasitic capacitance) of the photodetector output lines (e.g., column output lines). In such a stacked multiwell (non-avalanche) depth sensing sensor, the entirety or any part of the readout circuit (including the AFE / TDC) may be co-located on the same integrated circuit chip as the photodetector cell(s). Alternatively, the readout circuit, in whole or in part, may be disposed on a logic chip bonded or otherwise mounted within a stack configuration having a sensor chip supporting the photodetector cell (e.g., wafer bonding of a first wafer containing the readout circuit and a second wafer containing the photodetector, followed by unitization into a two-die stack where the exposed outer surface of the photodetector chip constitutes the back-side illumination surface).

[0025] The various detectors, readout circuits, and physical configurations disclosed herein can be described using computer-aided design tools in terms of their operation, register transfers, logic components, transistors, layout geometry, and / or other characteristics, and can be represented (or displayed) as data and / or instructions embodied in various computer-readable media. Formats for files and other objects that can implement such circuit representations include, but are not limited to, formats supporting operational languages ​​such as C, Verilog, and VHDL; formats supporting register-level description languages ​​such as RTE; and formats supporting geometry description languages ​​such as GDSII, GDSIII, GDSIV, CIF, and MEBES; as well as any other suitable formats and languages. Computer-readable media in which such formatted data and / or instructions can be embodied include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether thus independently distributed or stored "in-field" within an operating system).

[0026] When received within a computer system via one or more computer-readable media, such data and / or instruction-based representations of the above-mentioned circuit can be processed by processing entities within the computer system (e.g., one or more processors) in conjunction with the execution of one or more other computer programs, including but not limited to netlist generation programs, placement and routing programs, to generate a display or image of the physical representation of such circuit. Such a display or image can then be used in device manufacturing, for example, by enabling the generation of one or more masks used to form various components of the circuit in the device manufacturing process.

[0027] The foregoing description and accompanying drawings include specific terms and symbols to provide a complete understanding of the disclosed embodiments. In some cases, terms and symbols may suggest details that are not necessary for carrying out those embodiments. For example, certain threshold levels, amplification levels, conversion gains, number of components, interconnect topology, sensor implementation, and components may differ from those described above in alternative embodiments. Signal paths depicted or described as individual signal lines may instead be implemented by multi-conductor signal buses, and vice versa, and may include multiple conductors for each signal transmitted (e.g., differential or pseudo-differential signal transmission). The term “coupled” is used herein to describe direct connections as well as connections through one or more intervening functional components or structures. Device configuration or programming may include, for example, loading control values ​​into registers or other memory circuits within an integrated circuit device in response to host instructions (and thus controlling the operating mode of the device and / or establishing the device configuration) or through a one-time programming operation (e.g., blowing a fuse in the configuration circuit during device manufacturing), and / or establishing a specific device configuration or operating mode of the device (e.g., amplification factor, latch threshold, etc.) by connecting one or more selected pins or other contact structures of the device to a reference voltage line (also known as stripping). The terms “exemplary” and “embodiment” are used to describe examples, not preferences or requirements. The terms “may” and “can” are used interchangeably to indicate optional (acceptable) subject matter. The absence of either term should not be interpreted as meaning that a given feature or technique is required.

[0028] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of this disclosure. For example, features or aspects of any embodiment can be applied in conjunction with any other embodiment, or in place of its corresponding features or aspects. Therefore, the specification and drawings should be viewed as illustrative rather than restrictive.

Claims

1. A sensing device, A photodiode having a photowell capable of accumulating two or more emitted electrons in response to light reflected from a surface, A readout circuit including a junction field-effect transistor (JFET) having a channel arranged adjacent to the photowell of the photodiode, the readout circuit generating an output signal that transitions between voltage levels in response to the accumulation of each of the electrons in the photowell, A sensing device comprising: a measuring circuit that generates a value representing the distance between the sensing device and the surface based on the output signal.

2. The sensing device according to claim 1, wherein the JFET comprises a doped source region and a drain region electrically exposed on the surface of a semiconductor substrate and interconnected by a conductive channel, and the photodiode extends more deeply below the surface of the semiconductor substrate below the conductive channel.

3. The sensing device according to claim 2, wherein the conductivity of the conductive channel of the JFET changes as photocharge accumulates in the photowell of the photodiode.

4. The sensing device according to claim 1, wherein the JFET comprises a doped source region and a drain region electrically exposed on the surface of a semiconductor substrate and interconnected by conductive channels, and the photodetector comprises an oxide trench for electrically isolating the JFET from the semiconductor substrate.

5. The sensing device according to claim 1, wherein the measurement circuit comprises a counter that outputs a series of incrementing count values, and a first latch circuit that stores any of the series of incrementing count values ​​output from the counter when the output signal exceeds a first voltage level.

6. The sensing device according to claim 5, further comprising a second latch circuit that stores any of a series of incrementing count values ​​output from the counter when the output signal exceeds a second voltage level.

7. The sensing device according to claim 6, wherein the first and second voltage levels constitute the trigger voltages of the first and second latch circuits, and the trigger voltage of the second latch circuit is greater than the trigger voltage of the first latch circuit.

8. The first latch circuit described above is A first amplifier that generates a first amplified version of the output signal, The sensing device according to claim 5, further comprising: a first latch element that stores any of the incrementing count values ​​output from the counter when the first amplified version of the output signal exceeds the trigger voltage of the first latch element.

9. The sensing device according to claim 1, further comprising a light source that emits light that propagates to the surface and is reflected from the surface in order to constitute the light reflected from the surface.

10. The sensing device according to claim 1, wherein the readout circuit transitions between voltage levels within 100 nanoseconds in response to the accumulation of each electron in the photodetector.

11. The sensing device according to claim 1, wherein the measurement circuit includes a circuit that measures the elapsed time between the emission of light from a light source and the transition of an output signal in response to light detection.

12. A method of operation within a sensing device, The method involves accumulating electrons in a photowell of a photodiode in response to light reflected from a surface, wherein the photowell can accumulate two or more emitted electrons, and the accumulation of electrons. A junction field-effect transistor (JFET) having a channel positioned adjacent to the photowell of the photodiode generates an output signal that transitions between voltage levels in response to the accumulation of each electron in the photodetector, A method comprising generating a measurement representing the distance between the sensing device and the surface based on the output signal.

13. The method according to claim 12, wherein the JFET comprises a doped source region and a drain region electrically exposed on the surface of a semiconductor substrate and interconnected by a conductive channel, and the photodiode extends more deeply below the surface of the semiconductor substrate below the conductive channel.

14. The method according to claim 13, wherein the conductivity of the conductive channel of the JFET changes as photocharge accumulates in the photowell of the photodiode.

15. The method according to claim 12, wherein the JFET comprises a doped source region and a drain region electrically exposed on the surface of a semiconductor substrate and interconnected by conductive channels, and the photodetector comprises an oxide trench for electrically isolating the JFET from the semiconductor substrate.

16. The method according to claim 12, wherein generating a measurement representing the distance between the sensing device and the surface based on the output signal includes outputting a series of incrementing count values ​​from a counter, and when the output signal exceeds a first voltage level, storing any of the series of incrementing count values ​​output from the counter in a first latch circuit.

17. The method according to claim 16, further comprising storing any of the incrementing count values ​​output from the counter in a second latch circuit when the output signal exceeds a second voltage level.

18. The method according to claim 17, wherein the first and second voltage levels constitute unequal trigger voltages for the first and second latch circuits, respectively.

19. The method according to claim 12, further comprising emitting light from the sensing device that propagates to the surface and is reflected from the surface in order to constitute the light reflected from the surface.

20. The method according to claim 12, wherein generating the output signal involves generating the output signal at the terminals of a JFET connected to the channel, and the output signal has a voltage level according to the amount of photocharge accumulated in the photodiode.

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