Photodetector and photodetector system

Abstract

To solve the problem in which: electric charges generated by a tunnel effect increase in proportion to the area of a region where the electric charges are detected; and when the area of the region where the electric charges are detected is reduced, light detection efficiency may be reduced.SOLUTION: The magnitude of the potential of a fourth semiconductor region is lower than the magnitude of the potential of a portion between the fourth semiconductor region and a third semiconductor region, and the difference between the magnitude of the potential of a first semiconductor region and the magnitude of the potential of a second semiconductor region is larger than the difference between the magnitude of the potential of the fourth semiconductor region and the magnitude of the potential of the portion between the fourth semiconductor region and the third semiconductor region. The magnitude of the potential of the third semiconductor region is lower than the magnitude of the potential of the fourth semiconductor region, and the difference between the magnitude of the potential of the first semiconductor region and the magnitude of the potential of the third semiconductor region is larger than the difference between the magnitude of the potential of the second semiconductor region and the magnitude of the potential of the fourth semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a photodetection device and a photodetection system that perform photoelectric conversion. [Background technology]

[0002] Conventionally, photodetectors capable of detecting weak light at the single-photon level are known, utilizing avalanche (electron avalanche) doubling.

[0003] Patent Document 1 discloses a SPAD (Single Photon Avalanche Diode) in which a photocharge originating from a single photon causes avalanche amplification in the PN junction region of the semiconductor region constituting the photoelectric conversion section.

[0004] Furthermore, in the SPAD described in Patent Document 1, a P-type semiconductor region with a high impurity concentration is arranged on the surface of the semiconductor substrate, and an N-type semiconductor region is arranged below the P-type semiconductor region. The N-type semiconductor region is arranged so as to be included in the N-type epitaxial layer. The P-type semiconductor region and the N-type semiconductor region form a PN junction, and a high reverse bias voltage is applied to the PN junction. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent No. 9,209,336 [Overview of the project] [Problems that the invention aims to solve]

[0006] In the SPAD described in Patent Document 1, the region for detecting charge is the PN junction region. Since a strong electric field is generated in the charge detection region, there is a risk that a tunneling effect will occur between the PN junctions due to the strong electric field. The charge generated by the tunneling effect may be detected as a false signal in the charge detection region and become noise. The amount of charge generated by this tunneling effect increases in proportion to the area of ​​the charge detection region.

[0007] On the one hand, when the area of the region for detecting charges is reduced, it is possible to suppress the charges generated by the tunneling effect. However, if the area of the region for detecting charges is reduced, there is a risk that the light detection efficiency will decrease.

[0008] Therefore, an object of the present invention is to provide a light detection device capable of suppressing noise and suppressing a decrease in light detection efficiency.

Means for Solving the Problems

[0009] The present invention is A photodetector comprising a semiconductor substrate having a first surface and a second surface, and a region on the semiconductor substrate in which a plurality of avalanche diodes are arranged, wherein the avalanche diode has a first semiconductor region of a first conductivity type arranged to a first depth relative to the first surface, a second semiconductor region of a second conductivity type which is the opposite conductivity type to the first conductivity type arranged to a second depth which is deeper relative to the first surface than the first depth, a third semiconductor region arranged to a third depth which is deeper relative to the first surface than the second depth, a fourth semiconductor region arranged to the first depth and adjacent to the first semiconductor region, and a separation portion provided between each of the plurality of avalanche diodes and the third semiconductor region, A region where avalanche amplification occurs is formed by the first semiconductor region and the second semiconductor region, the potential height for the charge of the first conductivity type in the portion between the fourth semiconductor region and the third semiconductor region is higher than the potential height for the charge of the first conductivity type in the fourth semiconductor region, and the difference between the potential height for the charge of the first conductivity type in the first semiconductor region and the potential height for the charge of the first conductivity type in the second semiconductor region is greater than the difference between the potential height for the charge of the first conductivity type in the fourth semiconductor region and the difference between the potential height for the charge of the first conductivity type in the portion between the fourth semiconductor region and the third semiconductor region.

Effects of the Invention

[0010] According to the present invention, it is possible to suppress noise and suppress a decrease in light detection efficiency.

Brief Description of the Drawings

[0011] [Figure 1] Schematic cross-sectional view of an avalanche diode [Figure 2] Schematic plan view of an avalanche diode [Figure 3] Potential diagram of an avalanche diode [Figure 4] Block diagram of a light detection device [Figure 5] Block diagram of a pixel including an equivalent circuit [Figure 6] Schematic cross-sectional view of an avalanche diode [Figure 7] Schematic plan view of an avalanche diode [Figure 8] Manufacturing method of an avalanche diode [Figure 9] Equivalent circuit diagram [Figure 10] Schematic cross-sectional view of an avalanche diode [Figure 11] Schematic cross-sectional view of an avalanche diode [Figure 12] Schematic cross-sectional view of an avalanche diode [Figure 13] Planar schematic diagram of an avalanche diode [Figure 14] Cross-sectional schematic diagram of an avalanche diode [Figure 15] Planar schematic diagram of an avalanche diode [Figure 16] Cross-sectional schematic diagram of an avalanche diode 《0000104》 Block diagram of a photodetection system [Figure 18] Block diagram of a photodetection system [Figure 19] Block diagram of a photodetection system [Figure 20] Cross-sectional schematic diagram of an avalanche diode [[ID=2C]]

Mode for Carrying Out the Invention

[0012] The photodetection device in the present embodiment will be described using FIGS. The photodetection device of the present embodiment has pixels including an avalanche diode. Among the charge pairs generated in the avalanche diode, the conductivity type of the charge used as the signal charge is called the first conductivity type. Also, the conductivity type opposite to the first conductivity type is called the second conductivity type.

[0013] FIG. 1 is a cross-sectional schematic diagram of an avalanche diode in the present embodiment. The avalanche diode of the present embodiment is disposed on a semiconductor substrate 15. The semiconductor substrate 15 has a first surface and a second surface facing the first surface. For example, the first surface is the surface of the semiconductor substrate of 15, and the second surface is the back surface of the semiconductor substrate 15. In the present embodiment, the depth direction is from the first surface toward the second surface. On the surface side of the semiconductor substrate 15, a gate electrode of a transistor and a multilayer wiring structure are disposed. [[ID=CC]]

[0014] In FIG. 1, a first semiconductor region 71 of the first conductivity type, a second semiconductor region 76, a third semiconductor region 7 of the first conductivity type, a fourth semiconductor region 72 of the second conductivity type, and a fifth semiconductor region 75 are disposed in a region sandwiched by the separation portion 16.

[0015] Note: In the translation, for the tags like [Figure 17] which are likely to be some specific internal identifiers in the original text, they are directly retained in the translation as they are. Also, for the Japanese text "

発明を実施するための形態

Mode for Carrying Out the Invention

[0016] A third semiconductor region 74 and a fourth semiconductor region 72 are located at a second depth Y that is deeper than the first depth X relative to the first surface. The third semiconductor region 74 and the fourth semiconductor region 72 are in contact.

[0017] The first semiconductor region 71 overlaps with at least a portion of the third semiconductor region 74, and the second semiconductor region 76 overlaps with at least a portion of the fourth semiconductor region 72. The fourth semiconductor region 72 is located between the third semiconductor region 74 and the separation portion 16.

[0018] A third semiconductor region 75 is located at a third depth Z that is deeper than the second depth Y relative to the first surface. The third semiconductor region 74 and the fourth semiconductor region 72 overlap with the fifth semiconductor region 75.

[0019] Figure 2 is a schematic plan view, where Figure 2(a) shows a schematic plan view at the first depth X, and Figure 2(b) shows a schematic plan view at the second depth Y.

[0020] As shown in Figure 2(a), at the first depth X, the first semiconductor region 71 is contained within the second semiconductor region 76. The second semiconductor region 76 is then contained within the separation portion 16.

[0021] As shown in Figure 2(b), at the second depth Y, the third semiconductor region 74 is contained within the fourth semiconductor region 72. The fourth semiconductor region 72 is contained within the separation portion 16. As is clear from Figures 1 and 2, in a plan view, the first semiconductor region 71 overlaps with at least a portion of the third semiconductor region 74, and the third semiconductor region 74 and the fourth semiconductor region 72 overlap with the fifth semiconductor region 75. Furthermore, the second semiconductor region 76 overlaps with at least a portion of the fourth semiconductor region 72.

[0022] Figure 3 shows the potential diagram of an avalanche diode. Figure 3 shows an example of the potential distribution of line segments JK and GH in the cross-sectional view shown in Figure 1. The dotted line 20 shows the potential distribution of line segment GH, and the solid line 21 shows the potential distribution of line segment JK. Here, the potential is shown as seen from the perspective of the signal charge, which is an electron. Note that if the signal charge is a hole, the relationship between the high and low potentials is reversed.

[0023] Furthermore, in Figure 3, depths X, Y, Z, and W correspond to the depths shown in Figure 1, and depth W is any depth between depth Y and depth Z.

[0024] The high potential at the XH level indicates the high potential of the fourth semiconductor region 72. The high potential at the H level indicates the high potential of the third semiconductor region 74. The high potential at the M level indicates the high potential of the second semiconductor region 76. The high potential at the L level indicates the high potential of the first semiconductor region 71. Note that here, the potential of the second semiconductor region 76 is assumed to be lower than the potential of the third semiconductor region 74, but the reverse is also acceptable.

[0025] The dotted line 20 represents the potential height between the XH level and the H level at depth Z. As you approach depth W from depth Z, the potential gradually decreases. Then, as you approach depth Y from depth W, the potential gradually increases, reaching the XH level at depth Y. As you approach depth X from depth Y, the potential gradually decreases, reaching the M level at depth X.

[0026] The solid line 21 represents the potential height between the XH and H levels at depth Z. The potential gradually decreases from depth Z as it approaches depth Y. As it approaches depth Y, the potential height begins to decrease sharply, reaching the H level at depth Y. From depth Y as it approaches depth X, the potential height decreases sharply, reaching the L level at depth X.

[0027] At depth Z, the potentials of dotted line 20 and solid line 21 are at approximately the same height, and the region indicated by line segments GH and JK has a potential gradient that gradually decreases toward the first surface of the semiconductor substrate 15. Therefore, the charge generated in the photodetector moves toward the first surface due to the gentle potential gradient.

[0028] As we approach depth Y from depth W, the solid line 21 exhibits a gradually decreasing potential gradient, causing charge to move towards the first surface. On the other hand, the dotted line 20 forms a potential gradient that acts as a potential barrier against charge moving toward the first surface. This potential barrier (fourth semiconductor region 72) suppresses the movement of charge from the fifth semiconductor region 75 to the second semiconductor region 76. Because the potential in the direction of movement from line segment GH to line segment JK is low relative to this potential barrier, charge present in line segment GH in the range from depth W to depth Y tends to move towards the vicinity of line segment JK during the process of moving toward the first surface.

[0029] Charges that have moved to the vicinity of the region indicated by line segment JK are accelerated by a steep potential gradient, i.e., a strong electric field, from depth Y to depth X, and the accelerated charges reach the first semiconductor region 71. Avalanche amplification occurs in the region from depth Y to X. In contrast, in the region indicated by line segment GH, avalanche breakdown does not occur, or the potential distribution is such that avalanche breakdown is less likely to occur than in the region indicated by line segment JK, especially the region from depth Y to X of line segment JK. As an example of realizing such a structure, it is preferable to configure the structure such that the difference in potential height between the first semiconductor region 71 and the third semiconductor region 74 is greater than the difference in potential height between the second semiconductor region 76 and the fourth semiconductor region 72.

[0030] By adopting such a potential structure, it is possible to reduce the noise charge generated by the tunneling effect described above, compared to conventional configurations in which avalanche breakdown occurs throughout the entire avalanche diode. In addition, the avalanche diode of this embodiment does not cause a decrease in sensitivity. This is because the potential structure makes it easy for signal charges present in the region of the fifth semiconductor region 75 that overlaps with the fourth semiconductor region 72 to move to the first semiconductor region via the third semiconductor region 74.

[0031] Specifically, this is because the potential of the third semiconductor region 74 is lower than that of the fourth semiconductor region 72. In other words, the fourth semiconductor region 72 acts as a potential barrier to the signal charge present in the fifth semiconductor region 75, and as a result, charge is more easily transferred to the first semiconductor region 71 via the third semiconductor region 74.

[0032] Figure 3 shows the potential structure when the third semiconductor region 74 is a P-type semiconductor region. However, even when the third semiconductor region 74 is an N-type semiconductor region, the potential height at position Y is higher for the dotted line 20 than for the solid line 21. Similarly, Figure 3 shows the potential structure when the second semiconductor region 76 is an N-type semiconductor region. However, even when the second semiconductor region 76 is a P-type semiconductor region, the potential height at position Y is higher for the dotted line 20 than for the solid line 21.

[0033] Furthermore, it is preferable that the entire area of ​​the first semiconductor region 71 overlaps with the third semiconductor region 74 in a plan view. With this configuration, a PN junction is not formed between the first semiconductor region 71 and the fourth semiconductor region 72. Therefore, it is possible to suppress avalanche amplification and noise caused by the tunnel effect at the PN junction between the first semiconductor region 71 and the fourth semiconductor region 72.

[0034] The embodiments of the present invention will be described below using specific examples. In each embodiment, a configuration in which the signal charge is an electron will be described, but the invention is also applicable when the signal charge is a hole. In that case, the semiconductor regions and potential relationships will be reversed.

[0035] (Example 1) An example of a photodetector applicable to the present invention will be described using Figures 4 to 9. Parts having the same function as those in Figures 1 to 3 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0036] Figure 4 is a block diagram of the light detection device 1010 of this embodiment. The light detection device 1010 includes a pixel unit 106, a control pulse generation unit 109, a horizontal scanning circuit unit 104, a column circuit 105, a signal line 107, and a vertical scanning circuit unit 103.

[0037] Multiple pixels 100 are arranged in a matrix within the pixel section 106. Each pixel 100 consists of a photoelectric conversion element 101 and a pixel signal processing unit 102. The photoelectric conversion element 101 converts light into an electrical signal. The pixel signal processing unit 102 outputs the converted electrical signal to the column circuit 105.

[0038] The vertical scanning circuit section 103 receives control pulses supplied from the control pulse generation section 109 and supplies control pulses to each pixel 100. Logic circuits such as a shift register and an address decoder are used in the vertical scanning circuit section 103.

[0039] The signal line 107 supplies the signal output from the pixel 100 selected by the vertical scanning circuit unit 103 as a potential signal to the circuit downstream of the pixel 100.

[0040] The column circuit 105 receives signals from each pixel 100 via the signal line 107 and performs predetermined processing. This predetermined processing involves noise reduction and amplification of the input signals, and converting them into a format that can be output outside the sensor. For example, the column circuit includes a parallel-to-serial conversion circuit.

[0041] The horizontal scanning circuit unit 104 supplies control pulses to the column circuit 105 for sequentially outputting the signals processed by the column circuit 105 to the output circuit 108.

[0042] The output circuit 108 consists of a buffer amplifier, a differential amplifier, etc., and outputs the signal output from the column circuit 105 to an external recording unit or signal processing unit of the photodetector 1010.

[0043] In Figure 4, the arrangement of pixels 100 in the pixel section 106 may be arranged in a one-dimensional manner, or it may consist of only single pixels. Furthermore, the vertical scanning circuit section 103, the horizontal scanning circuit section 104, and the column circuit 105 may be arranged in blocks, dividing the pixel section 106 into multiple pixel columns. Alternatively, they may be arranged in each pixel column.

[0044] The pixel signal processing unit 102 does not necessarily need to be provided for every pixel 100; for example, one pixel signal processing unit 102 may be shared by multiple pixels 100, and signal processing may be performed sequentially. Furthermore, the pixel signal processing unit 102 may be provided on a different semiconductor substrate from the photoelectric conversion element 101 in order to increase the aperture ratio of the photoelectric conversion element 101. In this case, the photoelectric conversion element 101 and the pixel signal processing unit 102 are electrically connected via connection wiring provided for each pixel. The vertical scanning circuit unit 103, the horizontal scanning circuit unit 104, the signal line 107, and the column circuit 105 may also be provided on different semiconductor substrates as described above.

[0045] Figure 5 shows an example of a block diagram of a pixel 100 including the equivalent circuit in this embodiment. In Figure 5, one pixel 100 has a photoelectric conversion element 101 and a pixel signal processing unit 102.

[0046] The photoelectric conversion element 101 has a photoelectric conversion unit 201 and a control unit 202.

[0047] The photoelectric conversion unit 201 generates charge pairs corresponding to the incident light through photoelectric conversion. An avalanche diode is used in the photoelectric conversion unit 201.

[0048] The cathode of the photoelectric conversion unit 201 is supplied with a potential based on a potential VH that is higher than the potential VL supplied to the anode. The anode and cathode of the photoelectric conversion unit 201 are supplied with a potential such that a reverse bias is applied, causing the photoelectric conversion unit 201 to function as an avalanche diode. By performing photoelectric conversion with this reverse bias potential supplied, the charge generated by the incident light undergoes avalanche amplification, generating an avalanche current.

[0049] Furthermore, when a reverse bias potential is supplied, if the potential difference between the anode and cathode is greater than the breakdown voltage, the avalanche diode operates in Geiger mode. A SPAD is a photodiode that uses Geiger mode operation to quickly detect weak signals at the single-photon level.

[0050] Furthermore, if the potential difference between the anode and cathode of the photoelectric conversion unit 201 is greater than or equal to the potential difference at which the charge generated in the photoelectric conversion unit 201 causes avalanche amplification, and less than or equal to the breakdown voltage, the avalanche diode will operate in linear mode. An avalanche diode that performs photodetection in linear mode is called an avalanche photodiode (APD). In this embodiment, the photoelectric conversion unit 201 may operate as either an avalanche diode. The potential difference at which avalanche amplification occurs will be described later.

[0051] The control unit 202 is connected to the power supply voltage that provides a high potential VH and to the photoelectric conversion unit 201. The control unit 202 has the function of converting the change in avalanche current generated in the photoelectric conversion unit 201 into a voltage signal. Furthermore, the control unit 202 functions as a load circuit (quench circuit) during signal amplification by avalanche amplification, suppressing the voltage supplied to the photoelectric conversion unit 201 and thereby suppressing avalanche amplification (quench operation). As the control unit 202, for example, a resistive element or an active quench circuit that actively suppresses avalanche amplification by detecting an increase in avalanche current and performing feedback control is used.

[0052] The pixel signal processing unit 102 includes a waveform shaping unit 203, a counter circuit 209, and a selection circuit 206. The waveform shaping unit 203 shapes the voltage change obtained when a photon-level signal is detected and outputs a pulse signal. For example, an inverter circuit can be used as the waveform shaping unit 203. Although an example using one inverter as the waveform shaping unit 203 has been shown, a circuit with multiple inverters connected in series may be used, or other circuits that have a waveform shaping effect may be used.

[0053] The pulse signals output from the waveform shaping unit 203 are counted by the counter circuit 209. The counter circuit 209, for example, an N-bit counter (N: positive integer), can count up to approximately 2 to the power of N pulse signals from single photons. The counted signals are held as detected signals. Furthermore, when a control pulse pRES is supplied via the drive line 207, the detected signals held in the counter circuit 209 are reset.

[0054] The selection circuit 206 is supplied with a control pulse pSEL from the vertical scanning circuit section 103 in Figure 4 via the drive line 208, which switches the electrical connection between the counter circuit 209 and the signal line 107. The selection circuit 206 may use, for example, a transistor or a buffer circuit for outputting signals outside the pixel.

[0055] Furthermore, switches such as transistors may be placed between the control unit 202 and the photoelectric conversion unit 201, or between the photoelectric conversion element 101 and the pixel signal processing unit 102, to switch the electrical connections. Similarly, the supply of the high potential VH supplied to the control unit 202 or the low potential VL supplied to the photoelectric conversion element 101 may be electrically switched using switches such as transistors.

[0056] In a pixel section 106 where multiple pixels 100 are arranged in a matrix, the counter circuit 209 may be reset row by row, and the detected signals held by the counter circuit 209 may be output row by row in a rolling shutter operation to acquire the captured image.

[0057] Alternatively, the captured image may be acquired by a global electronic shutter operation in which the counts of the counter circuits 209 for all pixel rows are simultaneously reset, and the detected signals held by the counter circuits 209 are output sequentially row by row. When performing a global electronic shutter operation, it is advisable to provide a means to switch between when to perform the count of the counter circuits 209 and when not to perform it. The means for switching is, for example, the switch mentioned above.

[0058] In this embodiment, a configuration is shown in which an image is acquired using a counter circuit 209. However, instead of the counter circuit 209, a photodetector 1010 may be used to acquire the pulse detection timing using a time-to-digital converter (TDC) and memory.

[0059] At this time, the generation timing of the pulse signal output from the waveform shaping unit 203 is converted into a digital signal by the TDC. The TDC is supplied with a control pulse pREF (reference signal) via a drive line from the vertical scanning circuit unit 103 in Figure 4 to measure the timing of the pulse signal. The TDC uses the control pulse pREF as a reference and acquires the signal as a digital signal when the input timing of the signal output from each pixel via the waveform shaping unit 203 is considered as a relative time.

[0060] The TDC circuit can use, for example, a delay line method that creates a delay by connecting buffer circuits in series, or a looped TDC method that connects delay lines in a loop. Other methods may be used, but it is preferable to use a circuit method that can achieve a time resolution equal to or greater than that of the photoelectric conversion unit 201.

[0061] The digital signal representing the pulse detection timing obtained at TDC is stored in one or more memories. If multiple memories are provided, multiple signals are supplied to the selection circuit 206, making it possible to control the output to the signal line 107 for each memory when outputting the digital signal held in the memory to the signal line 107.

[0062] Schematic cross-sectional and plan views of the avalanche diode of this embodiment will be explained using Figures 6 and 7. In Figure 6, the region where the first semiconductor region 71 in Figure 1 is located is an N-type semiconductor region 1, and the region where the second semiconductor region 76 in Figure 1 is located is an N-type semiconductor region 6. In Figure 6, the region where the third semiconductor region 74 in Figure 1 is located is an N-type semiconductor region 4, and the region where the fourth semiconductor region 72 in Figure 1 is located is a P-type semiconductor region 2. In Figure 6, the region where the fifth semiconductor region 75 in Figure 1 is located is an N-type semiconductor region 5.

[0063] First, using Figure 6, we will explain the cross-sectional structure of the separation section 16 and the photoelectric conversion region sandwiched between the separation sections 16.

[0064] A semiconductor substrate 15 on which multiple pixels 100 are arranged is provided with a separation unit 16 that separates each of the multiple pixels 100.

[0065] The separation section 16 is composed of P-type semiconductor regions arranged from the first surface in the depth direction. Specifically, the separation section 16 consists of a P-type semiconductor region 3 and a P-type semiconductor region 7, which are arranged in this order from the first surface in the depth direction and are in contact with each other. The P-type semiconductor region 3 is electrically connected to the P-type semiconductor region 7, the P-type semiconductor region 8 (described later), and the P-type semiconductor region 2 (described later).

[0066] The impurity concentration in P-type semiconductor region 3 is higher than the impurity concentrations in P-type semiconductor regions 7, 8, and 2. This makes it possible to achieve lower contact resistance by connecting P-type semiconductor region 3 to contact plug 17 than by connecting P-type semiconductor region 7 to contact plug 17.

[0067] N-type semiconductor region 1 is a region with a higher impurity concentration than N-type semiconductor region 6, N-type semiconductor region 4, and N-type semiconductor region 5 (described later). By using such an impurity concentration, it is possible to strengthen the electric field of the depletion layer that forms in N-type semiconductor region 1. A potential that is a reverse bias to the isolation region 16 is supplied to N-type semiconductor region 1.

[0068] The impurity concentration in N-type semiconductor region 4 is made lower than that in N-type semiconductor region 1. This makes it easier to transfer charge from the vicinity of N-type semiconductor region 4 to N-type semiconductor region 1.

[0069] The impurity concentration in N-type semiconductor region 6 is lower than the impurity concentration in N-type semiconductor region 1. For example, the impurity concentration in N-type semiconductor region 1 is 6.0 × 10⁻⁶. 18 [atms / cm 3 When the value is above this, the impurity concentration in the N-type semiconductor region 6 is 1.0 × 10⁻⁶. 16 [atms / cm 3 ] Above, 1.0 × 10 18 [atms / cm 3 The following applies:

[0070] In Figure 6, a configuration is shown in which an N-type semiconductor region 6 without an impurity concentration gradient is located in the second semiconductor region 76 of Figure 1. However, it is preferable that the semiconductor region located in the region where the second semiconductor region 76 is located in Figure 1 has an impurity concentration gradient. By configuring the region between the N-type semiconductor region 1 and the P-type semiconductor region 3 to have an impurity concentration gradient, the strong electric field that may occur between the N-type semiconductor region 1 and the P-type semiconductor region 3 is mitigated compared to the case where the N-type semiconductor region 6 does not have an impurity concentration gradient.

[0071] Two examples of regions with a gradient of impurity concentrations will be explained. The first example is a case where an N-type semiconductor region with a lower impurity concentration than that of N-type semiconductor region 1 is located in a region close to N-type semiconductor region 1, and an N-type semiconductor region with a lower impurity concentration than that of N-type semiconductor region is located in a region close to separation section 16. The second example is a case where an N-type semiconductor region with a lower impurity concentration than that of N-type semiconductor region 1 is located in a region close to N-type semiconductor region 1, and a P-type semiconductor region with a lower impurity concentration than that of P-type semiconductor region 3 is located in a region close to separation section 16. Specifically, as shown in Figure 20, a P-type semiconductor region 2000 with a lower impurity concentration than that of P-type semiconductor region 3 is provided between P-type semiconductor region 3 and N-type semiconductor region 6.

[0072] In this way, by configuring the region between the N-type semiconductor region 1 and the P-type semiconductor region 3 to have an impurity concentration gradient, the strong electric field that may occur between the N-type semiconductor region 1 and the P-type semiconductor region 3 is mitigated compared to the case where the N-type semiconductor region 6 does not have an impurity concentration gradient.

[0073] Next, the impurity concentration in the P-type semiconductor region 2 is set to be less than or equal to the impurity concentration in the P-type semiconductor region 7. The P-type semiconductor region 2 and the N-type semiconductor region 4 form a PN junction. This PN junction causes the entire region of the N-type semiconductor region 4 to become a depletion layer region. Furthermore, this depletion layer region extends to a portion of the N-type semiconductor region 1. A strong electric field is induced in the extended depletion layer region. This strong electric field causes avalanche amplification in the depletion layer region that extends to a portion of the N-type semiconductor region 1, and a current based on the amplified charge is output from the wiring 9. In other words, in this embodiment, the photodetector region is the depletion layer region in a portion of the N-type semiconductor region 1.

[0074] In this embodiment, the reason why the N-type semiconductor region 4 is composed of an N-type region rather than a P-type region is to extend the depletion layer deeper into the N-type semiconductor region 5, thereby enabling charge acquisition from deeper within the region.

[0075] Furthermore, if the N-type semiconductor region 6 were to be a P-type semiconductor region, a depletion layer region would be formed between this P-type semiconductor region and the N-type semiconductor region 1, potentially causing avalanche amplification between the P-type and N-type semiconductor regions. Since noise increases as the depletion layer region expands closer to the first surface of the P-semiconductor substrate 15, the N-type semiconductor region 1 in this embodiment is constructed of N-type semiconductor material.

[0076] Furthermore, the impurity concentrations of the N-type semiconductor region 1, the N-type semiconductor region 4, and the P-type semiconductor region 2 are set to impurity concentrations such that when a potential difference that causes avalanche amplification is supplied in the depletion layer region that occurs in a part of the N-type semiconductor region 1, not all regions of the N-type semiconductor region 1 are depleted. This is because if the depletion layer region spreads closer to the first surface of the semiconductor substrate 15, there is a risk of noise occurring on the first surface of the semiconductor substrate 15. On the other hand, the impurity concentration of all regions of the N-type semiconductor region 4 is set to an impurity concentration such that all regions are depleted.

[0077] The condition for all regions of the N-type semiconductor region 4 to be depleted is shown in Equation 1. Here, the impurity concentration of the N-type semiconductor region 4 is denoted as the impurity concentration Nd, the impurity concentration of the P-type semiconductor region 2 is denoted as the impurity concentration Na, and the elementary charge is denoted as the elementary charge q. Furthermore, the dielectric constant of the semiconductor is denoted as the dielectric constant ε, the potential difference between the PN junctions of the N-type semiconductor region 4 and the P-type semiconductor region 2 is denoted as the potential difference V, and the length of the N-type semiconductor region 4 sandwiched between the P-type semiconductor regions 2 is denoted as the length D.

[0078]

Equation

[0079] The impurity concentration at which not all regions of the N-type semiconductor region 1 are depleted is, for example, the impurity concentration of the N-type semiconductor region 1 is 6.0×10 18 [atms / cm 3 or higher. In that case, the impurity concentration that satisfies these depletion conditions is such that the impurity concentration of the P-type semiconductor region 2 is 1.0×10 16 [atms / cm 3 or higher. Also, the impurity concentration of the N-type semiconductor region 4 is 1.0×10 17 [atms / cm 3 or lower. However, it is not limited to these impurity concentrations.

[0080] Then, the potential difference between the N-type semiconductor region 1 and the isolation region 16 is set so that the depth-direction electric field induced in the extended depletion layer becomes sufficiently large. Here, a sufficiently large potential difference is the potential difference at which the charge affected by the electric field undergoes avalanche amplification. In other words, it is the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 at which the photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD).

[0081] Specifically, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 2 is 6V or more. At this time, as described above, all regions of the N-type semiconductor region 4 that are electrically connected to the N-type semiconductor region 1 become depletion layers, and a strong electric field is generated in the depletion layers that extend to a portion of the N-type semiconductor region 1, causing avalanche amplification.

[0082] Furthermore, considering the impurity concentration that satisfies the depletion conditions described above, more preferably, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 is 10V or more and 30V or less. In this case, for example, a potential of 10V or more is supplied to the N-type semiconductor region 1, and a potential of 0V or less is supplied to the P-type semiconductor region 3. However, these potential values ​​are not limited as long as the potential difference is 6V or more.

[0083] Furthermore, the depletion layer formed between the P-type semiconductor region 2 and the N-type semiconductor region 6 may extend to the N-type semiconductor region 1, potentially causing avalanche amplification. In this case, if the entire region of the N-type semiconductor region 1 is depleted, noise may be generated. Therefore, it is best to set the impurity concentration of the N-type semiconductor region 1 so as not to deplete the entire region of the N-type semiconductor region 1.

[0084] In this embodiment, charge is generated in the N-type semiconductor region 5, collected in the N-type semiconductor region 1, and read out. That is, the charge generated in the first conductivity type semiconductor region is read out from the first conductivity type semiconductor region.

[0085] In contrast, the device described in U.S. Patent No. 9,209,336 avalanche-amplified the charge generated in the N-type epitaxial layer 2 at the interface between the N-type epitaxial layer 2 and the p-type anode region 14, and reads the charge from the p-type anode region 14. That is, the charge generated in the semiconductor region of the first conductivity type is read from the semiconductor region of the second conductivity type. In this respect as well, this embodiment differs from the device described in U.S. Patent No. 9,209,336.

[0086] In Figure 6, we assume that instead of providing P-type semiconductor region 2 and N-type semiconductor region 4, an N-type semiconductor region 5 with a lower impurity concentration than N-type semiconductor region 1 is placed immediately below the N-type semiconductor region 1, which has a higher impurity concentration. In this case, it is possible to generate charge in N-type semiconductor region 5 and read charge from N-type semiconductor region 1, but it is difficult to perform avalanche amplification under the same voltage conditions as in this embodiment. This is because most of the potential difference applied between N-type semiconductor region 1 and P-type semiconductor region 3 is applied to the depletion layer region of N-type semiconductor region 5, which reduces the potential difference applied to the avalanche amplification region near N-type semiconductor region 1. On the other hand, in this embodiment, N-type semiconductor region 5 is surrounded by P-type semiconductor regions in all directions except where it is in contact with N-type semiconductor region 4, so the potential of N-type semiconductor region 5 is closer to the level of the surrounding P-type semiconductor region than that of N-type semiconductor region 1. In other words, by suppressing the excessive spread of the depletion layer deep into the substrate in the P-type semiconductor region 2, it becomes possible to concentrate most of the applied potential difference in the avalanche amplification region near the N-type semiconductor region 1. As a result, photocharge can be avalanche amplified at a lower voltage.

[0087] Next, the impurity concentration in N-type semiconductor region 5 is less than or equal to the impurity concentration in N-type semiconductor region 4. For example, the impurity concentration in N-type semiconductor region 5 is 1.0 × 10⁻⁶. 17 [atms / cm 3The following conditions apply: Since it is "less than or equal to," the impurity concentration in N-type semiconductor region 5 and the impurity concentration in N-type semiconductor region 4 may be the same. Furthermore, at a minimum, the impurity concentration in N-type semiconductor region 5 must be less than the impurity concentration in N-type semiconductor region 1.

[0088] In Figure 6, the N-type semiconductor region 5 is shown as an example, consisting of a region with the same impurity concentration. However, it is preferable for the N-type semiconductor region 5 to have an impurity concentration gradient such that it creates a potential structure where charge moves towards the first surface of the semiconductor substrate 15. By creating such an impurity concentration gradient, it is possible to facilitate the movement of charge to the N-type semiconductor region 1.

[0089] Furthermore, if the impurity concentration gradient is such that a potential structure is created in which charge moves to the first surface side of the semiconductor substrate 15, then in the region where the N-type semiconductor region 5 is located, the first surface side may be an N-type semiconductor region and the second surface side may be a P-type semiconductor region.

[0090] Alternatively, a P-type semiconductor region with a lower impurity concentration than the P-type semiconductor region 2 may be placed in place of the N-type semiconductor region 5. In this case as well, it is preferable to have an impurity concentration gradient such that a potential structure is created in which charge moves towards the first surface side of the semiconductor substrate 15.

[0091] For example, this P-type semiconductor region has a first region, a second region located deeper than the first region relative to the first surface, and a third region located deeper than the second region relative to the first surface. When the first region is defined as the first impurity concentration, the second region as the second impurity concentration, and the third region as the third impurity concentration, the first impurity concentration < second impurity concentration < third impurity concentration may be set. Note that the first impurity concentration will be lower than the impurity concentration of the P-type semiconductor region 2. Here, the P-type semiconductor region placed in place of the N-type semiconductor region 5 is divided into three regions, but this is not limited to this.

[0092] The P-type semiconductor region 8 is located deeper than the N-type semiconductor region 5, defining the depth of the photoelectric conversion region. The N-type semiconductor region 5 forms PN junctions with the P-type semiconductor region 2, the P-type semiconductor region 7, and the P-type semiconductor region 8, respectively. The impurity concentration in the P-type semiconductor region 8 is higher than that in the P-type semiconductor region 2. This makes it easier for charges generated near the P-type semiconductor region 8 to move in the direction of the first plane.

[0093] A contact plug 18 is connected to the N-type semiconductor region 1, and a wire 9 is connected to the contact plug 18. A contact plug 17 is connected to the P-type semiconductor region 3, and a wire 10 is connected to the contact plug 17. The wire 9 or wire 10 is then connected to a control unit 202, such as a resistive element, for performing a quench operation. In the following description, it will be assumed that the control unit 202 is connected to the wire 9.

[0094] In Figure 6, the contact plug 17 and wiring 10 are described as being located on the first side. However, the contact plug 17 and wiring 10 may also be located on the second side.

[0095] When the contact plug 17 and wiring 10 are arranged on the second side, the impurity concentration in the P-type semiconductor region 8 where the contact plug 17 is located should be higher than the impurity concentration in the P-type semiconductor region 7. In other words, it becomes a P-type semiconductor region 3. In this case, since the contact plug 17 is no longer connected to the P-type semiconductor region 3 that was located on the first side, it is preferable to set the impurity concentration to be about the same as that of the P-type semiconductor region 7. This makes it possible to mitigate the electric field generated between the P-type semiconductor region 3 and the N-type semiconductor region 1.

[0096] Furthermore, even when the separation portion 16 has an insulating separation portion on the first surface side, the contact plugs 17 and 10 are arranged on the second surface side. In this case, the separation portion 16 is arranged in contact with the insulating separation portion, the P-type semiconductor region 7, and the P-type semiconductor region 3 in the depth direction from the first surface.

[0097] Next, using Figure 7, we will describe the planar structure of the separation portion 16 and the photoelectric conversion region sandwiched between the separation portions 16 at an arbitrary depth in the cross-sectional structure of Figure 6. In Figure 7, the boundaries of each semiconductor region are drawn as circles, but this is not the only way.

[0098] Figure 7(a) shows a schematic planar view of line segment AB at depth X in Figure 6. N-type semiconductor region 1 is contained within N-type semiconductor region 6. N-type semiconductor region 6 is contained within P-type semiconductor region 3. Furthermore, the area of ​​N-type semiconductor region 6 is larger than the area of ​​N-type semiconductor region 1.

[0099] Figure 7(b) shows a schematic planar view of the line segment CD at depth Y in Figure 6. The N-type semiconductor region 4 is contained within the P-type semiconductor region 2. The P-type semiconductor region 2 is contained within the P-type semiconductor region 3.

[0100] Figure 7(c) shows a schematic planar view of the line segment EF at depth Z in Figure 6. The N-type semiconductor region 5 is contained within the P-type semiconductor region 7.

[0101] When Figure 7(b) and Figure 7(c) are superimposed, the N-type semiconductor region 4 and the P-type semiconductor region 2 overlap with the N-type semiconductor region 5 in a plan view.

[0102] Furthermore, when Figure 7(a) and Figure 7(b) are superimposed, in a plan view, the N-type semiconductor region 1 overlaps with at least a portion of the N-type semiconductor region 4, and the N-type semiconductor region 6 overlaps with at least a portion of the P-type semiconductor region 2.

[0103] Next, using Figure 8, the manufacturing method of the avalanche diode shown in the schematic cross-sectional diagram in Figure 6 will be explained. The order of steps not specifically mentioned can be changed as appropriate. Furthermore, for steps omitted in explanation in Figure 8, well-known manufacturing methods can be applied.

[0104] As shown in Figure 8(a), P-type impurity ions (hereinafter referred to as ion implantation) are implanted into the region that will become the N-type semiconductor region 5, from the direction normal to the first surface of the semiconductor substrate 15. This forms a P-type semiconductor region 8 at a depth relative to the first surface of the semiconductor substrate 15.

[0105] Next, as shown in Figure 8(b), a mask 77 is formed on the first surface of the semiconductor substrate 15. The mask 77 has an opening 30. Then, by performing P-type ion implantation from the direction normal to the first surface of the semiconductor substrate 15, P-type semiconductor regions 3 and P-type semiconductor regions 7 are formed so that they are arranged in this order from the first surface. At this time, a part of the P-type semiconductor region 7 and a part of the P-type semiconductor region 8 are connected. In addition, the impurity concentration of the P-type semiconductor region 3 is made higher than the impurity concentration of the P-type semiconductor region 7. Specifically, for example, this can be achieved by performing ion implantation multiple times with different ion implantation energies.

[0106] Next, mask 77 is removed and mask 78 is placed. Mask 78 has an opening 32. Then, as shown in Figure 8(c), P-type ion implantation is performed from a direction parallel to the normal direction to the first surface of the semiconductor substrate 15 to form a region that will become a P-type semiconductor region 2. Subsequently, N-type ion implantation is performed at a position shallower to the first surface than the position where P-type ion implantation was performed to form the region that will become the P-type semiconductor region 2 to form a region that will become an N-type semiconductor region 6. Here, the region that will become the P-type semiconductor region 2 is formed first and then the region that will become the N-type semiconductor region 6, but the reverse order may also be performed.

[0107] Next, mask 78 is removed and mask 73 is placed. Mask 73 has an opening 33. As shown in Figure 8(d), N-type ion implantation is performed from a direction parallel to the normal direction to the first surface of the semiconductor substrate 15 to the depth to which the region that will become the P-type semiconductor region 2 is located, thereby forming an N-type semiconductor region 4 in a part of the region that will become the P-type semiconductor region 2.

[0108] Next, an N-type semiconductor region 1 is formed by implanting N-type ions into the first surface of the semiconductor substrate 15 from a direction parallel to the normal direction to the first surface of the semiconductor substrate 15. Here, the N-type semiconductor region 4 was formed first, but the N-type semiconductor region 1 may be formed first.

[0109] Thus, when ion implantation is performed using impurity ions of the same conductivity type, the diffusion of impurity ions in a direction parallel to the first surface is greater when ion implantation is performed at a deeper position relative to the first surface (the incident surface) than when ion implantation is performed at a shallower position relative to the first surface (the incident surface). In other words, when ion implantation is performed using the same mask, the N-type semiconductor region 1 is contained within the N-type semiconductor region 4 in a plan view.

[0110] Furthermore, impurity ions with different thermal diffusion coefficients may be used as impurity ions implanted to form N-type semiconductor region 1 and N-type semiconductor region 4. With such a configuration, the degree of freedom in potential design in the region where N-type semiconductor region 1 and N-type semiconductor region 4 are located is improved.

[0111] In Figure 8(d), when ion implantation is performed using different masks to form N-type semiconductor region 1 and N-type semiconductor region 4, positional misalignment occurs, resulting in an asymmetrical electric field distribution and potentially causing a tunneling effect. On the other hand, according to the manufacturing method of this embodiment, since N-type semiconductor region 1 and N-type semiconductor region 4 are formed using the same mask, it is possible to suppress positional misalignment between the two semiconductor regions, thereby suppressing the tunneling effect that may occur due to positional misalignment.

[0112] Next, the control unit 202 of this embodiment will be described using Figure 9. In this embodiment, the control unit 202 has two configurations. The first configuration is one in which the control unit 202 is located on the cathode side to which the high potential VH of the photoelectric conversion unit 201 is supplied, as shown in Figure 9(a). The second configuration is one in which the control unit 202 is located on the anode side to which the low potential VL of the photoelectric conversion unit 201 is supplied, as shown in Figure 9(b).

[0113] In the configurations shown in Figures 9(a) and 9(b), a certain amount of time is required between the change in the input potential of the waveform shaping unit 203 due to the avalanche current and the return to the initial bias state of the photoelectric conversion unit 201 due to the voltage drop by the control unit 202. This period, from the detection of a charge to the return to a bias state where it is possible to detect another charge, is called the dead time. The shorter this dead time, the greater the number of charges that can be counted per unit of time, and the larger the dynamic range of the photodetector.

[0114] For example, if the control unit 202 is a resistive element, the Dead time (τd[s]) of the avalanche diode in this embodiment is determined by the product of the resistance (R[Ω]) and the capacitance of the input terminal (C[F]). In the following formula, the PN junction capacitance of the photoelectric conversion unit 201 is denoted by Cpd, the capacitance of the well of the photoelectric conversion unit 201 is denoted by Cw, and the parasitic capacitance of the wiring / diffusion layer is denoted by C.

[0115] In the case of Figure 9(a), the dead time can be calculated using formula 2. τd = R(Cpd + C) …(Equation 2) In the case of Figure 9(b), the dead time can be calculated using formula 3. τd = R(Cpd + Cw + C) …(Equation 3)

[0116] The PN junction capacitance Cpd of the photoelectric conversion unit 201 is the PN junction capacitance of the photodetector region that induces a strong electric field to produce avalanche amplification. Therefore, the PN junction capacitance Cpd changes in proportion to the area of ​​the photodetector region. In other words, if the area of ​​the photodetector region is increased to improve photodetection efficiency, the PN junction capacitance Cpd increases, and the dead time increases. As a result, the dynamic range decreases.

[0117] That is, there is a trade-off relationship between the light detection efficiency and the dynamic range. On the other hand, according to the pixel structure of this embodiment, while ensuring a large area of the photoelectric conversion region, the area of the light detection region can be reduced. Therefore, Cpd can be reduced and Dead time can be reduced. As a result, it is possible to achieve both high light detection efficiency and high dynamic range.

[0118] The improvement effect of the dynamic range by the pixel structure of this embodiment is more显著 shown in the configuration of FIG. 9(a) than in FIG. 9(b). For example, if the ratio of Cpd of the SPAD structure of this embodiment to the conventional SPAD structure is A (0 < A < 1), the improvement rate Δ of the dynamic range in each circuit method of FIGS. 9(a) and 9(b) is represented by Formula 4 and Formula 5, respectively. Δ\(_1\) = (1 - A)Cpd / (ACpd + C) …(Formula 4) Δ\(_2\) = (1 - A)Cpd / (ACpd + Cw + C) …(Formula 5)

[0119] In Formula 4 and Formula 5, the calculation is performed using the fact that the dynamic range is inversely proportional to the Dead time. From the above formula, it can be seen that Δ\(_1\) > Δ\(_2\) is always satisfied.

[0120] From the above, when FIGS. 9(a) and 9(b) are applied in the configuration of this embodiment, the improvement rate of the dynamic range is theoretically higher for FIG. 9(a) than for FIG. 9(b).

[0121] So far, the control unit 202 has been described as a resistive element, but the same applies to the case of an active quenching circuit.

[0122] From the above, the control unit 202 for the pixel of this embodiment can achieve a greater improvement effect on the dynamic range when arranged on the cathode side than when arranged on the anode side of the photoelectric conversion unit 201.

[0123] According to the configuration of this embodiment, it is possible to suppress the decrease in photodetection efficiency by forming a path for charge movement. In other words, it is possible to reduce noise while suppressing the decrease in photodetection efficiency.

[0124] (Example 2) Figure 10 is a schematic cross-sectional view of the avalanche diode in this embodiment. Figures 4, 5, 8, and 9 are the same as in Embodiment 1. Also, parts having the same function as in Figures 1 to 9 are denoted by the same reference numerals, and detailed explanations are omitted. Figure 10 differs in that a P-type semiconductor region 24 is arranged in the region where the N-type semiconductor region 4 is located in Figure 6.

[0125] In Figure 10, the N-type semiconductor region 1 and the P-type semiconductor region 24 form a PN junction. The P-type semiconductor region 24 is electrically connected to the P-type semiconductor region 3 via the P-type semiconductor region 2. Therefore, the potential of the P-type semiconductor region 24 is reverse-biased to that of the N-type semiconductor region 1. A strong electric field is induced in the PN junction region between the N-type semiconductor region 1 and the P-type semiconductor region 24. This strong electric field causes avalanche amplification in the PN junction region, and a current based on the amplified charge is output from wiring 9 or 10. In other words, in this embodiment, the photodetection region is the PN junction region between the N-type semiconductor region 1 and the P-type semiconductor region 24. With this configuration, the potential difference required to generate avalanche amplification can be reduced compared to Embodiment 1. That is, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in this embodiment can be reduced compared to the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 3 in Embodiment 1.

[0126] In Figure 10, the impurity concentration in the P-type semiconductor region 24 is lower than that in the P-type semiconductor region 2 and the P-type semiconductor region 7. Therefore, the potential relationship described in Figure 3 holds true in this embodiment as well.

[0127] The impurity concentration in the N-type semiconductor region 1 is set so that, when a potential that causes avalanche amplification is supplied between the PN junctions, the entire region of the N-type semiconductor region 1 does not become depleted, as described above.

[0128] In this embodiment, the impurity concentration at which all regions of the N-type semiconductor region 1 are not depleted is, for example, an impurity concentration of 6.0 × 10⁻⁶ in the N-type semiconductor region 1. 18 [atms / cm 3 That's all. The impurity concentration in the P-type semiconductor region 24 is 1.0 × 10⁻⁶. 17 [atms / cm 3 The following applies. This is because if the depletion layer region expands as it approaches the first surface of the semiconductor substrate 15, noise may be generated on the first surface of the semiconductor substrate 15. However, this is not limited to these impurity concentrations.

[0129] Specifically, the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 when the above-mentioned photoelectric conversion unit 201 operates as an avalanche diode (APD or SPAD) is 6V or more.

[0130] Considering the impurity concentration relationship described above, it is more preferable that the potential difference between the N-type semiconductor region 1 and the P-type semiconductor region 24 is 10V or more. In this case, for example, a potential of 10V or more is supplied to the N-type semiconductor region 1, and a potential of 0V or less is supplied to the P-type semiconductor region 24 via the P-type semiconductor region 2. However, the potentials are not limited to these, as long as the potential difference is 6V or more.

[0131] In this embodiment, when applying the manufacturing method shown in Figure 8, the P-type semiconductor region 24 is formed by performing N-type ion implantation to the extent that it locally reduces the impurity concentration in a portion of the region that will become the P-type semiconductor region 2, as shown in Figure 8(d).

[0132] This embodiment also has the same effects as Example 1.

[0133] (Example 3) Figure 11 is a schematic cross-sectional view of the avalanche diode in this embodiment. Parts having the same function as those in Figures 1 to 10 are denoted by the same reference numerals, and detailed explanations are omitted.

[0134] Figure 11 differs from the potential of the region where the N-type semiconductor region 5 is located in Figure 6, in that, in a direction parallel to the first surface, the potential height of the region farther from the separation region 16 is lower than the potential height of the region closer to the separation region 16.

[0135] In Figure 11, in a direction parallel to the first surface, an N-type semiconductor region 28 is arranged in the region close to the separation portion 16, and an N-type semiconductor region 27 is arranged in the region far from the separation portion 16.

[0136] In this embodiment, the impurity concentration relationship is set such that the potential of the N-type semiconductor region 27 is lower than the potential of the N-type semiconductor region 28, thereby facilitating the movement of charge from the N-type semiconductor region 28 to the N-type semiconductor region 27.

[0137] In other words, in the direction parallel to the first surface, the potential in the region far from the separation portion (N-type semiconductor region 27) is lower than the potential in the region close to the separation portion 16 (N-type semiconductor region 28).

[0138] Therefore, the impurity concentration in the N-type semiconductor region 28 should be lower than that in the N-type semiconductor region 27. Furthermore, in order to form a potential gradient to the photodetector region, the impurity concentration in the N-type semiconductor region 27 should be lower than that of the N-type semiconductor region 4.

[0139] Furthermore, if a P-type semiconductor region is placed in place of the N-type semiconductor region 27, a P-type semiconductor region with a higher impurity concentration than the P-type semiconductor region placed in its place is placed in place of the N-type semiconductor region 28.

[0140] With this configuration, when the direction from the position where the separation section 16 is located to the position where the N-type semiconductor region 27 is located is defined as the in-plane direction, an in-plane electric field is induced by creating an impurity distribution such that charges move in the in-plane direction. This electric field causes charges generated deep within the semiconductor substrate 15 to move in the in-plane direction.

[0141] With this configuration, for example, it becomes possible to shorten the time it takes for an electric charge generated at a deep location in the semiconductor substrate 15 to move to the photodetection region.

[0142] Furthermore, as mentioned above, it is preferable to create a potential that facilitates charge movement from deeper to shallower positions on the first surface of the semiconductor substrate 15. By creating such a potential relationship, it is possible to further reduce the time required for charge movement to the photodetection region.

[0143] This embodiment is applicable to all embodiments.

[0144] (Example 4) Figure 12 is a schematic cross-sectional view of the avalanche diode in this embodiment. Parts having the same function as in Figures 1 to 11 are denoted by the same reference numerals, and detailed explanations are omitted.

[0145] Figure 12 differs from the P-type semiconductor region 2 in Figure 6 in that it is composed of P-type semiconductor regions 2B and 2A with different depths.

[0146] In Figure 12, the P-type semiconductor region 2 comprises a P-type semiconductor region 2A and a P-type semiconductor region 2B. The P-type semiconductor region 2A is located between the N-type semiconductor region 6 and the P-type semiconductor region 3 constituting the separation portion 16 at a first depth X. The P-type semiconductor region 2B is located between the N-type semiconductor region 5 and the N-type semiconductor region 4 at a second depth Y. A portion of the P-type semiconductor region 2A is in contact with the N-type semiconductor region 5, and the other portion of the P-type semiconductor region 2A is in contact with the P-type semiconductor region 2B.

[0147] Next, using Figure 13, we will describe the planar structure of the separation portion 16 and the photoelectric conversion region sandwiched between the separation portions 16 at an arbitrary depth in the cross-sectional structure of Figure 12. In Figure 13, the boundaries of each semiconductor region are drawn as circles, but this is not the only way. Note that the schematic planar diagram of the line segment EF at depth Z is the same as in Figure 7(c) and is therefore omitted.

[0148] Figure 13(a) shows a schematic planar view of line segment AB at the first depth X in Figure 12. N-type semiconductor region 1 is contained within N-type semiconductor region 6. N-type semiconductor region 6 is contained within P-type semiconductor region 2A. P-type semiconductor region 2A is contained within P-type semiconductor region 3.

[0149] Figure 13(b) shows a schematic planar view of the line segment CD at the second depth Y in Figure 12. The N-type semiconductor region 4 is contained within the P-type semiconductor region 2B. The P-type semiconductor region 2B is contained within the N-type semiconductor region 5. The N-type semiconductor region 5 is contained within the P-type semiconductor region 3.

[0150] When Figure 13(a) and Figure 13(b) are superimposed, the P-type semiconductor region 2A overlaps with the P-type semiconductor region 2B and the N-type semiconductor region 5.

[0151] According to the configuration of this embodiment, it is possible to make a portion of the region where the P-type semiconductor region 2 is located at the second depth Y in Figure 6 into an N-type semiconductor region 5. This makes it possible to increase the short-wavelength light detection efficiency, especially when used in a surface-irradiated type.

[0152] This embodiment is applicable to all embodiments.

[0153] (Example 5) Figure 14 is a schematic cross-sectional view of the photodiode in this embodiment. Parts having the same function as in Figures 1 to 13 are denoted by the same reference numerals, and detailed explanations are omitted. Figure 14 differs from Figure 6 in that multiple N-type semiconductor regions 1 and N-type semiconductor regions 4 are arranged.

[0154] Figure 14 shows a configuration in which two N-type semiconductor regions 1 and two N-type semiconductor regions 4 are arranged, but the number is not limited to two as long as there are multiple of each.

[0155] N-type semiconductor region 1A is sandwiched between N-type semiconductor regions 6. Similarly, N-type semiconductor region 1B is sandwiched between N-type semiconductor regions 6.

[0156] N-type semiconductor region 4A is sandwiched between P-type semiconductor regions 2. Similarly, N-type semiconductor region 4B is sandwiched between P-type semiconductor regions 2.

[0157] Next, using Figure 15, we will describe the planar structure of the separation portion 16 and the photoelectric conversion region sandwiched between the separation portions 16 at an arbitrary depth in the cross-sectional structure of Figure 14. In Figure 15, the boundaries of each semiconductor region are drawn as circles, but this is not the only way. Note that the schematic planar diagram of the line segment EF at depth Z is the same as in Figure 7(c) and is therefore omitted.

[0158] Figure 15(a) shows a schematic planar view of line segment AB at depth X in Figure 14. N-type semiconductor region 1A and N-type semiconductor region 1B are each contained within N-type semiconductor region 6. N-type semiconductor region 6 is contained within P-type semiconductor region 3. The area of ​​N-type semiconductor region 6 is larger than the areas of N-type semiconductor region 1A and N-type semiconductor region 1B.

[0159] Figure 15(b) shows a schematic planar view of the line segment CD at depth Y in Figure 14. N-type semiconductor region 4A and N-type semiconductor region 4B are each contained within P-type semiconductor region 2. P-type semiconductor region 2 is contained within P-type semiconductor region 7.

[0160] When Figure 15(b) and Figure 7(c) are superimposed, the N-type semiconductor region 4A, N-type semiconductor region 4B, and P-type semiconductor region 2 overlap with the N-type semiconductor region 5.

[0161] Furthermore, when Figure 15(a) and Figure 15(b) are superimposed, in a plan view, the N-type semiconductor region 1A overlaps with at least a portion of the N-type semiconductor region 4A. In a plan view, the N-type semiconductor region 1B overlaps with at least a portion of the N-type semiconductor region 4B. As mentioned above, in a plan view, it is preferable that the entire region of the N-type semiconductor region 1 overlaps with the N-type semiconductor region 4 in a plan view such that it is contained within the N-type semiconductor region 4.

[0162] Furthermore, when Figure 15(a) and Figure 15(b) are superimposed, the N-type semiconductor region 6 overlaps with at least a portion of the P-type semiconductor region 2.

[0163] According to the configuration of this embodiment, the N-type semiconductor regions 1 and 4, which are arranged at multiple locations, make it possible to shorten the average travel distance of charges generated in the photoelectric conversion region to the photodetection region. Therefore, it is possible to shorten the time required to detect charges generated at deep locations in the photoelectric conversion region.

[0164] This embodiment is applicable to all embodiments.

[0165] (Example 6) Figure 16 is a schematic cross-sectional view of the avalanche diode and control unit in this embodiment. Parts having the same function as those in Figures 1 to 15 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0166] In Figure 16, the photoelectric conversion unit 201 and the control unit 202 are arranged on different semiconductor substrates. The configuration of the avalanche diode constituting the photoelectric conversion unit 201 is the same as in Example 1. Multiple photoelectric conversion units 201 are arranged on the semiconductor substrate 15, and here, as an example, a configuration in which two avalanche diodes are arranged is shown. The control unit 202 and the wiring 1107 connected to the control unit 202 are arranged on the semiconductor substrate 1102. Here, a configuration in which the control unit 202 and wiring 1107 are arranged on the semiconductor substrate 1102 is shown, but other circuits may also be arranged.

[0167] The avalanche diode in this embodiment has a back-illuminated configuration. Light is incident from the N-type semiconductor region 5 toward the N-type semiconductor region 1. At this time, the light passes through the microlens 1103 and the color filter 1104 before being incident on the N-type semiconductor region 5.

[0168] As mentioned above, photoelectric conversion occurs in the N-type semiconductor region 5, and the resulting charge moves through the N-type semiconductor region 4 to the N-type semiconductor region 1. Avalanche amplification occurs due to the electric field between the N-type semiconductor region 1 and the depletion layer formed between the P-type semiconductor region 2 and the N-type semiconductor region 4, causing current to flow through the wiring 9.

[0169] The wiring 9 is connected via the connection part 1105 to the control unit 202 provided on a separately manufactured semiconductor substrate 1102.

[0170] The signals detected by each avalanche diode are processed by a scanning circuit or the like, which is provided around the pixel area of ​​the semiconductor substrate 1102. The scanning circuit may be located on a semiconductor substrate different from semiconductor substrates 15 and 1102.

[0171] In this embodiment, a different semiconductor substrate 1102 is stacked on a semiconductor substrate 15 on which an avalanche diode is arranged. By placing processing circuits such as a control unit 202 on the stacked semiconductor substrate 1102, it becomes possible to increase the aperture ratio of the avalanche diode and improve the photodetection efficiency.

[0172] In this embodiment, when a microlens 1103 is placed on each avalanche diode, it is preferable that the optical axis of the microlens 1103 be positioned such that it is contained within the N-type semiconductor region 4 in a plan view. For example, when vertical light is incident on the central part of the photoelectric conversion element 101, the distribution of the probability of signal charge generation within the N-type semiconductor region 5 is maximum near the optical axis of the microlens 1103. Here, the optical axis of the microlens is the axis perpendicular to the semiconductor substrate 15 that passes through the center of the microlens in a plan view.

[0173] As in the configuration of this embodiment, if the optical axis of the microlens 1103 is planarly contained within the N-type semiconductor region 4, then in the N-type semiconductor region 5, charges are more likely to be generated at positions close to the N-type semiconductor region 4 in a planar view. This makes it possible to reduce the probability of charge generation at positions farther away in the planar view, and to suppress the decrease in the time resolution until charge detection in the photodetection region due to the difference between charges generated at shallow and deep positions relative to the first surface of the semiconductor substrate 15.

[0174] In this embodiment, a back-illuminated photodiode configuration is used, but even with a front-illuminated configuration, the effects of this embodiment, namely high photodetection efficiency and low DCR, can be achieved simultaneously. However, in this embodiment, since the photoelectric conversion unit is formed on the back side, the back-illuminated configuration can detect the charge generated near the outermost surface of the substrate (the side where light is incident) with higher efficiency compared to the front-illuminated configuration. In other words, it is preferable for the photoelectric conversion unit 201 in this embodiment to be a back-illuminated type because it can achieve high photodetection efficiency over a broad wavelength range from short to long wavelengths.

[0175] This embodiment is applicable to all embodiments.

[0176] (Example 7) This embodiment describes an example of a photodetection system using the photodetector 1010 of each embodiment. An invisible light detection system and a medical diagnostic system such as PET, which are examples of photodetection systems, will be described using Figure 17. Parts having the same function as in Figures 1 to 16 are denoted by the same reference numerals, and detailed explanations are omitted. Note that the pixel 100 in this embodiment has a TDC and memory instead of the counter circuit 209 in Figure 5. Here, the TDC will be referred to as TDC204 and the memory as memory205.

[0177] Figure 17 is a block diagram illustrating the configuration of the invisible light detection system. The invisible light detection system includes a wavelength conversion unit 1201, a data processing unit 1207, and multiple light detection devices 1010.

[0178] The irradiating object 1200 emits light in the wavelength range that is invisible. The wavelength conversion unit 1201 receives the light in the wavelength range that is invisible emitted from the irradiating object 1200 and emits visible light.

[0179] The photoelectric conversion unit 201 receives visible light irradiated from the wavelength conversion unit 1201 and performs photoelectric conversion. The photodetector 1010 then stores a digital signal based on the photoelectrically converted charge in the memory 205 via the control unit 202, waveform shaping unit 203, and TDC 204. Multiple photodetectors 1010 may be formed as a single device or as multiple devices arranged in a sequence.

[0180] Multiple digital signals held in the memory 205 of multiple light detection devices 1010 are processed by the data processing unit 1207. Here, the signal processing means involves combining multiple images obtained from the multiple digital signals.

[0181] Next, as a specific example of an invisible light detection system, we will explain the configuration of medical diagnostic systems such as PET.

[0182] The subject, which is the irradiated object 1200, emits radiation pairs from within its body. The wavelength conversion unit 1201 constitutes a scintillator, and when radiation pairs emitted from the subject are incident on the scintillator, it irradiates it with visible light.

[0183] The photoelectric conversion unit 201 receives the visible light irradiated from the scintillator and performs photoelectric conversion. The photodetector 1010 then stores a digital signal based on the photoelectrically converted charge in the memory 205 via the control unit 202, the waveform shaping unit 203, and the TDC 204. In other words, the photodetector 1010 is positioned to detect the arrival time of radiation pairs emitted from the subject, detects the visible light irradiated from the scintillator, and stores the digital signal in the memory 205.

[0184] The digital signals held in the memory 205 of the multiple photodetectors 1010 are processed by the data processing unit 1207. Here, as a signal processing means, multiple images obtained from the multiple digital signals are used to perform synthesis processing such as image reconstruction to form an image of the subject's body.

[0185] (Example 8) This embodiment describes an example of a photodetection system using the photodetector 1010 of each embodiment. Parts having the same function as those in Figures 1 to 16 are denoted by the same reference numerals, and detailed descriptions are omitted.

[0186] Figure 18 illustrates a distance detection system, which is an example of a light detection system. In this embodiment, pixel 100 has a TDC and memory instead of the counter circuit 209 in Figure 5. Here, the TDC will be referred to as TDC204 and the memory as memory205.

[0187] An example of a block diagram of the distance detection system in this embodiment will be explained using Figure 18. The distance detection system includes a light source control unit 1301, a light-emitting unit 1302, an optical element 1303, a light detection device 1010, and a distance calculation unit 1309.

[0188] The light source control unit 1301 controls the drive of the light-emitting unit 1302. When the light-emitting unit 1302 receives a signal from the light source control unit 1301, it emits short pulses (series) of light in the direction of shooting.

[0189] Light emitted from the light-emitting unit 1302 is reflected by the subject 1304. The reflected light is received by the photoelectric conversion unit 201 of the light detection device 1010 via the optical member 1303, and a signal based on the photoelectrically converted charge is input to the TDC 204 via the waveform shaping unit 203.

[0190] The TDC204 compares the signal obtained from the light source control unit 1301 with the signal input from the waveform shaping unit 203. It then digitally converts with high precision the time from when the light-emitting unit 1302 emits pulsed light until the reflected light reflected from the subject 1304 is received. The digital signal output from the TDC204 is stored in the memory 205.

[0191] The distance calculation unit 1309 calculates the distance from the light detection device to the subject based on the digital signals from multiple measurements stored in the memory 205. This distance detection system can be applied, for example, in a vehicle.

[0192] Next, Figure 19 shows an example of a light detection system using the counter circuit 209 shown in Figure 5. Figure 19 describes a light detection system related to an in-vehicle camera, which is an example of a light detection system.

[0193] The light detection system 1000 is a light detection system including a distance measuring pixel and an imaging pixel according to the present invention. The light detection system 1000 has an image processing unit 1030 that performs image processing on a plurality of digital signals acquired by the light detection device 1010. Furthermore, the light detection system 1000 has a disparity calculation unit 1040 that calculates disparity (phase difference of disparity images) from a plurality of image data acquired by the image processing unit 1030.

[0194] Furthermore, the light detection system 1000 includes a distance measurement unit 1050 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 1060 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax calculation unit 1040 and the distance measurement unit 1050 are examples of distance information acquisition means that acquire distance information to an object. That is, distance information is information related to parallax, defocus amount, distance to an object, etc.

[0195] The collision determination unit 1060 may use any of this distance information to determine the possibility of a collision. The distance information acquisition means may be implemented by specially designed hardware, by a software module, or by a combination of these. It may also be implemented by an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), or by a combination of these.

[0196] The optical detection system 1000 is connected to the vehicle information acquisition device 1310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The optical detection system 1000 is also connected to the control ECU 1410, which is a control device that outputs a control signal to generate braking force on the vehicle based on the judgment result of the collision judgment unit 1060.

[0197] Furthermore, the light detection system 1000 is also connected to a warning device 1420 that issues a warning to the driver based on the judgment result of the collision judgment unit 1060. For example, if the collision judgment unit 1060 determines that there is a high probability of collision, the control ECU 1410 performs vehicle control to avoid a collision or mitigate damage by applying the brakes, releasing the accelerator, or suppressing engine output. The warning device 1420 warns the user by sounding an alarm, displaying warning information on a screen such as a car navigation system, or vibrating the seat belt or steering wheel.

[0198] In this embodiment, the light detection system 1000 captures images of the area around the vehicle, for example, in front of or behind it. Figure 19(B) shows the light detection system when capturing images in front of the vehicle. Furthermore, although the above describes control to avoid collisions with other vehicles, it can also be applied to control that automatically follows other vehicles or control that automatically stays within the lane. In addition, the light detection system can be applied not only to vehicles such as the vehicle itself, but also to moving objects (mobile devices) such as ships, aircraft, or industrial robots. Moreover, it can be applied not only to moving objects, but also to a wide range of devices that utilize object recognition, such as intelligent transportation systems (ITS). [Explanation of symbols]

[0199] 1. N-type semiconductor region 2 P-type semiconductor region 4. N-type semiconductor region 5. N-type semiconductor region 6. N-type semiconductor region 15 Semiconductor substrates 16 Separation part

Claims

1. A semiconductor substrate having a first surface and a second surface, A photodetector having a region on the semiconductor substrate in which a plurality of avalanche diodes are arranged, The avalanche diode is A first semiconductor region of a first conductivity type is arranged to a first depth relative to the first surface, A second semiconductor region of a second conductivity type which is the opposite conductivity type to the first conductivity type, is located at a second depth which is deeper with respect to the first surface than the first depth, A third semiconductor region is located at a third depth that is deeper than the second depth relative to the first surface, and is a semiconductor region of the first conductivity type with a lower impurity concentration than the first semiconductor region. A fourth semiconductor region is located at the first depth, adjacent to the first semiconductor region, and is a semiconductor region of the first conductivity type having a lower impurity concentration than the first semiconductor region. The plurality of avalanche diodes each have a separation portion provided between the third semiconductor regions, The first semiconductor region and the second semiconductor region form a region where avalanche amplification occurs. In a cross-sectional view, the width of the first semiconductor region is narrower than the width of the second semiconductor region. The potential for the charge of the first conductivity type in the portion between the fourth semiconductor region and the third semiconductor region is higher than the potential for the charge of the first conductivity type in the fourth semiconductor region. A photodetector characterized in that the difference between the potential height for the charge of the first conductivity type in the first semiconductor region and the potential height for the charge of the first conductivity type in the second semiconductor region is greater than the difference between the potential height for the charge of the first conductivity type in the fourth semiconductor region and the difference in the potential height for the charge of the first conductivity type in the portion between the fourth semiconductor region and the third semiconductor region.

2. The photodetector according to claim 1, characterized in that, in a cross-sectional view, the width of the region where the first semiconductor region and the second semiconductor region overlap is narrower than the width of the third semiconductor region.

3. The photodetector according to claim 1 or 2, characterized in that the charge generated in the third semiconductor region is collected in the region where the avalanche amplification occurs.

4. The photodetector according to any one of claims 1 to 3, characterized in that, in a plan view, all areas of the first semiconductor region overlap with the second semiconductor region.

5. The impurity concentration in the first semiconductor region is 6.0 × 10⁻⁶. １８ [atms / cm ３ That's all, The impurity concentration in the second semiconductor region is 1.0 × 10⁻⁶. １７ [atms / cm ３ The light detection device according to any one of claims 1 to 4, characterized in that it is as follows:

6. The photodetector according to any one of claims 1 to 5, characterized in that the third semiconductor region has a lower potential for the charge of the first conductivity type at positions shallower to the first surface than at positions deeper to the first surface.

7. The photodetector according to any one of claims 1 to 6, characterized in that the separation portion includes a fifth semiconductor region of the second conductivity type.

8. The photodetector according to claim 7, characterized in that, in a direction parallel to the first surface, the potential height of the third semiconductor region is lower in the region far from the fifth semiconductor region than in the region close to the fifth semiconductor region.

9. The photodetector according to claim 7 or 8, characterized in that the avalanche diode includes a sixth semiconductor region of the second conductivity type, which is positioned at a fourth depth that is deeper than the third depth relative to the first surface.

10. The sixth semiconductor region is connected to the fifth semiconductor region, The photodetector according to claim 9, characterized in that the second semiconductor region is electrically connected to the fifth semiconductor region.

11. The photodetector according to any one of claims 1 to 10, characterized in that the separation section includes an insulating separation section.

12. The photodetector according to any one of claims 1 to 11, characterized in that a contact plug electrically connected to the second semiconductor region is connected to the first surface.

13. The photodetector according to any one of claims 1 to 11, characterized in that a contact plug electrically connected to the second semiconductor region is connected to the second surface.

14. The photodetector according to any one of claims 1 to 13, characterized in that the first conductivity type is N-type and the second conductivity type is P-type.

15. The photodetector according to any one of claims 1 to 14, characterized in that the portion between the fourth semiconductor region and the third semiconductor region is a semiconductor region of the second conductivity type.

16. Having a semiconductor substrate different from the aforementioned semiconductor substrate, The aforementioned different semiconductor substrate is provided with a control unit that controls the potential supplied to the first semiconductor region. The aforementioned semiconductor substrate and the aforementioned different semiconductor substrate are stacked, The photodetector according to any one of claims 1 to 15, characterized in that the first semiconductor region and the control unit are electrically connected via wiring.

17. It has microlenses, The photodetector according to any one of claims 1 to 16, characterized in that, in a plan view, the microlens is arranged to overlap with the second semiconductor region.

18. A photodetection system having a photodetector according to any one of claims 1 to 17, A wavelength conversion unit that converts light in a first wavelength band to light in a second wavelength band different from the first wavelength band, The photodetector into which the light of the second wavelength band output from the wavelength conversion unit is incident, A photodetection system characterized by having signal processing means for processing a digital signal corresponding to the light in the second wavelength band from the photodetector.

19. A photodetection system having a photodetector according to any one of claims 1 to 17, A light-emitting unit that emits light detected by the aforementioned light detection device, A light detection system characterized by having distance calculation means that calculates distance using a digital signal corresponding to the light detected from the light detection device.

20. It is a mobile object, A light detection device according to any one of claims 1 to 17, Distance information acquisition means for acquiring distance information to an object based on the signal from the aforementioned light detection device, A mobile body characterized by having control means for controlling the mobile body based on the distance information.

21. A photodetection system having a photodetector according to any one of claims 1 to 17, A photodetection system characterized by having signal processing means configured to process signals from the aforementioned photodetector.

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