Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device which can inhibit generation of voids in a case when a resin nut cover is molded by primary molding and a resin case is molded by secondary molding.SOLUTION: A semiconductor device includes: a plate-like terminal 4a including one main surface and the other main surface and having one end electrically connected to a semiconductor chip; a nut 9a arranged on the one main surface side at the other end of the terminal 4a; a nut cover 7a which is provided on the one main surface side at the other end of the terminal 4a and covers the nut 9a; and a case 1 which surrounds a periphery of the semiconductor chip and integrates the terminal 4a and the nut cover 7a. The nut cover 7a includes a protruding portion 72a protruding from a lower portion of the nut cover 7a to the one end side of the terminal 4a.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a semiconductor device (semiconductor module) and a method for manufacturing the same.

Background Art

[0002] A semiconductor module used for inverter drive of motors for electric vehicles or hybrid vehicles is known. In a semiconductor module, a resin case is provided so as to surround the periphery of a semiconductor chip mounted on an insulating circuit board. An external terminal is electrically connected to the semiconductor chip. The external terminal is insert-molded integrally with the case when the case is molded. A nut for fastening a conductor such as a bus bar extending from an electronic device such as an inverter to the external terminal is joined.

[0003] In order to insulate the nuts that come into contact with a plurality of external terminals from each other, when trying to cover the nuts during molding of the case, voids may occur in the portion between the nuts, and there is a risk of deterioration of the insulation between the nuts. Therefore, during the manufacture of a semiconductor module, a resin nut cover (nut glove) that covers the nuts is molded by primary molding, and a resin case is molded by secondary molding so as to cover the nut cover.

[0004] Patent Document 1 discloses a terminal block that is fastened by overlapping conductors and tightening bolts, and includes a plurality of nuts on which the conductors are placed and partition walls that partition between adjacent nuts. The partition wall extends in a direction intersecting the arrangement direction of the nuts and is located at least in the range from the lower surface of the nut to the upper surface of the bolt fastened to the nut in the vertical direction, and is composed of an insulating wall made of a primary molding resin that insulates between adjacent nuts, and a secondary molding portion made of a secondary molding resin that fills the gap between the insulating wall and the nut and covers the entire side surface of the insulating wall. It is disclosed that an exposed portion is provided on the upper surface of the secondary molding portion, where a part of a protruding portion provided to protrude upward from the upper end of the insulating wall is exposed.

[0005] Patent Document 2 discloses a method for forming an outer case for a power semiconductor device by pre-molding a terminal nut cover having a structure that includes a first recess capable of covering and supporting the terminal nut so as not to rotate when the bolt is fastened, and a second recess for allowing the tip of the threaded portion of the bolt to protrude, and then placing an electrode plate, whose terminal portion has been bent into a predetermined shape using a press machine or the like, and the terminal nut cover having a terminal nut inserted and supported in the first recess, into a mold for the outer case and integrally insert-molding them together with the outer case.

[0006] Patent Document 3 discloses a device comprising a pair of busbars and a resin sealant that seals the pair of busbars, wherein the pair of busbars are adjacent to each other at a predetermined distance in the thickness direction of the busbars, and the resin sealant has a first resin part and a second resin part that are in contact with each other.

[0007] Patent Document 4 discloses a power semiconductor module comprising a module body having a base substrate on which a primary molded body, which is a resin molded body having a power semiconductor element and a plurality of terminals, is mounted, and a secondary molded body that includes the module body inside and is resin molded with a portion of the plurality of terminals exposed, wherein the primary molded body has three or more legs that protrude toward the mounting surface side of the base substrate.

[0008] Patent Document 5 discloses a semiconductor device comprising a case and laminated substrates housed in the case's compartments, wherein a positive electrode is connected to the P terminal and a negative electrode is connected to the N terminal, and a control signal is applied to each control terminal, and outputs corresponding to the control signal are obtained from the U terminal, V terminal and W terminal. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2012-185926 [Patent Document 2] Japanese Patent Application Publication No. 9-69603 [Patent Document 3] Japanese Patent Publication No. 2019-192709 [Patent Document 4] Japanese Patent Publication No. 2019-0542967 [Patent Document 5] Japanese Patent Publication No. 2017-084881 [Overview of the project] [Problems that the invention aims to solve]

[0010] However, as described in Patent Document 1, in the method of molding a resin nut cover by primary molding and a resin case by secondary molding, there is a problem that voids tend to occur in the case molded by secondary molding.

[0011] In view of the above problems, the present invention aims to provide a semiconductor device and a method for manufacturing the same that can suppress the generation of voids in a resin case when a resin nut cover is molded by primary molding and a resin case is molded by secondary molding. [Means for solving the problem]

[0012] One aspect of the present invention is a semiconductor device comprising: (a) a plate-shaped terminal having one main surface and the other main surface, with one end electrically connected to a semiconductor chip and the other end having a bolt insertion hole; (b) a nut disposed on the side of one main surface of the other end of the terminal; (c) a nut cover provided on the side of one main surface of the other end of the terminal and covering the nut; and (d) a case surrounding the semiconductor chip and integrating the terminal and the nut cover, wherein the nut cover has a protrusion that extends toward one end of the terminal.

[0013] Another aspect of the present invention is a method for manufacturing a semiconductor device, comprising: (a) a step of molding a nut cover having a covering portion in which a hole for fitting a nut is formed and a protruding portion protruding from the covering portion; (b) a step of fitting the nut into the covering portion; (c) a step of arranging a plate-like terminal having one main surface and the other main surface, one end electrically connected to a semiconductor chip, and the other end provided with a bolt insertion hole, in a mold; (d) a step of arranging the nut cover with the nut fitted therein on one main surface side of the other end of the terminal such that the protruding portion protrudes toward one end side of the terminal; and (e) a step of molding a case for integrating the terminal and the nut cover.

Advantages of the Invention

[0014] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the same that can suppress the generation of voids in a case when molding a resin nut cover by primary molding and molding a resin case by secondary molding.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 15 is a schematic plan view of the semiconductor device according to the embodiment as viewed from the upper surface side. [Figure 2] FIG. 18 is an equivalent circuit diagram of the semiconductor device according to the embodiment. [Figure 3] FIG. 21 is a perspective view of a part of the semiconductor device according to the embodiment. [Figure 4] FIG. 24 is a cross-sectional view taken along line A-A' of FIG. 1. [Figure 5] FIG. 27 is a schematic plan view of a part of the semiconductor device according to the embodiment as viewed from the lower surface side. [Figure 6] FIG. 30 is a perspective view corresponding to FIG. 3 of the semiconductor device according to the comparative example. [Figure 7] FIG. 33 is a cross-sectional view corresponding to FIG. 4 of the semiconductor device according to the comparative example.

Embodiments of the Invention

[0016] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual ones. Also, there may be portions where the dimensional relationships and ratios are different between the drawings. Further, the embodiments shown below illustrate devices and methods for embodying the technical idea of the present invention, and the technical idea of the present invention does not specify the material, shape, structure, arrangement, etc. of the components as follows.

[0017] Also, the definitions of directions such as up and down, left and right in the following description are merely for convenience of explanation and do not limit the technical idea of the present invention. For example, if the object is rotated by 90° and observed, up and down are read as being converted to left and right, and if it is rotated by 180° and observed, up and down are read as being inverted, of course.

[0018] (Embodiment) <Configuration of the semiconductor device> As shown in FIG. 1, the semiconductor device (semiconductor module) according to the embodiment includes insulating circuit boards 6a to 6c, and power semiconductor elements (semiconductor chips) 61a to 64a, 61b to 64b, 61c to 64c mounted on the main surfaces (upper surfaces) of the insulating circuit boards 6a to 6c via a bonding material such as solder or a sintered material, and a case 1 arranged so as to surround the insulating circuit boards 6a to 6c and the semiconductor chips 61a to 64a, 61b to 64b, 61c to 64c.

[0019] As shown in FIG. 1, in the plan view of the semiconductor device according to the embodiment, the longitudinal direction of the semiconductor device according to the embodiment is defined as the X-axis, and the right direction in FIG. 1 is defined as the positive direction of the X-axis. Also, the short-side direction of the semiconductor device according to the embodiment orthogonal to the X-axis is defined as the Y-axis, and the upward direction in FIG. 1 is defined as the positive direction of the Y-axis. Further, the direction orthogonal to the X-axis and the Y-axis is defined as the Z-axis, and the front side in FIG. 1 is defined as the positive direction of the Z-axis. The same shall apply to FIGS. 3 and later.

[0020] For Case 1, resin materials such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polybutylene succinate (PBS), epoxy, and phenol can be used. Case 1 separates the area where the insulating circuit board 6a and semiconductor chips 61a to 64a are located, the area where the insulating circuit board 6b and semiconductor chips 61b to 64b are located, and the area where the insulating circuit board 6c and semiconductor chips 61c to 64c are located.

[0021] In the area partitioned by Case 1, where the insulating circuit board 6a and semiconductor chips 61a to 64a are located, sealing member 5a is filled to seal the insulating circuit board 6a and semiconductor chips 61a to 64a. In the area where the insulating circuit board 6b and semiconductor chips 61b to 64b are located, sealing member 5b is filled to seal the insulating circuit board 6b and semiconductor chips 61b to 64b. In the area where the insulating circuit board 6c and semiconductor chips 61c to 64c are located, sealing member 5c is filled to seal the insulating circuit board 6c and semiconductor chips 61c to 64c. As sealing members 5a to 5c, insulating materials such as silicone gel and thermosetting resins such as epoxy resins can be used. In Figure 1, the insulating circuit boards 6a to 6c and semiconductor chips 61a to 64a, 61b to 64b, and 61c to 64c sealed with sealing members 5a to 5c are schematically shown by dashed lines.

[0022] The insulated circuit boards 6a to 6c may be, for example, direct copper bond (DCB) boards or activated brazing (AMB) boards. The insulated circuit boards 6a to 6c comprise an insulating plate, a conductive plate (circuit board) disposed on the upper surface of the insulating plate, and a conductive plate (heat sink) disposed on the lower surface of the insulating plate. The insulating plate is made of a ceramic substrate consisting of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), etc., or a resin insulating substrate using polymer materials, etc. The conductive plate is made of a conductive foil such as copper (Cu) foil or aluminum (Al) foil, for example.

[0023] The semiconductor chips 61a-64a, 61b-64b, and 61c-64c can be composed of field-effect transistors (FETs) such as MOSFETs, insulated-gate bipolar transistors (IGBTs), electrostatic induction (SI) thyristors, or gate-turn-off (GTO) thyristors. Here, we will explain the case where the semiconductor chips 61a-64a, 61b-64b, and 61c-64c are MOSFETs.

[0024] Each semiconductor chip 61a-64a, 61b-64b, and 61c-64c comprises a semiconductor substrate, a first main electrode (drain electrode) provided on the lower side of the semiconductor substrate, and a second main electrode (source electrode) and a control electrode (gate electrode) provided on the upper side of the semiconductor substrate. The semiconductor substrate is composed of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), etc. The arrangement and number of semiconductor chips 61a-64a, 61b-64b, and 61c-64c are not particularly limited.

[0025] Figure 1 illustrates a 6-in-1 type power semiconductor module. For example, semiconductor chips 61a and 62a constitute the lower arm of the U phase of a 3-phase inverter circuit, and semiconductor chips 63a and 64a constitute the upper arm of the U phase. Semiconductor chips 61b and 62b constitute the lower arm of the V phase, and semiconductor chips 63b and 64b constitute the upper arm of the V phase. Semiconductor chips 61c and 62c constitute the lower arm of the W phase, and semiconductor chips 63c and 64c constitute the upper arm of the W phase.

[0026] Case 1 is insert-molded to integrate plate-shaped output terminals 4a-4c, plate-shaped positive terminals 2a-2c, and plate-shaped negative terminals 3a-3c. Output terminals 4a-4c are provided on one side of each of the insulating circuit boards 6a-6c of Case 1. In Figure 1, the portions of the output terminals 4a-4c that are embedded in Case 1 and extend toward the insulating circuit boards 6a-6c, and the portions sealed by the sealing members 5a-5c are schematically shown with dashed lines.

[0027] Output terminals 4a to 4c are each provided with bolt insertion holes 4x to 4z. Positive terminal 2a and negative terminal 3a are provided on the opposite side of the insulated circuit board 6a on which output terminal 4a of case 1 is located. Positive terminal 2b and negative terminal 3b are provided on the opposite side of the insulated circuit board 6b on which output terminal 4b of case 1 is located. Positive terminal 2c and negative terminal 3c are provided on the opposite side of the insulated circuit board 6c on which output terminal 4c of case 1 is located. Copper (Cu), Cu alloy, aluminum (Al), or Al alloy can be used as materials for positive terminals 2a to 2c, negative terminals 3a to 3c, and output terminals 4a to 4c.

[0028] The positive terminal 2a is electrically connected to the drain electrodes of semiconductor chips 63a and 64a via the insulating circuit board 6a. The negative terminal 3a is electrically connected to the source electrodes of semiconductor chips 61a and 62a via the insulating circuit board 6a. The output terminal 4a is electrically connected to the drain electrodes and source electrodes of semiconductor chips 61a and 62a via the insulating circuit board 6a.

[0029] The positive terminal 2b is electrically connected to the drain electrodes of semiconductor chips 63b and 64b via the insulating circuit board 6b. The negative terminal 3b is electrically connected to the source electrodes of semiconductor chips 61b and 62b via the insulating circuit board 6b. The output terminal 4b is electrically connected to the drain electrodes and source electrodes of semiconductor chips 61b and 62b via the insulating circuit board 6b.

[0030] The positive terminal 2c is electrically connected to the drain electrodes of semiconductor chips 63c and 64c via an insulating circuit board 6c. The negative terminal 3c is electrically connected to the source electrodes of semiconductor chips 61c and 62c via an insulating circuit board 6c. The output terminal 4c is electrically connected to the drain electrodes and source electrodes of semiconductor chips 61c and 62c via an insulating circuit board 6c.

[0031] Although not shown in Figure 1, the semiconductor device according to the embodiment further includes control terminals on the periphery of the insulating circuit boards 6a to 6c for applying control signals to the gate electrodes of the semiconductor chips 61a to 64a, 61b to 64b, and 61c to 64c. Furthermore, the semiconductor device according to the embodiment may further include current detection terminals on the periphery of the insulating circuit boards 6a to 6c for detecting the current flowing through the source electrodes of the semiconductor chips 61a to 64a, 61b to 64b, and 61c to 64c.

[0032] The lower surfaces of Case 1 and the insulating circuit boards 6a to 6c are joined to a heat dissipation base 10, which serves as a cooler made of a metal such as copper (Cu), via a bonding layer such as solder. Suitable materials for the heat dissipation base 10 include materials with high thermal conductivity such as copper (Cu), aluminum (Al), a composite material of Al and silicon carbide (AlSiC), and a composite material of magnesium (Mg) and silicon carbide (MgSiC). The lower surface of the heat dissipation base 10 is joined to a heat dissipation fin (not shown) made of a metal such as copper (Cu) via a thermal compound. Alternatively, the heat dissipation fin may be integrally formed on the lower surface of the heat dissipation base 10.

[0033] Figure 2 shows the equivalent circuit of the semiconductor device according to the embodiment shown in Figure 1. As shown in Figure 2, the semiconductor device according to the embodiment constitutes a three-phase bridge circuit. The drain electrode of transistor T1 on the upper arm side is connected to the positive terminal P1, and the source electrode of transistor T2 on the lower arm side is connected to the negative terminal N1. The source electrode of transistor T1 and the drain electrode of transistor T2 are connected to the output terminal U. The drain electrode of transistor T3 on the upper arm side is connected to the positive terminal P2, and the source electrode of transistor T4 on the lower arm side is connected to the negative terminal N2. The source electrode of transistor T3 and the drain electrode of transistor T4 are connected to the output terminal V. The drain electrode of transistor T5 on the upper arm side is connected to the positive terminal P3, and the source electrode of transistor T6 on the lower arm side is connected to the negative terminal N3. The source electrode of transistor T5 and the drain electrode of transistor T6 are connected to the output terminal W.

[0034] The output terminals U, V, and W shown in Figure 2 correspond to the output terminals 4a to 4c shown in Figure 1. The positive terminals P1 to P3 shown in Figure 2 correspond to the positive terminals 2a to 2c shown in Figure 1. The negative terminals N1 to N3 shown in Figure 2 correspond to the negative terminals 3a to 3c shown in Figure 1. The transistors T1 and T2 shown in Figure 2 correspond to the semiconductor chips 63a, 64a and 61a, 62a shown in Figure 1. The transistors T3 and T4 shown in Figure 2 correspond to the semiconductor chips 63b, 64b and 61b, 62b shown in Figure 1. The transistors T5 and T6 shown in Figure 2 correspond to the semiconductor chips 63c, 64c and 61c, 62c shown in Figure 1.

[0035] As shown in Figure 1, resin nut covers (nut gloves) 7a and 7b are provided on the lower surface of the output terminals 4a and 4b where the bolt insertion holes 4x and 4y are located. Figure 3 is a perspective view of the nut covers 7a and 7b and the output terminals 4a and 4b, with the case 1 not shown. Figure 4 is a cross-sectional view taken along line AA, which passes through the location of the bolt insertion hole 4x of the output terminal 4a in Figure 1. Figure 5 is a plan view of the nut cover 7a and the output terminal 4a as seen from the lower surface, with the case 1 not shown.

[0036] As shown in Figures 1, 3, and 4, the output terminal 4a has a Z-shaped bend when viewed from the side. The output terminal 4a has one main surface (top surface) and the other main surface (bottom surface), and has one end that is electrically connected to the drain electrode and source electrode of the semiconductor chips 61a and 62a, and the other end that is provided with a bolt insertion hole 4x. The output terminal 4a has an external connection portion 41 that extends in a substantially horizontal direction, a vertical portion 42 that is connected to the external connection portion 41 via a bent portion and extends in a direction perpendicular to the extension direction of the external connection portion 41 (substantially vertical direction), and an internal connection portion 43 that is connected to the vertical portion 42 via a bent portion and extends in a substantially horizontal direction.

[0037] The external connection portion 41 corresponds to the other end where a bolt insertion hole 4x is provided. As shown in Figure 4, the external connection portion 41 is provided with a bolt insertion hole 4x into which a bolt is inserted. The internal connection portion 43 corresponds to one end that is electrically connected to the drain electrode and the source electrode of the semiconductor chips 61a and 62a. The internal connection portion 43 extends toward the inside of the case 1 and is joined to the insulating circuit board 6a via a bonding layer such as solder.

[0038] As shown in Figure 4, a nut 9a is positioned on the lower surface of the external connection portion 41 of the output terminal 4a. The nut 9a has a threaded hole that communicates with the bolt insertion hole 4x of the external connection portion 41. A bolt is fastened through the threaded hole of the nut 9a, with a conductive material such as a busbar extending from an electronic device such as an inverter in between.

[0039] As shown in Figures 3 to 5, a nut cover 7a with a nut 9a fitted onto it is positioned on the lower surface of the external connection portion 41 of the output terminal 4a. The nut cover 7a can be made of resin materials such as polyphenylene sulfide (PPS), polybutylene terephthalate (PBT), polybutylene succinate (PBS), epoxy, or phenol. The nut cover 7a may be made of the same material as the case 1, or it may be made of a different material. The nut cover 7a has a hole (recess) into which the nut 9a is fitted, a covering portion 71a that covers the nut 9a fitted into the hole, and a protruding portion (lateral protrusion) 72a that protrudes laterally from the lower part of the covering portion 71a.

[0040] As shown in Figures 3 to 5, the covering portion 71a has a substantially rectangular parallelepiped shape. The side surface 71x of the covering portion 71a faces the vertical portion 42 of the output terminal 4a. Figures 3 to 5 illustrate the case where the side surface 71x of the covering portion 71a is spaced apart from the vertical portion 42 of the output terminal 4a, but the side surface 71x of the covering portion 71a may be in contact with the vertical portion 42 of the output terminal 4a.

[0041] As shown in Figures 3 to 5, the lateral projection 72a is provided to extend inward into the case 1, that is, toward the internal connection portion 43 of the output terminal 4a. The lateral projection 72a extends to a position below the internal connection portion 43 of the output terminal 4a, opposite the internal connection portion 43, and has a portion that overlaps with the internal connection portion 43 in a perpendicular direction.

[0042] As shown in Figure 4, the nut cover 7a is covered by the case 1. The case 1 is provided to cover the lower surface of the covering portion 71a, the lower surface of the lateral projection 72a, the side surface of the tip of the lateral projection 72a, and a portion of the lower surface of the internal connection portion 43. The resin of the case 1 also extends between the upper surface of the lateral projection 72a and the internal connection portion 43, and between the side surface 71x and the vertical portion 42 of the covering portion 71a. The side surface 71y of the covering portion 71a opposite to the side surface 71x is exposed from the side surface of the case 1. The portion of the nut cover 7 that is in contact with the case 1 may be textured. Textured nut cover 7 can increase the bonding strength between the resin of the nut cover 7 and the resin of the case 1.

[0043] The nut cover 7b shown in Figure 3 has the same structure as the nut cover 7a. As shown in Figure 3, the nut cover 7b is provided on the lower surface of the bolt insertion hole 4y (see Figure 1) of the output terminal 4b. The nut covers 7a and 7b are spaced apart from each other along the direction in which the output terminals 4a and 4b are aligned. The nut cover 7b has a covering portion 71b that covers a nut (not shown) and a lateral projection portion 72b that protrudes laterally from the lower part of the covering portion 71b. The lateral projection portion 72b of the nut cover 7b extends parallel to the lateral projection portion 72a of the nut cover 7a.

[0044] Although not shown in the illustration, a nut cover similar to nut covers 7a and 7b is also provided on the underside of the bolt insertion hole 4z of the output terminal 4c shown in Figure 1.

[0045] Here, a semiconductor device relating to the comparative example will be described. Figure 6 is a perspective view of the semiconductor device relating to the comparative example, corresponding to Figure 3, and Figure 7 is a cross-sectional view of the semiconductor device relating to the comparative example, corresponding to Figure 4. As shown in Figures 6 and 7, the semiconductor device relating to the comparative example differs from the semiconductor device according to the embodiment shown in Figures 3 to 5 in that it does not have lateral protrusions at the lower part of the nut covers 7a and 7b.

[0046] In the semiconductor device relating to the comparative example, as shown in Figure 7, since there is no lateral protrusion on the side surface of the covering portion 71a of the nut cover 7a, a portion of the case 1 is molded in the area A below the internal connection portion 43 of the output terminal 4a during secondary molding. However, if the case 1 to be secondary molded has a thick portion like area A, when the resin shrinks from a high temperature to a low temperature after the resin has been poured into the mold, the amount of shrinkage is greater in the thick portion, making it easy for cavities to form in the thick portion. In addition, when pouring the resin into the mold, air bubbles tend to remain due to the poor fluidity of the resin.

[0047] In contrast, according to the semiconductor device according to the embodiment, as shown in Figures 3 to 5, by providing a lateral projection 72a at the lower part of the covering portion 71a of the nut cover 7a, the volume of resin during the molding of the nut cover 7a by primary molding can be increased. As a result, because there is a solid lateral projection 72a in the secondary casting, the thickness of the lower part of the internal connection portion 43 of the output terminal 4a can be reduced, and resin shrinkage can be reduced. Therefore, the occurrence of cavities in the region below the internal connection portion 43 can be suppressed.

[0048] Furthermore, by providing the lateral projection 72a on the nut cover 7a, the strength against rotational stress generated when tightening the nut 9a with a bolt can be improved, and the rotation of the nut cover 7a can be suppressed.

[0049] <Manufacturing method for semiconductor devices> Next, an example of a method for manufacturing a semiconductor device according to the embodiment will be described with reference to Figures 1, 3 to 5. First, in primary molding, a resin primary molded body (nut cover) 7a shown in Figures 3 to 5 is molded by filling a mold with resin material. The nut cover 7a has a covering portion 71a in which a hole (recess) into which a nut 9a is fitted is formed, and a lateral projection portion 72a that protrudes laterally from the lower part of the covering portion 71a. Then, the nut 9a is fitted into the hole formed in the molded nut cover 7a. Although not shown, the nut cover 7b that is joined to the output terminal 4b and the nut cover that is joined to the output terminal 4c shown in Figure 1 are molded in the same way as the nut cover 7a, and nuts are fitted into them.

[0050] Next, as shown in Figure 1, plate-shaped output terminals 4a-4c, positive terminals 2a-2c, and negative terminals 3a-3c, which have been bent into a predetermined shape using a press or the like, are attached to a mold. Furthermore, a nut cover 7a with a nut 9a fitted onto it is attached to the mold. At this time, the nut cover 7a with the nut 9a fitted onto it is positioned so that the covering portion 71a contacts the outer surface of the external connection portion 41 of the output terminal 4a, and the lateral projection portion 72a protrudes toward the internal connection portion 43 of the output terminal 4a. Below the output terminal 4b shown in Figure 1, a nut cover 7b with a nut fitted onto it is positioned. Below the output terminal 4c, a nut cover with a nut fitted onto it, similar to nut covers 7a and 7b, is positioned.

[0051] Then, through secondary molding, resin material is filled into the mold, and as shown in Figure 1, the case 1 (secondary molded body) is insert-molded to integrate the nut covers 7a, 7b, positive terminals 2a-2c, negative terminals 3a-3c, and output terminals 4a-4c.

[0052] Next, as shown in Figure 1, semiconductor chips 61a-64a, 61b-64b, and 61c-64c are bonded to the insulating circuit boards 6a-6c via a bonding layer such as solder. Then, the insulating circuit boards 6a-6c, on which the semiconductor chips 61a-64a, 61b-64b, and 61c-64c are bonded, are bonded to the heat dissipation base 10 via a bonding layer such as solder, and the case 1 is bonded to the heat dissipation base 10 with adhesive so as to surround the insulating circuit boards 6a-6c. At this time, the positive terminals 2a-2c, negative terminals 3a-3c, and output terminals 4a-4c, which are integrated with the case 1, are bonded to the insulating circuit boards 6a-6c by ultrasonic bonding or the like.

[0053] Next, the source electrodes on the upper surfaces of semiconductor chips 61a-64a, 61b-64b, and 61c-64c are electrically connected to the positive terminals 2a-2c, negative terminals 3a-3c, and output terminals 4a-4c via lead frames or the like. In addition, the gate electrodes on the upper surfaces of semiconductor chips 61a-64a, 61b-64b, and 61c-64c are electrically connected to control terminals or the like (not shown) via wire bonding of aluminum (Al) or the like.

[0054] Next, as shown in Figure 1, the areas partitioned by case 1—the area where the insulating circuit board 6a and semiconductor chips 61a to 64a are located, the area where the insulating circuit board 6b and semiconductor chips 61b to 64b are located, and the area where the insulating circuit board 6c and semiconductor chips 61c to 64c are located—are sealed with sealing members 5a to 5c, respectively. In this way, the semiconductor device according to the embodiment is completed.

[0055] According to the semiconductor device of this embodiment, when forming the nut covers 7a and 7b by primary molding, the volume of resin during primary molding can be increased by forming lateral protrusions 72a and 72b at the lower part of the covering portions 71a and 71b of the nut covers 7a and 7b. Therefore, during secondary molding, the space can be filled by placing the primary molded lateral protrusions 72a and 72b in the thicker parts, thereby suppressing the occurrence of cavities during molding of the case 1 and the resulting indentations on the surface of the secondary molded product due to the shrinkage of cavities.

[0056] (Other embodiments) As described above, the present invention has been described by embodiments, but the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0057] For example, a 6-in-1 semiconductor module was given as an example of a semiconductor device according to the embodiment, but it is not limited to this. For example, a 1-in-1 or 2-in-1 semiconductor module may also be used.

[0058] Furthermore, the configurations disclosed in the embodiments can be combined as appropriate, within a non-contradictory scope. Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable based on the above description. [Explanation of Symbols]

[0059] 1…Case 2a~2c…Positive terminal 3a~3c…Negative terminal 4a~4c...Output terminals 4x~4z…Bolt insertion holes 5a~5c...Sealing member 6a~6c...Insulated circuit board 7a, 7b... Nut cover 9a... Nut 10…Heat dissipation base 41…External connection section 42...Vertical part 43...Internal connection section 61a~64a, 61b~64b, 61c~64c... Power semiconductor devices (semiconductor chips) 71a, 71b... Covering part 71x,71y…side 72a, 72b...lateral protrusion N1~N3…Negative terminal P1~P3... Positive terminals T1~T6... Transistors U, V, W… Output terminals

Claims

1. A plate-shaped terminal having one main surface and the other main surface, with one end electrically connected to a semiconductor chip and the other end having a bolt insertion hole, A nut positioned on the main surface side of the other end of the terminal, A nut cover is provided on the main surface side of the other end of the terminal, covering the nut. A case that surrounds the semiconductor chip and integrates the terminals and the nut cover, Equipped with, A semiconductor device characterized in that the nut cover has a covering portion that covers the nut and a lateral projection portion that protrudes laterally from the covering portion toward one end of the terminal.

2. The aforementioned terminals An external connection part corresponding to the other end, A vertical section connected to the external connection section, Connected to the vertical section, and having an internal connection section corresponding to one end, The semiconductor device according to claim 1, characterized by being equipped with the following features.

3. A plate-shaped terminal having one main surface and the other main surface, with one end electrically connected to a semiconductor chip and the other end having a bolt insertion hole, A nut positioned on the main surface side of the other end of the terminal, A nut cover is provided on the main surface side of the other end of the terminal, covering the nut. A case that surrounds the semiconductor chip and integrates the terminals and the nut cover, Equipped with, The nut cover has a protrusion that extends toward one end of the terminal, The aforementioned terminals An external connection part corresponding to the other end, A vertical section connected to the external connection section, Connected to the vertical section, and having an internal connection section corresponding to one end, Equipped with, The protruding portion extends to a position opposite the internal connection portion. A semiconductor device characterized by the following features.

4. Multiple of the aforementioned terminals are provided in parallel, The nut cover is provided on one of the main surfaces of each of the plurality of terminals. The semiconductor device according to any one of claims 1 to 3.

5. A step of molding a nut cover having a covering portion in which a hole for a nut is fitted and a protruding portion that protrudes from the covering portion, The process of fitting the nut onto the covering portion, A step of placing a plate-shaped terminal, having one main surface and the other main surface, with one end electrically connected to a semiconductor chip and the other end having a bolt insertion hole, into a mold; A step of positioning the nut cover, into which the nut is fitted, on one main surface side of the other end of the terminal such that the protruding portion protrudes toward the one end of the terminal, A step of forming a case that integrates the terminal and the nut cover, A method for manufacturing a semiconductor device, characterized by including [the necessary components].

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