Power converter

Abstract

To provide a power converter in which the size of a capacitor is downsized.SOLUTION: An inverter circuit 100 includes: a P bus bar connected to a higher potential side terminal P of a battery 200; an N bus bar connected to a lower potential side terminal N; and an M bus bar as the middle point between the P bus bar and the N bus bar. The inverter circuit 100 includes: a PM capacitor 30 connected to the P bus bar and the M bus bar; an MN capacitor 40 connected to the M bus bar and the N bus bar; and a PN capacitor 50 connected to the P bus bar and the N bus bar.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a power conversion device.

Background Art

[0002] Conventionally, as an example of a multilevel inverter, there is a power conversion device disclosed in Patent Document 1. The power conversion device includes two smoothing capacitors connected in series.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The power conversion device is provided with two smoothing capacitors for the purpose of suppressing the allowable voltage fluctuation at the midpoint between the two smoothing capacitors and reducing the current ripple flowing out to the outside of the power conversion device. However, the power conversion device requires a large capacitor capacitance to reduce the current ripple. Therefore For For, the power conversion device has a problem that the size of the smoothing capacitor becomes large. Further, from the above viewpoints or other viewpoints not mentioned, further improvement of the power conversion device is required.

[0005] One object of the disclosure is to provide a power conversion device with a reduced size of the capacitor.

Means for Solving the Problems

[0006] The power conversion device disclosed herein is a power conversion device that divides an input DC voltage into a plurality of values and can output voltages of a plurality of levels, a high - potential wiring (71) connected to the positive electrode of the power supply, Low-potential wiring (72) connected to the negative terminal of the power supply, At least one midpoint wiring (73) that is at a potential between the high-potential wiring and the low-potential wiring, A first capacitor (30) connected to the high-potential wiring and the midpoint wiring, A second capacitor (40) connected to the midpoint wiring and the low-potential wiring, The system comprises at least one third capacitor (50) connected to high-potential wiring and low-potential wiring. 、 Multiple semiconductor devices (10, 20) including switching elements connected to high-potential wiring, low-potential wiring, and midpoint wiring, The device further includes a cooler (90) for cooling the semiconductor device, The first and second capacitors are positioned closer to the cooler than the third capacitor. It is characterized by having this feature.

[0007] The power converter disclosed herein is provided with at least one third capacitor connected to high-potential wiring and low-potential wiring. Therefore, the power converter can reduce the total capacitance of the first capacitor, second capacitor, and third capacitor. Thus, the power converter can reduce the size of the first capacitor, second capacitor, and third capacitor.

[0008] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing the schematic configuration of the inverter circuit in the first embodiment. [Figure 2] This is a cross-sectional view showing the schematic configuration of the inverter circuit. [Figure 3] This is a cross-sectional view along line III-III in Figure 2. [Figure 4] This is a plan view from the direction of arrow IV in Figure 2. [Figure 5] It is a perspective view showing the arrangement of the capacitor device. [Figure 6] It is a perspective view showing the arrangement of the capacitor device in the second embodiment. [Figure 7] It is a cross-sectional view showing the schematic configuration of the inverter circuit in the third embodiment. [Figure 8] It is a cross-sectional view showing the schematic configuration of the inverter circuit in the fourth embodiment. [Figure 9] It is a cross-sectional view showing the schematic configuration of the inverter circuit in the fifth embodiment. [Figure 10] It is a cross-sectional view showing the schematic configuration of the inverter circuit in the sixth embodiment.

Modes for Carrying Out the Invention

[0010] Hereinafter, a plurality of modes for implementing the present disclosure will be described with reference to the drawings. In each mode, the same reference numerals may be assigned to the parts corresponding to those described in the preceding mode, and redundant descriptions may be omitted. In each mode, when only a part of the configuration is described, other parts of the configuration can be referred to and applied to other modes described previously.

[0011] (First Embodiment) The inverter circuit 100 of the first embodiment will be described with reference to FIGS. 1 to 5. The inverter circuit 100 is configured to divide an input DC voltage into a plurality of values and output voltages of a plurality of levels. The inverter circuit 100 is a so-called multilevel inverter. A multilevel inverter can output voltages of three levels or more, while a two-level inverter can output voltages of +E, -E, 0, and two levels other than 0 when the voltage of the battery 200 is E. In this embodiment, as an example, a three-level inverter circuit 100 is adopted.

[0012] The inverter circuit 100 can be mounted on a moving body such as a vehicle or an aircraft. As shown in FIG. 1, the inverter circuit 100 is electrically connected to the battery 200 and the motor 300. The motor 300 is a three-phase motor including a U-phase coil 301, a V-phase coil 302, and a W-phase coil 303. The motor 300 can employ, for example, a motor generator or the like. The inverter circuit 100 converts the DC power output from the battery 200 into three-phase AC power and supplies the three-phase AC power to the motor 300. The inverter circuit 100 corresponds to a power conversion device.

[0013] <Circuit Configuration of Inverter Circuit 100> The circuit configuration of the inverter circuit 100 will be described with reference to FIG. 1. The inverter circuit 100 includes switching elements 11 to 16, a U-phase middle section 21, a V-phase middle section 22, a W-phase middle section 23, a capacitor device 60, and the like. In FIG. 1, the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 included in the capacitor device 60 are illustrated.

[0014] The switching elements 11 to 16 can employ MOSFETs, IGBTs, or the like. Further, the switching elements 11 to 16 can employ those mainly composed of a wide bandgap semiconductor such as Si or SiC. The gate electrodes of the switching elements 11 to 16 are connected to an electronic control device (not shown). And the switching elements 11 to 16 are driven and controlled by the electronic control device.

[0015] The switching elements 11 to 16 include a U-phase upper arm element 11, a U-phase lower arm element 12, a V-phase upper arm element 13, a V-phase lower arm element 14, a W-phase upper arm element 15, and a W-phase lower arm element 16.

[0016] The U-phase upper arm element 11 and the U-phase lower arm element 12 are connected in series between the high-potential terminal (P) and the low-potential terminal (N) of the battery 200. The source terminal of the U-phase upper arm element 11 and the drain terminal of the U-phase lower arm element 12 are connected to the U-phase coil 301. The U-phase upper arm element 11 and the U-phase lower arm element 12 can be collectively referred to as the U-phase arm.

[0017] The V-phase upper arm element 13 and the V-phase lower arm element 14 are connected in series between the high-potential terminal and the low-potential terminal of the battery 200. The source terminal of the V-phase upper arm element 13 and the drain terminal of the V-phase lower arm element 14 are connected to the V-phase coil 302. The V-phase upper arm element 13 and the V-phase lower arm element 14 can be collectively referred to as the V-phase arm.

[0018] The W-phase upper arm element 15 and the W-phase lower arm element 16 are connected in series between the high-potential terminal and the low-potential terminal of the battery 200. The source terminal of the W-phase upper arm element 15 and the drain terminal of the W-phase lower arm element 16 are connected to the W-phase coil 303. The W-phase upper arm element 15 and the W-phase lower arm element 16 together can also be called the V-phase arm.

[0019] As described above, each arm is connected in series between the P busbar 71 and the N busbar 72, which will be explained later. Regarding the structure of the switching elements 11-16, the battery 200, which will be explained later, corresponds to the power source. The high-potential terminal corresponds to the positive electrode. The low-potential terminal corresponds to the negative electrode.

[0020] The U-phase middle section 21, V-phase middle section 22, and W-phase middle section 23 are connected to the midpoint (neutral point) M between high potential and low potential and to each arm. Each middle section 21-23 contains two switching elements. The switching elements can be the same as those used for the switching elements 11-16 described above. The gate electrodes of the switching elements are connected to an electronic control unit. The switching elements are driven and controlled by the electronic control unit. The midpoint M can be described as the point of intermediate potential between high potential and low potential. Furthermore, the midpoint M is located between the PM capacitor 30 and the MN capacitor 40.

[0021] The U-phase middle section 21 includes a first U-phase middle element 21a and a second U-phase middle element 21b as switching elements. The drain terminal of the first U-phase middle element 21a is connected to the midpoint M, and its source terminal is connected to the source terminal of the second U-phase middle element 21b. The drain terminal of the second U-phase middle element 21b is connected to the source terminal of the U-phase upper arm element 11 and the drain terminal of the U-phase lower arm element 12.

[0022] The V-phase middle section 22 includes a first V-phase middle element 22a and a second V-phase middle element 22b as switching elements. The drain terminal of the first V-phase middle element 22a is connected to the midpoint M, and its source terminal is connected to the source terminal of the second V-phase middle element 22b. The drain terminal of the second V-phase middle element 22b is connected to the source terminal of the V-phase upper arm element 13 and the drain terminal of the V-phase lower arm element 14.

[0023] The W-phase middle section 23 includes a first W-phase middle element 23a and a second W-phase middle element 23b as switching elements. The drain terminal of the first W-phase middle element 23a is connected to the midpoint M, and its source terminal is connected to the source terminal of the second W-phase middle element 23b. The drain terminal of the second W-phase middle element 23b is connected to the source terminal of the W-phase upper arm element 15 and the drain terminal of the W-phase lower arm element 16. The structures of the U-phase middle section 21, V-phase middle section 22, and W-phase middle section 23 will be explained later.

[0024] The capacitor device 60 includes a PM capacitor 30, an MN capacitor 40, and a PN capacitor 50 as smoothing capacitors. The PM capacitor 30 is connected to the high-potential terminal and the midpoint M. The MN capacitor 40 is connected to the midpoint M and the low-potential terminal. Therefore, the PM capacitor 30 and the MN capacitor 40 are connected in series.

[0025] The PM capacitor 30 and the MN capacitor 40 are primarily provided for voltage stabilization and current ripple absorption. In other words, the PM capacitor 30 and the MN capacitor 40 are provided to suppress the allowable voltage fluctuation at the midpoint M and to reduce the current ripple flowing out of the inverter circuit 100. The PM capacitor 30 corresponds to the first capacitor. The MN capacitor 40 corresponds to the second capacitor.

[0026] The PN capacitor 50 is connected to the high-potential terminal and the low-potential terminal. Therefore, the PN capacitor 50 is connected in parallel with the PM capacitor 30 and the MN capacitor 40. The PN capacitor 50 is provided for current ripple absorption. In other words, the PN capacitor 50 is provided to reduce the current ripple that flows out of the inverter circuit 100. The PN capacitor 50 corresponds to the third capacitor.

[0027] In the inverter circuit 100, the capacitor capacitance required to suppress the allowable voltage fluctuation at the midpoint M is low, while the capacitor capacitance required to reduce the current ripple flowing to the outside is large. Therefore, the inverter circuit 100 is provided with a PN capacitor 50. This PN capacitor 50 is connected in parallel with the PM capacitor 30 and the MN capacitor 40 as described above. As a result, the inverter circuit 100 can reduce the total capacitance of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50. Thus, the inverter circuit 100 can reduce the size of the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50.

[0028] Furthermore, this disclosure is also applicable to diode clamp type (T-type) inverter circuits 100. This disclosure can also be adopted for inverter circuits 100 with N-level (N=4) or higher. In this case, the intermediate potential will be N-2. The number of PN capacitors 50 will be N-1.

[0029] <Structure of Inverter Circuit 100> The structure of the inverter circuit 100 will be explained using Figures 2 to 5. The inverter circuit 100 consists of a capacitor device 60 and a structure in which semiconductor devices 10, 20 and a cooler 90 are integrally assembled, arranged side by side. In the drawings, the direction of arrangement of the capacitor device 60 and the structure is indicated by arrows A and D. Note that in Figure 5, the busbars 71 to 73 and insulating members 80 are omitted from the illustration. The same applies to Figure 6, which will be explained later.

[0030] Furthermore, as shown in Figures 2 and 3, the inverter circuit 100 includes busbars 71 to 74 that connect each capacitor 30 to 50 to each semiconductor device 10 and 20. The busbars 71 to 74 are conductive materials mainly composed of copper or the like. The busbars 71 to 74 are flat plate-shaped materials.

[0031] The P busbar 71 is connected to the high-potential terminal. Any terminal connected to the high-potential terminal is connected to the P busbar 71. The P busbar 71 corresponds to the high-potential wiring.

[0032] N-busbar 72 is connected to the low-potential side terminal. N-busbar 72 corresponds to the low-potential wiring. Terminals connected to the low-potential side terminal are connected to N-busbar 72.

[0033] The M busbar 73 constitutes the midpoint M. The potential of the M busbar 73 is between that of the P busbar 71 and the N busbar 72. The M busbar 73 is connected to the PM capacitor 30 and the MN capacitor 40. The terminal connected to the midpoint M is connected to the M busbar 73. The M busbar 73 corresponds to the midpoint wiring.

[0034] The O busbar 74 is an output terminal. The inverter circuit 100 is equipped with the O busbar 74 connected to the U-phase coil 301, the V-phase coil 302, and the W-phase coil 303, respectively.

[0035] In this embodiment, as an example, an example is adopted in which insulating members 80 are provided to electrically insulate the components from each other. The insulating members 80 are provided between the P busbar 71 and the M busbar 73, and between each busbar 71, 73 and the PM capacitor 30. In addition, the insulating members 80 are provided between the M busbar 73 and the N busbar 72, and between each busbar 72, 73 and the MN capacitor 40. However, if electrical insulation is possible, it is not necessary to provide the insulating members 80.

[0036] The semiconductor devices 10 and 20 are, for example, two bare-chip-shaped switching elements connected together and covered with an electrically insulating sealing resin. Furthermore, as shown in Figures 2 and 4, the semiconductor devices 10 and 20 have terminals 1 to 5 that protrude from the sealing resin. The inverter circuit 100 comprises multiple semiconductor devices 10 and multiple semiconductor devices 20. Each semiconductor device 10 and 20 is arranged side-by-side and assembled to a cooler 90. Note that in Figure 4, the cooler 90 is omitted for simplification of the drawing.

[0037] The inverter circuit 100 comprises three semiconductor devices 10 that constitute each arm. The semiconductor device 10 for the U-phase arm comprises a U-phase upper arm element 11 and a U-phase lower arm element 12. The semiconductor device 10 for the V-phase arm comprises a V-phase upper arm element 13 and a V-phase lower arm element 14. The semiconductor device 10 for the W-phase arm comprises a W-phase upper arm element 15 and a W-phase lower arm element 16. The semiconductor device 10 also comprises a P terminal 1, an N terminal 2, an O terminal 3, and a signal terminal 5. The semiconductor device 10 can also be called an arm device.

[0038] The inverter circuit 100 includes three semiconductor devices 20 that constitute each of the middle sections 21 to 23. The semiconductor device 20 of the U-phase middle section 21 includes a first U-phase middle element 21a and a second U-phase middle element 21b. The semiconductor device 20 of the V-phase middle section 22 includes a first V-phase middle element 22a and a second V-phase middle element 22b. The semiconductor device 20 of the W-phase middle section 23 includes a first W-phase middle element 23a and a second W-phase middle element 23b. The semiconductor device 20 also includes an O terminal 3, an M terminal 4, and a signal terminal 5. The semiconductor device 20 can also be called a middle device.

[0039] As shown in Figure 4, terminal P 1 is connected to busbar P 71. Terminal N 2 is connected to busbar N 72. Terminal O 3 is connected to busbar O 74. Terminal M 4 is connected to busbar M 73. As shown in Figure 2, signal terminal 5 is connected to the wiring board 110. The wiring board 110 is a board on which conductive wiring is provided on an insulating substrate such as resin. The wiring board 110 is connected to the electronic control unit.

[0040] The cooler 90 is configured to circulate a coolant such as water in order to cool each semiconductor device 10, 20. The cooler 90 sandwiches each semiconductor device 10, 20 between the parts through which the coolant flows.

[0041] Therefore, the connection points of busbars 71-74 to terminals 1-4 are positioned close to the cooler 90. Also, as described above, busbars 71-74 are connected to terminals 1-4 of semiconductor devices 10 and 20, which are cooled by the cooler 90. Therefore, busbars 71-74 are cooled by the cooler 90 together with semiconductor devices 10 and 20. It can also be said that busbars 71-73 have one end connected to the structure and the other end connected to the capacitor device 60.

[0042] As shown in Figures 2 and 3, the capacitor device 60 comprises capacitors 30 to 50, a capacitor case 61, and a sealing resin part 63. The capacitor case 61 houses each of the capacitors 30 to 50 and has an opening 62 in part. The sealing resin part 63 is provided in the capacitor case 61 with each of the capacitors 30 to 50 housed inside. In other words, the capacitor case 61 has a housing space in which each of the capacitors 30 to 50 and the sealing resin part 63 are provided. Each of the capacitors 30 to 50 is sealed by the sealing resin part 63.

[0043] Furthermore, parts of the P busbars 71, N busbars 72, and M busbars 73 are arranged inside the capacitor case 61 for connection to each of the capacitors 30 to 50. The parts of the P busbars 71, N busbars 72, and M busbars 73 that are located inside the capacitor case 61 are sealed with a sealing resin part 63. Also, as shown in Figure 3, the P busbars 71, N busbars 72, and M busbars 73 protrude from the opening 62.

[0044] Thus, the capacitor device 60 integrally holds three capacitors 30 to 50. The capacitor device 60 can also be called a capacitor structure. Furthermore, each capacitor 30 to 50 may be composed of a single capacitor element or multiple capacitor elements.

[0045] As shown in Figure 2, the PM capacitor 30 has a first PM terminal 31 and a second PM terminal 32. The first PM terminal 31 is connected to the P busbar 71. The second PM terminal 32 is connected to the M busbar 73.

[0046] The MN capacitor 40 has a first MN terminal 41 and a second MN terminal 42. The first MN terminal 41 is connected to the M busbar 73. The second MN terminal 42 is connected to the N busbar 72.

[0047] The PN capacitor 50 has a first PN terminal 51 and a second PN terminal 52. The first PN terminal 51 is connected to the P busbar 71. The second PN terminal 52 is connected to the N busbar 72.

[0048] As shown in Figure 2, the PM capacitor 30 and MN capacitor 40 are positioned closer to the cooler 90 than the PN capacitor 50. In this embodiment, as an example, the components are arranged in the order of cooler 90, PM capacitor 30 and MN capacitor 40, and PN capacitor 50 along the arrangement direction AD. Therefore, the PM capacitor 30 and MN capacitor 40 are more easily cooled by the cooler 90 than the PN capacitor 50. It can be said that the inverter circuit 100 has enhanced cooling capabilities for the PM capacitor 30 and MN capacitor 40 than for the PN capacitor 50.

[0049] Furthermore, the length of the P busbar 71 from the connection point with the structure to the connection point with the PM capacitor 30 is shorter than the length of the connection point with the structure to the connection point with the PN capacitor 50. Therefore, the PM capacitor 30 is more easily cooled than the PN capacitor 50 by the P busbar 71 which is cooled by the cooler 90.

[0050] On the other hand, the length of the N busbar 72 from the connection point with the structure to the connection point with the MN capacitor 40 is shorter than the length of the connection point with the structure to the connection point with the PN capacitor 50. Therefore, the MN capacitor 40 is more easily cooled than the PN capacitor 50 by the N busbar 72 which is cooled by the cooler 90.

[0051] Incidentally, the ripple current caused by heat generation is greater for PM capacitors 30 and MN capacitors 40 than for PN capacitor 50. Therefore, in this disclosure, PM capacitors 30 and MN capacitors 40 are placed closer to the cooler 90 than PN capacitor 50. As a result, the inverter circuit 100 can suppress the heat generated by PM capacitors 30 and MN capacitors 40. Thus, the inverter circuit 100 can increase the allowable current of PM capacitors 30 and MN capacitors 40. In other words, the inverter circuit 100 can increase the allowable current compared to a configuration where PN capacitor 50 is closer to the cooler 90 than PM capacitors 30 and MN capacitors 40. Note that the positional relationship between the cooler 90 and each capacitor 30-50 described above can also be applied to other embodiments.

[0052] The P busbar 71 and N busbar 72 may have higher thermal conductivity in the parts connected to the PM capacitor 30 and MN capacitor 40 than in the parts connected to the PN capacitor 50. For example, the part connected to the PN capacitor 50 may be mainly composed of copper, while the parts connected to the PM capacitor 30 and MN capacitor 40 may be mainly composed of silver. This also allows the inverter circuit 100 to increase the allowable current of the PM capacitor 30 and MN capacitor 40.

[0053] Furthermore, as shown in Figures 2 and 5, the PM capacitor 30 and the MN capacitor 40 are stacked in a direction intersecting the alignment direction A. In this embodiment, as an example, the PM capacitor 30 and the MN capacitor 40 are stacked in a direction perpendicular to the alignment direction A.

[0054] More specifically, the PM capacitor 30 and the MN capacitor 40 are stacked so that the second PM terminal 32 of the PM capacitor 30 and the first MN terminal 41 of the MN capacitor 40 face each other. A portion of the M busbar 73 is positioned between the PM capacitor 30 and the MN capacitor 40. Therefore, the second PM terminal 32 and the first MN terminal 41 are connected to the same M busbar 73.

[0055] Therefore, the inverter circuit 100 can be made smaller in size along the alignment direction AD than in a configuration where the PM capacitor 30 and MN capacitor 40 are arranged along the alignment direction AD. It can also be said that the inverter circuit 100 can be made smaller in size in the direction perpendicular to the stacking direction of the PM capacitor 30 and MN capacitor 40. The PN capacitor 50 is arranged along the alignment direction AD with respect to the PM capacitor 30 and MN capacitor 40. It can also be said that the PM capacitor 30 and MN capacitor 40 are stacked in the thickness direction of both capacitors 30 and 40. Furthermore, it can simply be said that the PM capacitor 30 and MN capacitor 40 are stacked.

[0056] In this embodiment, as an example, capacitors 30 to 50 arranged as described above are used. However, this disclosure is not limited thereto.

[0057] Preferred embodiments of the present disclosure have been described above. However, the present disclosure is not limited to the above embodiments, and various modifications are possible without departing from the spirit of the present disclosure. Other forms of the present disclosure, namely second to sixth embodiments, are described below.

[0058] (Second Embodiment) The inverter circuit 100 of the second embodiment will be described with reference to Figure 6. In this embodiment, the differences from the first embodiment will be mainly described. In this embodiment, the positional relationship between the PM capacitor 30 and the MN capacitor 40 is different from that of the first embodiment.

[0059] The PM capacitor 30 and the MN capacitor 40 are arranged in parallel. The first PM terminal 31 and the first MN terminal 41 of the PM capacitor 30 and the MN capacitor 40 are located on the same virtual plane. The second PM terminal 32 and the second MN terminal 42 of the PM capacitor 30 and the MN capacitor 40 are located on different virtual planes.

[0060] Therefore, the inverter circuit 100 can be made smaller in the direction perpendicular to the capacitor arrangement direction of the PM capacitor 30 and MN capacitor 40 compared to a configuration in which both capacitors 30 and 40 are stacked. Also, the inverter circuit 100 can be made smaller in the size of each capacitor 30 to 50, similar to the first embodiment. Note that the PN capacitor 50 is arranged in parallel with both the PM capacitor 30 and the MN capacitor 40. The first PN terminal 51 is arranged on the same virtual plane as the first PM terminal 31 and the first MN terminal 41. The second PN terminal 52 is arranged on the same virtual plane as the second PM terminal 32 and the second MN terminal 42.

[0061] (Third embodiment) The inverter circuit 100 of the third embodiment will be described with reference to Figure 7. In this embodiment, the differences from the first embodiment will be mainly described. In this embodiment, the positional relationship between the PM capacitor 30 and the MN capacitor 40 differs from that of the first embodiment. The PM capacitor 30 and the MN capacitor 40 are arranged offset in the alignment direction A and D. Similar to the first embodiment, the inverter circuit 100 allows for miniaturization of the size of each capacitor 30 to 50.

[0062] (Fourth Embodiment) The inverter circuit 100 of the fourth embodiment will be described with reference to Figure 8. In this embodiment, the differences from the second embodiment will be mainly described. In this embodiment, the positional relationship of the PN capacitor 50 with respect to the PM capacitor 30 and the MN capacitor 40 is different from that of the second embodiment.

[0063] The PN capacitor 50 is arranged in parallel with the PM capacitor 30 and the MN capacitor 40. In other words, the PM capacitor 30, the MN capacitor 40, and the PN capacitor 50 are arranged in a straight line.

[0064] Therefore, the inverter circuit 100 can be made smaller in the direction perpendicular to the capacitor arrangement direction of the capacitors 30 to 50 compared to a configuration in which the capacitors 30 to 50 are stacked. Also, the inverter circuit 100 can be made smaller in the size of each capacitor 30 to 50, similar to the first embodiment.

[0065] (Fifth embodiment) The inverter circuit 100 of the fifth embodiment will be described with reference to Figure 9. In this embodiment, the differences from the first embodiment will be mainly described. In this embodiment, the positional relationship of the PN capacitor 50 with respect to the PM capacitor 30 and the MN capacitor 40 is different from that of the first embodiment.

[0066] The PN capacitor 50 is stacked together with the PM capacitor 30 and the MN capacitor 40. Furthermore, each capacitor 30-50 is positioned so that its terminals do not face each other. The first PN terminal 51 is positioned parallel to the first PM terminal 31 and the first MN terminal 41 with respect to the same virtual plane. The second PN terminal 52 is positioned parallel to the second PM terminal 32 and the second MN terminal 42 with respect to the same virtual plane. The inverter circuit 100 can reduce the size of the capacitors 30-50 in the direction perpendicular to the capacitor arrangement direction compared to a configuration where the capacitors 30-50 are arranged in parallel. Also, similar to the first embodiment, the inverter circuit 100 can reduce the size of each capacitor 30-50.

[0067] (Sixth Embodiment) The inverter circuit 100 of the sixth embodiment will be described with reference to Figure 10. In this embodiment, the differences from the first embodiment will be mainly described. In this embodiment, the configuration of the P busbar 71 and the N busbar 72 differs from that of the first embodiment.

[0068] The P busbar 71 includes a PM busbar section 71m connected to the PM capacitor 30 and a PN busbar section 71p connected to the PN capacitor 50. The N busbar 72 includes an MN busbar section 72m connected to the MN capacitor 40 and a PN busbar section 72p connected to the PN capacitor 50. The PM busbar section 71m has a larger cross-sectional area than the PN busbar section 71p. The MN busbar section 72m has a larger cross-sectional area than the PN busbar section 72p.

[0069] This also allows the inverter circuit 100 to increase the allowable current of the PM capacitor 30 and the MN capacitor 40. Furthermore, similar to the first embodiment, the inverter circuit 100 allows for miniaturization of the size of each capacitor 30 to 50.

[0070] This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, while various combinations and forms are shown in this disclosure, other combinations and forms that include one, more, or fewer of those elements also fall within the scope and idea of ​​this disclosure. [Explanation of Symbols]

[0071] 100...Inverter circuit, 1...P terminal, 2...N terminal, 3...O terminal, 4...M terminal, 5...Signal terminal, 10,20...Electronic equipment, 11~16...Switching elements, 11...U-phase upper arm element, 12...U-phase lower arm element, 13...V-phase upper arm element, 14...V-phase lower arm element, 15...W-phase upper arm element, 16...W-phase lower arm element, 21...U-phase middle section, 22...V-phase middle section, 23...W-phase middle section, 21a...1st U-phase middle element, 21b...2nd U-phase middle element, 22a...1st V-phase middle element, 22b...2nd V-phase middle element, 23a...1st W-phase middle element, 23b...2nd W-phase middle element, 30...PM capacitor, 31...1st PM terminal, 32...2nd PM terminal, 40...MN capacitor, 41...1st MN terminal, 42...2nd MN terminal, 50...PN capacitor, 51...1st PN terminal, 52...2nd PN terminal, 60...Capacitor device, 61...Capacitor case, 62...Opening, 63...Sealing resin part, 71...P busbar, 71m...PM busbar part, 71p...PN busbar part, 72...N busbar, 72m...MN busbar part, 72p...PN busbar part, 73...M busbar, 74...O busbar, 80...Insulating material, 90...Cooler, 110...Wiring board, 200...Battery, 300...Motor, 301...U-phase coil, 302...V-phase coil, 303...W-phase coil

Claims

1. A power converter capable of dividing an input DC voltage into multiple values ​​and outputting multiple levels of voltage, A high-potential wire (71) connected to the positive terminal of the power supply, A low-potential wiring (72) connected to the negative terminal of the power supply, At least one midpoint wiring (73) that is at a potential between the high-potential wiring and the low-potential wiring, A first capacitor (30) connected to the high-potential wiring and the midpoint wiring, A second capacitor (40) connected to the midpoint wiring and the low-potential wiring, The system comprises the high-potential wiring and at least one third capacitor (50) connected to the low-potential wiring, A plurality of semiconductor devices (10, 20) including switching elements connected to the high-potential wiring, the low-potential wiring, and the midpoint wiring, The semiconductor device is further provided with a cooler (90) for cooling the semiconductor device, A power conversion device in which the first capacitor and the second capacitor are located closer to the cooler than the third capacitor.

2. The power conversion device according to claim 1, wherein the cross-sectional area of ​​the high-potential wiring and the low-potential wiring at the portion connected to the third capacitor is greater than the cross-sectional area of ​​the portion connected to the first capacitor and the portion connected to the second capacitor.

3. The power conversion device according to claim 1, wherein the thermal conductivity of the high-potential wiring and the low-potential wiring is higher at the parts connected to the first capacitor and the second capacitor than at the parts connected to the third capacitor.

4. The first capacitor, the second capacitor, and the third capacitor form a capacitor device that is held integrally. The power conversion device according to claim 1, wherein the capacitor device is arranged alongside the cooler.

5. The power conversion device according to claim 4, wherein the first capacitor and the second capacitor are arranged in a stacked configuration.

6. The power conversion device according to claim 5, wherein the third capacitor is stacked together with the first capacitor and the second capacitor.

7. The power conversion device according to claim 4, wherein the first capacitor and the second capacitor are arranged in parallel.

8. The power conversion device according to claim 7, wherein the third capacitor is arranged in parallel with the first capacitor and the second capacitor.

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