Semiconductor equipment

Abstract

To provide a technique to suppress the increase of switching losses in a reverse-conduction IGBT with a boundary region between the IGBT region and the diode region.SOLUTION: A reverse-conduction IGBTs 1, 2, 3, 4 have a semiconductor substrate 10 having an IGBT region 102, a diode region 104, and a boundary region 106 located between the IGBT region 102 and the diode region 104. The semiconductor substrate 10 is provided in the boundary region 106 and has an n-type boundary layer 18, which is located below a drift layer 13 and in contact with a collector electrode 22. The n-type boundary layer 18 is in Schottky contact with the collector electrode 22.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed herein relates to semiconductor devices. [Background technology]

[0002] Development is underway on a type of semiconductor device called a reverse-conducting insulated gate bipolar transistor (IGBT). The semiconductor substrate of this type of device has an IGBT region where an IGBT structure is provided, and a diode region where a diode structure is provided. The diode structure is connected in antiparallel to the IGBT structure and can operate as a freewheeling diode during recovery.

[0003] In this type of semiconductor device, during recovery operation, holes are injected obliquely from the p-type base layer of the IGBT region towards the n-type cathode layer of the diode region. When the amount of holes injected obliquely from the p-type base layer towards the n-type cathode layer increases, the recovery current increases, and the recovery loss increases. For this reason, as disclosed in Patent Document 1, a boundary region may be provided between the IGBT region and the diode region in this type of semiconductor device. In the boundary region, the p-type collector layer is formed extending from the IGBT region. As a result, the diode structure is not configured in the boundary region, and the amount of holes injected obliquely from the p-type base layer towards the n-type cathode layer during recovery operation is suppressed. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2022-15194 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] When a p-type collector layer is provided in the boundary region, holes are injected from the p-type collector layer in the boundary region toward the n-type drift layer in the boundary region when the IGBT structure is turned on. When the IGBT structure turns off, the holes injected into the boundary region drift layer move obliquely toward the p-type base layer in the IGBT region and are discharged through the p-type base layer. As a result, the time it takes for the holes to be discharged becomes longer, and there is a concern that switching losses will increase due to an increase in tail current.

[0006] This specification provides a technique for suppressing the increase in switching loss in a reverse-conducting IGBT having a boundary region between the IGBT region and the diode region. [Means for solving the problem]

[0007] The semiconductor devices (1, 2, 3, 4) disclosed herein are of a type called a reverse-conducting IGBT and may comprise a semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, a lower electrode (22) provided on the lower surface of the semiconductor substrate, and an upper electrode (24) provided on the upper surface of the semiconductor substrate. The semiconductor substrate may include: a first conductivity type drift layer (13) provided across the IGBT region, the diode region, and the boundary region; a second conductivity type base layer (14) provided across the IGBT region, the diode region, and the boundary region and positioned above the drift layer; a first conductivity type emitter layer (15) provided in the IGBT region and positioned above the base layer and in contact with the upper electrode; a second conductivity type collector layer (11) provided in the IGBT region and positioned below the drift layer and in contact with the lower electrode; a first conductivity type cathode layer (17) provided in the diode region and positioned below the drift layer and in contact with the lower electrode; and a first conductivity type boundary layer (18) provided in the boundary region and positioned below the drift layer and in contact with the lower electrode. The first conductivity type boundary layer may be in Schottky contact with the lower electrode. Here, "located above" and "located below" specify only the positional relationship between the two semiconductor layers in the vertical direction of the semiconductor substrate. For example, the two semiconductor layers may be arranged in contact with each other, or another semiconductor layer may be interposed between the two semiconductor layers.

[0008] In the above reverse-conducting IGBT, a first-conductivity-type boundary layer that makes Schottky contact with the lower electrode is provided in the boundary region of the semiconductor substrate. The Schottky contact between the lower electrode and the first-conductivity-type boundary layer forms a barrier that hinders the recovery current. Therefore, in the above reverse-conducting IGBT, during the recovery operation, a diode structure for flowing the recovery current is not formed in the boundary region, so the amount of carriers injected obliquely from the base layer of the IGBT region toward the cathode layer of the diode region is suppressed. Further, in the above reverse-conducting IGBT, since the first-conductivity-type boundary layer is provided in the boundary region of the semiconductor substrate, when the IGBT structure in the IGBT region is on, the amount of carriers injected into the drift layer in the boundary region is suppressed. Therefore, in the above reverse-conducting IGBT, an increase in switching loss is suppressed.

Brief Description of the Drawings

[0009] [Figure 1] It is a plan view of the semiconductor device of the present embodiment, schematically showing a plan view for explaining the layout of the IGBT region, the diode region, and the boundary region. [Figure 2] It is a cross-sectional view of a main part including an IGBT region, a diode region, and a boundary region partitioned in the element region of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the II-II line in FIG. 1. [Figure 3] It is a cross-sectional view of a main part including an IGBT region, a diode region, and a boundary region partitioned in the element region of a modified example of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the II-II line in FIG. 1. [Figure 4] It is a cross-sectional view of a main part including an IGBT region, a diode region, and a boundary region partitioned in the element region of a modified example of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the II-II line in FIG. 1. [Figure 5] It is a cross-sectional view of a main part including an IGBT region, a diode region, and a boundary region partitioned in the element region of a modified example of the semiconductor device of the present embodiment, schematically showing a cross-sectional view of the main part at a position corresponding to the II-II line in FIG. 1.

Best Mode for Carrying Out the Invention

[0010] Hereinafter, the semiconductor device of this embodiment will be described with reference to the drawings. For the purpose of clear illustration, only one of the repeatedly arranged components is labeled with a reference numeral, and the labeling of the other components is omitted.

[0011] FIG. 1 schematically shows a plan view of a semiconductor device 1 according to this embodiment. The semiconductor device 1 is a type of semiconductor device called a reverse-conducting IGBT and is manufactured using a semiconductor substrate 10. The semiconductor substrate 10 has an element region 10A and a termination region 10B located around the element region 10A. The element region 10A of the semiconductor substrate 10 is divided into an IGBT region 102 provided with an IGBT structure, a diode region 104 provided with a diode structure, and a boundary region 106 located between the IGBT region 102 and the diode region 104. The IGBT region 102 and the diode region 104 are alternately and repeatedly arranged along the y direction within the element region 10A when viewed from a direction perpendicular to the upper surface of the semiconductor substrate 10 (hereinafter referred to as "when the semiconductor substrate 10 is viewed in plan"). Within the range corresponding to the termination region 10B of the semiconductor substrate 10, a termination voltage withstand structure such as a guard ring is formed. Further, a plurality of small-signal pads 26 are provided in the range corresponding to the termination region 10B on the upper surface of the semiconductor substrate 10. The small-signal pads 26 may be, for example, a gate pad for inputting a gate signal, a temperature sense pad for outputting a temperature sense signal, and a current sense pad for outputting a current sense signal.

[0012] FIG. 2 schematically shows a cross-sectional view of a main part corresponding to line II-II of FIG. 1. As shown in FIG. 2, the semiconductor device 1 includes a semiconductor substrate 10 which is a silicon substrate, a collector electrode 22 (an example of a lower electrode) provided so as to cover the lower surface of the semiconductor substrate 10, an emitter electrode 24 (an example of an upper electrode) provided so as to cover the upper surface of the semiconductor substrate 10, a plurality of trench gates 30 provided in the upper layer portion of the semiconductor substrate 10, and a plurality of dummy trench gates 40 provided in the upper layer portion of the semiconductor substrate 10.

[0013] The semiconductor substrate 10 includes a p-type collector layer 11, an n-type buffer layer 12, an n - -type drift layer 13, a p-type base layer 14, a plurality of n + -type emitter layers 15, a plurality of p + -type contact layers 16, an n + -type cathode layer 17, and an n - -type n-type boundary layer 18.

[0014] The collector layer 11 is provided in a range corresponding to the IGBT region 102 in the lower layer portion of the semiconductor substrate 10, and is provided at a position exposed on the lower surface of the semiconductor substrate 10. The collector layer 11 is in ohmic contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. The collector layer 11 is formed by ion-implanting p-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The collector layer 11 may be formed by multi-step ion implantation and may have a plurality of peak concentrations in the thickness direction of the semiconductor substrate 10. The p-type impurity is not particularly limited, and may be, for example, boron. The peak concentration of the p-type impurity contained in the collector layer 11 is not particularly limited, and may be, for example, 1×10 16 cm- -3 -1×10 18 cm -3 .

[0015] The buffer layer 12 is provided across the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. In the IGBT region 102, the buffer layer 12 is provided between the collector layer 11 and the drift layer 13, separating the collector layer 11 and the drift layer 13, with its lower surface in contact with the collector layer 11 and its upper surface in contact with the drift layer 13. In the boundary region 106, the buffer layer 12 is provided between the n-type boundary layer 18 and the drift layer 13, separating the n-type boundary layer 18 and the drift layer 13, with its lower surface in contact with the n-type boundary layer 18 and its upper surface in contact with the drift layer 13. The buffer layer 12 is located in the diode region 104 between the cathode layer 17 and the drift layer 13, separating the cathode layer 17 and the drift layer 13. Its lower surface is in contact with the cathode layer 17, and its upper surface is in contact with the drift layer 13. The buffer layer 12 has a higher concentration of n-type impurities than the drift layer 13. The buffer layer 12 is formed by ion implanting n-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, but may include, for example, phosphorus. The peak concentration of n-type impurities in the buffer layer 12 is not particularly limited, but may include, for example, 1 × 10⁻⁶ 15 cm -3 ~1 × 10 18 cm -3 That's fine.

[0016] The drift layer 13 is provided across the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The drift layer 13 is located between the buffer layer 12 and the base layer 14, separating the buffer layer 12 and the base layer 14, with its lower surface in contact with the buffer layer 12 and its upper surface in contact with the base layer 14. The drift layer 13 is the remainder of the semiconductor substrate 10 after other semiconductor layers have been formed. The peak concentration of n-type impurities contained in the drift layer 13 is not particularly limited, but for example, 1 × 10⁻⁶ 13 cm -3 ~1 × 10 15 cm -3 That's fine.

[0017] The base layer 14 is provided across the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. In the IGBT region 102, the base layer 14 is provided between the drift layer 13, the emitter layer 15, and the contact layer 16, separating the drift layer 13 from the emitter layer 15 and the contact layer 16, with its lower surface in contact with the drift layer 13 and its upper surface in contact with the emitter layer 15 and the contact layer 16. In the boundary region 106 and the diode region 104, the base layer 14 is provided between the drift layer 13 and the contact layer 16, separating the drift layer 13 from the contact layer 16, with its lower surface in contact with the drift layer 13 and its upper surface in contact with the contact layer 16. The base layer 14 is formed by ion implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The p-type impurities are not particularly limited, but may be, for example, boron. The peak concentration of p-type impurities in the base layer 14 is not particularly limited, but for example, 1 × 10⁻⁶ 15 cm -3 ~1 × 10 17 cm -3 That's fine.

[0018] In this example, the base layer 14 further comprises a first base layer 14a and a second base layer 14b. The first base layer 14a is the portion of the base layer 14 that corresponds to the IGBT region 102 of the semiconductor substrate 10. The second base layer 14b is the portion of the base layer 14 that corresponds to the diode region 104 and the boundary region 106 of the semiconductor substrate 10. The concentration of p-type impurities in the first base layer 14a is adjusted so that the gate threshold voltage of the trench gate 30 is a desired value. The concentration of p-type impurities in the second base layer 14b is adjusted to control the amount of holes injected during recovery operation. For this reason, the concentration of p-type impurities in the second base layer 14b is lower than the concentration of p-type impurities in the first base layer 14a.

[0019] Each of the multiple emitter layers 15 is partially provided in the upper part of the semiconductor substrate 10 in a region corresponding to the IGBT region 102, and is positioned to be exposed on the upper surface of the semiconductor substrate 10. Each of the multiple emitter layers 15 is in contact with the side surface of the corresponding trench gate 30 and is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the multiple emitter layers 15 is selectively formed in the IGBT region 102 of the semiconductor substrate 10, and is not formed in the diode region 104 and boundary region 106 of the semiconductor substrate 10. In other words, the region of the semiconductor substrate 10 in which the multiple emitter layers 15 are provided is the IGBT region 102. Each of the multiple emitter layers 15 is formed by ion implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, but may be phosphorus, for example. The peak concentration of the n-type impurities contained in each of the multiple emitter layers 15 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 18 cm -3 ~1 × 10 20 cm -3 This may also be the case. In addition, in the technology disclosed herein, the layout of the plurality of emitter layers 15 formed on the upper layer of the semiconductor substrate 10 is not particularly limited, and various layouts can be adopted.

[0020] Each of the multiple contact layers 16 is partially provided across the IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10, and is positioned to be exposed on the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is in ohmic contact with the emitter electrode 24 covering the upper surface of the semiconductor substrate 10. Each of the multiple contact layers 16 is formed by ion implanting p-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The p-type impurities are not particularly limited, but may be, for example, boron. The peak concentration of the p-type impurities contained in each of the multiple contact layers 16 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 17 cm -3 ~1 × 10 20 cm-3 This may also be the case. Furthermore, in the technology disclosed herein, the layout of the multiple contact layers 16 formed on the upper layer of the semiconductor substrate 10 is not particularly limited, and various layouts can be adopted.

[0021] The cathode layer 17 is provided in the lower part of the semiconductor substrate 10 in the area corresponding to the diode region 104, and is positioned to be exposed on the lower surface of the semiconductor substrate 10. The cathode layer 17 is in ohmic contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. The cathode layer 17 is selectively formed in the diode region 104 of the semiconductor substrate 10, and is not formed in the IGBT region 102 and the boundary region 106 of the semiconductor substrate 10. In other words, the area of ​​the semiconductor substrate 10 in which the cathode layer 17 is provided is the diode region 104. The cathode layer 17 is formed by ion implantation of n-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The cathode layer 17 is formed by multi-stage ion implantation and may have multiple peak concentrations in the thickness direction of the semiconductor substrate 10. The n-type impurities are not particularly limited, but may be phosphorus, for example. The peak concentration of the n-type impurities contained in the cathode layer 17 is not particularly limited, but may be, for example, 1 × 10⁻⁶ 18 cm -3 ~1 × 10 20 cm -3 That's fine.

[0022] The n-type boundary layer 18 is provided in the lower part of the semiconductor substrate 10, in the area corresponding to the boundary region 106, and is located in a position exposed on the lower surface of the semiconductor substrate 10. The end of the n-type boundary layer 18 on the IGBT region 102 side is in contact with the collector layer 11, and the end on the diode region 104 side is in contact with the cathode layer 17. The n-type boundary layer 18 is provided between the collector electrode 22 and the buffer layer 12, separating the collector electrode 22 and the buffer layer 12, with its lower surface in contact with the collector electrode 22 and its upper surface in contact with the buffer layer 12. The n-type boundary layer 18 is the portion of the lower part of the semiconductor substrate 10 where impurities were not ion-implanted, and the concentration of n-type impurities is the substrate concentration. That is, the concentration of n-type impurities in the n-type boundary layer 18 is the same as the concentration of n-type impurities in the drift layer 13. Thus, because the n-type boundary layer 18 has a low concentration of n-type impurities, it makes Schottky contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. Alternatively, the n-type boundary layer 18 may be formed by ion implanting n-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. In this case as well, the concentration of n-type impurities in the n-type boundary layer 18 is adjusted to a range that makes Schottky contact with the collector electrode 22.

[0023] Each of the multiple trench gates 30 is provided within a trench formed in the upper layer of the semiconductor substrate 10 in a region corresponding to the IGBT region 102, and has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is insulated from the semiconductor substrate 10 by the gate insulating film 34 and insulated from the emitter electrode 24 by the interlayer insulating film. Each of the multiple trench gates 30 penetrates the base layer 14 from the upper surface of the semiconductor substrate 10 to reach the drift layer 13. In this example, each of the multiple trench gates 30 extends along the x-direction when the semiconductor substrate 10 is viewed from above, and is spaced apart from each other in the y-direction. That is, when the semiconductor substrate 10 is viewed from above, the multiple trench gates 30 are spaced apart from each other along the direction in which the IGBT region 102 and diode region 104 are repeatedly arranged, and have a striped layout. Instead of this example, the multiple trench gates 30 may have other types of layouts.

[0024] Each of the multiple dummy trench gates 40 is provided within a trench formed in the upper layer of the semiconductor substrate 10, in the area corresponding to the diode region 104 and the boundary region 106. The multiple dummy trench gates 40 are manufactured using the same process as the multiple trench gates 30, and differ from the trench gates 30 in that the interlayer insulating film that insulates the gate electrode 32 and the emitter electrode 24 has been removed. The multiple dummy trench gates 40 have the same layout as the multiple trench gates 30. The provision of such dummy trench gates 40 can mitigate electric field concentration in the diode region 104 and the boundary region 106.

[0025] The semiconductor device 1 can control the on / off state of the current flowing from the collector electrode 22 to the emitter electrode 24 in the IGBT region 102 based on the gate voltage applied to the gate electrode 32 of the trench gate 30. Furthermore, the semiconductor device 1 allows the diode structure formed in the diode region 104 to operate as a freewheeling diode during recovery operation.

[0026] During the recovery operation in which the diode structure is operating, if the amount of holes injected obliquely from the p-type base layer 14 of the IGBT region 102 to the n-type cathode layer 17 of the diode region 104 increases, the recovery current increases, and the recovery loss increases. In semiconductor device 1, an n-type boundary layer 18 that makes Schottky contact with the collector electrode 22 is provided in the boundary region 106. The Schottky contact between the collector electrode 22 and the n-type boundary layer 18 forms a barrier that hinders the recovery current. Thus, in semiconductor device 1, a diode structure that carries the recovery current is not configured in the boundary region 106. As a result, in semiconductor device 1, the distance between the p-type base layer 14 of the IGBT region 102 and the n-type cathode layer 17 of the diode region 104 becomes longer. Therefore, the amount of holes injected obliquely during the recovery operation is suppressed, and the recovery current is suppressed. Consequently, semiconductor device 1 can have characteristics of low recovery loss.

[0027] The width of the boundary region 106, measured along the direction connecting the IGBT region 102 and the diode region 104, is adjusted to a size necessary to suppress the amount of holes injected in the oblique direction. The width of the boundary region 106 is not particularly limited, but may be, for example, 0.5 μm or more, preferably 1.0 μm or more. The width of the boundary region 106 may also be greater than the width between adjacent dummy trench gates 40 (i.e., the pitch width of the dummy trench gates 40). Alternatively, the width of the boundary region 106 may be greater than the substrate thickness of the semiconductor substrate 10. In order to reduce area consumption, the width of the boundary region 106 may also be less than twice the substrate thickness of the semiconductor substrate 10.

[0028] Now, let's consider the case where an n-type boundary layer 18 is not provided in the boundary region 106, but a collector layer 11 is provided. In this case, when the IGBT structure is on, holes are injected from the collector layer 11 of the boundary region 106 towards the n-type drift layer 13 of the boundary region 106. When the IGBT structure turns off, the holes injected into the drift layer 13 of the boundary region 106 move diagonally toward the p-type base layer 14 of the IGBT region 102 and are discharged through the p-type base layer 14. As a result, the time until the holes are discharged becomes longer, and the switching loss increases due to the increase in tail current.

[0029] In semiconductor device 1, an n-type boundary layer 18 is provided in the boundary region 106. The n-type boundary layer 18 does not have the function of injecting holes when the IGBT structure is turned on. Therefore, in semiconductor device 1, when the IGBT structure is turned on, the amount of holes injected toward the drift layer 13 in the boundary region 106 is suppressed. Consequently, semiconductor device 1 can have characteristics of low switching loss.

[0030] The semiconductor device 1 described above can be modified as follows. The semiconductor device 2 shown in Figure 3 is characterized by having a plurality of p-type boundary collector layers 111 within the semiconductor substrate 10. Alternatively, one boundary collector layer 111 may be provided within the semiconductor substrate 10. Each of the plurality of boundary collector layers 111 is provided in the lower part of the semiconductor substrate 10 in a range corresponding to the boundary region 106, and is provided in a position exposed on the lower surface of the semiconductor substrate 10. Each of the plurality of boundary collector layers 111 is in ohmic contact with the collector electrode 22 covering the lower surface of the semiconductor substrate 10. Each of the plurality of boundary collector layers 111 is dispersed within the n-type boundary layer 18 along the direction connecting the IGBT region 102 and the diode region 104. Each of the plurality of boundary collector layers 111 is provided between the collector electrode 22 and the buffer layer 12, separating the collector electrode 22 and the buffer layer 12, with its lower surface in contact with the collector electrode 22 and its upper surface in contact with the buffer layer 12. Each of the multiple boundary collector layers 111 is formed by ion implanting p-type impurities toward the underside of the semiconductor substrate 10 using ion implantation technology. Each of the multiple boundary collector layers 111 may be formed in a common ion implantation process with the collector layer 11.

[0031] As shown in Figure 2, when an n-type boundary layer 18 is provided over the entire boundary region 106, as in semiconductor device 1, holes are substantially not injected into the drift layer 13 of the boundary region 106 when the IGBT structure is turned on. In this case, there is a concern that the on-voltage will be high when the IGBT structure is turned on. In semiconductor device 2 shown in Figure 3, since multiple boundary collector layers 111 are provided in the boundary region 106, an appropriate amount of holes can be injected into the drift layer 13 of the boundary region 106 when the IGBT structure is turned on. The amount of hole injection can be controlled by adjusting the area of ​​the multiple boundary collector layers 111 and the peak concentration of p-type impurities. Semiconductor device 2 can have low switching loss characteristics while keeping the on-voltage low when the IGBT structure is turned on.

[0032] The semiconductor device 3 shown in Figure 4 is characterized by having a p-type boundary layer 19 within the semiconductor substrate 10. The p-type boundary layer 19 is provided in the lower part of the semiconductor substrate 10 in a range corresponding to the boundary region 106. The p-type boundary layer 19 has an end on the IGBT region 102 side that is in contact with the collector layer 11, and an end on the diode region 104 side that is in contact with the cathode layer 17. The p-type boundary layer 19 is provided between the n-type boundary layer 18 and the buffer layer 12, separating the n-type boundary layer 18 and the buffer layer 12, with its lower surface in contact with the n-type boundary layer 18 and its upper surface in contact with the buffer layer 12. The p-type boundary layer 19 is formed by ion implanting p-type impurities toward the lower surface of the semiconductor substrate 10 using ion implantation technology. The p-type impurities are not particularly limited, but may be, for example, boron. The peak concentration of p-type impurities contained in the p-type boundary layer 19 is not particularly limited, but for example, 1 × 10⁻⁶ 16 cm -3 ~1 × 10 18 cm -3 This may also be the case. If such a p-type boundary layer 19 is provided, the recovery current can be further suppressed.

[0033] The semiconductor device 4 shown in Figure 5 is characterized by having an n-type barrier layer 21 within the semiconductor substrate 10. The barrier layer 21 is provided over the entire IGBT region 102, boundary region 106, and diode region 104 of the semiconductor substrate 10. The barrier layer 21 is embedded in the base layer 14, dividing the base layer 14 into upper and lower sections. The barrier layer 21 is formed by ion implanting n-type impurities toward the upper surface of the semiconductor substrate 10 using ion implantation technology. The n-type impurities are not particularly limited, but may be phosphorus, for example. The effective peak concentration of n-type impurities in the barrier layer 21 may be smaller than the effective peak concentration of p-type impurities in the second base layer 14b. With such a barrier layer 21 provided, hole injection from the base layer 14 can be suppressed during recovery operation. Therefore, the semiconductor device 4 can have low recovery loss characteristics.

[0034] The following summarizes the features of the technology disclosed in this specification. Note that each of the technical elements described below is an independent technical element, and exhibits technical usefulness either individually or in various combinations.

[0035] (Feature 1) The IGBTs (1,2,3,4) are reverse conduction IGBTs, A semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, The lower electrode (22) provided on the lower surface of the semiconductor substrate, The semiconductor substrate is provided with an upper electrode (24) on its upper surface, The aforementioned semiconductor substrate is A first-conductivity drift layer (13) is provided across the IGBT region, the diode region, and the boundary region, A second conductivity type base layer (14) is provided extending across the IGBT region, the diode region, and the boundary region, and is positioned above the drift layer. A first conductivity type emitter layer (15) is provided in the IGBT region, positioned above the base layer, and in contact with the upper electrode, A second conductivity type collector layer (11) is provided in the IGBT region, positioned below the drift layer, and in contact with the lower electrode, A first conductivity type cathode layer (17) is provided in the diode region, positioned below the drift layer, and in contact with the lower electrode, The first conductivity type boundary layer (18) of a first conductivity type is provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode, The first conductive boundary layer is in Schottky contact with the lower electrode, and is a reverse-conducting IGBT.

[0036] (Feature 2) The reverse-conducting IGBT according to feature 1, wherein the concentration of the first conductivity type impurity in the first conductivity type boundary layer is the same as the concentration of the first conductivity type impurity in the drift layer.

[0037] (Feature 3) The aforementioned semiconductor substrate is The reverse conducting IGBT according to feature 1 or 2, further comprising a second conductive type boundary collector layer (111) provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode.

[0038] (Feature 4) The aforementioned base layer is The IGBT region includes a first base layer (14a), It has a second base layer (14b) provided in the diode region and the boundary region, A reverse-conducting IGBT according to any one of features 1 to 3, wherein the concentration of the second conductivity type impurity in the second base layer is lower than the concentration of the second conductivity type impurity in the first base layer.

[0039] (Feature 5) The aforementioned semiconductor substrate is A reverse conducting IGBT according to any one of features 1 to 4, further comprising a first conductivity type barrier layer (21) provided across the IGBT region, the diode region, and the boundary region, and embedded in the base layer.

[0040] (Feature 6) The reverse conducting IGBT according to any one of features 1 to 5, further comprising a trench gate (30) provided in the IGBT region and located within a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

[0041] (Feature 7) The reverse conducting IGBT according to any one of features 1 to 6, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, and provided in a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

[0042] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of Symbols]

[0043] 10: Semiconductor substrate, 11: Collector layer, 12: Buffer layer, 13: Drift layer, 14: Base layer, 14a: First base layer, 14b: Second base layer, 15: Emitter layer, 16: Contact layer, 17: Cathode layer, 18: n-type boundary layer, 22: Collector electrode, 24: Emitter electrode, 30: Trench gate, 32: Gate electrode, 34: Gate insulating film, 40: Dummy trench gate, 102: IGBT region, 104: Diode region, 106: Boundary region

Claims

1. These are reverse-conducting IGBTs (1, 2, 3, 4), A semiconductor substrate (10) having an IGBT region (102), a diode region (104), and a boundary region (106) located between the IGBT region and the diode region, The lower electrode (22) provided on the lower surface of the semiconductor substrate, The semiconductor substrate is provided with an upper electrode (24) on its upper surface, The aforementioned semiconductor substrate is A first-conductivity drift layer (13) is provided across the IGBT region, the diode region, and the boundary region, A second conductivity type base layer (14) is provided extending across the IGBT region, the diode region, and the boundary region, and is positioned above the drift layer. A first conductivity type emitter layer (15) is provided in the IGBT region, positioned above the base layer, and in contact with the upper electrode, A second conductivity type collector layer (11) is provided in the IGBT region, positioned below the drift layer, and in contact with the lower electrode, A first conductivity type cathode layer (17) is provided in the diode region, positioned below the drift layer, and in contact with the lower electrode, The first conductivity type boundary layer (18) of a first conductivity type is provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode. The first conductive boundary layer is in Schottky contact with the lower electrode. A reverse-conducting IGBT in which the concentration of the first conductivity type impurity in the first conductivity type boundary layer is the same as the concentration of the first conductivity type impurity in the drift layer.

2. The semiconductor substrate is The reverse-conducting IGBT according to claim 1, further comprising a second conductivity type boundary layer (19) of a second conductivity type provided in the boundary region and disposed between the first conductivity type boundary layer and the drift layer.

3. The aforementioned semiconductor substrate is The reverse-conducting IGBT according to claim 1, further comprising a second conductive type boundary collector layer (111) provided in the boundary region, positioned below the drift layer, and in contact with the lower electrode.

4. The aforementioned base layer is The IGBT region includes a first base layer (14a), The diode region and the boundary region are provided with a second base layer (14b), The reverse-conducting IGBT according to claim 1, wherein the concentration of the second conductivity type impurity in the second base layer is lower than the concentration of the second conductivity type impurity in the first base layer.

5. The aforementioned semiconductor substrate is The reverse-conducting IGBT according to claim 1, further comprising a first-conductivity type barrier layer (21) provided across the IGBT region, the diode region, and the boundary region, and embedded in the base layer.

6. The reverse conducting IGBT according to claim 1, further comprising a trench gate (30) provided in the IGBT region and located within a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

7. The reverse conducting IGBT according to claim 1, further comprising a dummy trench gate (40) provided in the diode region and the boundary region, and located in a trench that penetrates the base layer from the upper surface of the semiconductor substrate and reaches the drift layer.

8. The semiconductor substrate is The reverse-conducting IGBT according to any one of claims 1 to 7, further comprising a temperature sensing structure for measuring the temperature of the semiconductor substrate.

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