Sorting method for silicon carbide semiconductor devices

Abstract

To provide a silicon carbide semiconductor device and a manufacturing method of a silicon carbide semiconductor device, enabling accurate selection of a device whose Von fluctuates after a body diode is energized by improving Von measurement accuracy.SOLUTION: In a first region within 30 μm from the cross section of a silicon carbide semiconductor device, the roughness Rp of the back surface of the silicon carbide semiconductor device is 4 μm or less, and in a second region other than the first region, the roughness Rp of the back surface of the silicon carbide semiconductor device is 2 μm or less. A manufacturing method of a silicon carbide semiconductor device comprises: defining the roughness Rp of the back surface of the silicon carbide semiconductor device having a MOS gate structure; then measuring the on-voltage of the silicon carbide semiconductor device; flowing a forward current through a body diode of the silicon carbide semiconductor device; then measuring the on-voltage of the silicon carbide semiconductor device after the forward current is flowed; then calculating the change rate of the on-voltage of the silicon carbide semiconductor device from the on-voltage before and after the forward current is applied; and then selecting silicon carbide semiconductor device having a calculated rate of change lower than 3%.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This invention relates to charcoal silicon carbide semiconductor devices Selection method and pertains thereto.

Background Art

[0002] Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices for controlling high voltages and large currents. There are multiple types of power semiconductor devices such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used appropriately according to the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can handle larger currents, but cannot be switched at high speeds. Specifically, the use of bipolar transistors is limited to a switching frequency of about several kHz, and the use of IGBTs is limited to a switching frequency of about several tens of kHz. On the other hand, power MOSFETs have a lower current density than bipolar transistors and IGBTs and it is difficult to handle large currents, but can perform high-speed switching operations up to about several MHz.

[0004] However, in the market, there is a strong demand for power semiconductor devices that combine large current and high speed, and efforts are being made to improve IGBTs and power MOSFETs. Currently, development has progressed to almost the limit of materials. Semiconductor materials to replace silicon are being considered from the perspective of power semiconductor devices, and silicon carbide (SiC) has attracted attention as a semiconductor material capable of fabricating (manufacturing) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics.

[0005] The background is that SiC is a chemically very stable material, has a wide bandgap of 3 eV, and can be used very stably as a semiconductor even at high temperatures. In addition, the maximum electric field strength is more than one order of magnitude larger than that of silicon. Since SiC has a high potential to exceed the material limits in silicon, it is highly expected to have significant growth in future power semiconductor applications, especially MOSFETs. In particular, its on-resistance is expected to be small. A vertical SiC-MOSFET with even lower on-resistance while maintaining high breakdown voltage characteristics can be expected.

[0006] Regarding the structure of a conventional silicon carbide semiconductor device, a vertical MOSFET will be described as an example. FIG. 9 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 9 is an example of a trench-type MOSFET 150. As shown in FIG. 9, an n-type buffer layer 118 is deposited on the front surface of an n-type silicon carbide substrate 101, and an n + -type silicon carbide epitaxial layer 102 is deposited on the front surface of the n-type buffer layer 118. -

[0007] n - -type regions 117, a first p + -type base region 103, a second p + -type base region 104, an n-type high-concentration region 105, and a p-type base layer 106 are selectively provided inside the n + -type silicon carbide epitaxial layer 102. Also, an n ++ -type source region 107 and a p ++ -type contact region 108 are selectively provided on the surface of the p-type base layer 106.

[0008] Also, a trench 116 is provided that penetrates the n ++ -type source region 107 and the p-type base layer 106 and reaches the n-type high-concentration region 105. Along the inner wall of the trench 116, a gate insulating film 109 is provided on the bottom and side walls of the trench 116, and a gate electrode 110 is provided inside the gate insulating film 109 in the trench 116. A p ++ -type contact region 108 and an n ++A source electrode 112 is provided on the surface of the type source region 107, and a source electrode pad 115 is provided on the source electrode 112. Furthermore, an interlayer insulating film 111 is provided over the entire surface of the first main surface of the silicon carbide semiconductor substrate, covering the gate electrode 110 embedded in the trench 116. A barrier metal 114 is provided between the source electrode 112 and the interlayer insulating film 111. + A back electrode 113 is provided on the back surface of the silicon carbide substrate 101.

[0009] A vertical MOSFET with this structure incorporates a parasitic pn diode between the source and drain, formed by a p-type base layer 106 and an n-type high-concentration region 105 as a body diode. This parasitic pn diode can be operated by applying a high potential to the source electrode 112, and current flows in the direction indicated by arrow A in Figure 9. Thus, unlike IGBTs, MOSFETs incorporate a parasitic pn diode, allowing for the omission of a freewheeling diode (FWD) used in the inverter, contributing to cost reduction and miniaturization. Hereafter, the parasitic pn diode of the MOSFET will be referred to as the body diode.

[0010] In such silicon carbide semiconductor devices, n + The silicon carbide substrate 101 may have defects in its crystal structure. In this case, when current flows through the body diode, p ++ A hole is injected from the type contact region 108, n - Type silicon carbide epitaxial layer 102 or n + Recombination of electrons and holes occurs in the silicon carbide substrate 101. The recombination energy equivalent to the band gap (3eV) generated at this time is n + A basal plane dislocation, a type of crystal defect present in the silicon carbide substrate 101, moves, and the stacking fault sandwiched between two basal plane dislocations expands.

[0011] As stacking faults expand, the on-resistance of the MOSFET and the forward voltage of the body diode increase because the stacking faults are less ductile. If this operation continues, the stacking faults will expand cumulatively, increasing losses in the inverter circuit over time and generating more heat, which can lead to equipment failure. To prevent this problem, a SiC-SBD (Schottky Barrier Diode) can be connected in antiparallel to the MOSFET to prevent current from flowing through the MOSFET's body diode.

[0012] In testing methods for semiconductor devices, a technique is known in which a metal block with a gold-plated surface (such as gold) that has low contact resistance is bonded to the back surface of a semiconductor device by a bonding layer made of a conductive bonding material, thereby enabling pulse current and DC current with low thermal and contact resistance and a large duty cycle (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] Japanese Patent Publication No. 2019-021740 [Overview of the project] [Problems that the invention aims to solve]

[0014] However, even when a SiC-SBD is connected in antiparallel to a MOSFET, current may flow through the MOSFET's body diode at the moment the MOSFET switches from on to off, potentially expanding the stacking fault of the MOSFET. For this reason, conventionally, silicon carbide semiconductor devices were screened to select those without stacking faults.

[0015] Figure 10 is a flowchart showing a sorting method in a conventional silicon carbide semiconductor device manufacturing method. As shown in Figure 10, first, the initial on-voltage (Von) is measured (step S101). The initial on-voltage is measured in order to determine the growth of stacking faults in the substrate by the change in on-voltage. The on-voltage measured here is defined as Von0. Next, a forward current is applied to the body diode of the MOSFET (step S102). Specifically, the gate electrode and source electrode of the MOSFET are short-circuited, a positive voltage is applied to the source electrode, and the potential of the drain electrode is set to 0.

[0016] Next, the on-voltage is measured (step S103). This measured on-voltage is denoted as Von1. Next, the rate of change of the on-voltage is calculated (step S104). The rate of change of the on-voltage ΔVon is the rate of change from the on-voltage in the initial state. For example, the rate of change of the on-voltage ΔVon can be calculated using ΔVon = (Von1 - Von0) / Von0.

[0017] Next, it is determined whether the rate of change of the on-voltage ΔVon < 0.03 (less than 3%) (step S105). If it is determined that the rate of change of the on-voltage ΔVon < 0.03 (step S105: Yes), the MOSFET is selected as a suitable product (step S106). If it is determined that the rate of change of the on-voltage ΔVon < 0.03 (step S105: No), the MOSFET is selected as a non-suitable product (step S107).

[0018] Here, Figure 11 is a schematic diagram of a sorting method in a conventional silicon carbide semiconductor device manufacturing method. As shown in Figure 11, the on-voltage is measured by placing the back surface of the trench-type MOSFET 150 on a cemented carbide stage 151 and bringing a probe 152 into contact with the front surface of the trench-type MOSFET 150.

[0019] In this case, a large current (~100A) is applied to the trench-type MOSFET 150, which increases the variation in contact resistance between the probe 152, the trench-type MOSFET 150, and the cemented carbide stage 151. As a result, variations in heat generation due to contact resistance are large, leading to increased measurement errors.

[0020] Figure 12 is a graph showing the measurement variability of the sorting method in a conventional silicon carbide semiconductor device manufacturing method. In Figure 12, the vertical axis represents the rate of change ΔVon of the on-voltage measured at room temperature (RT, approximately 25°C), in units of %. The horizontal axis represents the number of measurements. Figure 12 shows the results of measuring the rate of change ΔVon of the on-voltage 57 times for each of 15 trench-type MOSFETs 150 to be sorted.

[0021] As shown in Figure 12, the variation in the difference between the maximum and minimum values ​​of the rate of change ΔVon is 20.4% in measurements for the same trench-type MOSFET 150. Therefore, the selection method in the conventional silicon carbide semiconductor manufacturing method has a measurement variation of approximately σ (standard deviation) = 1.8%, and a detection accuracy of approximately 3σ = 5.4%, which presents a problem in that it cannot accurately detect the 3% variation that is set as the lower limit of detection for the Von variation.

[0022] This invention aims to solve the problems of the prior art described above by improving the accuracy of Von measurement, thereby enabling accurate selection of devices in which Von fluctuates after the body diode is energized. charcoal silicon semiconductor device Selection method The purpose is to provide. [Means for solving the problem]

[0024] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention Selection methodThe method has the following characteristics: A first step is performed to define the roughness Rp of the electrodes on the back surface of a silicon carbide semiconductor device having a MOS gate structure. Next, a second step is performed to measure the on-voltage of the silicon carbide semiconductor device. Next, a third step is performed to pass a forward current through the body diode of the silicon carbide semiconductor device. Next, a fourth step is performed to measure the on-voltage of the silicon carbide semiconductor device after the forward current has been passed through it. Next, a fifth step is performed to calculate the rate of change of the on-voltage of the silicon carbide semiconductor device from the on-voltage measured in the second step and the on-voltage measured in the fourth step. Next, a sixth step is performed to select silicon carbide semiconductor devices whose calculated rate of change is less than 3%. In the first step, the roughness Rp of the electrodes on the back surface is defined as 4 μm or less in a first region within 30 μm from the cross-section of the silicon carbide semiconductor device, and as 2 μm or less in a second region other than the first region, and the roughness Rp is defined as Average height of the linear portion at a predetermined distance from the cross-section of the electrode This is the height of the highest point.

[0026] Furthermore, the silicon carbide semiconductor device according to this invention Selection method The invention described above is characterized in that, in the second and fourth steps, the silicon carbide semiconductor device is placed on a gold-plated stage and the on-voltage is measured.

[0027] Furthermore, the silicon carbide semiconductor device according to this invention Selection method The invention described above is characterized in that the thickness of the gold plating is 1 μm or more.

[0028] According to the invention described above, the roughness of the back surface of the MOSFET is specified. This reduces variations in contact resistance in the sorting method, reduces measurement errors, and improves the accuracy of Von measurement during electrical characteristic measurement. Therefore, MOSFETs whose Von fluctuates after the body diode is energized can be accurately sorted. [Effects of the Invention]

[0029] The present invention relates to charcoal silicon semiconductor device Selection methodAccording to this research, improving the accuracy of Von measurement allows for the precise selection of devices where Von fluctuates after the body diode is energized. [Brief explanation of the drawing]

[0030] [Figure 1] This is a flowchart showing the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. [Figure 2] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 1. [Figure 3] This graph shows the chip back surface roughness Rp of the silicon carbide semiconductor device according to Embodiment 1. [Figure 4] This is a schematic diagram of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. [Figure 5] This graph shows the measurement variation of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. [Figure 6] This is a schematic diagram of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 2. [Figure 7] This graph shows the measurement variation of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 2. [Figure 8] This table shows the sorting methods in the conventional method and the silicon carbide semiconductor device manufacturing method according to Embodiments 1 and 2. [Figure 9] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 10] This is a flowchart showing a sorting method in a conventional silicon carbide semiconductor device manufacturing method. [Figure 11] This is a schematic diagram of a sorting method used in the conventional manufacturing method of silicon carbide semiconductor devices. [Figure 12] This graph shows the measurement variability in the sorting method used in conventional silicon carbide semiconductor device manufacturing methods. [Figure 13] This graph shows the back surface roughness Rp of a conventional silicon carbide semiconductor chip. [Modes for carrying out the invention]

[0031] The present invention relates to the attached drawings below. charcoal silicon semiconductor device Selection method Preferred embodiments will be described in detail. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted. In this specification, in the notation of Miller indices, "-" indicates a bar attached to the exponent immediately following it, and a "-" before the exponent indicates a negative exponent. The description of "same" or "equivalent" includes up to 5% to account for manufacturing variations. It would be best to do so.

[0032] (Embodiment 1) Figure 1 is a flowchart showing the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. In the following description, a MOSFET will be used as an example of a silicon carbide semiconductor device, but the same applies to other silicon carbide semiconductor devices having a MOS gate structure. First, the silicon carbide semiconductor device according to Embodiment 1 will be described. Figure 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 1.

[0033] As shown in Figure 2, the silicon carbide semiconductor device according to Embodiment 1 is n + On the first main surface (front surface), for example, the (0001) surface (Si surface) of the silicon carbide substrate (silicon carbide substrate) 1, n - A silicon carbide epitaxial layer (first semiconductor layer of the first conductivity type) 2 is deposited.

[0034] Also, n + Silicon carbide substrate 1 and n -An n-type buffer layer 18 may be provided between the n-type silicon carbide epitaxial layers 2. The n-type buffer layer 18 may be, for example, n + A nitrogen (N) is provided on the front surface of the silicon carbide substrate 1. + A silicon carbide epitaxial layer (n-type low-concentration buffer layer 18a) doped to a lower concentration than the silicon carbide substrate 1, and a nitrogen atom provided on the front surface of the n-type low-concentration buffer layer 18a. + It consists of two layers: a silicon carbide epitaxial layer (n-type high-concentration buffer layer 18b) that is highly doped from a silicon carbide substrate 1. The n-type buffer layer 18 causes holes generated at the pn interface to recombine within the n-type buffer layer 18, and n + It is prevented from reaching the silicon carbide substrate 1, + This prevents the generation of stacking faults from the silicon carbide substrate 1.

[0035] n + The silicon carbide substrate 1 is a silicon carbide single crystal substrate. - The silicon carbide epitaxial layer 2 is n + This is a low-concentration n-type drift layer with a lower impurity concentration than the silicon carbide substrate 1. - n + An n-type high-concentration region 5 may be provided on the surface opposite to the silicon carbide substrate 1 side. The n-type high-concentration region 5 is n + Lower than type silicon carbide substrate 1 n - This is a high-concentration n-type drift layer with a higher impurity concentration than the silicon carbide epitaxial layer 2.

[0036] n - n + On the surface side opposite to the silicon carbide substrate 1, a p-type base layer (second semiconductor layer of the second conductivity type) 6 is provided. Hereinafter, n + Silicon carbide substrate 1 and n - A silicon carbide epitaxial layer 2 and a p-type base layer 6 are combined to form a silicon carbide semiconductor substrate.

[0037] n +A drain electrode, which will serve as the back electrode 13, is provided on the second main surface (back surface, i.e., the back surface of the silicon carbide semiconductor substrate) of the silicon carbide substrate 1. A drain electrode pad (not shown) is provided on the surface of the back electrode 13.

[0038] A trench structure is formed on the first main surface side (p-type base layer 6 side) of the silicon carbide semiconductor substrate. Specifically, the trench 16 is n + From the surface opposite to the silicon carbide substrate 1 (the first main surface side of the silicon carbide semiconductor substrate), the n-type high-concentration region 5 penetrates the p-type base layer 6 (if the n-type high-concentration region 5 is not provided, then n - The silicon carbide epitaxial layer 2, hereafter simply referred to as (2), is reached. The trench 16 has a striped planar pattern. Along the inner wall of the trench 16, a gate insulating film 9 is formed at the bottom and side walls of the trench 16, and a gate electrode 10 is formed inside the gate insulating film 9 in the trench 16. The gate insulating film 9 makes the gate electrode 10 n - The silicon carbide epitaxial layer 2 and the p-type base layer 6 are insulated from each other. A portion of the gate electrode 10 may protrude from above the trench 16 (the side where the source electrode pad 15 is provided) toward the source electrode pad 15.

[0039] n-type high-concentration region 5(2) + On the surface layer opposite to the silicon carbide substrate 1 side (the first main surface side of the silicon carbide semiconductor substrate), the second p + A type base region 4 is selectively provided. Below the trench 16 is the first p + A type base region 3 is formed, and the first p + The width of the base region 3 is wider than the width of the trench 16. (p. 1) + Type base region 3 and 2p + The mold base region 4 is doped with, for example, aluminum. In Figure 2, the first p + The mold base region 3 is in contact with the bottom of the trench 16, but may be located deeper than the bottom of the trench 16. (1p) + The mold base region 3 extends to a position deeper than the bottom of the trench 16, towards the drain side.

[0040] 1st p. + Type base region 3 and 2p + By providing the base region 4, the first p is positioned close to the bottom of the trench 16 and in the depth direction (from the source electrode 12 to the back electrode 13). + Type base region 3 and 2p + A pn junction can be formed between the n-type base region 4 and the n-type high-concentration region 5(2). In this way, the first p + Type base region 3 and 2p + By forming a pn junction between the n-type base region 4 and the n-type high-concentration region 5(2), it is possible to prevent a high electric field from being applied to the gate insulating film 9 at the bottom of the trench 16. Therefore, even when a wide-bandgap semiconductor is used as the semiconductor material, it is possible to achieve a high voltage withstand voltage.

[0041] n - Within the silicon carbide epitaxial layer 2, between the trenches 16, the second p + The peak impurity concentration is higher in the n-type high-concentration region 5(2) at a depth deeper than the n-type base region 4. + A type region 17 may be provided. + Type region 17 is defined as a region where the peak impurity concentration is higher than the impurity concentration in the n-type high-concentration region 5(2). + The impurity concentration does not need to be higher than the n-type high-concentration region 5(2) in all regions of type region 17. Also, in a configuration in which the n-type high-concentration region 5 is not provided, n + Type region 17 has a peak impurity concentration of n - The impurity concentration is higher than that of the silicon carbide epitaxial layer 2. Furthermore, n + Type region 17 has an impurity concentration of 2p + It is preferable that the impurity concentration is lower than that of the base region 4.

[0042] n + The type region 17 determines the part that determines the breakdown voltage of the element, the first p at the bottom of the trench 16. + Not type base region 3, but the second p between trenches 16. + This can be a type base region 4. That is, the first p at the bottom of the trench 16 +The pressure resistance of the base region 3 is determined by the second p between the trenches 16. + The breakdown voltage can be made higher than that of the base region 4 of the mold.

[0043] Furthermore, within the p-type base layer 6, on the first main surface side of the silicon carbide semiconductor substrate, ++ A type source region (first semiconductor region of the first conductivity type) 7 is selectively provided. ++ Type contact region 8 may be selectively provided. Also, n ++ Type source region 7 and p ++ The contact regions 8 are in contact with each other. Also, p ++ The type contact region 8 may be selectively provided in the direction extending in a stripe-like manner from the trench 16.

[0044] The interlayer insulating film 11 is provided over the entire surface of the first main surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 10 embedded in the trench 16. The source electrode 12 is connected through a contact hole opened in the interlayer insulating film 11, n ++ Type source region 7 and p ++ Type Contact Area 8 (p ++ If a type contact region 8 is not provided, it contacts the p-type base layer 6). The source electrode 12 is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad 15 is provided on the source electrode 12. A barrier metal 14 may be provided between the source electrode 12 and the interlayer insulating film 11 to prevent the diffusion of metal atoms from the source electrode 12 to the gate electrode 10.

[0045] Figure 2 illustrates only one cell (a structure consisting of a trench 16, gate insulating film 9, gate electrode 10, interlayer insulating film 11, and source electrode 12), but many more MOS gate (insulating gate consisting of metal-oxide-semiconductor) structures of cells may be arranged in parallel.

[0046] Returning to Figure 1, the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1 will be explained. Here, Figure 13 is a graph showing the chip back surface roughness Rp of a conventional silicon carbide semiconductor device. Roughness Rp is the height of the highest part from the back surface of the chip. In Figure 13, the vertical axis shows the chip back surface roughness Rp, and the horizontal axis shows the distance from the chip cross-section (cross-section of the silicon carbide semiconductor device). The chip cross-section is the cross-section of a silicon carbide semiconductor device (semiconductor chip) that has been formed on a silicon carbide semiconductor wafer and then individualized by dicing. As shown in Figure 13, in the region within 20 μm from the chip cross-section, there are chips with a chip back surface roughness Rp greater than 4 μm, and in the region outside the region within 20 μm from the chip cross-section, there are chips with a chip back surface roughness Rp greater than 2 μm. Thus, in conventional silicon carbide semiconductor devices, because the chip back surface roughness Rp is large, there is a large variation in the contact resistance between the back surface of the trench-type MOSFET 150 and the cemented carbide stage 151, resulting in a large measurement error.

[0047] Therefore, in the silicon carbide semiconductor device according to Embodiment 1, the roughness (Rp) of the back surface of the trench-type MOSFET 50 is defined (Step S1, First Step). Figure 3 is a graph showing the chip back surface roughness Rp of the silicon carbide semiconductor device according to Embodiment 1. In Figure 3, the vertical axis represents the chip back surface roughness Rp, and the horizontal axis represents the distance from the chip cross-section. As shown in Figure 3, the chip back surface roughness Rp is defined to be 4 μm or less in the region within 30 μm from the chip cross-section (First Region), and to be 2 μm or less in the region other than the region within 30 μm from the chip cross-section (Second Region). More preferably, the chip back surface roughness Rp is defined to be 4 μm or less in the region within 20 μm from the chip cross-section, and to be 2 μm or less in the region other than the region within 20 μm from the chip cross-section.

[0048] Chip back surface roughness can be caused by jagged burrs generated during the dicing of silicon carbide semiconductor wafers. Therefore, the chip back surface roughness Rp can be kept within the aforementioned range by performing dicing from the surface of the silicon carbide semiconductor wafer, dicing according to the off-angle of the silicon carbide semiconductor wafer, or performing dicing with a laser. Alternatively, the back surface roughness (Rp) of MOSFETs can be measured in advance, and only MOSFETs within the aforementioned range can be selected.

[0049] Next, the initial on-voltage is measured (Step S2, second step). The initial on-voltage is measured in order to determine the growth of stacking faults on the substrate by the change in on-voltage. The on-voltage is the potential difference between the drain electrode and the source electrode when the MOSFET is in the on state, that is, when a positive voltage is applied to the drain electrode and the gate voltage is gradually increased, causing current to flow from the drain electrode to the source electrode, or from the source electrode to the drain electrode. The on-voltage measured here is denoted as Von0.

[0050] For example, the on-voltage of a MOSFET can be measured by determining the source-drain voltage Vdson when a positive voltage is applied to the drain electrode with the source electrode potential set to 0, and a current of a predetermined value flows from the drain electrode to the source electrode. In this case, the current flows through path A in Figure 2 as described above.

[0051] Next, a forward current is applied to the MOSFET's body diode (step S3, third step). Specifically, the gate electrode and source electrode of the MOSFET are short-circuited or a negative bias is applied, a positive voltage is applied to the source electrode, and the potential of the drain electrode is set to 0. In Embodiment 1, a DC or forward current with a frequency of 100 kHz or less is applied. The forward current of the body diode is the current that flows from the source electrode to the drain electrode in the diode formed between the source and drain of the MOSFET. Alternatively, the forward current of the body diode can be applied by applying a negative voltage to the drain electrode while the potential of the source electrode is set to 0.

[0052] Next, the on-voltage is measured (step S4, fourth step). The on-voltage is measured in the same way as in step S2. The voltage measured here is denoted as Von1. Next, the rate of change of the on-voltage is calculated (step S5, fifth step). The rate of change of the on-voltage ΔVon is the rate of change from the on-voltage in the initial state. For example, the rate of change of the on-voltage ΔVon can be calculated as ΔVon = (Von1 - Von0) / Von0.

[0053] Next, it is determined whether the rate of change of the on-voltage is <0.03 (less than 3%) (step S6, sixth step). If it is determined that the rate of change of the on-voltage is <0.03 (step S6: Yes), the MOSFET is selected as a suitable product (step S7). On the other hand, if it is determined that the rate of change of the on-voltage is not <0.03 (step S6: No), the MOSFET is selected as a non-suitable product (step S8).

[0054] Figure 4 is a schematic diagram of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. As shown in Figure 4, the on-voltage is measured by placing the back surface of the trench-type MOSFET 50 on a cemented carbide stage 51 and bringing a probe 52 into contact with the front surface of the trench-type MOSFET 50.

[0055] In Embodiment 1, since the roughness of the back surface of the trench-type MOSFET 50 is specified, even when a large current (~100A) is applied to the trench-type MOSFET 50, the variation in contact resistance between the probe 52, the trench-type MOSFET 50, and the cemented carbide stage 51 is small. As a result, variations in heat generation due to contact resistance are small, and measurement errors are reduced.

[0056] Figure 5 is a graph showing the measurement variability of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 1. In Figure 5, the vertical axis represents the rate of change ΔVon of the on-voltage measured at room temperature (RT, approximately 25°C), and the unit is %. The horizontal axis represents the number of measurements. Figure 5 shows the results of measuring the rate of change ΔVon of the on-voltage 57 times for each of 15 trench-type MOSFETs 50 to be sorted.

[0057] As shown in Figure 5, the variation in the difference between the maximum and minimum values ​​of the rate of change ΔVon is 12.18% in measurements for the same trench-type MOSFET 50. Therefore, in the silicon carbide semiconductor device manufacturing method according to Embodiment 1, the measurement variation is low, at approximately σ = 1.09%, and the 3% variation set as the lower detection limit for Von fluctuation can be detected with high accuracy of 5.5σ.

[0058] As described above, the silicon carbide semiconductor device according to Embodiment 1 specifies the roughness of the back surface of the MOSFET. This reduces the variation in contact resistance in the selection method, reduces measurement errors, and improves the accuracy of Von measurement during electrical characteristic measurement. Therefore, MOSFETs whose Von fluctuates after the body diode is energized can be accurately selected.

[0059] (Embodiment 2) Next, Embodiment 2 will be described. The flowchart for the sorting method in the structure and manufacturing method of the silicon carbide semiconductor device according to Embodiment 2 is the same as that of Embodiment 1, so its description will be omitted.

[0060] Figure 6 is a schematic diagram of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 2. The difference between the schematic diagram of Embodiment 2 and the schematic diagram of Embodiment 1 is that the surface of the cemented carbide stage 51 is covered with gold plating 53.

[0061] The gold (Au) material of the gold plating 53 is soft, and the irregularities on the back surface of the trench-type MOSFET 50 bite into the gold plating 53, thereby improving contact between the back surface of the trench-type MOSFET 50 and the cemented carbide stage 51. Furthermore, to allow the irregularities on the back surface to bite in sufficiently, the thickness of the gold plating 53 is preferably 1 μm or more. In addition, since gold is resistant to oxidation, it can prevent the formation of irregularities due to oxide films on the cemented carbide stage 51.

[0062] Figure 7 is a graph showing the measurement variability of the sorting method in the manufacturing method of a silicon carbide semiconductor device according to Embodiment 2. In Figure 7, the vertical axis represents the rate of change ΔVon of the on-voltage measured at room temperature (RT, approximately 25°C), and the unit is %. The horizontal axis represents the number of measurements. Figure 7 shows the results of measuring the rate of change ΔVon of the on-voltage 46 times for each of 20 trench-type MOSFETs 50 to be sorted.

[0063] As shown in Figure 7, the variation in the difference between the maximum and minimum values ​​of the rate of change ΔVon is 2.53% when measured for the same trench-type MOSFET 50. Therefore, in the silicon carbide semiconductor device manufacturing method according to Embodiment 2, the measurement variation is lower than in Embodiment 1, at approximately σ = 0.55%, and the 3% variation set as the lower detection limit for Von fluctuation can be detected with high accuracy of 5.5σ.

[0064] As described above, in the sorting method for manufacturing a silicon carbide semiconductor device according to Embodiment 2, the contact between the back surface of the trench-type MOSFET and the cemented carbide stage can be improved by covering the surface of the cemented carbide stage with gold plating. As a result, the variation in contact resistance can be reduced compared to Embodiment 1, the measurement error can be reduced, and the accuracy of Von measurement during electrical characteristic measurement can be improved. Therefore, MOSFETs whose Von fluctuates after the body diode is energized can be sorted with high accuracy.

[0065] Figure 8 is a table showing the sorting method in the conventional and embodiment 1 and 2 silicon carbide semiconductor device manufacturing method. Figure 8 is a table summarizing the items described above, where Von in Figure 8 shows the measurement result of Von after the body diode is energized, σ is the standard deviation of the Von fluctuation amount, and MAX-MIN shows the difference between the maximum and minimum values ​​of the rate of change ΔVon.

[0066] As described above, the present invention can be modified in various ways without departing from the spirit of the invention, and in each of the embodiments described above, for example, the dimensions of each part, the impurity concentration, etc. can be set in various ways according to the required specifications. Furthermore, although the above embodiments are described using silicon carbide as the wide bandgap semiconductor as an example, the invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, although the trench type MOSFET was described as an example, the invention can also be applied to planar type MOSFETs. In addition, although the first conductivity type is n type and the second conductivity type is p type in each embodiment, the present invention can also be similarly held even if the first conductivity type is p type and the second conductivity type is n type. [Industrial applicability]

[0067] As described above, the present invention relates to charcoal silicon semiconductor device Selection method This is useful for silicon carbide semiconductor devices used in inverter circuits where a diode is connected in antiparallel to the silicon carbide semiconductor device. [Explanation of Symbols]

[0068] 1, 101 n + Silicon carbide substrate 2, 102 n - Silicon carbide epitaxial layer 3, 103 1st p. + Type-based domain 4, 104 2nd p. + Type-based domain 5, 105 n-type high concentration region 6. 10⁶ p-type base layer 7, 107 n ++ Type source area 8, 108 p ++ Type Contact Area 9, 109 Gate Insulator 10, 110 TT 11, 111 Interlayer insulating film 12, 112 Source electrodes 13, 113 Backside electrodes 14, 114 Barrier Metal 15, 115 Source electrode pads 16, 116 Trench 17, 117 n + type area 18, 118 n-type buffer layers 18a n-type low-concentration buffer layer 18b n-type high-concentration buffer layer 50, 150 trench type MOSFETs 51, 151 Carbide alloy stage 52, 152 probes 53 Gold Plated

Claims

1. A first step of defining the roughness Rp of the electrodes on the back surface of a silicon carbide semiconductor device having a MOS gate structure, A second step involves measuring the on-voltage of the silicon carbide semiconductor device, A third step involves applying a forward current to the body diode of the silicon carbide semiconductor device, A fourth step involves measuring the on-voltage of the silicon carbide semiconductor device after the forward current has been applied, A fifth step involves calculating the rate of change of the on-voltage of the silicon carbide semiconductor device from the on-voltage measured in the second step and the on-voltage measured in the fourth step, A sixth step in which silicon carbide semiconductor devices with a calculated rate of change of less than 3% are selected, Includes, In the first step, the roughness Rp of the back surface electrode in a first region within 30 μm from the cross-section of the silicon carbide semiconductor device is specified to be 4 μm or less, and in a second region other than the first region, the roughness Rp of the back surface electrode is specified to be 2 μm or less. A method for sorting silicon carbide semiconductor devices, characterized in that the roughness Rp is the height of the highest part of the linear portion at a predetermined distance from the cross-section of the electrode.

2. The method for sorting silicon carbide semiconductor devices according to claim 1, characterized in that in the second and fourth steps, the silicon carbide semiconductor device is placed on a gold-plated stage and the on-voltage is measured.

3. The method for sorting silicon carbide semiconductor devices according to claim 2, characterized in that the thickness of the gold plating is 1 μm or more.

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