Shared column ADC for in-memory computing macros

Abstract

Various embodiments include systems, methods, architectures, mechanisms, devices, and improvements thereto that scale and aggregate a plurality of weighted data representation analog signals supplied by columns of in-memory computing bit cells within an N×M array of bit cells, and perform analog accumulation or aggregation of the weighted data representation analog signals such that the scaled result is supplied for further processing.

Description

[Technical Field]

[0001] Cross-reference of related applications This application relates to U.S. Patent Application No. 17 / 221,399, filed 2 April 2021, and is a continuation of U.S. Patent Application No. 17 / 252,521. U.S. Patent Application No. 17 / 252,521 claims the interests of U.S. Provisional Patent Application No. 62 / 686,296, filed 18 June 2018, U.S. Provisional Patent Application No. 62 / 702,629, filed 24 July 2018, U.S. Provisional Patent Application No. 62 / 754,805, filed 2 November 2018, and U.S. Provisional Patent Application No. 62 / 756,951, filed 7 November 2018, all of which are incorporated herein by reference in their entirety.

[0002] The present invention relates to the field of in-memory computing, and more specifically to the scaling, aggregation, and conversion of analog signals representing weighted data, such as those supplied by multiple parallel outputs of an array of in-memory computing cells, into digital data. [Background technology]

[0003] This section is intended to introduce to the reader various aspects of the technology that may relate to the various aspects of the invention described and / or claimed below. This discussion is intended to help provide the reader with background information to facilitate a better understanding of the various aspects of the invention. Therefore, these descriptions should be read in this context and not as endorsements of the prior art.

[0004] In-memory computing (IMC) of charge domains has recently emerged as a robust and scalable way to perform in-memory computing. Here, the computational operations within the memory bit cells generally use voltage-charge conversion through capacitors to provide the results as charge. Thus, the bit cell circuit involves appropriate switching of local capacitors within a given bit cell, and the local capacitors are also appropriately coupled to other bit cell capacitors, and the computational results aggregated across the combined bit cells are obtained. In-memory computing is well-suited for performing matrix-vector multiplications, where matrix elements are stored in a memory array and vector elements are broadcast in parallel over the memory array.

[0005] Advantageously, the IMC computing architecture obtains computational results over a large number of bits stored in the memory, rather than fetching individual bits one by one as in conventional memories. This improves the energy efficiency and speed of the system by reducing the number of necessary data collection cycles. The computational results are often derived within the memory columns, where parallel input data is supplied to the rows, the computational operations (such as multiplication) are performed by the memory bit cells storing the data, and further computational operations (such as accumulation) are performed on the column bit lines, resulting in a reduction to a single output. Reducing the output generally increases the dynamic range (i.e., the number of signal levels) compared to single-bit access, which needs to be addressed. Further, to fit the computations within the constrained memory circuits (bit cells, bit lines, etc.) and to enable the expansion of the dynamic range, analog operations are often employed for column computations. This requires an analog-to-digital converter (ADC) for each column to convert the analog output of the column into a digital representation suitable for further processing within the architecture. SUMMARY OF THE INVENTION

[0006] Various deficiencies in the prior art are addressed by a system, method, architecture, mechanism, device, and improvements thereto that scale and aggregate a plurality of weighted data representation analog signals supplied by columns of in-memory computing bit cells within an N×M array of bit cells, and provide the scaled result for further processing by analog accumulation or aggregation of the weighted data representation analog signals.

[0007] Each bit cell provides the result of an operation during a measurement or evaluation phase with its respective output element (e.g., an output capacitor), and the result associates a weight (e.g., a binary or other weighting from the LSB to the MSB of the result) based on the position of the bit cell within the row of bit cells such that each bit cell within a column of bit cells is associated with the same weight.

[0008] The analog signal (e.g., voltage or charge) associated with each column is scaled according to the weight of its respective column during a scaling phase such that the aggregation or accumulation of the scaled analog signals (e.g., voltage or charge) provides an accumulated / aggregated analog signal that includes an analog domain representation of the in-memory computing result, and is then subjected to analog-to-digital conversion (ADC) and further processing.

[0009] The scaling phase may include disconnecting a portion of the bit cells within a column of bit cells according to the corresponding weighting value of that column such that the charge contributed by each column is proportional to the weighting value of that column when the charge levels of the remaining bit cells within each column (e.g., their output capacitors) are accumulated to provide the accumulated / aggregated analog signal.

[0010] The scaling stage may include a signal divider, such as a charge divider or a charge divider network, where the total charge provided by the bit cells in a column of bit cells is divided according to the corresponding weighted values ​​of the column to provide a charge level or an analog signal representing it. This may be performed before the ADC so that the accumulated / aggregated analog signal presented to the ADC is properly scaled, or it may be performed in connection with the sample-and-hold (S / H) operation of the ADC, such as by selective switching of charge divider elements in a successive approximation ADC.

[0011] Some embodiments provide a device for scaling and aggregating multiple weighted data representation analog signals, each analog signal comprising voltages associated with multiple coupled bit cell outputs in an in-memory computing (IMC) array of bit cells, and the device comprising multiple charge-dividing circuits, each signal-dividing circuit configured to process each weighted data representation analog signal to generate an output signal across each output capacitor with a capacitance value scaled according to its respective weight, and during the measurement phase of the calculation, the output capacitors of the charge-dividing circuits are coupled to a sample-and-hold circuit associated with the input of an analog-to-digital converter (ADC) configured to generate a digital output from which an aggregate of the weighted data representation analog signals is generated.

[0012] Further objects, advantages, and novel features of the present invention are partially described in the following description and will be partially apparent to those skilled in the art through the following considerations or will be known through the practice of the present invention. The objects and advantages of the present invention will be realized and achieved by means and combinations particularly indicated in the appended claims.

[0013] The accompanying drawings incorporated herein and constituting part thereof illustrate embodiments of the present invention and, together with the general description of the present invention above and the detailed description of embodiments below, are useful in illustrating the principles of the present invention. [Brief explanation of the drawing]

[0014] [Figure 1] This diagram illustrates a typical structure of an in-memory computing architecture. [Figure 2] This shows a block diagram of a fully row / column parallel (1152 rows x 256 columns) array of multiplication bit cells (M-BCs) for an in-memory computing (IMC) macro that enables N-bit (5-bit) input processing. [Figure 3] Figure 2 shows a circuit architecture for a multiplication bit cell suitable for use in the M-BC array. [Figure 4A] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 4B] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 4C] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 4D] This diagram illustrates the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. [Figure 5] This is a diagram illustrating an example of an IMC column within an M-BC sequence. [Figure 6] This diagram illustrates an example of binary weighting scaling within a bit cell array in an in-memory computing architecture, which is useful for understanding the embodiments. [Figure 7] The schematics show various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. [Figure 8] The schematics show various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. [Figure 9]These are schematic diagrams of various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. [Figure 10] Circuit diagrams of various embodiments of a binary weighted current division scaling circuit suitable for use in various embodiments are shown. [Modes for carrying out the invention]

[0015] Please understand that the attached drawings are not necessarily to scale and represent various features illustrating the basic principles of the present invention in a somewhat simplified manner. Specific design features of the series of operations disclosed herein, such as the specific dimensions, orientation, position, and shape of various illustrated components, are determined in part by the specific intended use and operating environment. Certain features of the illustrated embodiments are enlarged or distorted compared to others to facilitate visualization and clear understanding. In particular, thin features may be represented in bold for clarity and explanatory purposes.

[0016] The following description and drawings are merely illustrative of the principles of the present invention. Therefore, those skilled in the art will understand that various modifications embodying the principles of the present invention and falling within its scope can be devised, even if not explicitly described or shown herein. Furthermore, all examples cited herein are explicitly intended solely for educational purposes, primarily to help the reader understand the principles of the present invention and the concepts provided by the inventor(s) to further advance the art, and should be construed as not being limited to such specifically cited examples and conditions. Furthermore, the term “or” as used herein means non-exclusive “or” unless otherwise indicated (e.g., “or, otherwise” or “or, in an alternative”). Also, since some embodiments can be combined with one or more other embodiments to form new embodiments, the various embodiments described herein are not necessarily mutually exclusive.

[0017] Numerous innovative teachings of this application are described with particular reference to currently preferred exemplary embodiments. However, it should be understood that these types of embodiments provide only a few examples of the many advantageous applications of the innovative teachings herein. In general, the descriptions made in the specification of this application are not necessarily limited to the various inventions claimed. Furthermore, some descriptions may apply to certain inventive features but not to others. Those skilled in the art and who have gained knowledge from the teachings herein will understand that the invention is applicable to a variety of other technical fields or embodiments.

[0018] Before describing the present invention in further detail, it should be understood that the present invention is not limited to the specific embodiments described and, therefore, can, of course, be modified. It should also be understood that the scope of the present invention is limited only by the appended claims, and therefore the terms used herein are intended solely to describe and not to limit specific embodiments.

[0019] Where a range of values ​​is provided, it should be understood that each intermediate value between the upper and lower limits of that range, and any other stated or intermediate values ​​within the stated range, are included in the present invention. Unless otherwise explicitly indicated in the context, these intermediate values ​​are up to one-tenth of the lower limit. These smaller upper and lower limits may independently be included within the smaller range and are also included in the present invention, subject to any specific excluded limitations within the stated range. Where a stated range includes one or both of the limit values, ranges excluding one or both of those limit values ​​are also included in the present invention.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which the present invention pertains. Any methods and materials similar to or equivalent to those described herein may also be used in the practice or testing of the present invention, but only a limited number of exemplary methods and materials are described herein. Note that, as used herein and in the appended claims, the singular forms “a,” “an,” and “the” include multiple references unless the context explicitly indicates otherwise.

[0021] Various embodiments will be considered within the context of an IMC computing architecture that obtains computation results across multiple bits stored in memory, such as computation results derived in memory columns. In this case, parallel input data is fed into rows, computations (e.g., multiplication) are performed by memory bit cells where the data is stored, and further computations (e.g., accumulation) are performed on column bit lines, so that each column bit line is supplied with a corresponding analog output signal representing the computation result associated with each bit line, which is described herein exemplary as being provided as a charge level, but in alternative embodiments, the analog output of a column may consist of a current level or a voltage level.

[0022] Some of the various embodiments relate to IMC computing architectures, apparatus, methods, and parts thereof configured to obtain computational result display outputs of multiple parallel columns or bit lines in a manner that does not require the use of a separate analog-to-digital converter (ADC) for each column or bit line. That is, rather than converting the analog output signal associated with each bit line or column into a separate digital representation suitable for further processing within the IMC computing architecture, various embodiments use the analog output signal associated with the bit line or column to perform some of this further processing, thereby reducing the number of ADCs required to perform the functions of the IMC computing architecture while maintaining the accuracy of the analog output signal (i.e., reducing the effects of ADC quantization errors and other errors).

[0023] Figure 1 illustrates a typical structure of an in-memory computing architecture. Specifically, the in-memory computing architecture 100 shown in Figure 1 includes a memory array (which may be based on standard bit cells or modified bit cells), and in-memory computing involves two further "vertical" signal sets: (1) input lines and (2) accumulation lines. Referring to Figure 1, it can be seen that a two-dimensional array of bit cells is shown, where each of the multiple in-memory computing channels 110-1 to 110-N (collectively, in-memory computing channels 110) contains a column of bit cells, and each bit cell within a channel is associated with a common accumulation line and bit line (column), and its own input line and word line (row). Note that the columns and rows of signals are described as "perpendicular" to each other in this specification, but this is simply to indicate the row / column relationship in the context of an array of bit cells, such as the two-dimensional array of bit cells shown in Figure 1. The term "perpendicular" as used herein is not intended to convey any specific geometric relationship.

[0024] The input / bit sets and cumulative / bit sets of signals may be physically combined with existing signals in memory (e.g., word lines, bit lines) or they may be separate. To perform matrix-vector multiplication, the matrix elements are first loaded into the memory cell. Then, multiple input vector elements (possibly all) are applied simultaneously via the input lines. This performs a local computational operation, typically some form of multiplication, at each memory bit cell. The result of the computational operation is sent to a shared cumulative line. In this way, the cumulative line represents the result of a computation across multiple bit cells activated by the input vector elements. This is in contrast to standard memory access, where bit cells are accessed one at a time via bit lines and activated by a single word line.

[0025] The in-memory computing described has several important characteristics. First, the computation is typically analog. This is because the constrained structure of memory and bit cells requires a richer computation model than would be possible with a simple digital switch-based abstraction. Second, local operations on bit cells typically involve computation using the 1-b representation stored in the bit cell. This is because bit cells in a standard memory array do not couple to each other in a binary weighting scheme. Such coupling must be achieved by methods of accessing / reading bit cells from the periphery. The extensions of in-memory computing proposed in this invention are described below.

[0026] In memory computing, while conventional digital acceleration may be insufficient for handling matrix-vector multiplication, a typical computation pipeline will involve various other operations surrounding matrix-vector multiplication. Typically, such operations are adequately handled by conventional digital acceleration. However, to address the parallelism and high throughput (and therefore the need for high round-trip bandwidth) associated with in memory computing, and common computation patterns, placing such acceleration hardware close to the in-memory computing hardware in a suitable architecture can yield significant benefits. Since many peripheral operations are preferably performed in the digital domain, analog-to-digital conversion via ADCs is included following each in-memory computing cumulative line, referred to as the in-memory computing channel. The main challenge is integrating the ADC hardware at a pitch with each in-memory computing channel, but this is made possible by the appropriate layout approach employed in this invention.

[0027] Introducing an ADC following each computing channel enables an efficient method for extending in-memory computing, supporting multi-bit matrices and vector elements via bit-parallel / bit-serial (BPBS) computing, respectively. Bit-parallel computing involves loading bits of different matrix elements into different in-memory computing columns. The ADC outputs from the different columns are then appropriately bit-shifted to represent the corresponding bit weights, and digital accumulation is performed across the group of columns to obtain the multi-bit matrix element computation result. Bit-serial computing, on the other hand, involves applying each bit of the input vector element one at a time, storing the ADC output each time, appropriately bit-shifting the stored output, and then digitally accumulating it with the next output corresponding to the subsequent input vector bits. Such a BPBS approach, enabling a hybrid of analog and digital computing, is highly efficient because it utilizes the high-efficiency low-precision region (1-b) of analog along with the high-efficiency high-precision region (multi-bit) of digital computing, overcoming the access costs associated with conventional memory computations.

[0028] Figure 2 shows a block diagram of a fully row / column parallel (1152 rows × 256 columns) array of multiplication bit cells (M-BCs) of an in-memory computing (IMC) macro that enables N-bit (5-bit) input processing, according to one embodiment.

[0029] An example of the IMC macro in Figure 2 may be used to implement structures such as the compute-in-memory array (CIMA) structure discussed earlier. This example of the IMC macro was rendered via a 28nm manufacturing process and provides fully row / column parallel matrix-vector multiplication (MVM). It utilizes high-precision analog computation based on metal fringe (wire) capacitors, extends binary input vector elements to 5-bit (5-b) input vector elements, and is configured to improve energy efficiency by approximately 16 times and throughput by approximately 5 times compared to the IMC and CIMA embodiments discussed above.

[0030] The embodiments shown in Figures 2 and 3 perform MVM operations, which constitute the majority of computationally and data-intensive AI workloads, in a way that drastically reduces computational energy and data movement. This is achieved by efficiently performing analog calculations at the bit cell level and accessing the calculation result (e.g., the inner product) from memory rather than individual bits. However, this fundamentally introduces an energy / throughput versus SNR trade-off, as the analog approach generates computational noise and accessing the calculation result widens the dynamic range (i.e., reduces the SNR of the given read architecture).

[0031] Advantageously, IMCs based on metal fringe capacitors have very low noise due to analog non-idealism and therefore can have extremely high dynamic range. At least some embodiments utilize this precise capacitor-based calculation mechanism to ensure that improvements in dynamic range, such as those discussed herein, are possible.

[0032] Figure 2 shows a block diagram of the in-memory computing macro 200, which comprises a 1152 (rows) x 256 (columns) array 210 of 10T SRAM multiplying bit cells (M-BCs), peripherals for standard write / read operations thereto (e.g., bit line (BL) decoders 240 and 256 BL drivers 242-1 to 242-256, word line (WL) decoders 250 and 1152 WL drivers 252-1 to 252-1152, and a control block 245 for controlling decoders 240 / 250), peripherals for supplying 5-bit input vector elements thereto (e.g., 1152 dynamic range doubling (DRD) DACs 220-1 to 220-1152, and corresponding controllers 225), and peripherals for digitizing the calculation results from each column (e.g., 256 8-bit SARs). ADC260-1~260-256) and column reset mechanism 265-1~265-256 (for example, resetting the output voltage level of column calculation line CL during the calculation reset phase with voltage V RSTIncludes a CMOS switch that pulls up to a certain point, and is configured so that the voltage level of the column calculation line CL reflects the respective calculation result during the evaluation phase of the calculation.

[0033] The array 210 of 10T SRAM multiplication bit cells (M-BCs) in IMC macro 200 operates in a similar manner to that described above for various figures. In particular, writes / reads are typically performed row by row, while MVM operations are typically performed by applying input vector elements corresponding to the input activations of the neural network to all rows or some rows at once. That is, each DRD-DAC220 j Each of the 5-bit input vector elements X j [4:0] In response to each differential output signal (IA j / IAb j This generates a differential output signal for each M-BC in the corresponding row of the M-BC. j Then, the stored weight (W ij / Wb ij It is subjected to a 1-bit multiplication with ), accumulated through charge redistribution across the M-BC capacitors on the calculation line (CL), to obtain the dot product of each column, which is then digitized via the respective ADC260 of each column. The operations of the individual 10T SRAM M-BCs forming array 210 will be discussed in more detail below with respect to Figure 3.

[0034] Figure 3 shows the circuit architecture of a multiplying bit cell (M-BC) according to an embodiment, which is suitable for use when implementing the 10T SRAM M-BC in Figure 2 and array elements similar to those described above for various figures. The M-BC300 in Figure 3 includes a high-density structure for achieving weight storage and multiplication, thereby minimizing data broadcast distance and control signals within the context of an i-row j-column array implemented using an M-BC, such as an i-row j-column array 210 of 1152 (rows) × 256 (columns) array 210 of 10T SRAM multiplying bit cells (M-BCs).

[0035] An example of the M-BC300 includes a six-transistor bit cell section 320, a first switch SW1, a second switch SW2, a capacitor C, a word line (WL) 210, a first bit line (BLj) 312, a second bit line (BLbj) 314, and a calculation line (CL) 315.

[0036] The six-transistor bit cell section 320 is shown to be located in the central part of the M-BC300 and includes six transistors 304a to 304f. The six-transistor bit cell section 320 can be used for storing and reading / writing data. In one example, the six-transistor bit cell section 320 stores filter weights. In some examples, data is written into the M-BC300 via the word line (WL) 310, the first bit line (BL) 312, and the second bit line (BLb) 314.

[0037] The multiplication bit cell 300 includes a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW1, when closed, is shown to be controlled by a first activation signal A (A ij ) such that SW1 couples one of the received differential output signals supplied by the DRD-DAC 220, illustratively IA, to the first terminal of the capacitor C. The second switch SW2, when closed, is shown to be controlled by a second activation signal Ab (Ab ij ) such that SW2 couples the other of the received differential output signals of the corresponding DRD-DAC 220, illustratively IAb, to the first terminal of the capacitor C. The second terminal of the capacitor C is connected to the calculation line (CL). Note that in various other embodiments, the input signals supplied to the switches SW1 and SW2 may include a fixed voltage (e.g., V dd ), ground, or other voltage levels.

[0038] The M-BC300, including the first SW1 switch and the second SW2 switch, can perform calculations on the data stored in the 6-transistor bit cell section 320. The calculation result is driven as the charge of capacitor C. In various implementations, capacitor C may be located above the bit cell 300, and no other area on the circuit may be used. In some implementations, V dd Either the logic value of or ground is driven by capacitor C. In other embodiments, the voltage driven by capacitor C may include positive or negative voltages, depending on the operation of switches SW1 and SW2 and the corresponding output voltage levels generated by the DRD-DAC220.

[0039] Therefore, the charge stored in capacitor C (as a function of the drive voltage) is very stable because the value of capacitor C itself is very stable and the drive voltage is very stable (for example, driven up to the power supply voltage or to ground). In some examples, capacitor C is a metal-oxide-metal (MOM) finger capacitor, and in some examples, capacitor C is a 1.2fF MOM capacitor. MOM capacitors have excellent temperature and process characteristic matching, allowing for highly linear and stable calculation operations. Furthermore, by changing the connection method and / or operation method of transistor 304 and / or switches SW1 and SW2 during the reset and evaluation phases of the M-BC calculation, other types of logic functions can be implemented using M-BC.

[0040] In various implementations, the 6-transistor bit cell section 320 may be implemented using a different number of transistors and have a different architecture. In some examples, the bit cell section 320 may be SRAM, DRAM, MRAM, or RRAM. Improved IMC cumulative and M-BC output scaling

[0041] As discussed above with respect to Figure 2, the N=5 (5-bit) input processing in-memory computing (IMC) macro 200 assumes a fully row / column parallel (1152 rows × 256 columns) array of multiplication bit cells (M-BCs) like the M-BC300 described above with respect to Figure 3. Furthermore, it should be noted that the IMC macro 200 is indicated to use one 8-bit analog-to-digital converter (ADC) for each of the connected columns of M-BCs in the array 210. That is, the analog output signals provided by each of the 256 exemplary columns are individually converted to their respective 8-bit digital representations by their respective 8-bit ADCs before further processing, as discussed above and in various related patent applications.

[0042] In particular, various embodiments are described below within the context of an IMC architecture configured to combine the outputs of multiple parallel columns, such as when multiplication with multibit data stored in bit cells is required, but the bit precision cannot be adjusted within a single bit cell. In this case, bit parallelism can be employed, where the most significant bit of the stored data is in the bit cell of one column, the next most significant bit of the stored data is in the bit cell of the next column, and so on, down to the least significant bit of the stored data (usually all bits of the stored data elements are in the same row). In this case, each column represents a component corresponding to a specific bit weighting of the computation output. Due to the linear nature of the multiplication and accumulation operation, the overall computation output can be derived by scaling each column output with appropriately binary-weighted coefficients and aggregating the differently scaled column output components. In general, the bit weighting of data stored in different columns does not need to be binary. This is easily supported by applying scaling coefficients (which do not necessarily need to be binary weights) corresponding to each column output.

[0043] Scaling and aggregation of the calculation result output of multiple parallel columns or bit lines can be performed before or after the ADC. If performed before the ADC, the scaling and aggregation operations must be applied to the corresponding analog signals, which can be voltage, current, charge, etc.

[0044] For example, in the context of an in-memory computing (IMC) array of bit cells configured to multiply two vectors (or a vector and a scalar), each element of V1 is multiplied by each element of V2, and the sums are accumulated to obtain the result. Multiple bits of the vector V1 stored in memory are mapped to multiple columns, and the input bits of the input vector V2 are sequentially fed into each column, with multiplication and bit shifting being repeated. Each column (in this example) contains the respective total voltage or stored charge associated with the weighted result (e.g., bit position in a multi-bit word), and exemplify this by a binary weighted result such as a 4-bit binary word (MSB, MSB-1, MSB-2, LSB) representing the result of multiplying each element of the stored vector V1 by a 4-bit input vector V2.

[0045] Instead of performing a bit shift in the digital domain after the A / D conversion of the columns to resolve the multiplication result (e.g., the result of multiplying all input vector elements by all stored vector elements), various embodiments provide, for the analog domain, a scaling of all voltages or stored charges associated with each column according to a weighting or scaling factor (e.g., bit position) of the columns, and an accumulation of the scaled voltages / charges for each column, providing an analog representation of the multiplication result (e.g., an analog voltage / charge level representing the result of multiplying a 4-bit input vector V2 with each element of the stored vector V1). This accumulated voltage / charge level is then subjected to A / D conversion to provide a digital representation of the final multiplication result. For example, for a 4-bit input vector, instead of performing 4 cycles of bit-parallel bit-series operations, the 4 bits are represented at analog levels, requiring only one cycle.

[0046] Figures 4A and 4B illustrate the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments.

[0047] Specifically, each mechanism is shown as scaling and aggregating four calculation result display outputs, each output representing one of four columns or bit lines representing voltage levels associated with the charge stored in each column of the connected bit cell output capacitor, and this voltage level represents each weighted portion of the cumulative result, such as the binary weighted portion of the cumulative result. As shown, the four columns b, b+1, b+2, and b+3 represent the binary weighted data of the cumulative 4-bit calculation result, with the most significant bit (MSB) represented by column b and the least significant bit (LSB) represented by column b+3.

[0048] As shown in Figures 4A to 4B and as generally described herein, each of the four IMC columns (IMCb to IMCb+3) supplies the respective voltage signal or voltage level, which represents the respective binary weighted portion of the cumulative result, stored across the multi-bit cell output capacitors that form the column.

[0049] In various embodiments, instead of voltage signals / levels, each of the four IMC columns (IMCb to IMCb+3) may provide a current signal / level or other type of signal / level to represent the respective binary weighted portion of the cumulative result for each IMC column (e.g., a signal such as a current or voltage signal provided by a buffer circuit, or a signal provided by a resistor or transistor-based voltage or charge divider circuit rather than an IMC output capacitor and / or a capacitor-based voltage or charge divider circuit). Furthermore, instead of using binary weighting and / or scaling, other embodiments may use other types of weighting and / or scaling depending on the application, the components selected for the IMC, and / or other factors. Thus, various embodiments provide a mechanism for selectively attenuating or amplifying the weighted signal (or whatever type is used) according to its weighting coefficient, and after aggregation, providing an aggregated signal level (voltage level, current level, charge level, etc.) representing the cumulative result. The mechanism in Figure 4A assumes scaling and aggregation of the cumulative weighted portion of the calculation result before ADC processing.

[0050] As shown in Figure 4A and as generally described herein, each of the four IMC columns (IMCb to IMCb+3) supplies its respective voltage signal or voltage level, representing each binary weighted portion of the cumulative result, stored across the multiple bit cell output capacitors that form the column. These voltage signals / levels are scaled to reflect their respective binary weights relative to each other. Specifically, the LSB column (b+3) has a scaling factor of 2 0 =1 is multiplied, and the next column (b+2) has a scaling factor of 2 1 =2 is multiplied, and the next column (b+1) has a scaling factor of 2 2 =4 is multiplied, and the last column (b) has a scaling factor of 2 3 The voltage levels are multiplied by 8. The scaled voltage levels are then aggregated to form a cumulative voltage level, which is then converted into a digital representation by an ADC converter.

[0051] The mechanism in Figure 4B assumes scaling and aggregation of the cumulative weighting portion of the calculation results related to ADC processing. Specifically, the scaling and aggregation functions described in relation to Figure 4A are implemented by changing various parameters of the ADC calculation, as will be discussed in more detail below.

[0052] Figures 4A and 4B show cases where four columns are combined before or within the ADC, but generally any number of columns can be combined in this way. Furthermore, such scaling and aggregation before / within the ADC can be combined with scaling and aggregation across any number of outputs after the ADC. This involves the application of digital scaling factors (which reduce bitwise shifts for binary weighting) and aggregation in the digital domain. As will be discussed later, this allows for optimal management of the effects of quantization errors, in addition to optimizing the practicality of implementation.

[0053] Figures 4C to 4D illustrate the scaling and aggregation mechanisms of the calculation result display output, which are useful for explaining various embodiments. The above considerations regarding Figures 4A to 4B can generally be applied to Figures 4C to 4D. Note that in Figures 4C to 4D, the LSB column (b+3) has a scaling factor of 1 / 2. 0 Multiply by and add a scaling factor of 1 / 2 to the next column (b+2). 1 Multiply by this, and in the next column (b+1) add a scaling factor of 1 / 2 2 Multiply by and add a scaling factor of 1 / 2 to the last column (b). 3 A scaling function is assumed that multiplies by a certain factor. The scaled voltage levels are then aggregated to form a cumulative voltage level, which is then converted into a digital representation by an ADC converter. Capacitor-based analog scaling and aggregation

[0054] Figure 5 illustrates an example of an IMC column within the M-BC sequence. As shown in Figure 5, each of the columns (1 to N) of M-BC300 is an input (IA 1 / IAb1~IA N / IAb N ) weighted value (W b,1 ~W b,N ) is multiplied by and the respective results are provided as output voltages stored in the respective output capacitors, which are selectively output in the output column CL b They may be coupled. In particular, Figure 5 shows the use of swap capacitors, which perform column accumulation (subtraction) operations via charge redistribution across the capacitors of a particular column. Essentially, the individual bit cell capacitors form legs of a signal division circuit, such as a voltage / charge division circuit, so that the output voltage (i.e., the node that couples all the capacitors) settles to the average of the entire voltage / charge division input (i.e., the driving side of the legs). Such an average provides a scaled / normalized version of the accumulation, where the scaling factor is set by the total capacitance to which the charge is distributed (i.e., V = Q / C). As a result, scaling and aggregation of column output voltages can be achieved by setting the capacitances involved and short-circuiting the involved column capacitances across columns.

[0055] According to various embodiments, capacitor-based analog scaling and aggregation may be achieved through several approaches, as described below. Exemplary examples include (1) setting and shorting a column capacitance, and (2) sampling the column voltage over an auxiliary capacitance, followed by setting and shorting the auxiliary capacitance (where the auxiliary capacitance may be combined with an ADC sample-and-hold circuit). Column capacity setting and short circuit

[0056] Capacitance-based IMCs typically involve two stages: (1) Reset. The charge on all capacitors is reset by shorting the capacitor coupling nodes to a specific reference voltage. (2) Evaluation. The capacitor coupling nodes are released from the short circuit to the reference voltage, and the input legs of a signal divider circuit, such as a voltage / charge divider, are driven (via bit cells). After this, an ADC can sample and then digitize the output voltage of each column.

[0057] An additional step can be added before the ADC to perform analog scaling and short-circuiting between columns, which is referred to herein as scaling. After the column output voltage stabilizes, all couplings between column capacitors can be disconnected, and the remaining capacitance of the entire short-circuited column, scaled, can be obtained. The short-circuit capacitance between columns can then be sampled and digitized by the ADC. This approach is illustrated in Figure 6 as an example for binary weighted scaling.

[0058] Figure 6 illustrates an example of binary weighting scaling within a bit cell array of an in-memory computing architecture, which is useful for understanding this embodiment. Specifically, Figure 6 shows four IMC columns (CL) of multiplying bit cells. b ~CL b An example of an arrangement of bit cell output capacitors for eight IMC rows (R1~R8) by +3) is shown, where each IMC row is a switch (S b ~S b+3 The array is selectively coupled to the ADC input via ). The array is further coupled to the CL between rows R7 and R8. b+3 , CL between lines R6 and R7 b+2 , CL between lines R4 and R5 b+1 Each of these includes an additional switch S. The additional switches S are introduced into the column at these locations, disconnecting / connecting some of the column capacitors at different positions in the column.

[0059] During the calculation reset phase and the calculation evaluation phase, the additional switch S is closed, thereby enabling the joining of all capacities in the column. During the calculation scaling phase, the additional switch S is opened, and the remaining column capacities are joined by the column switch S. b ~S b+3 This causes a short circuit, and the resulting signal is supplied to the ADC.

[0060] Furthermore, if the capacitance C of each output capacitor is substantially the same, the use of an additional switch S will result in a greater charge contribution to the subsequent signal voltage of a column with more output capacitors. Thus, a column CL with eight bit cell capacitors will have a larger charge contribution. b This is a column CL with four bit cell capacitors. b+1 Effectively weighted twice as much as the weight of column CL b+1 This is a column CL with two bit cell capacitors. b+2 Effectively weighted twice as much as the weight of column CL b+2 This is a column CL with one bit cell capacitor. b+3 It is effectively weighted twice as much as the original weight.

[0061] Given the charge weighting achieved by using the additional switch S, the resulting voltage signal applied to the ADC represents a scaled cumulative power signal, which can then be directly digitized by the ADC to provide a digital representation of the cumulative power signal.

[0062] The inventors note that introducing a switch (whether to disconnect a column capacitor coupling or to enable a short circuit between column capacitances) adds parasitic capacitances, and these parasitic capacitances also need to be appropriately weighted (binary or otherwise) for accurate scaling and aggregation of the entire column. Thus, in various embodiments, a parasitic offset switch S PO Alternatively, add other structures to the array to balance all switch-related parasitic capacities within the column.

[0063] Parasitic offset switch S POOther structures may include functional or non-functional switches. For example, for each additional switch S functioning as described above in the row, the substrate used to form the bit cell array (e.g., a VLSI substrate) may include similar functional or non-functional (e.g., normally closed) switches.

[0064] Therefore, in some embodiments where binary weighting is used, in addition to the additional switch S that operates in the column to perform weighting as described herein, there are parasitic offset switches S of a similar structure in one or more other columns. PO This is formed in the corresponding location to avoid differences in capacity between columns. This technique may also be used in embodiments that implement weighting schemes other than binary weighting. Parasitic offset switch S PO The number and location of the parasitic offset switches S may be changed depending on the manufacturing technology and other factors, and importantly, the parasitic offset switches S should be used to balance or offset the parasitic capacitance added to the circuit by the additional switches S so as to avoid the associated scaling errors as much as possible. PO It is simply about forming it. Auxiliary capacitance sampling, setting, and short circuit

[0065] In other embodiments, instead of using the same capacitor for both column calculations and scaling operations across columns, the voltage of each group of column capacitors is first sampled via an auxiliary sampling capacitor in a signal division circuit (i.e., a capacitor network configured for charge sharing / sampling), such as a voltage / charge division circuit, and the auxiliary sampling capacitor associated with a column has a value selected to produce a scaled output appropriate for that column. The sampling capacitors may include additional capacitors formed for each column, sample-and-hold capacitors in the ADC itself (integrated within the ADC or separate from the ADC), or other capacitors.

[0066] In these embodiments, the signal associated with a particular column is sampled through an auxiliary capacitor of a charge division circuit associated with that column, which may be selectively coupled to that column or division circuit.

[0067] Various embodiments envision processing the signals associated with each column via a weighted input ADC. A weighted input ADC is an ADC having multiple inputs, each of which is weighted, and the resulting weighted signals may be aggregated for ADC processing, thereby providing a digital output signal.

[0068] Figures 7–9 show schematics of various embodiments of binary weighting scaling in the vicinity of or within the output ADC of an in-memory computing architecture. While the embodiments in Figures 7–9 are generally shown and described as processing voltage signals provided by the charge stored in the entire bit cell output capacitor as described above, the embodiments may also be used to process other types of signals (e.g., voltage, current, etc.) as previously considered in relation to Figures 4A–4B.

[0069] Figure 7 shows a circuit diagram useful for understanding various embodiments. Specifically, the circuit 700 in Figure 7 envisions multiple (e.g., four) capacitive circuits, each of which operates to share a portion of the charge stored across multiple bit cell output capacitors with its respective sampling capacitor or auxiliary capacitor(s), providing therewith a respective voltage output signal representing each weighted portion of the cumulative result, and the voltage sampled across the sampling capacitor or auxiliary capacitor(s) is provided to the ADC for further processing.

[0070] It is important to note that the sampling operation of the auxiliary capacitor is achieved by the charge sharing operation. Therefore, sampling is performed by the coefficient C of the sampled voltage. COL / (CCOL +C AUX This reduces to scaling by C, where COL C is the total column capacity. AUX This is the auxiliary sampling capacity. Therefore, C COL and C AUX To ensure sufficient matching across the entire column and reduce errors, C AUX It is important to discharge it completely at the start. After that, C AUX The data is split into binary-weighted components, and the appropriately binary-weighted components are short-circuited for accurate scaling and aggregation.

[0071] Specifically, the capacitance of a charge-dividing circuit (or more broadly, a signal-dividing circuit) is important if the capacitance-sharing mechanism is a scaling (binary weighting or otherwise) mechanism in the case of charge-sharing events, such as sharing the charge stored across multiple bit cell output capacitors with the corresponding capacitor voltage / charge-dividing circuit. In this case, load-balancing capacitors are used (as shown in Figures 7-9) to ensure that each capacitor charge-dividing circuit has substantially the same capacitance.

[0072] In addition to charge sharing, scaling can be achieved by other means alone or in combination in various embodiments. For example, in various embodiments, scaling of each weighted data representation analog signal may be achieved via charge, voltage, current, or impedance scaling techniques (e.g., using weighted or binary weighted capacitor division networks, resistor division networks, etc.), depending on the nature of the analog signal being scaled. As most frequently shown herein, various embodiments provide charge division circuits based on capacitive charge sharing or redistribution to scale charge-based or voltage-based weighted data representation analog signals.

[0073] Generally speaking, each of multiple weighted data representation analog signals (e.g., column-by-column binary weighting) is scaled such that the analog signal contribution (charge, voltage, current, etc.) of a particular weighted data representation analog signal to the total signal level or cumulative signal level of all the various weighted data representation analog signals is proportional to the weight of that data representation analog signal (e.g., the weight associated with the column position of that data representation analog signal).

[0074] For example, if the bit cell calculation output is provided through a resistive / conductive output impedance (rather than a capacitive one), the scaling circuit may include resistive scaling or signal division components, transistor scaling or signal division components, or other scaling or signal division components suitable for representing the weighting / scaling of charge levels or signals indicating charge levels (e.g., voltage / charge division circuits, charge sharing networks, etc.). In this case, since the stable signal does not depend on capacitive loading, there is no need to use load balancing capacitors.

[0075] In this binary weighting example, column CL b The signal sampled from is from column CL. b+1 The signal is given twice the weight, and column CL b+1 The signal is column CL b+2 The signal is given twice the weight, and column CL b+2 The signal is column CL b+3 Twice the weight is given. Thus, as can be seen in Figure 7, various switches are controlled so that the capacitance of the voltage / charge divider circuits in each column is the same (i.e., C), but the sampling capacitor or auxiliary capacitor of each voltage / charge divider circuit is different. Specifically, column CL b The sampling capacitor or auxiliary capacitor is C(C / 2+C / 2), and column CL b+1 For C / 2, column CL b+2 For C / 4, column CL b+3The capacitance for is C / 8. The signals present in each sampling capacitor or auxiliary capacitor represent the respective scaled portions of the cumulative result, and a digital representation of the cumulative result may be generated by connecting each of the sampling capacitors or auxiliary capacitors in the column together and supplying the signals to the ADC. As shown, the capacitances of the voltage / charge divider circuits in each column are made the same so that errors due to charge sharing events are equalized across the voltage / charge divider circuits and no relative errors occur between the voltage / charge divider circuits.

[0076] Figure 8 shows a circuit diagram useful for understanding various embodiments. Specifically, Figures 8 and 9 show the voltage / charge division circuit of Figure 7, where the voltage sampled across all sampling capacitors or auxiliary capacitors is combined with a sample-and-hold (SH) of a successive approximation register (SAR) ADC during charge-sharing events (e.g., during the measurement or evaluation phase of the operation), and the SH also functions as a feedback digital-to-analog converter (DAC). This approach allows for a compact layout, which is desirable for IMC readout ADCs.

[0077] Figures 8 and 9 show an 8-bit ADC that receives the cumulative input voltage associated with only four weighted input signals. If eight weighted input signals were processed by the 8-bit ADC, each of the eight weighted input signals would first be scaled by its respective divider circuit. If capacitor divider circuits are used, the capacitance of each of the four additional (e.g., LSB) voltage / charge divider circuits would be the same as that of the first four (e.g., MSB) voltage / charge divider circuits, and each sampling capacitor or auxiliary capacitor would be scaled accordingly (e.g., C / 16, C / 32, C / 64, and C / 128, assuming the four columns represent the next four LSB values ​​of the cumulative result).

[0078] In the context of the S / H SAR ADC shown in Figures 8-9, the S / H is integrated into the ADC. The SAR ADC includes a feedback circuit where the digital-to-analog converter (DAC) is tuned via different digital input signals supplied by the SAR logic to ultimately generate a DAC output voltage corresponding to the analog input voltage supplied to the ADC, thereby determining a digital word or bit representing the analog input voltage to the ADC.

[0079] The analog input voltage is sampled at the lower plate of each sampling capacitor in each voltage / charge division circuit (i.e., the capacitors labeled C, C / 2, C / 4, and C / 8). The voltage associated with the DAC's feedback code is then successively applied to the other plate of the capacitor, thereby generating a binary weighted signal there for comparison purposes (i.e., to determine the ADC output value).

[0080] The circuit 800 in Figure 8 assumes, as an example, that the ADC SH / DAC is divided into four segments to take input from four IMC columns. Each of the four segments has equal capacitance to avoid large relative sampling errors and scaling. Each of the four segments is further divided into a portion to be processed by the ADC for digitization and a portion that is not processed. The portion to be processed corresponds to the binary weighted capacitance of the entire column. The output of each column is sampled on one side of each segment, and only the portion to be processed is then coupled on the other side. The remaining portion is left uncoupled (short-circuited with a reference voltage) on the other side and is then discharged before sampling.

[0081] By combining the segments in this way, scaling and aggregation of the column outputs are performed within the ADC SH / DAC. Subsequently, the SAR is digitized in a standard manner to obtain the final digital output code. As an example, the scaled and aggregated charge is sampled at one end of the SH / DAC, and the other end is driven by a feedbacked digital control signal. This feedbacked digital control signal then introduces a corresponding negative voltage shift to the signal supplied to the comparator. When the negative voltage shift cancels out the voltage due to the sampled charge (i.e., returns the comparator voltage to a fixed reference), the final digital output code is obtained. Other forms of SAR digitization can also be employed, such as separating the DAC from the SH / DAC.

[0082] Figure 10 shows schematics of various embodiments of a binary weighted current division scaling circuit suitable for use in various embodiments. MSB column CL b The weighted data representation analog signal from column CL b+1 The signal weights are effectively weighted twice as much as the column CL. b+1 The signal is column CL b+2 The signal weights are effectively weighted twice as much as the column CL. b+2 The signal is column CL b+3 It can be seen that the signal is effectively weighted twice as much as the signal weight. Advantages and limitations

[0083] The embodiments described above utilize an approach that performs scaling and aggregation in front of the ADC, and have the main advantage that the ADC is shared across aggregated columns within the context of the in-memory computing embodiment. This allows for the amortization of the energy and area consumption of the ADC.

[0084] The approach based on setting up and shorting column capacitors has the special advantage of not requiring the addition of auxiliary capacitors. The advantage of auxiliary capacitors being used in combination with ADC SH is that the complexity of the ADC does not increase (a standard ADC can be used).

[0085] A sampling-based approach to auxiliary capacitors (possibly integrated with the ADC SH and DAC) has the advantage of not requiring additional scaling steps (after reset and evaluation) and not increasing the complexity of the IMC architecture (for example, due to the addition of switches to couple / disconnect between groups of bit cell capacitors).

[0086] Overall, the limitation of analog scaling and aggregation is that the total dynamic range of the signal digitized by the ADC increases. Since the ADC then quantizes the signal to a specific resolution, quantization errors occur. These quantization errors are somewhat mitigated compared to scaling and aggregation after the ADC, where quantization occurs at each column output (i.e., the analog residual cannot be recovered after digitizing each column output, whereas scaling and aggregation before the ADC has one quantization event). However, scaling and aggregation after the ADC has a net advantage in terms of quantization errors due to the lower energy / area cost of increasing the number of digital bits. The quantization errors of scaling and aggregation before the ADC can be reduced by increasing the ADC resolution at the expense of the ADC's energy / area overhead.

[0087] While various embodiments are described primarily within the context of binary weighted scaling factors, they are suitable for use with arbitrary analog scaling of column values. In other words, this disclosure primarily describes structures where columns supplied to a shared ADC have binary weighted scaling factors, but it should be understood that any scaling factor can be used.

[0088] Furthermore, it should be understood that the scaling factor may be configurable. The main advantage of non-binary weighted scaling factors is that alternative numerical formats (i.e., non-binary integers) may be used for the weights of the matrices stored in the memory cells. This is beneficial because quantized neural networks can utilize alternative numerical formats (e.g., where bit positions represent powers such as 1.5, 4, etc., instead of 2) to optimize how they manage the trade-off between weights and dynamic range.

[0089] Furthermore, the total charge signal may be increased compared to a single-column calculation by using uniform scaling factors. This may mitigate the effects of various charge noise sources.

[0090] Furthermore, the ability to set a scaling factor allows the two features described above to be dynamically realized, for example, to optimize different in-memory calculations scheduled during execution time. Such configurability requires configurable capacitor settings across the entire column, which can be achieved using capacitive digital-to-analog converters (DACs) coupled to different column outputs, thus providing digital configuration control.

[0091] Various embodiments assume compensation for overall column capacity mismatch. Specifically, when column scaling is determined by the relative ratio of overall column capacities, deviations in the relative ratio due to parasitic capacities can lead to calculation errors. This is overcome in various embodiments through one of several practical approaches, as discussed herein.

[0092] For example, in some embodiments, critical capacitances are matched through careful layout and parasitic capacitance estimation. In particular, layout features that affect parasitic capacitance are matched within the array or periphery of the array, such as on the substrate or layers of a very large-scale integrated circuit (VLSI) during manufacturing.

[0093] When configuring column capacitances and dealing with short circuits, it is necessary to consider the column switches used to couple / disconnect between the column capacitances. For example, this can be achieved by introducing dummy MOSFET switches (which can be kept statically on or off) to match the parasitic characteristics of the actual MOSFET switches in other columns, or by adjusting the geometry of the MOSFET switches to maintain the intended ratio scaling across the entire column.

[0094] For sampling, setting, and short-circuiting of auxiliary capacitances, this can be achieved by matching the layout of connections from the column to the auxiliary capacitance (and the features around it), as well as matching the layout of the auxiliary capacitance itself.

[0095] Furthermore, capacitive DACs may be coupled to each column output to enable trimmable capacitive loading, which introduces linearly adjustable voltage attenuation and compensates for mismatches in parasitic capacitance.

[0096] As described herein, some of the various embodiments relate to IMC computing architectures, apparatus, methods, and parts thereof configured to obtain computational result display outputs of multiple parallel columns or bit lines in a manner that does not require the use of a separate analog-to-digital converter (ADC) for each column or bit line. That is, rather than converting the analog output signal associated with each bit line or column into a separate digital representation suitable for further processing within the IMC computing architecture, various embodiments use the analog output signal associated with the bit line or column to perform some of this further processing, thereby reducing the number of ADCs required to perform the functions of the IMC computing architecture while maintaining the accuracy of the analog output signal (i.e., reducing the effects of ADC quantization errors and other errors).

[0097] With respect to various figures, the systems, methods, apparatus, mechanisms, techniques, and parts thereof described herein may be modified in various ways, and such modifications are assumed to be within the scope of the invention. For example, while various embodiments described herein show a particular sequence of steps or arrangement of functional elements, various other sequences / arrangements of steps or functional elements may be used within the context of the various embodiments. Furthermore, modifications to embodiments may be considered individually, and the various embodiments may use multiple modifications simultaneously or sequentially, or use a combination of modifications, etc.

[0098] As described above, specific systems, apparatus, methodologies, mechanisms, etc., are disclosed, but it will be apparent to those skilled in the art that many more modifications are possible in addition to those already described, without departing from the concept of the present invention as herein. Therefore, the subject matter of the present invention should not be limited to anything other than the spirit of this disclosure. Furthermore, in interpreting this disclosure, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms “comprises” and “comprising” should be interpreted in a non-exclusive manner as referring to elements, components, or processes, indicating that the elements, components, or processes mentioned may exist with, be used with, or be combined with other elements, components, or processes not explicitly mentioned. Furthermore, the references cited herein are also part of this application and are incorporated in their entirety by reference as if they were fully described herein.

[0099] Although various embodiments incorporating the teachings of the present invention have been shown and described in detail herein, those skilled in the art can easily devise many other various embodiments still incorporating these teachings. Therefore, while the foregoing covers various embodiments of the present invention, other embodiments and further embodiments of the present invention may be devised without departing from its basic scope.

Claims

1. A device for scaling and aggregating multiple weighted data representation analog signals, wherein each analog signal includes voltages associated with multiple coupled bit cell outputs in an in-memory computing (IMC) array of bit cells, and the device The system includes multiple signal splitting circuits, each of which is configured to process a weighted data representation analog signal in order to generate an output signal having a value scaled according to its respective weighting value. An apparatus in which, during the measurement phase of the calculation, the output signal of the signal division circuit is coupled to the input of an analog-to-digital converter (ADC) configured to generate a digital output representing the sum of the weighted data representation analog signals.

2. The apparatus according to claim 1, wherein the signal division circuit includes a voltage division circuit.

3. Each bit cell output is provided through its respective output capacitor. The apparatus according to claim 1, wherein the signal division circuit includes a charge division circuit.

4. The apparatus according to claim 3, wherein at least some of the rows of bit cells are located in separate disconnect switches for disconnecting a first portion of the row of bit cells from the rest of the row of bit cells, such that the analog signals provided by the rest of the row of bit cells are scaled to weights associated with the row.

5. The apparatus according to claim 2, wherein the signal division circuit is integrated with the sample-and-hold circuit in the ADC.

6. The analog signal includes N binary-weighted analog signals, where N is an integer greater than 1, and the device is An LSB signal splitting circuit having a total capacitance C and an output capacitor of C / 2N-1, configured to process an LSB-represented analog signal, and The apparatus according to any one of claims 1 to 5, comprising: an MSB signal splitting circuit having a total capacitance C and an output capacitor C, configured to process an MSB-represented analog signal;

7. An LSB+1 signal splitting circuit having a total capacitance C and a C / N output capacitor, wherein the LSB+1 signal splitting circuit is configured to process an LSB+1 represented analog signal, The apparatus according to any one of claims 1 to 5, comprising an MSB signal splitting circuit having a total capacitance C and an output capacitor of C / 2, configured to process an MSB-represented analog signal.

8. Each analog signal represents the charge stored in the entire set of coupled bit cell output capacitors within the IMC array of the bit cell. The apparatus according to claim 3 or 4, wherein each of the plurality of signal splitting circuits has substantially similar total capacitance, and each output capacitor has capacitance selected to provide a corresponding scaled output signal in response to a portion of the charge stored in the plurality of coupled bit cell output capacitors moving to the output capacitor.

9. The apparatus according to claim 4, further comprising a plurality of switches configured to combine the remaining portions of the column of bit cells with one another, thereby providing an analog signal representing a weighted cumulative result.

10. An analog scaling and aggregation device for capacitor-based in-memory computing (IMC), wherein each bit cell in an N×M array of bit cells provides a voltage level associated with each weighted portion of an IMC operation at its respective output capacitor, and a sequence of bit cell output capacitors storing voltage levels associated with the same weights is coupled to provide an analog signal representing the respective weighted data for that weight, and the device, The system includes multiple signal splitting circuits, each of which is configured to process the respective weighted data representation analog signals of each column of bit cell output capacitors in order to generate an output signal across each output capacitor with capacitance values ​​scaled according to their respective weighting values, An apparatus in which, during the measurement phase of the calculation, the output capacitor of the signal splitting circuit is coupled to a sample-and-hold circuit associated with the input of an analog-to-digital converter (ADC) configured to generate a digital output from which the sum of the weighted data representation analog signals is represented.

11. The apparatus according to claim 10, wherein each column of the weighted data representation analog signal represents a bit of the binary weighted data of the cumulative result of the IMC calculation.

12. During the reset phase of the operation, the charge stored in each of the rows of bit cell output capacitors is substantially removed. During the evaluation phase of the calculation, the charge stored in each of the rows of bit cell output capacitors provides a contribution corresponding to the total charge of each row. The apparatus according to claim 11, wherein during the measurement stage of the calculation, each of the weighted data representation analog signals is scaled according to its weighting level, thereby providing a weighted portion of the analog signal representing the cumulative result processed by the ADC.

13. An analog scaling and aggregation device for capacitor-based in-memory computing (IMC), wherein each bit cell in an N×M array of bit cells provides a voltage level associated with each weighted portion of an IMC operation at its respective output capacitor, and a sequence of bit cell output capacitors storing voltage levels associated with the same weights is coupled to provide an analog signal representing the respective weighted data for that weight, and the device, The invention includes a plurality of signal splitting circuits, each of which is configured to process its respective weighted data representation analog signal to generate an output signal across its respective output capacitors, which are selectively controlled by a successive approximation register (SAR) analog-to-digital converter (ADC), During the reset phase of the operation, the charge stored in each of the rows of bit cell output capacitors is substantially removed. During the evaluation phase of the calculation, the charge stored in each of the rows of bit cell output capacitors provides a contribution corresponding to the total charge of each row. Analog scaling and summarizing device, wherein during the measurement phase of the calculation, switches in one or more rows of the bit cell output capacitors are activated, disconnecting at least a portion of the bit cell output capacitors, the remaining portions of the bit cell output capacitors in each row having a total capacitance reflecting the weighting value of the row, and the remaining coupled capacitors in each row are coupled together and connected to the input of the ADC.

14. A device for scaling and aggregating multiple weighted data representation analog signals, Each weighted data representation analog signal includes an electron voltage, current, or charge provided by each column of combined bit cells in an in-memory computing (IMC) array of bit cells, and the device At least some of the combined bit cell columns are arranged in separate disconnection switches for separating a first portion of the bit cell column from the rest of the bit cell column, and the analog signal provided by the rest of the bit cell column is scaled to a weight associated with the column, with at least some of the combined bit cell columns. The apparatus further comprises a plurality of switches configured to combine the remaining portions of the column of bit cells with each other, thereby providing an analog signal representing a weighted cumulative result.

Images