Semiconductor device manufacturing system and manufacturing method

Abstract

To provide a manufacturing system of a semiconductor device which has a processing yield improved, and provide a manufacturing method of the semiconductor device.SOLUTION: A manufacturing system of a semiconductor device comprises: a wafer stage 200 which has a wafer 205 mounted onto an upper surface; a semiconductor device manufacturing device 101 that is provided with a heater control part for adjusting a plurality of heaters 201a to 201j arranged below a plurality of regions on the upper surface in an inner part of the wafer stage, and an output of a plurality of heater power supplies 202a to 202j supplied to the plurality of heaters, and performs a processing of the wafer; and a wafer temperature calculation system that determines whether or not a first output value of the plurality of heater power supplies calculated previously in order to realize a target temperature in the processing of the wafer is within an allowable range, and when the value is out of the allowable range, calculates a second output value obtained by correcting all of the first output values to a value within the allowable range.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method for setting the wafer temperature in a semiconductor wafer processing system.

Background Art

[0002] With the three-dimensionalization of the structure of semiconductor devices, the demand for manufacturing technologies for uniformly fabricating complex device structures within the wafer plane has been increasing year by year. In the manufacture of semiconductor devices, a process using a plurality of semiconductor manufacturing devices such as an exposure apparatus, a heat treatment apparatus, a dry etching apparatus, a wet cleaning apparatus, a film forming apparatus, and a CMP (Chemical Mechanical Polishing) apparatus is repeated to form a target pattern on the entire surface of the wafer, and chips are fabricated.

[0003] In addition, in order to confirm that the fabricated chips are good chips that meet the target requirements, specific physical quantities such as the dimensions and film thicknesses of the patterns of multiple layers of films formed on the surface of the wafer are measured using semiconductor inspection apparatuses such as a CD-SEM (Critical Dimension Scanning Electron Microscope), OCD (Optical Critical Dimension), STEM (Scanning Transmission Electron Microscope), TEM (Transmission Electron Microscope), an optical film thickness meter, and an ellipsometer. In the measurements using these semiconductor inspection apparatuses, in order to inspect the number of good chips that can be obtained from within the wafer plane, it is common to measure not only one location within the wafer plane but also multiple locations.

[0004] Furthermore, the measurement results obtained in this way, such as dimensions and film thickness, are fed back or feedforward to each semiconductor manufacturing device and reflected in the wafer processing conditions (process conditions). By adjusting the operation of the semiconductor manufacturing device to approach the processing conditions that can obtain the desired wafer surface shape after processing, the number of good chips that can be obtained from a single wafer surface is increased, thereby improving the processing yield. Each such semiconductor manufacturing device is equipped with a control method that allows for feedback or feedforward control based on the measured data, enabling the distribution of specific physical quantities within the wafer surface to be adjusted to the desired level.

[0005] One known method for controlling the in-plane distribution of specific physical quantities, such as pattern dimensions and film thickness, to a desired level is to control the temperature distribution in the in-plane direction of the wafer when processing the wafer in a semiconductor manufacturing apparatus. An example of such prior art is disclosed in Japanese Patent Application Publication No. 2006-228816 (Patent Document 1). Patent Document 1 discloses a method for controlling the in-plane temperature of a heat treatment plate, which is divided into multiple regions and heated separately, in a post-exposure baking process to promote chemical reactions within the resist film after exposure of a resist pattern with an exposure apparatus, thereby controlling the pattern dimensions in the in-plane direction of the wafer held above the heat treatment plate. It also discloses a method for calculating a target temperature distribution in the in-plane direction for uniform pattern formation on the wafer surface from a relationship between the temperature of the heat treatment plate and the pattern dimensions, which has been acquired in advance, and setting the temperature of each region of the heat treatment plate to achieve that temperature distribution.

[0006] Furthermore, Japanese Patent Publication No. 2009-302390 (Patent Document 2) discloses a plasma etching apparatus, which is a type of dry etching apparatus, that calculates the temperature distribution on the wafer surface from the temperature of the refrigerant used to cool the sample stage, the power of heaters arranged in three circular and ring-shaped regions (center, middle, and edge) within a dielectric film covering the upper surface of the sample stage to heat the sample stage, and the temperature of a sensor placed on the sample stage to measure the temperature of the sample stage. In addition, Japanese Patent Publication No. 2013-513967 (Patent Document 3) discloses a plasma etching apparatus that calculates the in-plane temperature distribution for which a uniform pattern is formed on the wafer surface from a previously acquired relationship between wafer temperature and pattern dimensions, and controls the output of heater power to achieve a target in-plane temperature distribution. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2006-228816 [Patent Document 2] Japanese Patent Publication No. 2009-302390 [Patent Document 3] Special Publication No. 2013-513967 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] The above-mentioned conventional technology had problems because it did not adequately consider the following points.

[0009] In other words, in the conventional technology described above, the target in-plane temperature distribution for the formation of a desired semiconductor device circuit pattern on the wafer surface is calculated from a relationship between the wafer temperature and the pattern dimensions, such as the CD (Critical Dimension) value, which have been acquired in advance, and the output of the heater power is adjusted to achieve the target in-plane temperature distribution. However, in reality, the target temperature calculated during wafer processing, or the amount of power supplied to the heater required to achieve it, may exceed the range that the plasma processing apparatus can achieve. In this case, it has been found that the target temperature cannot be achieved, and the formed circuit pattern may not achieve the expected performance, thus impairing the processing yield.

[0010] Thus, one reason why the wafer temperature and heater output values ​​required to achieve the target wafer temperature are calculated to exceed the feasible range of the device is that, due to heat transfer within the wafer, the amount of heat required to achieve the target temperature of a single wafer region is physically difficult to achieve with the heat generation of the heater corresponding to that region. In other words, the inventors' investigations have revealed that, as some of the heat generated by the heater corresponding to one region moves to other adjacent or nearby regions, the amount of heat generated by the heater required to bring the temperature of that single wafer region to the target value may exceed the maximum possible value, or conversely, even if the amount of heat generated is zero, the temperature of that region may exceed the target value, making it impossible to adjust the power supplied to multiple heaters corresponding to multiple regions and the amount of heat generated by them to achieve the target wafer temperature distribution.

[0011] Thus, conventional technologies failed to address the problem that the temperature distribution of the wafer during processing could not be restored to its initial state, resulting in a loss of wafer processing yield.

[0012] The object of the present invention is to provide a semiconductor device manufacturing system and a semiconductor device manufacturing method that improve processing yield. [Means for solving the problem]

[0013] To solve the above problems, the invention provides a means for correcting the wafer temperature distribution, which is difficult to achieve, to a distribution that is feasible.

[0014] In other words, the above objective is to provide a container comprising: a stage located inside a processing chamber within the container, on which a wafer to be processed is placed on its upper surface; a plurality of heaters located inside the stage below a plurality of regions on the upper surface of the stage; and a controller that adjusts the power supplied to these plurality of heaters. A wafer processing apparatus in which the wafer on the stage is processed while the heat generation of the plurality of heaters is adjusted, The controller is achieved by a wafer processing device that adjusts the power so that a second target temperature distribution is obtained by correcting a predetermined first target temperature distribution so that it is possible to bring the wafer during processing to a target temperature. [Effects of the Invention]

[0015] According to the present invention, a target temperature distribution capable of forming a desired shape in the in-plane direction of the wafer is calculated using a relationship between the wafer temperature and a specific physical quantity obtained in advance. Then, the amount of power to be supplied to multiple heaters capable of achieving this target temperature distribution is calculated. Furthermore, the feasibility of achieving this target temperature distribution is determined using the value of the power supply before the wafer is processed. If, as a result, it is determined that the output value from the heater power supply cannot be achieved, a second target temperature distribution that minimizes the objective function among the achievable heater power supply outputs, and the amount of power to be supplied to multiple heaters capable of achieving this second target temperature distribution are calculated.

[0016] This prevents the wafer from failing to achieve the target temperature distribution during processing, thereby reducing the likelihood of wafer processing being halted. Furthermore, it prevents the wafer temperature from deviating from the intended temperature during processing, improving processing yield. [Brief explanation of the drawing]

[0017] [Figure 1]FIG. 1 is a schematic diagram showing the configuration of a semiconductor device manufacturing system according to an embodiment of the present invention. [Figure 2] FIG. 2 is a longitudinal sectional view schematically showing the configuration of a wafer stage included in a semiconductor device manufacturing apparatus according to an embodiment. [Figure 3] FIG. 3 is a plan view schematically showing an example of the arrangement of heater zones on the upper surface of the wafer stage. [Figure 4] FIG. 4 is a schematic diagram showing a heater zone determined to be impossible to realize in a wafer temperature calculation system according to an embodiment shown on a display connected to a semiconductor device manufacturing apparatus. [Figure 5A] FIG. 5A is a flowchart showing the operation flow of a wafer temperature calculation system according to an embodiment. [Figure 5B] FIG. 5B is a flowchart showing the operation flow of a wafer temperature calculation system according to an embodiment. [Figure 6] FIG. 6 is a flowchart showing the operation flow of a wafer temperature calculation system according to an embodiment. [Figure 7] FIG. 7 is a flowchart showing the operation flow of additional operations added to the present embodiment shown in FIG. 5.

Mode for Carrying Out the Invention

[0018] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0019] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited by this embodiment. Also, in the description of the drawings, the same parts are denoted by the same reference numerals. When there are a plurality of components having the same or similar functions, they may be described with the same reference numeral and different subscripts. Also, when it is not necessary to distinguish these plurality of components, the subscripts may be omitted in the description. The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0020] In this disclosure, "surface" may refer not only to the surface of the plate-like member, but also to the interface of a layer contained within the plate-like member that is substantially parallel to the surface of the plate-like member. Furthermore, "upper surface" and "lower surface" refer to the surfaces shown above or below the plate-like member or the layers contained within the plate-like member in the drawing. In addition, "upper surface" and "lower surface" may also be referred to as "first surface" and "second surface."

[0021] Furthermore, "upward" refers to the direction vertically upward when a plate-like member or layer is placed horizontally. The direction opposite to upward is called "downward." Furthermore, "in-plane distribution" refers to the distribution in the in-plane direction. It is also called "distribution in the in-plane direction."

[0022] [Example 1] Examples of the present invention will be described with reference to Figures 1 to 6.

[0023] Figure 1 is a schematic diagram showing the configuration of a semiconductor device manufacturing system according to an embodiment of the present invention. This figure schematically shows the overall configuration of a semiconductor device manufacturing system, and illustrates a semiconductor wafer processing apparatus such as an etching apparatus, which processes a semiconductor wafer to realize the distribution of a specific physical quantity (for example, the shape or dimensions of a circuit pattern formed on the wafer surface) in the in-plane direction of the wafer.

[0024] The semiconductor device manufacturing system in this example includes, within a container, a plurality of semiconductor device manufacturing apparatuses 101 (shown as 101a, 101b, etc. in this figure), each equipped with a sample stage (wafer stage) on which a wafer is placed on the top surface and which has the function of variably adjusting the temperature distribution in the in-plane direction of the wafer, a plurality of wafer measuring devices 102 (102a to 102z) capable of measuring the distribution of specific physical quantities in the in-plane direction of the wafer, and a wafer temperature calculation system 100 that calculates the temperature distribution in the in-plane direction of the wafer processed by the semiconductor device manufacturing apparatus 101. Furthermore, these wafer temperature calculation system 100, the plurality of semiconductor device manufacturing apparatuses 101, and wafer measuring devices 102 are connected to each other via wired or wireless communication means so that they can send and receive signals to each other. For sending and receiving data, it is desirable that the wafer temperature calculation system 100, each semiconductor device manufacturing apparatus 101, and each wafer measuring device 102 are connected to a so-called network such as Ethernet and configured to communicate via the network, but any configuration that allows data to be sent and received to each other is acceptable. For example, the system may be configured to allow data to be exchanged between devices using recording media such as floppy disks, USB memory sticks, SD cards, or CDs, DVDs, or Blu-ray discs (registered trademarks).

[0025] Furthermore, the wafer temperature calculation system 100 includes a arithmetic unit 103 such as a microprocessor, a storage device 104 in which data related to the wafer and software that drives the arithmetic unit 103 are stored in a read / write manner, and an interface 105 that is connected to a network in a communicative manner and sends and receives signals including data, and these are configured to communicate. The wafer temperature calculation system 100 may also be configured in which the arithmetic unit 103, storage device 104 and interface 105 are built into a so-called computer such as a PC or server, and the storage device 104 may be located in a remote location that is connected in a communicative manner. Each semiconductor device manufacturing device 101 and each wafer measurement device 102 do not need to be located inside the same building, and each may be located in a separate building or in a separate location that is connected in a communicative manner.

[0026] Figure 2 is a schematic longitudinal cross-sectional view showing the configuration of a wafer stage in a semiconductor device manufacturing apparatus according to an embodiment. Each semiconductor device manufacturing apparatus 101 in this example has a wafer stage 200, as shown in Figure 2, inside a processing chamber within a container. The wafer stage 200 has a disc or cylindrical shape with a common central axis with the central axis of a cylindrical processing chamber, and is equipped with a plurality of heaters 201 (201a to 201j) arranged inside along the upper surface of its metal substrate, and multiple concentric or spiral arrangements inside the substrate below the heaters 201, through which a coolant for cooling the wafer flows.

[0027] By adjusting the heat output of multiple heaters 201 and the temperature of the refrigerant flowing through the refrigerant channel 204, the temperature distribution in the in-plane direction of the wafer 205 is adjusted while the wafer 205 is placed and held on the dielectric film covering the upper surface of the wafer stage 200. In the wafer stage 200 of this example, each heater 201 is positioned below each of the multiple zones corresponding to the radial or circumferential division of the upper surface of the wafer stage 200 on which the wafer 205 is placed, and each heater 201 constitutes multiple heater zones. Heater power supplies 202 (202a~202j) electrically connected to each heater 201 receive command signals from the heater control unit 203 which is communicably connected to them, and the value of the power (current or voltage) output based on the command signal is adjusted so that the heat output and temperature of each heater zone, and consequently the temperature of the region of the placed wafer 205 corresponding to the heater zone, are adjusted to a value within a range suitable for processing.

[0028] Although not shown in Figure 2, temperature sensors for detecting the temperature of the substrate of the wafer stage 200 may be placed inside the substrate below each heater zone. Furthermore, the output from the temperature sensors can be transmitted to the heater control unit 203, and the detected temperature information can be fed back or feedforward to adjust the output of the heater power supply 202.

[0029] Furthermore, the refrigerant circulates between the refrigerant flow path 204 and a refrigerant temperature controller connected via a pipeline (not shown), and is regulated to a predetermined temperature range in the refrigerant temperature controller. If necessary, multiple refrigerants set to different temperatures may be supplied to each of the refrigerant flow paths 204. Also, the wafer stage 200 can be configured without the refrigerant flow path 204 if sufficient temperature control is possible within the wafer surface.

[0030] In Figure 2, the refrigerant flow path 204 is located below the heater 201, but the refrigerant flow path 204 can also be installed above the heater. In addition, although not shown in Figure 2, the wafer stage 200 is equipped with a holding mechanism such as a mechanical chuck, vacuum chuck, or electrostatic chuck that can hold the wafer 205 placed on its upper surface and suppress displacement.

[0031] Figure 3 shows an example of the heater zone on the top surface of the wafer stage 200 as seen from above. Figure 3 is a schematic plan view showing an example of the arrangement of the heater zone on the top surface of the wafer stage. Figure 3(a) shows an example of a pattern in which the heater zone is divided into a grid, and Figure 3(b) shows an example of a pattern on concentric circles.

[0032] In this example, the size, arrangement, and number of heater zones are not limited to those illustrated in Figure 3, as long as the desired temperature distribution in the in-plane direction of the wafer 205 is achieved by appropriately selecting the shape and position of the heater 201 or the output of the heater power supply 202.

[0033] In each semiconductor device manufacturing apparatus 101, a specific correlation exists between the output (heat generation) of the multiple heaters 201 provided in each apparatus, or the output from the heater power supply 202 and the temperature of the refrigerant, and the temperature of each zone of the wafer 205 placed on the wafer stage 200. In this example, this correlation is called the first correlation, and the temperature distribution in the in-plane direction of the wafer 205 can be predicted using the data showing the first correlation, which has been calculated or acquired in advance, and the set values ​​of the output of the heater power supply 202 and the temperature of the refrigerant. Furthermore, if temperature sensors are placed to detect the temperature of each heater zone, the accuracy can be improved by including the temperature data obtained from the output of the temperature sensors in the first correlation, or by using it together with the first correlation to predict the temperature of the wafer 205.

[0034] The first correlation can be represented using a matrix to relate the temperatures of multiple heater zones to specific locations within multiple regions of the wafer 205. Alternatively, the first correlation can also be represented using a system of differential equations.

[0035] The upper and lower limits of the output of the multiple heater power supplies 202 provided in each semiconductor device manufacturing apparatus 101 in this example, and the upper and lower limits of the wafer temperature obtained using the first correlation, are determined from the configuration of each semiconductor device manufacturing apparatus 101 and are therefore unique to that apparatus. Furthermore, if the output of the heater power supply 202 or the temperature of the wafer 205 falls outside the permissible range determined by the above-mentioned unique values ​​during the processing of any wafer 205, the processing of the wafer 205 is stopped to avoid malfunction or damage to the wafer stage 200. For this reason, when processing a wafer 205, the output of the heater power supply 202 and the temperature of the wafer 205 must be set to values ​​within the permissible range that do not exceed the above-mentioned upper and lower limits.

[0036] The wafers 205 processed by each semiconductor device manufacturing apparatus 101 are transported to one of the multiple wafer measuring devices 102 (102a to 102z), where the distribution of specific physical quantities to be detected or evaluated in the in-plane direction of the wafer 205 is detected. If necessary, the distribution of the specific physical quantities before processing by each semiconductor device manufacturing apparatus 101 can also be detected by one of the wafer measuring devices 102. However, it is not always necessary to detect the specific physical quantities of the processed wafer 205 immediately after processing by each semiconductor device manufacturing apparatus 101. The wafers 205 processed by each semiconductor device manufacturing apparatus 101 can be transported to another device for at least one further processing, and then transported to the wafer measuring device 102 to detect the distribution of specific physical quantities in the in-plane direction of the wafer 205.

[0037] Furthermore, the surface of a wafer 205 processed by a single semiconductor device manufacturing apparatus 101 can be measured using multiple wafer measuring devices 102. That is, the wafer 205 processed by the semiconductor device manufacturing apparatus 101a can be transported to wafer measuring device 102a, and then to wafer measuring device 102b, and the distribution of one or more specific physical quantities on the surface of the wafer 205 can be detected in each of these devices.

[0038] Next, we will describe the operation of calculating a target temperature distribution in the in-plane direction of the wafer 205 in one of the semiconductor device manufacturing apparatuses 101 using the wafer temperature calculation system 100, and the operation of correcting to a target temperature distribution that can be achieved if it is determined that the target temperature distribution cannot be achieved. In the following description, we will use the semiconductor device manufacturing apparatus 101a as the target for calculating the target temperature distribution and the wafer measurement apparatus 102a as the device for detecting a specific physical quantity as an example, but in the embodiments of the present invention, the same operation can be performed even if other semiconductor device manufacturing apparatuses or wafer measurement apparatuses are used.

[0039] The wafer temperature calculation system 100 has the function of reading and writing data in each semiconductor device manufacturing apparatus 101 for each wafer stage 200 in each semiconductor device manufacturing apparatus 101a to 101z, including a first correlation between the output from each heater power supply 202 and the in-plane temperature distribution of the wafer 205, as well as data on the output range of the heater power supply 202 and the allowable temperature range of the wafer 205, and updating the data as needed. This data is periodically transmitted and received between the wafer temperature calculation system 100 and the semiconductor device manufacturing apparatus 101a, and the same content is maintained in both. If the structure of the wafer stage 200, including the heater 201 and heater power supply 202 of the wafer stage 200, or the temperature of the refrigerant is changed, the information related to that change is stored and remembered in the wafer temperature calculation system 100 during the periodic data transmission and reception and is reflected in its operation. As a result, by using the shared data for any wafer 205, the target temperature distribution can be achieved and highly accurate wafer 205 processing can be performed.

[0040] Next, the wafer temperature calculation system 100 has a function to associate the processing recipe used to process the wafer 205 in the semiconductor device manufacturing apparatus 101a with data obtained by the wafer measurement device 102a from the distribution of specific physical quantities in the in-plane direction for the processed wafer 205. Here, the processing recipe also includes data on the in-plane temperature distribution of the target temperature of the wafer 205 set in the wafer stage 200, the temperature distribution detected during actual processing using a temperature sensor, or the output values ​​of each heater power supply 202. This makes it possible to associate the temperature distribution of the wafer 205 in the semiconductor device manufacturing apparatus 101 with the distribution of specific physical quantities in the in-plane direction of the wafer 205 measured by the wafer measurement device 102.

[0041] Furthermore, the wafer temperature calculation system 100 has a function to associate data with the processing recipe of the semiconductor device manufacturing apparatus 101a if the distribution of a specific physical quantity in the in-plane direction of the wafer 205 is detected before the wafer 205 is processed in the semiconductor device manufacturing apparatus 101a. With this configuration, the distribution of a specific physical quantity in the in-plane direction of the wafer 205 before and after processing in the semiconductor device manufacturing apparatus 101a can be associated, and the in-plane distribution of the wafer temperature set in the semiconductor device manufacturing apparatus 101a and the in-plane distribution of the change in the specific physical quantity before and after processing can be associated from the difference in the in-plane distribution of the wafer before and after processing.

[0042] Furthermore, the wafer temperature calculation system 100 has the function of calculating a second correlation between a set value for the temperature distribution in the in-plane direction of the wafer 205 in the semiconductor device manufacturing apparatus 101a and the distribution of a specific physical quantity in the in-plane direction of the wafer 205, and storing and remembering this as data related to the semiconductor device manufacturing apparatus 101a. This second correlation can be calculated, for example, using data obtained by processing two or more wafers 205 using different temperature distribution settings in the semiconductor device manufacturing apparatus 101a prior to processing the wafers 205 for manufacturing semiconductor devices, and then transporting each wafer 205 to the wafer measuring device 102a to detect a specific physical quantity.

[0043] In other words, the second correlation is calculated using the results obtained by associating the set conditions for different temperature distributions for two or more wafers 205 with the detection results of the distribution of a specific physical quantity in the in-plane direction for each wafer 205. While a least squares method using linear or polynomial approximation can be used to calculate the second correlation, other methods may also be employed.

[0044] Next, the wafer temperature calculation system 100 has a function to calculate the target temperature distribution that minimizes an objective function using specific physical quantities on the wafer stage 200 of the semiconductor device manufacturing apparatus 101a, using the second correlation that has been stored. As an example of the objective function in this embodiment, target values ​​of specific physical quantities are set on multiple coordinates in the in-plane direction of the wafer 205, and the square of the difference between the target value at a specified coordinate on the surface of the wafer 205 and the predicted value at that specified coordinate calculated based on the second correlation is calculated, and these squared values ​​are summed up for the multiple specified coordinates.

[0045] The target values ​​of specific physical quantities used when calculating such an objective function do not necessarily have to be set to the same value in the in-plane direction of the wafer 205. Different target values ​​may be set for each coordinate in the in-plane direction of the wafer 205, for example, so that the processed shape can be obtained as a result of the processing. Furthermore, even at the same coordinate on the wafer 205, the target values ​​in each processing step may differ depending on the type, content, and conditions of the preceding and succeeding processing. Thus, in this embodiment, an appropriate objective function is set, and the temperature distribution in the in-plane direction of the wafer 205 that minimizes the set objective function is calculated. The target temperature distribution of the wafer 205 during processing is calculated so that the desired distribution of physical quantities is achieved after processing.

[0046] Furthermore, the wafer temperature calculation system 100 has a function to calculate predicted values ​​for the output of the heater power supplies 202 connected to each heater zone in order to achieve the calculated target temperature distribution, using the first correlation in the semiconductor device manufacturing apparatus 101a. In actual wafer 205 processing, the output of the heater power supplies 202 is set to a value of 0 or greater, but the predicted output values ​​calculated here may be negative values ​​that are physically impossible to achieve by extrapolating the first correlation. In other words, due to heat transfer between multiple heater zones via the wafer 205, even if the target temperature distribution of the wafer 205 is not actually achievable, the calculation will determine the output values ​​of multiple heater power supplies 202 during processing that can theoretically achieve this distribution.

[0047] Next, the wafer temperature calculation system 100 has a function to determine whether the calculated target temperature distribution of the wafer stage 200 can be achieved, based on the upper and lower limits of the allowable temperature range of the wafer 205 during processing in the semiconductor device manufacturing apparatus 101a and the upper and lower limits of the output range of the heater power supply 202. That is, the wafer temperature calculation system 100 compares the calculated target temperature value and the predicted output value of the heater power supply 202 with the two upper and lower limits. If the already calculated target temperature during processing of the wafer 205 and the predicted output value of the heater power supply 202 do not exceed their respective upper and lower limits in all heater zones, the calculated target temperature distribution is recorded in the wafer temperature calculation system 100 as an achievable target temperature distribution.

[0048] On the other hand, if it is determined that at least one of the target temperature or the predicted output of the heater power supply 202 exceeds two of the above upper and lower limits in one or more heater zones, it is recorded as an unattainable target temperature distribution. In this case, the heater zones where the target temperature or the predicted output of the heater power supply 202 cannot be achieved are identified and recorded using corresponding codes or numbers, so that the information can be checked when needed.

[0049] When recording heater zones that fail to achieve the target temperature distribution, each heater zone can be assigned a name, code, or number, and these unsuccessful zones can be displayed on a display or other indicator connected to the wafer temperature calculation system 100. An example of this display is shown in Figure 4.

[0050] Figure 4 is a schematic diagram showing heater zones that were determined to be impossible to implement in the wafer temperature calculation system according to an embodiment shown on a display connected to the semiconductor device manufacturing equipment. As shown by 401 in Figure 4(a) or Figure 4(b), the location of the heater zone that was determined to be impossible to implement in the wafer temperature calculation system 100 is shown as the shaded heater zone 401 in the figure, and this location within the entire set of heater zones on the upper surface of the wafer stage 200 can be easily determined using the GUI (Graphical User Interface).

[0051] Next, if the wafer temperature calculation system 100 determines that the target temperature distribution cannot be achieved, it calculates a second target temperature distribution that can be achieved. The second target temperature distribution may be one in which only the predicted output values ​​of the heater power supply 202 in the heater zones where the predicted values ​​of the target temperature or the output of the heater power supply 202 are outside the acceptable range have been changed.

[0052] On the other hand, if the heat transfer in the wafer 205 causes the heater zone to fall outside the acceptable range, simply changing the predicted output of the heater power supply 202 of the heater 201 corresponding to that zone may also change the temperature at an unexpected specified coordinate of the wafer 205, increasing the objective function and potentially causing the target temperature distribution to deviate significantly from the desired processing result. Therefore, using a first correlation that predicts the in-plane temperature distribution of the wafer 205 from the output values ​​of multiple heater power supplies 202, and a second correlation between the set value of the in-plane temperature distribution of the wafer 205 and the distribution of a specific physical quantity in the in-plane direction of the wafer 205, the temperature distribution of the wafer 205 that minimizes the objective function among the achievable temperature distributions can be calculated and calculated as the second target temperature distribution.

[0053] Furthermore, the wafer temperature calculation system 100 incorporates either the target temperature distribution determined to be achievable or the second target temperature distribution into the processing conditions (processing recipe) of the semiconductor device manufacturing apparatus 101a, and transmits the said processing recipe to the semiconductor device manufacturing apparatus 101a. The semiconductor device manufacturing apparatus 101a can process the target wafer 205 using the processing recipe that includes the transmitted information on the achievable target temperature distribution after calculation by the wafer temperature calculation system 100.

[0054] As described above, by using the semiconductor device manufacturing system including the wafer temperature calculation system 100 of this embodiment, even if the initial target temperature distribution calculated to obtain the desired processing results is not achievable, a second target temperature distribution that minimizes the objective function among the achievable temperature distributions is calculated, and semiconductor devices are manufactured based on this, thereby suppressing a decrease in manufacturing yield.

[0055] Next, the operation of the wafer temperature calculation system 100 according to the embodiment shown in Figure 1 for calculating the target temperature distribution will be explained using Figures 5A to 6. Figures 5A to 6 are flowcharts showing the operation flow of the wafer temperature calculation system according to the embodiment. In this example, an example using semiconductor device manufacturing equipment 101a and wafer measurement equipment 102a is described, but similar operation and results can be obtained using other semiconductor device manufacturing equipment or wafer measurement equipment.

[0056] Figures 5A and 5B show a series of operations in which the wafer temperature calculation system 100 calculates the set value for the target temperature distribution. Figure 6 shows in more detail the operation flow for setting the output value of the heater power supply 202 in step 512 shown in Figure 5B. The wafer temperature calculation system 100 of this embodiment has a function to manage, for each semiconductor device manufacturing apparatus 101a to 101z, a first correlation relationship showing the relationship between the output value of each of the multiple heater power supplies 202 and the temperature of the refrigerant flowing through the refrigerant channel 204, and the allowable range value (tolerance) of the temperature of the wafer 205, for each semiconductor device manufacturing apparatus 101a to 101z. These data are periodically synchronized between the wafer temperature calculation system 100 and each semiconductor device manufacturing apparatus, such as the semiconductor device manufacturing apparatus 101a, so that the same data is stored and shared between them. If the structure of the wafer stage 200 or the set temperature of the refrigerant is changed, the data and information reflecting the changes are periodically transmitted to and stored in the wafer temperature calculation system 100.

[0057] Next, in step 502, the semiconductor device manufacturing apparatus 101a associates a processing recipe for processing the wafer 205 with data on the distribution of specific physical quantities in the in-plane direction of the processed wafer 205, which is detected by the wafer measuring apparatus 102a after processing the wafer using the processing recipe. Here, the processing recipe also includes data indicating the in-plane temperature distribution of the wafer 205 during processing, set by the wafer stage 200, or the output values ​​of each heater power supply 202. This associates the in-plane temperature distribution of the wafer 205 set by the semiconductor device manufacturing apparatus 101 with the in-plane distribution of specific physical quantities of the wafer 205 detected by the wafer measuring apparatus 102.

[0058] Furthermore, the wafer temperature calculation system 100 has a function to associate data with the processing recipe of the semiconductor device manufacturing apparatus 101a if the wafer measurement device 102a detects the distribution of a specific physical quantity in the in-plane direction of the wafer 205 before processing by the semiconductor device manufacturing apparatus 101a. With this configuration, the distribution of a specific physical quantity in the in-plane direction of the wafer 205 before and after processing by the semiconductor device manufacturing apparatus 101a can be associated, and the distribution of the temperature distribution in the in-plane direction of the wafer 205 set in the semiconductor device manufacturing apparatus 101a and the distribution of the change in the specific physical quantity in the in-plane direction before and after processing can be associated from the distribution of the difference in the specific physical quantity in the in-plane direction before and after processing.

[0059] Here, each heater power supply 202 is assigned a number ranging from N=1 to the number of heater power supplies, and this number is used to determine which heater zone the heater power supply is connected to. The names of the heater power supplies can be anything as long as each heater power supply can be distinguished, but in this embodiment, a positive integer of N=1 or greater is assigned.

[0060] Next, in step 503, the wafer temperature calculation system 100 has a function to calculate a second correlation that predicts the distribution of a specific physical quantity in the in-plane direction of the wafer 205 from a set value of the temperature distribution in the in-plane direction of the wafer 205 in the semiconductor device manufacturing apparatus 101a, and has a function to associate this with data related to the semiconductor device manufacturing apparatus 101a and record and store it in the internal storage device 104. The second correlation is calculated using the results of associating the in-plane distribution data of values ​​when a specific physical quantity is detected by the wafer measuring device 102a for each wafer 205 after processing two or more wafers 205 in advance using the semiconductor device manufacturing apparatus 101a under different temperature distribution conditions in the in-plane direction.

[0061] In other words, a second correlation is calculated using the conditions for the temperature distribution in the in-plane direction of two or more wafers 205 and the results of detecting the distribution of a specific physical quantity in the in-plane direction. The second correlation may be calculated using a least squares method with linear or polynomial approximation, or other methods may be used.

[0062] Next, the wafer temperature calculation system 100 has a function to calculate the target temperature distribution in the semiconductor device manufacturing apparatus 101a that minimizes the objective function calculated from specific physical quantities, using the second correlation recorded in step 504. As the objective function, for example, target values ​​for specific physical quantities may be set at multiple coordinates on the plane of the wafer 205, the square of the difference between the target value at a specified coordinate on the plane and the predicted value at that specified coordinate calculated based on the second correlation may be calculated, and the sum of these squared values ​​at multiple specified coordinates may be set as the objective function.

[0063] The target values ​​of the specific physical quantities used in calculating this objective function do not necessarily have to be set to the same target values ​​across the wafer plane. It is sufficient that the desired processing results and their distributions are ultimately achieved across the wafer plane, and the target values ​​may change for each coordinate depending on the processing before and after. In this way, by setting an appropriate objective function and calculating the temperature distribution of the wafer 205 that minimizes that objective function, a target temperature distribution is calculated that ultimately achieves the desired values ​​and distributions of the physical quantities in the in-plane direction of the wafer 205.

[0064] Next, in step 505, the wafer temperature calculation system 100 uses the first correlation in the semiconductor device manufacturing apparatus 101a to calculate predicted values ​​for the output of multiple heater power supplies 202 connected to each heater zone for calculating the target temperature distribution. Although the output of each heater power supply 202 is set to a value of 0 or greater during the actual processing of the wafer 205, the predicted output values ​​calculated here may be negative values ​​that are impossible to achieve by extrapolating the first correlation. This allows for obtaining a set of heater power supply 202 output values ​​that computationally correspond to the target temperature distribution, even if the target temperature distribution includes values ​​that cannot actually be achieved due to heat transfer in the wafer 205.

[0065] Next, in step 506, the wafer temperature calculation system determines whether the predicted output value of the heater power supply meets the limit conditions. That is, based on the result of comparing the upper and lower limits of the allowable range of the wafer temperature 205 and the output of the heater power supply in the semiconductor device manufacturing apparatus 101a, it determines whether the target temperature distribution calculated in step 504 can be achieved. If the target temperature and the predicted output value of the heater power supply 202 are within the allowable range in all heater zones, the process proceeds to the END step, and the calculated temperature distribution is reflected as an achievable target temperature distribution in the processing recipe of the semiconductor device manufacturing apparatus 101a and included as data, and the recipe is transmitted to the semiconductor device manufacturing apparatus 101a via the network 106. The semiconductor device manufacturing apparatus 101a can then process the wafer 205 using the processing recipe transmitted from the wafer temperature calculation system 100.

[0066] On the other hand, if either the target temperature or the predicted output of the heater power supply 202 is determined to be outside the acceptable range in at least one heater zone, the target temperature distribution calculated in step 504 is recorded in the storage device 104 as unattainable, and the process proceeds to step 507. At this time, the heater zones in which the target temperature or the predicted output of the heater power supply 202 is determined to be unattainable are recorded in the storage device 104, and the information of those heater zones can be checked when necessary.

[0067] Next, in step 507, only the heater power supplies 202 corresponding to heater zones whose predicted output values ​​are outside the acceptable range are modified so that their output values ​​fall within the acceptable range. In other words, the output values ​​of heater power supplies whose predicted output values ​​are outside the feasible range are changed to values ​​within the feasible range. In addition, the distribution of all heater power supplies 202 is recorded as the initial distribution. Step 507 allows us to obtain an initial distribution in which the output of all heater power supplies is feasible.

[0068] Next, in step 508, the current output values ​​of all heater power supplies 202 are recorded as a C distribution. This C distribution will be updated as needed according to the flow shown in the figure, but the output of the heater power supplies 202 calculated in step 507 is recorded as the initial distribution.

[0069] Next, in step 509, the output value of the Nth heater power supply is increased or decreased within the minimum control range. That is, the output value of each heater power supply 202, which was assigned a positive integer in step 502, is sequentially increased or decreased by a predetermined value. The magnitude of this change can be arbitrarily selected in the semiconductor device manufacturing system or semiconductor device manufacturing apparatus 101a, but it must be set to a value greater than the minimum range by which the output of the heater power supply 202 can be changed. Also, depending on the configuration of the heater power supply 202, it is possible to change the output value for each heater power supply 202 even if they are used for the same wafer stage 200. For example, if the output value of any heater power supply 202 in the C distribution recorded in step 508 is 50W, and the minimum control range of that heater power supply 202 is 0.1W, then the output values ​​of the heater power supply 202 increased or decreased by the minimum possible range will be 50.1W and 49.9W.

[0070] Next, in step 510, it is determined whether the output value of the heater power supply satisfies the limiting conditions. That is, it is determined whether the output of the heater power supply 202 or the wafer temperature falls within the acceptable range based on the output value of the heater power supply 202 that was increased or decreased in step 509. If it is determined that the conditions for the acceptable range are met, the process proceeds to step 511 as the set of output values, including the output value of the heater power supply 202 that was increased or decreased in step 509, which is the distribution of feasible output values. On the other hand, if it is determined that the values ​​fall outside the acceptable range, the positive integer N assigned to each heater power supply 202 is increased to N+1 as the distribution of unrealizable outputs (set of output values) of the heater power supply 202, and then the process returns to step 509 to consider a different heater power supply 202.

[0071] Next, in step 511, the value of the objective function is calculated using the predicted values ​​of all the heater power supplies 202 outputs output in step 510, using a first correlation between the output value of each heater power supply 202 and the in-plane temperature distribution of the wafer 205, and a second correlation between the set value of the in-plane temperature distribution of the wafer 205 and the in-plane distribution of a specific physical quantity of the wafer 205.

[0072] In the next step 512, the output value of the heater power supply 202 is updated and set based on the value of the objective function calculated in step 511. The objective function is calculated using the C distribution obtained in step 508, and then compared with the value of the objective function calculated from the output values ​​of the heater power supply 202 that were increased or decreased in steps 509 to 511. The distribution (combination) of the output values ​​of the heater power supply 202 is selected according to the result. The detailed operation flow of this process will be described later with reference to Figure 6.

[0073] Next, in step 513, the value of the positive integer N assigned to each heater power supply 202 is checked. If the value of N is the largest value equal to the number of heater power supplies 202 being used, it is determined that all heater power supplies have been changed (adjusted at least once), and the process proceeds to the next step 514. If the value of N is determined to be less than the number of heater power supplies 202 being used, the value of N is increased by one, and the process returns to step 509.

[0074] Next, in step 514, in order to determine whether the calculation of the objective function and the output distribution of the heater power supply 202 has converged, it is determined whether the distribution of the output values ​​of each heater power supply 202 set in step 512 (i.e., the current output values ​​of each heater power supply) is the same as the C distribution. If it is different from the C distribution, it means that the calculation has not converged, so the value of N is reset to 1 and the process returns to step 508. On the other hand, if it is determined that the values ​​are the same as the C distribution, it is determined that the calculation has converged and the second target temperature distribution has been calculated, and the process proceeds to step 515.

[0075] In step 515, the calculated target temperature distribution calculated in step 506 or step 514 is reflected in the processing recipe of the semiconductor device manufacturing apparatus 101a, and the data of the said temperature distribution is included in the processing recipe, and the recipe is transmitted to the semiconductor device manufacturing apparatus 101a. The semiconductor device manufacturing apparatus 101a can then process the wafer 205 using the processing recipe calculated and transmitted by the wafer temperature calculation system 100.

[0076] As described above, the operation of the wafer temperature calculation system 100 shown in Figures 5A and 5B determines whether a target temperature distribution that minimizes a predetermined objective function can be achieved. Even if it is determined that the target temperature distribution cannot be achieved, a second target temperature distribution that minimizes the objective function among the achievable temperature distributions is calculated, and the wafer 205 is processed based on a processing recipe that reflects this second target temperature distribution. As a result, a distribution of specific physical quantities in the in-plane direction that yields the desired processing result is achieved during processing, improving the yield of the wafer 205.

[0077] Figure 6 provides a more detailed explanation of the operation flow of step 512 shown in Figure 5B. First, in step 601, the objective function value calculated in step 511 is compared with the objective function value calculated using the C distribution value in step 508. If, as a result of this comparison, it is determined in step 602 that only one of the objective function values ​​has decreased, the process proceeds to step 604, where the distribution of the output values ​​of the heater power supply 202 whose objective function value has decreased is determined to be the distribution (set) of the output values ​​of the heater power supply 202 that should be set. In other words, the output value of the heater power supply is set to the value corresponding to the decreased objective function. If the objective function value calculated in step 511 decreases, the distribution of the output values ​​of the heater power supply 202 corresponding to that objective function is updated as a new distribution.

[0078] Furthermore, if it is not determined in step 602 that only the value of one of the objective functions has decreased, the process proceeds to step 603, where the value of the objective function calculated from the C distribution is compared with the value of the objective function calculated in step 511 to determine whether the values ​​of both objective functions have decreased. If it is determined that the values ​​of both objective functions have decreased, the process proceeds to step 605, where the distribution of the output values ​​of the heater power supply 202 corresponding to the one with the larger decrease in the value of the objective function is determined to be the distribution (set) of the output values ​​of the heater power supply 202 that should be set. In other words, the output value of the heater power supply is set to the one with the larger decrease in the objective function. If the value of the objective function calculated in step 511 has decreased more significantly, the distribution of the output values ​​of the heater power supply 202 corresponding to that objective function is updated as a new distribution.

[0079] On the other hand, if it is not determined in step 603 that the values ​​of both objective functions have decreased, it is assumed that the values ​​of both objective functions have not increased or changed. In this case, the process proceeds to step 606, and the distribution of the output values ​​of the heater power supply 202 remains unchanged from the C distribution. Based on the above determination, the distribution of the output values ​​of the heater power supply 202 is updated, and as a result of increasing or decreasing the output of the heater power supply 202 from the C distribution, the distribution of the output values ​​of the heater power supply changes to the distribution that minimizes the value of the objective function from the C distribution.

[0080] In the above embodiment, if the output value of the heater power supply 202 is determined to be outside the acceptable range in step 506, a process of reallocating the positive integer N assigned to each heater power supply 202 in order to shorten the calculation time will be explained with reference to Figure 7. Figure 7 is a flowchart showing the operation flow added to the embodiment shown in Figure 5. Figure 7 shows the process performed between steps 507 and 508 in Figure 5.

[0081] In step 507, only the heater power supply 202 whose predicted output values ​​fall outside the acceptable range is modified so that its output value falls within the acceptable range. Additionally, the distribution of all heater power supplies 202 is recorded as the initial distribution. In this step 507, the current output of all heater power supplies 202 is assumed to be the feasible initial distribution.

[0082] Next, in step 1001, the wafer temperature calculation system 100 calculates and stores the coordinates of the center of the heater zone connected to the heater power supply 202 whose predicted output value has fallen outside the acceptable range. In other words, it calculates and records the coordinates of the center of the heater zone connected to the heater power supply whose predicted output value has exceeded the limit. Next, proceeding to step 1002, the wafer temperature calculation system 100 calculates and stores the difference between the target temperature and the wafer temperature calculated from the output value of the heater power supply 202 changed in step 507, in the heater zone connected to the heater power supply 202 whose predicted output value has fallen outside the acceptable range. In other words, it records the difference between the target temperature and the wafer temperature calculated from the output value of the heater power supply changed in step 507, in the heater zone connected to the heater power supply whose predicted output value has exceeded the limit. The temperature difference is calculated, for example, by (Equation 1) below, but is not limited to (Equation 1) as long as it is an index that represents the magnitude of the difference in temperature of the wafer 205 calculated from the target temperature and the output value of the heater power supply.

[0083]

number

[0084] Here, e is a positive integer assigned to the heater zone connected to the heater power supply whose predicted output exceeds the limit, E e This is the difference in wafer temperature in heater zone e, Tt e The target temperature in heater zone e is Tp e This is the wafer temperature calculated from the output value of the heater power supply modified in 507 in heater zone e.

[0085] Next, in step 1003, the distance D between the coordinates of the center of the zone connected to the heater power supply 202 where the predicted output value of the heater power supply 202 fell outside the acceptable range, and the coordinates of the centers of other heater zones. ie The following is calculated. In other words, the distance between the center coordinates of the heater zone connected to the heater power supply whose predicted output value exceeds the limit and the center coordinates of each heater zone is calculated. Here, i is a positive integer assigned to each heater zone, and e is a positive integer assigned to the heater zone connected to heater power supply 202 whose predicted output value of the heater power supply has fallen outside the acceptable range.

[0086] Next, in step 1004, the wafer temperature calculation system 100 calculates the weight for each heater zone. The weight for each heater zone is calculated, for example, using the following formula.

[0087]

number

[0088]

number

[0089] In the above formula, N e This represents the number of heater zones connected to heater power supplies whose predicted output exceeds the limit value, and the weight in each heater zone i can be calculated using (Equation 3).

[0090] In the following 1005 flow, the larger the weight calculated in (Equation 3), the smaller the positive integer N assigned to the heater power supply connected to each heater zone.

[0091] In the next step 508, the wafer temperature calculation system 100 records the output values ​​of each heater power supply 202 as a C distribution using a positive integer N reallocated in 1005 to each heater power supply 202 connected to each heater zone.

[0092] As a result of the above operation, heater power supplies 202 with a larger difference between the target temperature and the predicted temperature are assigned a smaller positive integer value N, and the predicted output values ​​are calculated preferentially starting with heater power supplies 202 with smaller integer N values, thus shortening the calculation time for the objective function value and the distribution of output values. Although this example describes the use of central coordinates, the coordinates are not limited to those within the heater zone. For example, the coordinates directly above the point where the input terminal of heater power supply 202 is connected may be used in the calculation.

[0093] According to the above embodiment, in a semiconductor device manufacturing apparatus that adjusts the temperature and distribution of a wafer 205 placed on a wafer stage 200 using a plurality of heaters 201 inside the wafer stage 200, a first target temperature distribution that minimizes the value of an objective function related to the distribution of a specific physical quantity after processing is calculated in advance before processing the wafer 205. Furthermore, the output values ​​of heater power supplies 202 connected to the plurality of heaters 201 to realize the target temperature distribution are calculated, and it is determined whether the output values ​​of all the calculated heater power supplies 202 are within an acceptable range. If it is determined that the output value of at least one of the plurality of heater power supplies 202 is outside the acceptable range and therefore cannot be realized, a second target temperature distribution that can be realized using the plurality of heater power supplies 202 and minimizes the objective function value is calculated, the temperature and distribution settings of the wafer stage 200 are updated in place of the first target temperature distribution, a temperature distribution of the wafer 205 during processing that yields the desired processing result is realized, and the processing yield is improved.

[0094] It should be noted that the present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail to make the present invention easier to understand, and are not necessarily limited to those having all the configurations described. It is also possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations. [Explanation of Symbols]

[0095] 100... Wafer temperature calculation system, 101... Semiconductor device manufacturing equipment, 102...Wafer measuring device, 200...wafer stage, 201... Heater, 202... Heater power supply, 203... Heater control unit, 204... Refrigerant flow path, 401... Heater zone.

Claims

1. A wafer processing apparatus comprising a stage located inside a processing chamber within a container on which a wafer to be processed is placed on its upper surface, a plurality of heaters located inside the stage below a plurality of regions on the upper surface of the stage, and a controller for adjusting the power supplied to these plurality of heaters, wherein the wafer on the stage is processed while the heat generated by the plurality of heaters is adjusted, The controller adjusts the power so that a second target temperature distribution is obtained by correcting a predetermined first target temperature distribution so that it is possible to bring the wafer during processing to a target temperature. The controller is a wafer processing apparatus that adjusts the power so that the first target temperature distribution becomes the second target temperature distribution obtained by correcting the first target temperature distribution when it is determined that the power value for achieving the first target temperature distribution is not within an acceptable range.

2. The wafer processing apparatus according to claim 1, wherein the controller adjusts the power so that if any of the power supplied to the plurality of heaters in order to achieve the first target temperature distribution is outside the allowable range, the power becomes a second target temperature distribution such that the power is within the allowable range.

3. The wafer processing apparatus according to claim 1, wherein the controller adjusts the output of the plurality of power sources that supply power to the plurality of heaters, when the output of at least one of the plurality of power sources is outside the permissible range, so that the output of at least one of the power sources becomes a second target temperature distribution corresponding to a second output value that has been brought within the permissible range.

4. The wafer processing apparatus according to claim 2, wherein the controller adjusts the output of the plurality of power sources that supply power to the plurality of heaters, when the output of at least one of the plurality of power sources is outside the acceptable range, so that the output of at least one of the power sources becomes a second target temperature distribution corresponding to a second output value that has been brought within the acceptable range.

5. The wafer processing apparatus according to claim 1, wherein the controller adjusts the outputs of the plurality of power sources that supply power to the plurality of heaters, when the output of at least one of the plurality of power sources is outside the acceptable range, so that the output of at least one of the power sources is brought within the acceptable range and the temperature distribution becomes a second target that minimizes the value of a predetermined objective function.

6. The wafer processing apparatus according to claim 5, wherein the controller adjusts the outputs of the plurality of power supplies to obtain a second target temperature distribution corresponding to the output of the power supplies obtained by sequentially increasing or decreasing the output of each of the plurality of power supplies until the value of the objective function is smallest.

7. A wafer processing apparatus according to claim 1, further comprising: a display that displays the region of the heater corresponding to the power supply of at least one of the multiple power supplies that supply power to the multiple heaters when the output value of at least one of the multiple power supplies is outside the permissible range.

8. A wafer processing apparatus comprising a stage located in a processing chamber inside a container on which a wafer to be processed is placed on its upper surface, a plurality of heaters located inside the stage below a plurality of regions on the upper surface of the stage, and a controller for adjusting the power supplied to these plurality of heaters, wherein the wafer is processed on the stage while adjusting the heat generated by the plurality of heaters, The power is adjusted so that a second target temperature distribution is obtained by correcting a predetermined first target temperature distribution so that the wafer during the processing can be brought to a target temperature. A wafer processing method that includes a step of adjusting the power so that the first target temperature distribution becomes the second target temperature distribution obtained by correcting the first target temperature distribution, if it is determined that the power value for achieving the first target temperature distribution is not within an acceptable range.

9. The wafer processing method according to claim 8, further comprising the step of adjusting the power supplied to the plurality of heaters in order to achieve the first target temperature distribution if any of the power supplied to the plurality of heaters is outside the allowable range, so that the power becomes a second target temperature distribution within the allowable range.

10. The wafer processing method according to claim 8, further comprising the step of adjusting the outputs of the plurality of power sources that supply power to the plurality of heaters, if the output of at least one of the plurality of power sources is outside the permissible range, so that the output of at least one of the power sources becomes the second target temperature distribution corresponding to the second output value that has been brought within the permissible range.

11. The wafer processing method according to claim 9, further comprising the step of adjusting the outputs of the plurality of power sources that supply power to the plurality of heaters, if the output of at least one of the plurality of power sources is outside the permissible range, so that the output of at least one of the power sources becomes the second target temperature distribution corresponding to the second output value that has been brought within the permissible range.

12. The wafer processing method according to claim 8, further comprising the step of adjusting the outputs of the plurality of power sources that supply power to the plurality of heaters, such that if the output of at least one of the plurality of power sources is outside the acceptable range, the output of at least one of the power sources is brought within the acceptable range and the temperature distribution becomes the second target temperature distribution that minimizes the value of a predetermined objective function.

13. The wafer processing method according to claim 12, further comprising the step of adjusting the outputs of the plurality of power supplies so that the output of each of the plurality of power supplies is obtained in correspondence with the output of the power supplies obtained by sequentially increasing or decreasing the output of each of the plurality of power supplies until the value of the objective function is smallest.

14. A wafer processing method for a wafer processing apparatus further comprising a display device, The wafer processing method according to claim 8, further comprising the step of displaying the region of the heater corresponding to the power supply of at least one of the multiple power supplies that supply power to the multiple heaters if the output value of at least one of the multiple power supplies is outside the permissible range.

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