Integrated circuits and power supply circuits

Abstract

To provide an integrated circuit that reduces switching noise of a transistor when an AC-DC converter is started.SOLUTION: An integrated circuit that includes a transistor for controlling a current flowing to a coil and drives the transistor of a power supply circuit for generating an output voltage having a target level from an input voltage includes: a determination circuit for determining whether or not a predetermined period elapses since the power supply voltage of the integrated circuit rises to a first predetermined level; an oscillation circuit for outputting an oscillation signal having a first frequency before the predetermined period elapses and outputting the oscillation signal that changes at least within a range between the first frequency and a second frequency higher than the first frequency based on the output voltage after the predetermined period elapses; and a driving circuit for switching the transistor based on the oscillation signal so as to gradually increase an ON period of the transistor for the predetermined period and switching the transistor based on the oscillation signal after the predetermined period elapses.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an integrated circuit and a power supply circuit.

Background Art

[0002] Some integrated circuits for controlling a power supply circuit perform so-called soft start, in which the on-period of a transistor in the power supply circuit is gradually increased at startup.

[0003] Also, some integrated circuits increase the switching frequency of a transistor during the soft start period (for example, Patent Documents 1 to 5).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, it is generally known that when the switching frequency of a transistor is high, the switching loss increases and the noise increases. Also, during the soft start period, since the load is not operating, it may not be necessary to increase the switching frequency to rapidly increase the output voltage. Further, when a transistor is switched in a state where the generated noise is large, it may have an adverse effect on the transistor.

[0006] The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide an integrated circuit that reduces the switching noise of transistors during startup of an AC-DC converter. [Means for solving the problem]

[0007] A first aspect of the integrated circuit according to the present invention, which solves the aforementioned problems, is an integrated circuit that drives a transistor in a power supply circuit that controls the current flowing through a coil and generates an output voltage of a target level from an input voltage, and includes a determination circuit that determines whether a predetermined period has elapsed since the power supply voltage of the integrated circuit rose to a first predetermined level; an oscillation circuit that outputs an oscillation signal of a first frequency before the predetermined period has elapsed, and outputs an oscillation signal that changes in the range of at least the first frequency to a second frequency higher than the first frequency based on the output voltage after the predetermined period has elapsed; and a drive circuit that switches the transistor based on the oscillation signal so as to gradually increase the on period of the transistor for the predetermined period, and switches the transistor based on the oscillation signal after the predetermined period has elapsed.

[0008] A second aspect of the integrated circuit according to the present invention, which solves the aforementioned problems, is an integrated circuit that drives the transistor of a power supply circuit that controls the current flowing through a coil and generates an output voltage of a target level from an input voltage, and includes a determination circuit that determines whether a predetermined period has elapsed since the power supply voltage of the integrated circuit rose to a first predetermined level; an oscillation circuit that outputs an oscillation signal that changes in a first range from a first frequency to a third frequency lower than the first frequency based on the output voltage before the predetermined period has elapsed, and outputs the oscillation signal that changes in a second range from the third frequency to a second frequency higher than the first frequency based on the output voltage after the predetermined period has elapsed; and a drive circuit that switches the transistor based on the oscillation signal that changes in the first range for the predetermined period, and switches the transistor based on the oscillation signal that changes in the second range after the predetermined period has elapsed.

[0009] The power supply circuit according to the present invention, which solves the aforementioned problems, is a power supply circuit that generates an output voltage of a target level from an input voltage, and comprises a transistor that controls the current flowing through a coil, and an integrated circuit that drives the transistor, wherein the integrated circuit includes a determination circuit that determines whether a predetermined period has elapsed since the power supply voltage of the integrated circuit rose to a first predetermined level, an oscillation circuit that outputs an oscillation signal of a first frequency before the predetermined period has elapsed, and after the predetermined period has elapsed, an oscillation signal that changes in the range of at least the first frequency to a second frequency higher than the first frequency based on the output voltage, and a drive circuit that switches the transistor based on the oscillation signal so as to gradually increase the on period of the transistor for the predetermined period, and switches the transistor based on the oscillation signal after the predetermined period has elapsed. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated circuit that reduces the switching noise of transistors during startup of an AC-DC converter. [Brief explanation of the drawing]

[0011] [Figure 1] This figure shows an example of the configuration of the AC-DC converter 10. [Figure 2] This figure shows an example of the configuration of the control IC32. [Figure 3] This figure shows an example of the configuration of the oscillator circuit 46. [Figure 4] This figure shows an example of the configuration of a voltage-controlled oscillator circuit 62. [Figure 5A] This figure shows the change in the frequency Fsw of the drive signal Vg during a normal period. [Figure 5B] This table shows the relationship between voltages V1 and V3 and reference voltages VREF1 to VREF3 when voltage Vfb becomes voltage Vfba to Vfbd. [Figure 6A] This figure shows the change in the frequency Fsw of the drive signal Vg during the soft-start period. [Figure 6B]It is a table showing the relationships between voltages V1, V3, V4 and reference voltages VREF1, VREF2 when voltage Vfb becomes voltages Vfba to Vfbd. [Figure 7] It is a diagram showing an example of the operation of control IC32 during the normal period. [Figure 8] It is a diagram showing an example of the operation of control IC32 during the soft start period. [Figure 9] It is a diagram showing an example of the configuration of voltage output circuit 75.

Embodiments for Carrying Out the Invention

[0012] From the descriptions in this specification and the attached drawings, at least the following matters become clear. =====This Embodiment===== FIG. 1 is a diagram showing an example of the configuration of an AC-DC converter 10 according to an embodiment of the present invention. The AC-DC converter 10 is a flyback power supply circuit that generates an output voltage Vout at a target level from the input voltage of the alternating current voltage Vac of a commercial power supply. And the AC-DC converter 10 supplies power to the motor 11. Also, the AC-DC converter 10 supplies an output current Iout to the motor 11.

[0013] <<<Overview of AC-DC Converter 10>>> The AC-DC converter 10 is configured to include a full-wave rectifier circuit 20, capacitors 21, 26, a transformer 22, a control block 23, diodes 24, 25, a constant voltage circuit 27, and a light-emitting diode 28.

[0014] The full-wave rectifier circuit 20 full-wave rectifies the input predetermined alternating current voltage Vac and outputs it as voltage Vrec to the primary coil L1 of the transformer 22 and the capacitor 21. Also, the capacitor 21 smoothes the voltage Vrec. Note that the alternating current voltage Vac is, for example, a voltage with an effective value of 100 to 240V and a frequency of 50 to 60Hz.

[0015] The transformer 22 has a primary coil L1 and a secondary coil L2 and an auxiliary coil L3 that are magnetically coupled to the primary coil L1. Here, the secondary coil L2 and the auxiliary coil L3 are wound such that the voltage generated in the secondary coil L2 and the auxiliary coil L3 has the opposite polarity to the voltage generated in the primary coil L1.

[0016] The control block 23 controls the voltage generated in the secondary coil L2 on the secondary side of the transformer 22 by controlling the inductor current IL flowing through the primary coil L1 on the primary side of the transformer 22. As a result, an output voltage Vout of the desired level is generated on the secondary side of the transformer 22.

[0017] Diode 24 half-wave rectifies the AC voltage Vac. The voltage from diode 24 is applied to terminal VH of the control IC 32 (described later) included in the control block 23.

[0018] Diode 25 rectifies the current from the secondary coil L2 of transformer 22 and supplies it to capacitor 26. Since capacitor 26 is charged by the current from diode 25, an output voltage Vout is generated across the terminals of capacitor 26.

[0019] The constant voltage circuit 27 is a circuit that generates a constant DC voltage, and is constructed, for example, using a shunt regulator.

[0020] The light-emitting diode 28 is an element that emits light of an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 27, and together with the phototransistor 36, which will be described later, it constitutes a photocoupler. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light from the light-emitting diode 28 increases.

[0021] <<<Overview of Control Block 23>>> The control block 23 is a circuit block for controlling the AC-DC converter 10. The control block 23 consists of a power transistor 30, resistors 31, 34, 39, a control IC 32, capacitors 33, 37, 35, a phototransistor 36, and a diode 38.

[0022] The power transistor 30 is an NMOS transistor for controlling the power supplied to the motor 11. In this embodiment, the power transistor 30 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. The power transistor 30 may be any transistor capable of controlling power, such as a bipolar transistor.

[0023] Resistor 31 is used to detect the inductor current IL flowing through the primary coil L1 when the power transistor 30 is turned on. One end is connected to the source electrode of the power transistor 30, and the other end is grounded.

[0024] The control IC 32 is an integrated circuit (IC) that controls the switching of the power transistor 30 so that the output voltage Vout reaches a target level. Specifically, the control IC 32 drives the power transistor 30 based on the inductor current IL and the output voltage Vout.

[0025] Details of the control IC 32 will be described later, but the control IC 32 is provided with terminals CS, FB, OUT, VCC, and VH. The gate electrode of the power transistor 30 is connected to terminal OUT. In addition, the actual control IC 32 has other terminals, but they are omitted for the sake of explanation.

[0026] Capacitor 33 is placed between terminal CS and ground, and the voltage across resistor 31, which is generated by the inductor current IL, is applied via resistor 34. Capacitor 33 and resistor 34 constitute a low-pass filter, stabilizing the voltage Vcs at terminal CS.

[0027] Capacitor 37 is placed between terminal VCC and ground. Diode 38 has its anode connected to auxiliary coil L3 and its cathode connected to terminal VCC via resistor 39. The voltage Va generated across auxiliary coil L3 is applied to capacitor 37 via diode 38 and resistor 39, and the voltage across capacitor 37 becomes the power supply voltage Vcc of control IC 32.

[0028] Capacitor 35 is placed between terminal FB and ground to stabilize the voltage Vfb at terminal FB. Voltage Vfb is a feedback voltage corresponding to the output voltage Vout and is applied to terminal FB. As will be explained in detail later, control IC 32 turns on power transistor 30 at a frequency corresponding to voltage Vfb. Normally, if the voltage Vcs exceeds the voltage Vfb_div (described later), which is the voltage obtained by dividing voltage Vfb, while power transistor 30 is on, control IC 32 turns off power transistor 30.

[0029] The phototransistor 36 is located between terminal FB and ground, and together with the light-emitting diode 28 on the secondary side of the transformer 22, it forms a photocoupler. Furthermore, when the intensity of the light emitted by the light-emitting diode 28 increases, the phototransistor 36 sends a larger sink current Ia to terminal FB.

[0030] <<<Configuration of Control IC32>>> Figure 2 shows an example of the configuration of the control IC 32. The control IC 32 consists of a startup circuit 40, an undervoltage protection circuit (UVLO) 41, resistors 42-44, a timer 45, an oscillator circuit 46, an output circuit 47, a drive circuit 48, and a comparator 49.

[0031] ==Startup Circuit 40== The startup circuit 40 charges the capacitor 37 shown in Figure 1 with the voltage at terminal VH when the AC-DC converter 10 is started, and generates the power supply voltage Vcc.

[0032] The startup circuit 40 turns on when an AC voltage Vac is applied to the AC-DC converter 10 and the power supply voltage Vcc is lower than a predetermined level Vccoff, and stops operating when the power supply voltage Vcc reaches the predetermined level Vccoff.

[0033] ==Low Voltage Protection Circuit (UVLO) 41== The undervoltage protection circuit 41 resets the control IC 32 when the power supply voltage Vcc falls below a predetermined level. Specifically, when the power supply voltage Vcc falls below a predetermined level Vccuvlo, the undervoltage protection circuit 41 outputs a signal rst to reset the control IC 32. On the other hand, when the power supply voltage Vcc is at or above the predetermined level Vccuvlo, the undervoltage protection circuit 41 outputs a signal rst to release the reset of the control IC.

[0034] ==Resistance 42~44== Resistor 42 is placed between the node to which the internal voltage Vdd, generated by the internal power supply (not shown) from the power supply voltage Vcc, is applied and terminal FB, generating a voltage Vfb corresponding to the sink current Ia flowing through the phototransistor 36. Resistors 43 and 44 are a voltage divider circuit that divides the voltage Vfb. A voltage Vfb_div is generated at the connection point of resistors 43 and 44.

[0035] ==Timer 45== Timer 45 determines whether the soft-start period (hereinafter referred to as "predetermined period P") has elapsed after receiving the signal rst which releases the reset of the control IC 32. Specifically, Timer 45 determines whether the predetermined period P has elapsed since the power supply voltage Vcc rose to a predetermined level Vccuvlo and the low-voltage protection circuit 41 outputted the signal rst which releases the reset of the control IC 32. Also, before the predetermined period P has elapsed (i.e., during the soft-start period), Timer 45 outputs a low-level signal ssend (hereinafter referred to as "L" level) to the oscillation circuit 46. On the other hand, after the predetermined period P has elapsed (hereinafter referred to as the "normal period"), Timer 45 outputs a high-level signal ssend (hereinafter referred to as "H" level) to the oscillation circuit 46. Note that Timer 45 corresponds to the "determination circuit," and the predetermined level Vccuvlo corresponds to the "first predetermined level."

[0036] ==Oscillator Circuit 46== The oscillator circuit 46 outputs an oscillation signal Vosc with oscillation frequency Fsw based on whether or not it is a soft-start period. Specifically, before a predetermined period P has elapsed, the oscillator circuit 46 outputs an oscillation signal Vosc with an oscillation frequency of Fsw1 or lower. After the predetermined period P has elapsed, the oscillator circuit 46 outputs an oscillation signal Vosc that changes in the range from at least oscillation frequency Fsw1 to oscillation frequency Fsw2 which is higher than oscillation frequency Fsw1, based on the output voltage Vout.

[0037] Furthermore, before a predetermined period P has elapsed, the oscillation circuit 46 outputs an oscillation signal Vosc that changes in the range from oscillation frequency Fsw1 to oscillation frequency Fsw0, which is lower than oscillation frequency Fsw1, based on the output voltage Vout. After a predetermined period P has elapsed, the oscillation circuit 46 outputs an oscillation signal Vosc that changes in the range from oscillation frequency Fsw0 to oscillation frequency Fsw2, which is higher than oscillation frequency Fsw1, based on the output voltage Vout.

[0038] <<<Configuration of oscillator circuit 46>>> Figure 3 shows an example of the configuration of the oscillator circuit 46. The oscillator circuit 46 outputs an oscillation signal Vosc with a frequency Fsw, or a frequency Fsw0 or Fsw1, corresponding to the voltage Vfb. Specifically, when an "L" level signal ssend is input to the oscillator circuit 46, it outputs an oscillation signal Vosc with a frequency Fsw0 or Fsw1. On the other hand, when an "H" level signal ssend is input to the oscillator circuit 46, it outputs an oscillation signal Vosc with a frequency of Fsw0 to Fsw2, based on a voltage Vfb corresponding to the decrease in the output voltage Vout, and with a frequency of Fsw0 or higher.

[0039] Furthermore, as will be described in detail later, when the output voltage Vout falls below the target level, the oscillation circuit 46 lowers the oscillation frequency of the oscillation signal Vosc during the soft-start period compared to the oscillation frequency of the oscillation signal Vosc during the normal period. This allows the control IC 32 to reduce switching noise during the soft-start period when the output voltage Vout is low. The oscillation circuit 46 is composed of a selection circuit 60, an adjustment circuit 61, and an oscillation signal output circuit 62.

[0040] ===Selection Circuit 60=== The selection circuit 60 selects a different reference voltage based on whether or not it is the soft-start period. Specifically, if the timer 45 outputs a "L" level signal ssend before a predetermined period P has elapsed, the selection circuit 60 selects a reference voltage VREF1 corresponding to the oscillation frequency Fsw1 as voltage V4. On the other hand, if the timer 45 outputs a "H" level signal ssend after a predetermined period P has elapsed, the selection circuit 60 selects a reference voltage VREF2 corresponding to the oscillation frequency Fsw2 as voltage V4. Reference voltage VREF1 corresponds to the "first voltage," reference voltage VREF2 corresponds to the "second voltage," and voltage V4 corresponds to the "selected voltage."

[0041] ===Adjustment circuit 61=== The adjustment circuit 61 outputs a voltage that adjusts the frequency of the oscillation signal Vosc based on a voltage Vfb corresponding to the output voltage Vout. The adjustment circuit 61 is composed of a voltage divider circuit 70 and voltage output circuits 71 and 72.

[0042] ====Voltage Divider Circuit 70==== The voltage divider circuit 70 divides the voltage Vfb_div to generate voltages Vfb0 and Vfb1. The voltage divider circuit 70 divides the voltage Vfb_div and outputs the voltage such that voltage Vfb0 is lower than voltage Vfb1.

[0043] The voltage divider circuit 70 is composed of resistors 80 to 82. The voltage divider circuit 70 has one end to which a voltage Vfb_div is applied and the other end to ground. Resistors 80 to 82 are connected in series between the one end and the other end. The voltage divider circuit 70 generates a voltage Vfb1 at the connection point between resistor 80 and resistor 81, and a voltage Vfb0 at the connection point between resistor 81 and resistor 82.

[0044] ====Voltage Output Circuit 71==== The voltage output circuit 71 outputs a voltage that changes the oscillation frequency Fsw of the oscillation signal Vosc from oscillation frequency Fsw1 to oscillation frequency Fsw2. Specifically, the voltage output circuit 71 outputs a reference voltage VREF1 corresponding to the oscillation frequency Fsw1 and a voltage V3 corresponding to the voltage Vfb, with the voltage that increases the frequency of the oscillation signal Vosc being output as voltage V2.

[0045] Furthermore, the voltage output circuit 71 outputs the reference voltage VREF1 as voltage V2 when the voltage Vfb changes and the voltage V3 corresponding to the voltage Vfb1 is lower than the reference voltage VREF1. Also, when the voltage Vfb changes and the voltage V3 becomes higher than the reference voltage VREF1, the voltage output circuit 71 outputs the voltage V3 as voltage V2. The voltage output circuit 71 is also composed of operational amplifiers 90, 95 and resistors 91 to 94.

[0046] Op-amp 90 and resistors 91-94 output a voltage V3 that increases as the voltage Vfb1 increases. Op-amp 95 outputs the higher of the two voltages connected to its non-inverting inputs, V3 or the reference voltage VREF1, as voltage V2.

[0047] Therefore, the operational amplifier 95, i.e., the voltage output circuit 71, outputs the reference voltage VREF1 as voltage V2 until the voltage Vfb1 rises and voltage V3 becomes equal to the reference voltage VREF1, and when voltage V3 becomes higher than the reference voltage VREF1, it outputs voltage V3 as voltage V2. Note that the voltage output circuit 71 corresponds to the "first voltage output circuit", voltage V3 corresponds to the "third voltage", and voltage V2 corresponds to the "first adjustment voltage".

[0048] ====Voltage Output Circuit 72===== The voltage output circuit 72 outputs a voltage that changes the oscillation frequency Fsw of the oscillation signal Vosc from oscillation frequency Fsw0 to oscillation frequency Fsw1. Specifically, the voltage output circuit 72 outputs a reference voltage VREF3 corresponding to Fsw0, which is lower than oscillation frequency Fsw1, and a voltage V1 corresponding to voltage Vfb, of which the voltage that increases the frequency of the oscillation signal Vosc is output as voltage V0.

[0049] Furthermore, the voltage output circuit 72 outputs the reference voltage VREF3 as voltage V0 when the voltage Vfb changes and the voltage V1 corresponding to the voltage Vfb0 is lower than the reference voltage VREF3. Also, when the voltage Vfb changes and the voltage V1 becomes higher than the reference voltage VREF3, the voltage output circuit 72 outputs the voltage V1 as voltage V0. The voltage output circuit 72 is also composed of operational amplifiers 100 and 105 and resistors 101 to 104.

[0050] Furthermore, op-amp 100 corresponds to op-amp 90, resistors 101-104 correspond to resistors 91-94, and op-amp 105 corresponds to op-amp 95. Also, voltage Vfb0 corresponds to voltage Vfb1, and voltage V0 corresponds to voltage V2. Therefore, voltage output circuit 72 operates in the same way as voltage output circuit 71. Voltages V0, V2, and V4 correspond to "voltages that adjust the frequency of the oscillation signal," and voltage output circuit 72 corresponds to the "second voltage output circuit." In addition, reference voltage VREF3 corresponds to the "fourth voltage," voltage V1 corresponds to the "fifth voltage," and voltage V0 corresponds to the "second adjustment voltage."

[0051] ===Output circuit 62 for oscillation signal=== The oscillation signal output circuit 62 changes the oscillation frequency Fsw of the oscillation signal Vosc based on the input voltage and outputs it. Specifically, the oscillation signal output circuit 62 outputs the oscillation signal Vosc based on the voltage that lowers the frequency of the oscillation signal Vosc (i.e., the lowest voltage) among the voltages V0 and V2 from the adjustment circuit 61 and the voltage V4 from the selection circuit 60.

[0052] <<<Configuration of the oscillation signal output circuit 62>>> Figure 4 shows an example of the configuration of the oscillation signal output circuit 62. The oscillation signal output circuit 62 outputs an oscillation signal Vosc with an oscillation frequency Fsw based on the lowest voltage among the voltages V0, V2, and V4. Note that the reference voltage VREF1 is lower than the reference voltage VREF2, and the reference voltage VREF3 is lower than the reference voltage VREF1.

[0053] First, we will explain the change in the frequency of the oscillation signal Vosc output by the oscillation signal output circuit 62 when the signal ssend is at a "H" level (i.e., during the normal period). After that, we will explain the configuration of the oscillation signal output circuit 62.

[0054] Furthermore, when the signal ssend is at the "L" level (i.e., during the soft-start period), the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw0 or Fsw1.

[0055] As shown in Figure 5A, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw0 based on the reference voltage VREF3 when the voltage Vfb changes and the voltage V1 corresponding to the voltage Vfb0 is lower than the reference voltage VREF3. Furthermore, when the voltage Vfb changes and the voltage V1 becomes higher than the reference voltage VREF3, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw based on the voltage V1, which is higher than frequency Fsw0. Note that, as shown in Figure 5B, the voltage Vfba is the voltage of voltage Vfb when the voltage V1 becomes the reference voltage VREF3.

[0056] As shown in Figure 5A, when the voltage Vfb changes and the voltage V1 becomes higher than the reference voltage VREF1, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw1 based on the reference voltage VREF1. Also, when the voltage Vfb changes and the voltage V3 becomes higher than the reference voltage VREF1, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw based on voltage V3, which is higher than frequency Fsw1. As shown in Figure 5B, the voltage of voltage Vfb when voltage V1 becomes the reference voltage VREF1 is denoted as voltage Vfbb, and the voltage of voltage Vfb when voltage V3 becomes the reference voltage VREF1 is denoted as voltage Vfbc.

[0057] Then, as shown in Figure 5A, when the voltage Vfb changes and the voltage V3 becomes higher than the reference voltage VREF2, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw2 based on the reference voltage VREF2. Note that, as shown in Figure 5B, the voltage of Vfb when the voltage V3 becomes the reference voltage VREF2 is denoted as the voltage Vfbd.

[0058] The oscillation signal output circuit 62 is composed of an operational amplifier 110, NMOS transistors 111, 116, 117, 119, a resistor 112, PMOS transistors 113, 114, 115, 118, a capacitor 120, and a hysteresis comparator 121.

[0059] The operational amplifier 110 adjusts the gate voltage V6 of the NMOS transistor 111 so that the lowest voltage among the voltages V0, V2, and V4 applied to the three non-inverting inputs becomes the voltage V5 at the node to which the inverting input is connected. As a result, if the current flowing through the resistor 112 is current I0, the voltage generated across the resistor 112 due to the flow of current I0 through the resistor 112 is voltage V5.

[0060] PMOS transistors 113 to 115 form a current mirror circuit. PMOS transistor 114 supplies a current corresponding to the current I0 flowing through PMOS transistor 113, and PMOS transistor 115 supplies a current I1 corresponding to the current I0 flowing through PMOS transistor 113 when PMOS transistor 118 is turned on.

[0061] NMOS transistors 116 and 117 also constitute a current mirror circuit. NMOS transistor 116 supplies the current flowing through PMOS transistor 114. When NMOS transistor 119 is turned on, NMOS transistor 117 supplies a current I2 corresponding to the current flowing through PMOS transistor 114 and NMOS transistor 116.

[0062] The PMOS transistor 118 and the NMOS transistor 119 are switched on and off according to the logic level of the oscillation signal Vosc. When the oscillation signal Vosc is at the "L" level, the PMOS transistor 118 is turned on and the capacitor 120 is charged with current I1. At this time, the NMOS transistor 119 is turned off.

[0063] On the other hand, when the oscillation signal Vosc is at a "H" level, the NMOS transistor 119 is turned on and the capacitor 120 is discharged with current I2. At this time, the PMOS transistor 118 is turned off.

[0064] The hysteresis comparator 121 compares the voltage of capacitor 120 with a high threshold voltage Vthh or a low threshold voltage Vthl generated based on the reference voltage VREF4. If the voltage of capacitor 120 is higher than the high threshold voltage Vthh, the hysteresis comparator 121 outputs an oscillation signal Vosc at the "H" level. On the other hand, if the voltage of capacitor 120 is lower than the low threshold voltage Vthl, the hysteresis comparator 121 outputs an oscillation signal Vosc at the "L" level.

[0065] As explained above, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with a frequency Fsw that changes according to the voltage Vfb when the signal ssend is at the "H" level. As is clear from the circuit configuration of the oscillation signal output circuit 62 described above, the op-amp 110 flows a larger current I0 through the resistor 112 as the voltage of voltage V5, i.e., the lowest voltage among voltages V0, V2, and V4, increases. As currents I1 and I2 increase, the oscillation signal output circuit 62 outputs an oscillation signal Vosc with a higher oscillation frequency Fsw because the charging and discharging of capacitor 120 occurs faster when currents I1 and I2 increase.

[0066] Furthermore, as shown in Figure 6A, when the signal ssend is at the "L" level, even if the voltage Vfb becomes voltage Vfbd, the selection circuit 60 selects the reference voltage VREF1, so the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw1. Note that, as shown in Figure 6B, when the voltage Vfb becomes voltage Vfbc, the voltage V4 remains the reference voltage VREF1. Therefore, even when the voltage Vfb becomes voltage Vfbc, the operational amplifier 110 generates current I0 according to the reference voltage VREF1 from the selection circuit 60.

[0067] Furthermore, when the signal ssend is at the "L" level, if the voltage Vfb becomes voltage Vfba, then voltage V1 becomes voltage VREF3, and the oscillation signal output circuit 62 outputs an oscillation signal Vosc with frequency Fsw0.

[0068] Frequency Fsw1 corresponds to the "first frequency," frequency Fsw2 corresponds to the "second frequency," and frequency Fsw0 corresponds to the "third frequency." Furthermore, the range from oscillation frequency Fsw1 to oscillation frequency Fsw0 corresponds to the "first range," and the range from oscillation frequency Fsw0 to oscillation frequency Fsw2 corresponds to the "second range."

[0069] ==Output Circuit 47== Returning to Figure 2, the output circuit 47 is explained. When the power supply voltage Vcc rises to a predetermined level Vccuvlo, the output circuit 47 outputs a voltage Vss that changes in steps. Specifically, when the low-voltage protection circuit 41 outputs a signal rst that releases the reset of the control IC 32, the output circuit 47 outputs a voltage Vss that increases in steps. Then, when the timer 45 outputs a signal ssend at the "H" level, the output circuit 47 sets the voltage Vss to a voltage at least higher than the voltage Vfb_div (for example, the voltage Vdd). Note that the voltage Vss corresponds to the "sixth voltage".

[0070] ==Drive Circuit 48== The drive circuit 48 outputs a drive signal Vg based on the oscillation signal Vosc. Specifically, the drive circuit 48 switches the power transistor 30 based on the oscillation signal Vosc to gradually increase the ON period of the power transistor 30 in Figure 1 for a predetermined period P. On the other hand, after the predetermined period P has elapsed, the drive circuit 48 switches the power transistor 30 based on the oscillation signal Vosc.

[0071] Furthermore, the drive circuit 48 turns on the power transistor 30 based on the oscillation signal Vosc. The drive circuit 48 also turns off the power transistor 30 based on the voltage Vfb and the voltage Vss, which corresponds to the voltage that shortens the on period of the power transistor 30, and the voltage corresponding to the inductor current IL flowing through the power transistor 30.

[0072] Furthermore, the drive circuit 48 switches the power transistor 30 based on the oscillation signal Vosc, which changes within the range of oscillation frequency Fsw1 to oscillation frequency Fsw0 for a predetermined period P. After the predetermined period P has elapsed, the drive circuit 48 switches the power transistor 30 based on the oscillation signal Vosc, which changes within the range of oscillation frequency Fsw0 to oscillation frequency Fsw2.

[0073] The drive circuit 48 is composed of a one-shot circuit 50, an SR flip-flop 51, an OR circuit 52, a comparator 53, and a buffer 54.

[0074] ===One-shot circuit 50=== The one-shot circuit 50 outputs a pulse signal Vp1 at the rising edge of the oscillation signal Vosc, corresponding to the frequency Fsw of the oscillation signal Vosc.

[0075] ===SR Flip-Flop 51=== The SR flip-flop 51 outputs a high-level signal Vd when the one-shot circuit 50 outputs a pulse signal Vp1. On the other hand, the SR flip-flop 51 outputs a low-level signal Vd when the comparator 53 outputs a high-level signal Vr.

[0076] ===OR Circuit 52=== The OR circuit 52 performs a logical OR operation between the pulse signal Vp1 and the signal Vd and outputs it as signal Vq1. That is, when the pulse signal Vp1 or the signal Vd is at an "H" level, it outputs a "H" level signal Vq1. On the other hand, when the pulse signal Vp1 and the signal Vd are at an "L" level, the OR circuit 52 outputs a "L" level signal Vq1.

[0077] ===Comparator 53=== The comparator 53 compares the voltage Vcs when the power transistor 30 is ON with the lower of the voltages Vfb_div and Vss. If the voltage Vcs is higher than the voltage Vfb_div or the voltage Vss, it outputs a "H" level signal Vr. If the voltage Vcs when the power transistor 30 is ON is lower than the voltages Vfb_div and Vss, the comparator 53 outputs a "L" level signal Vr.

[0078] The voltage Vcs may also be input to the comparator 53 as voltage Vcs1 via a slope compensation circuit (not shown). In this case, voltage Vcs1 is compared with the lower of voltage Vfb_div and voltage Vss, and the comparator 53 outputs a "H" level signal Vr if voltage Vcs1 exceeds voltage Vfb_div or voltage Vss. On the other hand, the comparator 53 outputs a "L" level signal Vr if voltage Vcs1 is lower than voltage Vfb_div and voltage Vss.

[0079] Therefore, the SR flip-flop 51 outputs a low-level signal Vd when the voltage Vcs becomes higher than the voltage Vfb_div or voltage Vss, causing the comparator 53 to output a high-level signal Vr. As a result, the power transistor 30 is turned off when the voltage Vcs becomes higher than the voltage Vfb_div or voltage Vss.

[0080] ===Buffer 54=== Buffer 54 amplifies the signal Vq1 and outputs it as a drive signal Vg. Specifically, when the OR circuit 52 outputs a high-level signal Vq1, buffer 54 outputs a drive signal Vg that turns on the power transistor 30. On the other hand, when the OR circuit 52 outputs a low-level signal Vq1, buffer 54 outputs a drive signal Vg that turns off the power transistor 30. Note that the inductor current IL corresponds to the "current flowing through the transistor".

[0081] ===Comparator 49=== When the motor 11 in Figure 1 is under light load, and the output voltage Vout rises to a predetermined level, the comparator 49 instructs the drive circuit 48 to stop switching the power transistor 30. Specifically, when the voltage Vfb drops to the reference voltage Vref_stop, the comparator 49 outputs a signal "stop" to the drive circuit 48 to stop switching the power transistor 30. On the other hand, when the voltage Vfb is higher than the reference voltage Vref_stop, the comparator 49 outputs a signal "stop" to the drive circuit 48 to continue switching the power transistor 30. The comparator 49 corresponds to a "stop circuit," and the reference voltage Vref_stop corresponds to a "second predetermined level."

[0082] <<<Changes in frequency Fsw during normal periods>>> Figure 5A shows the change in the frequency Fsw of the signal Vg during the normal period. Figure 5B is a table showing the relationship between voltages V1, V3 and reference voltages VREF1 to VREF3 when voltage Vfb becomes voltage Vfba to Vfbd. As described above, when the signal ssend is at the "H" level, the oscillation circuit 46 outputs an oscillation signal Vosc with a frequency Fsw corresponding to the voltage Vfb.

[0083] Specifically, when voltage Vfb is lower than voltage Vfba, that is, when voltage V1 is lower than the reference voltage VREF3, the frequency Fsw of the pulse signal Vp1 becomes frequency Fsw0, which is based on the reference voltage VREF3. Furthermore, when voltage Vfb drops further below the reference voltage Vref_stop, the comparator 49 outputs a signal stop to stop switching the power transistor 30, so the frequency Fsw of the drive signal Vg becomes 0Hz.

[0084] Furthermore, when voltage Vfb becomes voltage Vfba, voltage V1 becomes the reference voltage VREF3, and the frequency Fsw of the drive signal Vg becomes the frequency based on voltage V1.

[0085] Furthermore, if voltage Vfb is higher than voltage Vfba and lower than voltage Vfbb, and voltage V1 is higher than reference voltage VREF3 and lower than reference voltage VREF1, the frequency Fsw of the drive signal Vg will increase in proportion to the increase in voltage Vfb (i.e., the increase in voltage V1).

[0086] Furthermore, when voltage Vfb becomes voltage Vfbb, voltage V1 becomes the reference voltage VREF1, and the frequency Fsw of the drive signal Vg becomes frequency Fsw1 based on the reference voltage VREF1.

[0087] Furthermore, if voltage Vfb is higher than voltage Vfbb and lower than voltage Vfbc, and voltage V3 is lower than the reference voltage VREF1, then the frequency Fsw of the drive signal Vg will be frequency Fsw1 based on the reference voltage VREF1.

[0088] Furthermore, when voltage Vfb becomes voltage Vfbc, voltage V3 becomes the reference voltage VREF1, and the frequency Fsw of the drive signal Vg becomes frequency Fsw1 based on voltage V3.

[0089] Furthermore, if voltage Vfb is higher than voltage Vfbc and lower than voltage Vfbd, and voltage V3 is higher than reference voltage VREF1 and lower than reference voltage VREF2, the frequency Fsw of the drive signal Vg will increase in proportion to the increase in voltage Vfb (i.e., the increase in voltage V3).

[0090] Furthermore, when voltage Vfb becomes voltage Vfbd, voltage V3 becomes the reference voltage VREF2, and the frequency Fsw of the drive signal Vg becomes the frequency Fsw2 based on the reference voltage VREF2.

[0091] Finally, when voltage Vfb becomes higher than voltage Vfbd and voltage V3 becomes higher than the reference voltage VREF2, the frequency Fsw of signal Vg becomes frequency Fsw2 based on the reference voltage VREF2.

[0092] <<<Changes in frequency Fsw during the soft start period>>> Figure 6A shows the change in frequency Fsw of the drive signal Vg during the soft-start period. Figure 6B is a table showing the relationship between voltages V1, V3, V4 and reference voltages VREF1, VREF3 when voltage Vfb becomes voltage Vfba to Vfbd. As described above, even when the signal ssend is at the "L" level (i.e., during the soft-start period), the oscillator circuit 46 outputs an oscillator signal Vosc with frequency Fsw corresponding to voltage Vfb.

[0093] Specifically, the change in the frequency Fsw of the drive signal Vg when the voltage Vfb changes from the reference voltage Vref_stop to the voltage Vfbc is the same as when the signal ssend is at the "H" level.

[0094] Furthermore, when the signal ssend is at the "L" level, the selection circuit 60 in Figure 3 selects the reference voltage VREF1 as voltage V4. Therefore, when voltage Vfb is higher than voltage Vfbc, unlike when the signal ssend is at the "H" level, the frequency Fsw of the drive signal Vg remains the same as frequency Fsw1 based on the reference voltage VREF1.

[0095] Therefore, when the output voltage Vout is lower than the target level and the voltage Vfb is higher than the voltage Vfbc, the oscillation frequency Fsw during the soft-start period becomes oscillation frequency Fsw1, as shown in Figure 6A. Under similar conditions, the oscillation frequency Fsw during the normal period becomes higher than oscillation frequency Fsw1, as shown in Figure 5A.

[0096] As a result, the frequency of the drive signal Vg output by the drive circuit 48 during the soft-start period is lower than the frequency of the drive signal Vg during the normal period, assuming the output voltage Vout is the same. Consequently, the switching frequency of the power transistor 30 in Figure 1 decreases during the soft-start period, and the switching noise from the power transistor 30 also decreases.

[0097] However, if the motor 11 does not require much power during normal operation, the output voltage Vout may rise above the target level. In this case, as shown in Figure 5A, the voltage Vfb may decrease and become lower than the voltage Vfbb, so the frequency of the drive signal Vg during the soft start period is not necessarily lower than the frequency of the drive signal Vg during normal operation.

[0098] <<<Operation of control IC32 during normal periods>>> Figure 7 shows an example of the operation of the control IC 32 during normal operation. Note that the voltage Vfb is higher than the reference voltage Vref_stop, and the drive circuit 48 outputs a drive signal Vg to switch the power transistor 30.

[0099] At time t0, when the oscillator circuit 46 outputs an oscillation signal Vosc at the "H" level based on a frequency corresponding to the voltage Vfb, the one-shot circuit 50 outputs a signal Vp1. Then, when the OR circuit 52 receives the signal Vp1, it outputs a "H" level Vq1. Also, when the SR flip-flop 51 receives the signal Vp1, it outputs a "H" level signal Vd.

[0100] As a result, the power transistor 30 is turned on, and the inductor current IL flows through the primary coil L1. When the inductor current IL flows through the power transistor 30, a voltage corresponding to the inductor current IL is generated across the resistor 31. Subsequently, as the inductor current IL increases, the voltage across the resistor 31 increases, and the voltage Vcs gradually rises.

[0101] At time t1, when the voltage Vcs rises and equals the voltage Vfb_div, the comparator 53 outputs a high-level signal Vr. As a result, the SR flip-flop 51 outputs a low-level signal Vd. Also, the OR gate 52 outputs a low-level signal Vq1. Therefore, the power transistor 30 is turned off. When the power transistor 30 is turned off, the inductor current IL does not flow through the primary coil L1. The period from time t0 to time t1 is the on-period of the power transistor 30.

[0102] From time t2 onward, when the oscillator circuit 46 outputs an oscillation signal Vosc at the "H" level, the operation from time t0 to time t2 is repeated.

[0103] <<<Operation of control IC32 during the soft-start period>>> Figure 8 shows an example of the operation of the control IC 32 during the soft-start period. Note that before time t10, the voltage Vfb is higher than the voltage Vfbd, and the drive circuit 48 outputs a drive signal Vg and switches the power transistor 30.

[0104] As the startup circuit 40 charges the capacitor 37 in Figure 1, at time t10 when the power supply voltage Vcc reaches a predetermined level Vccuvlo, the undervoltage protection circuit 41 outputs a signal rst ("H" level) that releases the reset of the control IC 32.

[0105] When the low-voltage protection circuit 41 outputs a signal rst at the "H" level, the timer 45 outputs a signal ssend at the "L" level. When the timer 45 outputs a signal ssend at the "L" level, the selection circuit 60 selects the reference voltage VREF1 as voltage V4.

[0106] In this case, as shown in Figure 6B, the oscillation frequency of the oscillation signal Vosc is frequency Fsw1. Then, when the undervoltage protection circuit 41 outputs a signal rst at the "H" level, the output circuit 47 outputs a voltage Vss that rises stepwise from the ground voltage.

[0107] At time t11, the output circuit 47 raises the voltage Vss from the ground voltage.

[0108] At time t12, when the oscillation signal Vosc reaches a high level, the one-shot circuit 50 outputs signal Vp1. When signal Vp1 is output, the drive circuit 48 sets the drive signal Vg to a high level. As a result, the power transistor 30 in Figure 1 is turned on.

[0109] When the power transistor 30 is turned on, at time t13, when the voltage Vcs becomes voltage Vss, the comparator 53 outputs a high-level signal Vr because voltage Vss is lower than voltage Vfb_div. When signal Vr becomes high, the SR flip-flop 51 outputs a low-level signal Vd. When the low-level signal Vd is output, the drive circuit 48 outputs a low-level drive signal Vg. As a result, the power transistor 30 in Figure 1 is turned off.

[0110] Subsequently, after the low-voltage protection circuit 41 outputs a "H" level signal rst, a predetermined period P has elapsed, and the timer 45 outputs a "H" level signal ssend at time t14, repeating the operation from time t12 to time t13. In addition, since the output circuit 47 outputs a voltage Vss that increases in stages, the ON period of the power transistor 30 gradually lengthens from time t12 to time t14.

[0111] At time t14, when the soft-start period (i.e., the predetermined period P) has elapsed and timer 45 outputs a signal ssend at the "H" level, the selection circuit 60 selects the reference voltage VREF2 as voltage V4. In this case, if the output voltage Vout is lower than the target level, the oscillation frequency of the oscillation signal Vosc becomes frequency Fsw2, as shown in Figure 5B.

[0112] Furthermore, when a "H" level signal ssend is input, the output circuit 47 sets the voltage Vss to a voltage higher than the voltage Vfb_div (for example, voltage Vdd). As a result, the voltage Vfb_div becomes lower than the voltage Vss, and from time t14 onwards, the control IC 32 operates as shown in Figure 7.

[0113] ===Unique Text=== Figure 9 shows an example of the configuration of the voltage output circuit 75. The voltage output circuit 75 is a modified version of the voltage output circuit 72. When the timer 45 outputs a signal ssend at an "L" level (i.e., for a predetermined period P), even if the voltage Vfb falls below the voltage Vfbb in Figure 6A, the voltage output circuit 75 outputs the reference voltage VREF1 as voltage V0.

[0114] The voltage output circuit 75 consists of operational amplifiers 100 and 105, resistors 101 to 104, analog switches 200 and 201, and an inverter 202. Components with the same reference numerals as the voltage output circuit 72 are identical to those in the voltage output circuit 72. Therefore, the differences, specifically the operation of the analog switches 200 and 201 and the inverter, will be explained below.

[0115] Analog switches 200 and 201 output voltage V1 or reference voltage VREF1 as voltage Vx based on the signal ssend from timer 45. Specifically, when the signal ssend is at the "H" level and the output of inverter 202 is at the "L" level, analog switch 200 is turned on and voltage Vx becomes voltage V1. Conversely, when the signal ssend is at the "L" level, analog switch 200 is turned off.

[0116] On the other hand, when the signal ssend is at a "L" level and the output of inverter 202 is at a "H" level, the analog switch 201 is turned on, and the voltage Vx becomes the reference voltage VREF1. Also, when the signal ssend is at a "H" level, the analog switch 201 is turned off.

[0117] The operational amplifier 105 outputs the voltage V0, whichever of the two voltages, VREF3 and Vx, increases the oscillation frequency Fsw of the oscillation signal Vosc. When the signal ssend is at a "H" level, the voltage output circuit 75 operates in the same way as the voltage output circuit 72. When the signal ssend is at a "L" level, since the reference voltage VREF1 is higher than the reference voltage VREF3, the voltage output circuit 75 outputs the reference voltage VREF1 as the voltage V0.

[0118] From the above, if the voltage output circuit 75 is used instead of the voltage output circuit 72, when the timer 45 outputs a signal ssend at the "L" level, the oscillator circuit 46 outputs an oscillator signal Vosc with frequency Fsw1.

[0119] ===Summary=== The AC-DC converter 10 of this embodiment has been described above. The control IC 32 includes a timer 45, an oscillator circuit 46, and a drive circuit 48. The oscillator circuit 46 outputs an oscillation signal Vosc with oscillation frequency Fsw1 before a predetermined period P has elapsed (i.e., during the soft-start period). Also, when the AC-DC converter 10 is started up, the output voltage Vout is lower than the target level, so the voltage Vfb is high. The oscillation frequency Fsw1 is lower than the oscillation frequency Fsw2 of the oscillation signal Vosc when the voltage Vfb is similarly high after a predetermined period P has elapsed (i.e., during the normal period). Therefore, the switching frequency of the power transistor 30 when the AC-DC converter 10 is started up is lower than the switching frequency during the normal period when the output voltage Vout is the same. This makes it possible to provide an integrated circuit that reduces the switching noise of the transistor when the AC-DC converter is started up.

[0120] The oscillation circuit 46 includes a selection circuit 60, an adjustment circuit 61, and an oscillation signal output circuit 62. Before a predetermined period P has elapsed, the selection circuit 60 selects a reference voltage VREF1 corresponding to the oscillation frequency Fsw1 as voltage V4, and after a predetermined period P has elapsed, it selects a reference voltage VREF2 corresponding to the oscillation frequency Fsw2 as voltage V4. As a result, the oscillation circuit 46, with a simple circuit, can output an oscillation signal Vosc with a lower oscillation frequency Fsw than during the normal period when the output voltage Vout is lower than the target level before a predetermined period P has elapsed.

[0121] The adjustment circuit 61 includes voltage output circuits 71 and 72. Because the adjustment circuit 61 includes voltage output circuits 71 and 72, the oscillation circuit 46 can change the oscillation frequency Fsw in response to a change in voltage Vfb, as shown in Figure 5A.

[0122] The control IC 32 includes a comparator 49. When the voltage Vfb becomes the reference voltage Vref_stop, that is, when the output voltage Vout rises above the target level, the comparator 49 stops switching the power transistor 30. This allows the control IC 32 to suppress further increases in the output voltage Vout.

[0123] The control IC 32 includes an output circuit 47. When the power supply voltage Vcc reaches a predetermined level Vccuvlo, the output circuit 47 outputs a voltage Vss that changes in steps (for example, increases). This allows the control IC 32 to gradually increase the output voltage Vout when the AC-DC converter 10 is started up.

[0124] The embodiments described above are provided to facilitate understanding of the present invention and are not intended to limit its interpretation. Furthermore, the present invention may be modified or improved without departing from its spirit, and it goes without saying that equivalents thereof are included. [Explanation of Symbols]

[0125] 10 AC-DC Converters 11 Motor 20 Full wave rectifier circuit 21 Capacitors 22 transformers 23 Control Block 24, 25, 38 diodes 26, 33, 35, 37, 120 Capacitors 27 Constant Voltage Circuit 28 Light-emitting diodes 30 Power Transistors 31, 34, 39, 42~44, 80~82, 91~94, 101~104, 112 resistors 32 control ICs 36 Phototransistors 40 Startup Circuit 41. Low-voltage protection circuit 45 timer 46 Oscillator Circuit 47 Output Circuit 48 Drive Circuit 49, 53 Comparators 50 One-Shot Circuits 51 SR Flip-Flop 52 OR circuits 54 buffers 60 Selection Circuits 61 Adjustment circuit 62 Oscillation signal output circuit 70 Voltage Divider Circuit 71,72 Voltage output circuit 90, 95, 100, 105, 110 op-amps 111, 116, 117, 119 NMOS transistors 113, 114, 115, 118 PMOS transistors 121 Hysteresis comparator

Claims

1. An integrated circuit for driving a transistor in a power supply circuit that includes a transistor for controlling the current flowing through a coil and for generating an output voltage of a target level from an input voltage, A determination circuit that determines whether a predetermined period has elapsed since the power supply voltage of the integrated circuit rose to a first predetermined level, An oscillator circuit that outputs an oscillation signal of a first frequency before the predetermined period has elapsed, and outputs the oscillation signal that changes in a range of at least from the first frequency to a second frequency higher than the first frequency based on the output voltage after the predetermined period has elapsed, A drive circuit that switches the transistor based on the oscillation signal to gradually increase the ON period of the transistor during the predetermined period, and switches the transistor based on the oscillation signal after the predetermined period has elapsed, An integrated circuit that includes [this component].

2. The integrated circuit according to claim 1, The aforementioned oscillator circuit is A selection circuit that, before the predetermined period has elapsed, selects a first voltage corresponding to the first frequency as the selected voltage, and after the predetermined period has elapsed, selects a second voltage corresponding to the second frequency as the selected voltage, An adjustment circuit that outputs a voltage to adjust the frequency of the oscillation signal based on a feedback voltage corresponding to the output voltage, An oscillation signal output circuit outputs the oscillation signal based on a voltage that lowers the frequency of the oscillation signal, among the voltage from the adjustment circuit and the selected voltage. including, Integrated circuit.

3. The integrated circuit according to claim 2, The adjustment circuit described above is A first voltage output circuit outputs a first adjustment voltage, which is one of the first voltages corresponding to the first frequency and a third voltage corresponding to the feedback voltage, and which increases the frequency of the oscillation signal. A second voltage output circuit outputs a voltage that increases the frequency of the oscillation signal, among a fourth voltage corresponding to a third frequency lower than the first frequency and a fifth voltage corresponding to the feedback voltage, as a second adjustment voltage. Includes, The aforementioned oscillation signal output circuit is Based on the selected voltage, the first adjustment voltage, and the second adjustment voltage, the oscillation signal is output based on the voltage that lowers the frequency of the oscillation signal. Integrated circuit.

4. An integrated circuit according to claim 2 or 3, When the output voltage rises and the feedback voltage reaches a second predetermined level, the drive circuit is configured to stop the switching of the transistor. Equipped with, Integrated circuit.

5. An integrated circuit according to any one of claims 2 to 4, When the power supply voltage rises to the first predetermined level, an output circuit outputs a sixth voltage that changes in steps. Equipped with, The aforementioned drive circuit is Based on the oscillation signal, the transistor is turned on, and based on the feedback voltage and the sixth voltage, the voltage that shortens the on-period of the transistor and the voltage corresponding to the current flowing through the transistor are used to turn off the transistor. Integrated circuit.

6. An integrated circuit for driving a transistor in a power supply circuit that includes a transistor for controlling the current flowing through a coil and for generating an output voltage of a target level from an input voltage, A determination circuit that determines whether a predetermined period has elapsed since the power supply voltage of the integrated circuit rose to a first predetermined level, An oscillator circuit that, before the predetermined period has elapsed, outputs an oscillation signal that changes in a first range from a first frequency to a third frequency lower than the first frequency based on the output voltage, and after the predetermined period has elapsed, outputs the oscillation signal that changes in a second range from a third frequency to a second frequency higher than the first frequency based on the output voltage, A drive circuit that switches the transistor based on the oscillation signal which changes within the first range for a predetermined period, and switches the transistor based on the oscillation signal which changes within the second range after the predetermined period has elapsed, An integrated circuit that includes [this component].

7. A power supply circuit that generates an output voltage of a target level from an input voltage, A transistor controls the current flowing through the coil, An integrated circuit that drives the aforementioned transistor, Equipped with, The aforementioned integrated circuit is A determination circuit that determines whether a predetermined period has elapsed since the power supply voltage of the integrated circuit rose to a first predetermined level, An oscillator circuit that outputs an oscillation signal of a first frequency before the predetermined period has elapsed, and outputs the oscillation signal that changes in a range of at least from the first frequency to a second frequency higher than the first frequency based on the output voltage after the predetermined period has elapsed, A drive circuit that switches the transistor based on the oscillation signal to gradually increase the ON period of the transistor during the predetermined period, and switches the transistor based on the oscillation signal after the predetermined period has elapsed, A power supply circuit including this.

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