Semiconductor equipment

Abstract

To provide a semiconductor device that preferably has a structure which is easily made compact while suppressing an influence of a defective region on a transistor part.SOLUTION: There is provided a semiconductor device that has a first part which is not provided with a lifetime adjustment region while a border region between a transistor part and a diode part is in contact with the transistor part, and a second part which is in contact with the diode part and is provided with a lifetime adjustment region for the diode part in an extended state. The density distribution of a lifetime killer in a first direction has a lateral slop decreasing in the density of the lifetime killer from the second part to the first part of the border region, and the width of the first part is smaller than that of the second part in the first direction and also larger than that of the lateral slope in the first direction.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] In semiconductor devices having a transistor section and a diode section, a structure is known in which a defect region is partially formed in the diode section to adjust the carrier lifetime (see, for example, Patent Documents 1 and 2). Patent document 1 WO2018 / 110703 Patent document 2 WO2019 / 111572 [Overview of the Initiative] [Problems that the invention aims to solve]

[0003] In semiconductor devices, it is preferable to have a structure that is easy to miniaturize while suppressing the influence of defect regions on the transistor portion. [Means for solving the problem]

[0004] To solve the above problems, a first embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface. The semiconductor device may include a transistor portion provided on the semiconductor substrate. The semiconductor device may include a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction. The semiconductor device may include a boundary region provided on the semiconductor substrate and arranged between the transistor portion and the diode portion. In any of the above semiconductor devices, the diode portion may be arranged on the upper surface side of the semiconductor substrate and have a lifetime adjustment region including a lifetime killer for adjusting the lifetime of carriers. In any of the above semiconductor devices, the boundary region may have a first portion in contact with the transistor portion and not having the lifetime adjustment region. In any of the above semiconductor devices, the boundary region may have a second portion in contact with the diode portion and having an extension of the lifetime adjustment region of the diode portion. In any of the above semiconductor devices, the density distribution of the lifetime killer in the first direction may have a lateral slope in which the density of the lifetime killer decreases from the second portion of the boundary region toward the first portion. In any of the above semiconductor devices, the width of the first portion may be smaller than the width of the second portion in the first direction. In any of the above semiconductor devices, the width of the first portion may be greater than or equal to the width of the lateral slope in the first direction.

[0005] In any of the above semiconductor devices, the density distribution of the lifetime killer in the depth direction of the semiconductor substrate may have a density peak in the second portion. In any of the above semiconductor devices, the width of the first portion in the first direction may be greater than or equal to the peak width of the density peak in the depth direction.

[0006] In any of the semiconductor devices described above, the width of the first portion in the first direction may be greater than or equal to the distance from the upper surface of the semiconductor substrate to the density peak.

[0007] In any of the above semiconductor devices, the transistor portion may have a plurality of trench portions arranged side by side in the first direction. In any of the above semiconductor devices, the transistor portion may have a mesa portion sandwiched between two of the trench portions. In any of the above semiconductor devices, the width of the first portion in the first direction may be twice or more the width of the mesa portion in the first direction.

[0008] In any of the above semiconductor devices, the transistor portion may have a plurality of trench portions arranged side by side in the first direction. In any of the above semiconductor devices, the transistor portion may have a mesa portion sandwiched between two of the trench portions. In any of the above semiconductor devices, the width of the first portion in the first direction may be greater than the combined width of at least one of the trench portions in the boundary region and the widths of the two mesa portions sandwiching the trench portion.

[0009] In any of the semiconductor devices described above, the width of the first portion in the first direction may be 1 μm or more.

[0010] In any of the semiconductor devices described above, the width of the first portion in the first direction may be 10 μm or more.

[0011] In any of the above semiconductor devices, the width of the boundary region in the first direction may be 200 μm or less.

[0012] In any of the above semiconductor devices, the width of the first portion in the first direction may be 10% or more of the width of the boundary region in the first direction.

[0013] In any of the above semiconductor devices, the width of the second portion in the first direction may be greater than or equal to the distance from the upper surface of the semiconductor substrate to the density peak.

[0014] In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type. In any of the above semiconductor devices, the transistor portion may have an emitter region disposed between the drift region and the upper surface of the semiconductor substrate, and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the transistor portion may have a base region of a second conductivity type disposed between the emitter region and the drift region. In any of the above semiconductor devices, the transistor portion may have a storage region disposed between the base region and the drift region, and having a doping concentration higher than that of the drift region. In any of the above semiconductor devices, the storage region may be disposed in at least a part of the first portion. In any of the above semiconductor devices, the storage region may not be disposed in the second portion.

[0015] In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type. In any of the above semiconductor devices, the transistor portion may have an emitter region disposed between the drift region and the upper surface of the semiconductor substrate, and having a higher doping concentration than the drift region. In any of the above semiconductor devices, the transistor portion may have a base region of a second conductivity type disposed between the emitter region and the drift region. In any of the above semiconductor devices, the diode portion may have an anode region of a second conductivity type disposed between the drift region and the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the doping concentrations of the base region and the anode region may be different.

[0016] In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type. In any of the above semiconductor devices, the transistor portion may have a plurality of trench portions arranged side by side in the first direction. In any of the above semiconductor devices, the transistor portion may have a lower end region of a second conductivity type provided in contact with at least the lower end of the trench portion closest to the boundary region among the plurality of trench portions. In any of the above semiconductor devices, the lower end region may be provided so as to extend to the second portion.

[0017] In any of the above semiconductor devices, the semiconductor substrate may have a drift region of a first conductivity type. In any of the above semiconductor devices, the transistor portion may have a plurality of trench portions arranged side by side in the first direction. In any of the above semiconductor devices, the transistor portion may have a lower end region of a second conductivity type provided in contact with at least the lower end of the trench portion closest to the boundary region among the plurality of trench portions. In any of the above semiconductor devices, the lower end region may be provided so as to extend to the first portion and may not be provided in the second portion.

[0018] In any of the above semiconductor devices, in the first direction, the distance between the lower end region and the second portion may be equal to or greater than the width of the horizontal slope.

[0019] Any of the above semiconductor devices may include an upper surface electrode disposed above the upper surface of the semiconductor substrate. Any of the above semiconductor devices may include an interlayer insulating film disposed between the upper surface electrode and the semiconductor substrate. In any of the above semiconductor devices, a contact hole that connects the upper surface electrode and the semiconductor substrate and has a longitudinal direction in a second direction may be provided in the interlayer insulating film in the boundary region. In any of the above semiconductor devices, when the end portion of the contact hole in the second direction is taken as the end portion of the boundary region in the second direction, the second portion in a top view of Area Sk and the boundary region of Area S may satisfy the following formula. 0.8 ≤ Sk / S < 1

[0020] A second embodiment of the present invention provides a semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface. The semiconductor device may include a transistor portion provided on the semiconductor substrate. The semiconductor device may include a diode portion provided on the semiconductor substrate and arranged alongside the transistor portion in a first direction. The semiconductor device may include a boundary region provided on the semiconductor substrate and arranged between the transistor portion and the diode portion. The semiconductor device may include an upper electrode arranged above the upper surface of the semiconductor substrate. The semiconductor device may include an interlayer insulating film arranged between the upper electrode and the semiconductor substrate. In any of the above semiconductor devices, the diode portion may have a lifetime adjustment region arranged on the upper surface side of the semiconductor substrate and including a lifetime killer for adjusting the lifetime of carriers. In any of the above semiconductor devices, the boundary region may have a first portion in contact with the transistor portion and not having the lifetime adjustment region. In any of the above semiconductor devices, the boundary region may have a second portion in contact with the diode portion and having an extension of the lifetime adjustment region of the diode portion. In any of the above semiconductor devices, the interlayer insulating film may be provided with a contact hole having a longitudinal length in the second direction that connects the upper electrode and the semiconductor substrate in the boundary region. In any of the above semiconductor devices, when the end of the contact hole in the second direction is the end of the boundary region in the second direction, the second portion in a top view is Area Sk and the boundary region Area S And may satisfy the following equation. 0.8 ≤ Sk / S < 1

[0021] The above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0022] [Figure 1]This is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. [Figure 2] This is a magnified view of region D in Figure 1. [Figure 3] Figure 2 shows an example of an ee cross-section. [Figure 4] Figure 3 shows an example of the lifetime killer density distribution 210 along the line a-a'. [Figure 5] Figure 3 shows an example of the lifetime killer density distribution 220 along the b-b' line. [Figure 6] This figure shows another example of the configuration of boundary region 200. [Figure 7] This figure shows another example of an ee section. [Figure 8] This figure shows another example of an ee section. [Figure 9] This figure shows another example of an ee section. [Figure 10] This figure shows another example of an ee section. [Figure 11] This figure shows another example of an ee section. [Figure 12] This figure shows an example of the arrangement of the first part 201 and the second part 202 in a top view. [Figure 13] This figure shows the relationship between the area ratio Sk / S and the reverse recovery loss Err of the diode section 80. [Figure 14] This figure shows the relationship between lifetime killer density, carrier lifetime, and charged particle concentration in the lifetime adjustment region 206. [Modes for carrying out the invention]

[0023] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0024] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0025] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0026] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0027] The region from the center of the semiconductor substrate in the depth direction to the top surface of the semiconductor substrate is sometimes referred to as the top surface. Similarly, the region from the center of the semiconductor substrate in the depth direction to the bottom surface of the semiconductor substrate is sometimes referred to as the bottom surface.

[0028] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0029] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0030] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N D , the acceptor concentration is N A Therefore, the net doping concentration at any given position is N D -N A In this specification, net doping concentration may be simply referred to as doping concentration.

[0031] Donors have the function of supplying electrons to a semiconductor. Acceptors have the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to impurities themselves. For example, a VOH defect in a semiconductor, which is a combination of a vacancy (V), oxygen (O), and hydrogen (H), functions as an electron-supplying donor. A hydrogen donor may be a donor with at least a vacancy (V) and hydrogen (H) bonded together. Alternatively, an interstitial Si-H bond in a silicon semiconductor, which is a combination of interstitial silicon (Si-i) and hydrogen, also functions as an electron-supplying donor. In this specification, VOH defects or interstitial Si-H may be referred to as hydrogen donors.

[0032] In this specification, in the semiconductor substrate, N-type bulk donors are distributed throughout. The bulk donors are donors by dopants contained substantially uniformly in the ingot at the time of manufacturing the ingot that is the source of the semiconductor substrate. The bulk donors in this example are elements other than hydrogen. The dopants of the bulk donors are, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited thereto. The bulk donor in this example is phosphorus. The bulk donors are also included in the P-type regions. The semiconductor substrate may be a wafer cut out from a semiconductor ingot, or may be a chip obtained by singulating the wafer. The semiconductor ingot may be manufactured by any of the Czochralski method (CZ method), magnetic field applied Czochralski method (MCZ method), and float zone method (FZ method). The ingot in this example is manufactured by the MCZ method. The oxygen concentration contained in the substrate manufactured by the MCZ method is 1×10 17 ~7×10 17 / cm 3 . The oxygen concentration contained in the substrate manufactured by the FZ method is 1×10 15 ~5×10 16 / cm 3 . There is a tendency that a higher oxygen concentration makes it easier to generate hydrogen donors. The bulk donor concentration may use the chemical concentration of the bulk donors distributed throughout the semiconductor substrate, and may be a value between 90% and 100% of the chemical concentration. Also, a non-doped substrate that does not contain dopants such as phosphorus may be used as the semiconductor substrate. In that case, the bulk donor concentration (D0) of the non-doping substrate is, for example, 1×10 10 / cm 3 or more and 5×10 12 / cm 3 or less. The bulk donor concentration (D0) of the non-doping substrate is preferably 1×10 11 / cm 3 or more. The bulk donor concentration (D0) of the non-doping substrate is preferably 5×10 12 / cm 3 or less. Incidentally, each concentration in the present invention may be a value at room temperature. The value at room temperature may use, as an example, the value at 300 K (Kelvin) (about 26.9°C).

[0033] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type. Unless otherwise specified, the units used in this specification are SI units. Although units of length may be expressed in cm, calculations may be performed after converting to meters (m).

[0034] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0035] If the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of the donor, acceptor, or net doping in that region. If the concentrations of the donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of the donor, acceptor, or net doping in that region may be used as the concentration of the donor, acceptor, or net doping. In this specification, concentrations per unit volume are expressed as atoms / cm³. 3 , or / cm 3This unit is used for donor or acceptor concentrations in semiconductor substrates, or for chemical concentrations. The atom notation may be omitted.

[0036] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0037] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV method or SR method may be lower than the chemical concentrations of the elements that act as donors or acceptors. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which also acts as a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0038] Figure 1 is a top view showing an example of a semiconductor device 100 according to one embodiment of the present invention. In Figure 1, the positions of each component projected onto the upper surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted.

[0039] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has edges 162 when viewed from above. In this specification, when simply referred to as "top view," it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 162 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 162. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0040] The semiconductor substrate 10 is provided with an active area 160. The active area 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active area 160, but it is omitted in Figure 1. The active area 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Also, the region sandwiched between the active areas 160 when viewed from above may be included in the active area 160.

[0041] The active section 160 is provided with a transistor section 70 including a transistor element such as an IGBT (Insulated Gate Bipolar Transistor), and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are alternately arranged along a predetermined first direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). A boundary region is located between the transistor section 70 and the diode section 80 in the X-axis direction, but it is omitted in Figure 1.

[0042] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, a direction different from the first direction in a top view may be referred to as the second direction (the Y-axis direction in Figure 1). The second direction may be perpendicular to the first direction. The transistor section 70 and the diode section 80 may each have their longitudinal length in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0043] The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0044] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0045] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current sensing pad. Each pad is located near the edge 162. The vicinity of the edge 162 refers to the area between the edge 162 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0046] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 164 to the gate trench. In Figure 1, the gate wiring is shown with diagonal hatching.

[0047] The gate wiring in this example has an outer gate wiring 130 and an active gate wiring 131. The outer gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 in a top view. In this example, the outer gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer gate wiring 130 in a top view may be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher density than the base region, which will be described later, and is formed from the top surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region in a top view may be considered the active portion 160.

[0048] The outer perimeter gate wiring 130 is connected to the gate pad 164. The outer perimeter gate wiring 130 is located above the semiconductor substrate 10. The outer perimeter gate wiring 130 may be a metal wiring containing aluminum or the like.

[0049] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 164 can be reduced for each region of the semiconductor substrate 10.

[0050] The outer periphery gate wiring 130 and the active side gate wiring 131 are connected to the gate trench portion of the active portion 160. The outer periphery gate wiring 130 and the active side gate wiring 131 are positioned above the semiconductor substrate 10. The outer periphery gate wiring 130 and the active side gate wiring 131 may be wirings formed from a semiconductor such as polysilicon doped with impurities.

[0051] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction from one outer gate wiring 130 to the other outer gate wiring 130 that sandwiches the active section 160, crossing the active section 160 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0052] The semiconductor device 100 may include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0053] In this example, the semiconductor device 100 includes an edge termination structure 90 between the active portion 160 and the edge 162 when viewed from above. In this example, the edge termination structure 90 is positioned between the outer peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0054] Figure 2 is an enlarged view of region D in Figure 1. Region D is the region including the transistor section 70, the diode section 80, and the active-side gate wiring 131. Although omitted in Figure 1, a boundary region 200 is located between the transistor section 70 and the diode section 80 in the X-axis direction. The semiconductor device 100 in this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. The semiconductor device 100 in this example also includes an emitter electrode 52 and an active-side gate wiring 131 provided above the upper surface of the semiconductor substrate 10. The emitter electrode 52 is an example of an upper surface electrode. The emitter electrode 52 and the active-side gate wiring 131 are provided separately from each other.

[0055] An interlayer insulating film is provided between the emitter electrode 52 and the active gate wiring 131 and the upper surface of the semiconductor substrate 10, but this is omitted in Figure 2. In this example, contact holes 54 are provided in the interlayer insulating film, penetrating the film. In Figure 2, each contact hole 54 is hatched with diagonal lines.

[0056] The emitter electrode 52 is provided above the gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. The emitter electrode 52 contacts the emitter region 12, contact region 15, and base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. The emitter electrode 52 is also connected to a dummy conductive part in the dummy trench 30 through a contact hole provided in the interlayer insulating film. The emitter electrode 52 may be connected to a dummy conductive part of the dummy trench 30 at its tip in the Y-axis direction. The dummy conductive part of the dummy trench 30 does not need to be connected to the emitter electrode 52 and the gate conductive part, and may be controlled to a potential different from the potential of the emitter electrode 52 and the gate conductive part.

[0057] The active gate wiring 131 connects to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active gate wiring 131 may be connected to the gate conductive portion of the gate trench portion 40 at the tip portion 41 of the gate trench portion 40 in the Y-axis direction. The active gate wiring 131 is not connected to the dummy conductive portion in the dummy trench portion 30.

[0058] The emitter electrode 52 is formed from a material containing metal. Figure 2 shows the area in which the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. The emitter electrode 52 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Furthermore, it may have a plug formed by embedding tungsten or the like in the contact hole so as to be in contact with the barrier metal and the aluminum or the like.

[0059] The well region 11 is provided overlapping with the active gate wiring 131. The well region 11 also extends to a predetermined width in an area that does not overlap with the active gate wiring 131. In this example, the well region 11 is provided away from the Y-axis end of the contact hole 54 towards the active gate wiring 131. The well region 11 is a second conductivity type region with a higher doping concentration than the base region 14. In this example, the base region 14 is P-type, and the well region 11 is P+-type.

[0060] Each of the transistor section 70, the diode section 80, and the boundary region 200 has multiple trench sections arranged in a first direction. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the first direction. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the first direction. In this example, the diode section 80 does not have gate trench sections 40. In this example, the boundary region 200 has multiple dummy trench sections 30 provided along the first direction. In this example, the boundary region 200 does not have gate trench sections 40.

[0061] The gate trench section 40 in this example may have two straight sections 39 (the trench section which is linear along the second direction) extending along a second direction perpendicular to the first direction, and a tip section 41 connecting the two straight sections 39. In Figure 2, the second direction is the Y-axis direction.

[0062] Preferably, at least a portion of the tip portion 41 is provided in a curved shape when viewed from above. By connecting the ends of the two straight portions 39 in the Y-axis direction with the tip portion 41, electric field concentration at the ends of the straight portions 39 can be mitigated.

[0063] In the transistor section 70, the dummy trench section 30 is provided between each of the straight sections 39 of the gate trench section 40. There may be one dummy trench section 30 between each of the straight sections 39, or there may be multiple dummy trench sections 30. The dummy trench section 30 may have a straight shape extending in a second direction, and like the gate trench section 40, it may have a straight section 29 and a tip section 31. The semiconductor device 100 shown in Figure 2 includes both a dummy trench section 30 with a straight shape without a tip section 31 and a dummy trench section 30 with a tip section 31.

[0064] The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 11 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 11. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0065] In the first direction, mesa portions are provided between each trench portion. A mesa portion refers to the region sandwiched between the trench portions within the semiconductor substrate 10. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the second direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80 and the boundary region 200. In this specification, when simply referred to as a mesa portion, it refers to the mesa portion 60 and the mesa portion 61, respectively.

[0066] Each mesa portion is provided with a base region 14. Of the base regions 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, the region closest to the active gate wiring 131 is defined as base region 14-e. Figure 2 shows the base region 14-e located at one end of each mesa portion in the second direction, but a base region 14-e is also located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0067] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 60 in contact with the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0068] Each of the contact region 15 and emitter region 12 in the mesa portion 60 extends from one trench portion to the other in the X-axis direction. As an example, the contact region 15 and emitter region 12 of the mesa portion 60 are arranged alternately along the second direction (Y-axis direction) of the trench portion.

[0069] In other examples, the contact region 15 and emitter region 12 of the mesa portion 60 may be arranged in a stripe pattern along the second direction (Y-axis direction) of the trench portion. For example, the emitter region 12 may be provided in the region adjacent to the trench portion, and the contact region 15 may be provided in the region sandwiched between the emitter regions 12.

[0070] The diode portion 80 and the mesa portion 61 of the boundary region 200 do not have an emitter region 12. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa portion 61. In the region on the upper surface of the mesa portion 61 sandwiched between the base regions 14-e, a contact region 15 may be provided in contact with each base region 14-e. In the region on the upper surface of the mesa portion 61 sandwiched between the contact regions 15, a base region 14 may be provided. The base region 14 may be arranged in the entire region sandwiched between the contact regions 15.

[0071] A contact hole 54 is provided above each mesa portion. The contact hole 54 is located in the region sandwiched between the base region 14-e. In this example, the contact hole 54 is provided above the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not provided in the region corresponding to the base region 14-e and the well region 11. The contact hole 54 may be located in the center of the mesa portion 60 in the first direction (X-axis direction).

[0072] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. In Figure 2, the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0073] The cathode region 82 is positioned away from the well region 11 in the Y-axis direction. This ensures a distance between the cathode region 82 and the P-type region (well region 11), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance. In this example, the Y-axis end of the cathode region 82 is positioned further from the well region 11 than the Y-axis end of the contact hole 54. In other examples, the Y-axis end of the cathode region 82 may be positioned between the well region 11 and the contact hole 54.

[0074] Figure 3 shows an example of the ee cross-section in Figure 2. The ee cross-section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section.

[0075] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, and other insulating films. The interlayer insulating film 38 is provided with contact holes 54 as described in Figure 2.

[0076] The emitter electrode 52 is located above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through a contact hole 54 in the interlayer insulating film 38. The collector electrode 24 is located on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0077] The semiconductor substrate 10 has N-type or N-type drift regions 18. The drift regions 18 are provided in the transistor section 70, the diode section 80, and the boundary region 200, respectively.

[0078] The mesa portion 60 of the transistor portion 70 is provided with an N+ type emitter region 12 and a P type base region 14, arranged sequentially from the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18.

[0079] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0080] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60.

[0081] The accumulation region 16 is located below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. In other words, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced and the on-voltage can be reduced. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0082] A P-type base region 14 is provided in the mesa region 61 of the diode region 80 and the boundary region 200, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. A storage region 16 may also be provided below the base region 14 in the mesa region 61.

[0083] In each of the transistor section 70, the diode section 80, and the boundary region 200, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration in the buffer region 20 is higher than the doping concentration in the drift region 18. The buffer region 20 may have a concentration peak with a higher doping concentration than the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the peak of the concentration peak. In addition, the doping concentration of the drift region 18 may be the average value of the doping concentration in a region where the doping concentration distribution is almost flat.

[0084] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0085] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0086] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than that of the drift region 18. The donor in the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that act as donors and acceptors in each region are not limited to the examples described above.

[0087] In the boundary region 200, a P+ type collector region 22 is provided below the buffer region 20. The collector region 22 of the boundary region 200 is the transistor section 70 Collector area 22 It may have the same doping concentration. The boundary position in the X-axis direction between the cathode region 82 and the collector region 22 is set as the boundary position in the X-axis direction between the diode section 80 and the boundary region 200. In addition, of the gate trench sections 40 that are in contact with the emitter region 12, the gate trench section 40 that is closest to the diode section 80 in the X-axis direction is set as the boundary position in the X-axis direction between the transistor section 70 and the boundary region 200. The central position in the X-axis direction of this gate trench section 40 may be set as the boundary position in the X-axis direction between the transistor section 70 and the boundary region 200. Of the two trench sections that are in contact with the emitter region 12 and are closest to the diode section 80 in the X-axis direction, the trench section on the diode section 80 side may be a dummy trench section 30. In this case, the dummy trench section 30 may be set as the boundary position in the X-axis direction between the transistor section 70 and the boundary region 200. For example, in the boundary region 200, the structure of the mesa portion 61 located on the upper surface 21 side of the semiconductor substrate 10 is the same as that of the diode portion 80, and the structure on the lower surface 23 side (collector region 22 and buffer region 20 in this example) is the same as that of the transistor portion 70.

[0088] An emitter region 12 may be provided in the boundary region 200. However, in that case, the gate trench 40 is not provided in the boundary region 200. Also, the trench at the boundary position between the transistor 70 and the boundary region 200 is a dummy trench 30. That is, no transistor operation occurs in the boundary region 200. A gate trench 40 may be provided in the boundary region 200. However, in that case, the emitter region 12 is not provided in the boundary region 200. That is, no transistor operation occurs in the boundary region 200.

[0089] The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed from a metallic material such as aluminum.

[0090] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and down to below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and storage region 16 is provided, each trench also penetrates these doping regions. The statement that a trench penetrates a doping region is not limited to manufacturing in the order of forming the doping region before forming the trench. Manufacturing in which doping regions are formed between the trenches after the trenches have been formed is also included in the statement that a trench penetrates a doping region.

[0091] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 and the boundary region 200 are provided with a dummy trench section 30, but the gate trench section 40 is not provided. However, the boundary between the boundary region 200 and the transistor section 70 may have a gate trench section 40, or a dummy trench section 30.

[0092] The gate trench portion 40 has a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0093] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0094] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed from a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0095] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The bottom portions of the dummy trench portion 30 and the gate trench portion 40 may be curved (curved in cross-section) with a downward convex shape.

[0096] The semiconductor device 100 in this example includes a lifetime adjustment region 206 that includes a lifetime killer to adjust the lifetime of carriers. The lifetime adjustment region 206 in this example is a region where the lifetime of charge carriers is locally short. Charge carriers are electrons or holes. Charge carriers are sometimes simply referred to as carriers.

[0097] By injecting charged particles such as helium into a semiconductor substrate 10, lattice defects 204, such as vacancies, are formed near the injection site. These lattice defects 204 generate recombination centers. The lattice defects 204 may be mainly vacancies, such as single-atom vacancies (V) or double-atom vacancies (VV), but may also be dislocations, interstitial atoms, or transition metals. For example, atoms adjacent to a vacancy have dangling bonds. In a broad sense, lattice defects 204 may also include donors and acceptors, but in this specification, lattice defects 204 mainly consisting of vacancies may be referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, lattice defects 204 may be referred to simply as recombination centers or lifetime killers, as they contribute to carrier recombination. Lifetime killers may be formed by injecting helium ions into the semiconductor substrate 10. The density of lattice defects 204 may be defined as the helium chemical concentration. Furthermore, since the lifetime killer formed by helium injection may be terminated by hydrogen present in the buffer region 20, the depth position of the density peak of the lifetime killer may not coincide with the depth position of the helium chemical concentration peak. In addition, when hydrogen ions are injected into the semiconductor substrate 10, the lifetime killer may be formed in the hydrogen ion passage region on the injection surface side of the range.

[0098] Lattice defects 204 are an example of lifetime killers. In Figure 3, lattice defects 204 at the injection site of charged particles are schematically shown with an "x". In regions where many lattice defects 204 remain, carriers are trapped by the lattice defects 204, thus shortening the carrier lifetime. By adjusting the carrier lifetime, characteristics such as the reverse recovery time and reverse recovery loss of the diode section 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the position where the carrier lifetime shows a minimum value may be set as the depth position of the lifetime adjustment region 206.

[0099] The lifetime adjustment region 206 is located on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side is the region from the central position in the depth direction of the semiconductor substrate 10 to the upper surface 21 of the semiconductor substrate 10. In this example, the lifetime adjustment region 206 is located below the lower end of the trench.

[0100] The lifetime adjustment region 206 is provided in the diode section 80. The lifetime adjustment region 206 may be provided over the entire diode section 80 in the X-axis direction. The lifetime adjustment region 206 may also be provided in a part of the boundary region 200. In the boundary region 200, the area where the lifetime adjustment region 206 is not provided is designated as the first section 201, and the area where the lifetime adjustment region 206 is provided is designated as the second section 202. The first section 201 is a region in which the carrier lifetime at the same depth position as the lifetime adjustment region 206 is shorter than the carrier lifetime of the lifetime adjustment region 206 of the diode section 80. The first section 201 may also be a region in which charged particles such as helium have not been injected to form lifetime killers such as lattice defects 204. The chemical concentration of charged particles such as helium in the first section 201 is ( / cm³). 3 ) may be the same as the chemical concentration of the charged particle at the center of the drift region 18 in the Z-axis direction.

[0101] The first part 201 is in contact with the transistor section 70 in the X-axis direction. The width of the first part 201 in the X-axis direction is W1. The second part 202 is in contact with the diode section 80 in the X-axis direction. The width of the second part 202 in the X-axis direction is W2. The lifetime adjustment region 206 of the second part 202 is a region provided by extending the lifetime adjustment region 206 of the diode section 80 in the X-axis direction. The lifetime adjustment region 206 of the boundary region 200 may be provided at the same depth position as the lifetime adjustment region 206 of the diode section 80. The first part 201 and the second part 202 are in contact with each other in the X-axis direction. The width of the boundary region 200 in the X-axis direction is W1 + W2.

[0102] Figure 4 shows an example of the lifetime killer density distribution 210 along the line a-a' in Figure 3. As mentioned above, the lifetime killer in this example is a lattice defect 204. The line a-a' passes near the boundary between the first part 201 and the second part 202, its depth position is the same as that of the lifetime adjustment region 206, and it is a straight line parallel to the X-axis.

[0103] Let k1 be the lifetime killer density in the first section 201. Density k1 may be the minimum lifetime killer density of the first section 201 at that depth, or the average value may be used. Let k2 be the lifetime killer density in the second section 202. Density k2 may be the maximum lifetime killer density of the second section 202 at that depth, or the average value may be used. Density k2 is greater than density k1. The position where the lifetime killer density is the average value of k1 and k2 (i.e., (k1+k2) / 2) may be defined as the boundary position in the X-axis direction between the first section 201 and the second section 202. Density k1 may be defined as the detection limit concentration when the minimum lifetime killer density is less than or equal to the detection limit of measurement by SIMS or the like. As shown by the dashed line in Figure 4, if the lifetime killer density continues to decrease and the minimum value of the lifetime killer density cannot be measured, then density k1 may be defined as, for example, 1% of density k2, 0.1% of density k2, or 0.01% of density k2. The same definition may be used when the minimum value of the lifetime killer density is below the detection limit of the measurement by SIMS or the like.

[0104] The density distribution 210 in the X-axis direction has a lateral slope 212 in which the density of lifetime killers decreases from the second section 202 to the first section 201. The lateral slope 212 is the portion in which the density of lifetime killers decreases continuously from k2 to k1. In other words, the lateral slope 212 does not have a portion in which the density of lifetime killers increases in the direction from the second section 202 to the first section 201.

[0105] Let the width of the horizontal slope 212 in the X-axis direction be W3. The width W3 may be the width of the portion where the density of the lifetime killer decreases from β×k2 to α×k1. β may be 1 or may be a value smaller than 1. When the position where the density of the lifetime killer starts to decrease from k2 is unclear, β may be set to a value smaller than 1 (for example, 0.9). α may be 1 or may be a value larger than 1. When the position where the density of the lifetime killer converges to k1 is unclear, α may be set to a value larger than 1 (for example, 1.1). Twice the width W4 of the portion where the density of the lifetime killer decreases from k2 to the average value of k1 and k2 may be used as the width of the horizontal slope 212 in the X-axis direction.

[0106] Figure 3 The width W1 of the first portion 201 described in FIG. is smaller than the width W2 of the second portion 202. That is, W1 < W2. Thereby, the portion where the lifetime adjustment region 206 is provided in the boundary region 200 can be enlarged. For this reason, the flow of carriers from the transistor portion 70 to the diode portion 80 can be suppressed, and the reverse recovery loss of the diode portion 80 can be reduced. The width W1 may be half or less of the width W2, or may be 1 / 4 or less.

[0107] The width W1 of the first portion 201 is greater than or equal to the width of the horizontal slope 212 (for example, W3). Thereby, the influence on the threshold voltage etc. of the transistor portion 70 by the lifetime adjustment region 206 can be reduced. Lifetime killers such as lattice defects 204 can be formed by partially irradiating the semiconductor substrate 10 with charged particles such as helium using a mask or the like. Thereby, the lifetime adjustment region 206 can be formed in the region not covered by the mask. On the other hand, near the end of the mask, it is considered that charged particles also penetrate below the mask. For this reason, even in the region covered by the mask, lifetime killers are formed within a predetermined range from the end of the mask. For this reason, the density distribution 210 of the lifetime killer in the X-axis direction has a horizontal slope 212.

[0108] In this example, by making the width W1 of the first section 201 greater than or equal to the width of the horizontal slope 212, the horizontal slope 212 can be prevented from reaching the transistor section 70. This suppresses the formation of a lifetime killer in the transistor section 70 and suppresses fluctuations in the threshold voltage, etc. The width W1 may be twice or more the width of the horizontal slope 212, five times or more, or ten times or more.

[0109] As shown in Figure 3, let Wm be the width of the mesa portion 60 of the transistor portion 70 in the X-axis direction. The width of the mesa portion 60 of the transistor portion 70 may be constant. If the width of the mesa portion 60 of the transistor portion 70 is not constant, the width of the mesa portion 60 closest to the boundary region 200 shall be defined as the width Wm of the mesa portion 60. The width W1 of the first portion 201 may be greater than the width Wm of the mesa portion 60. The width W1 of the first portion 201 may be twice or more the width Wm of the mesa portion 60, and may also be three times or more. The first portion 201 may contain one or more mesa portions 61, or may contain multiple mesa portions 61.

[0110] As shown in Figure 3, the width in the arrangement direction (X-axis direction) of the multiple trench sections is denoted as Wt. The width Wt may be the width of the gate trench section 40, or the width of the dummy trench section 30. The width Wt may be the width of the trench section on the upper surface 21, or the width at a depth position half the depth of the trench section in the depth direction (Z-axis direction), and is the widest width of the trench section. too Good. In this example, width Wt is the widest width of the trench section. The width W1 of the first section 201 may be greater than the combined width (Wt + 2Wm) of the width Wt of at least one trench section in the boundary region 200 and the widths (2 × Wm) of the two mesa sections flanking the trench section. In this case, the width Wm of the trench section may be the width Wm of the dummy trench section 30, or the width Wm of the gate trench section 40. The width Wm of the trench section may be the maximum, minimum, or average value of the widths Wm of one or more trench sections in the boundary region 200. The width Wm of the trench section may be the maximum, minimum, or average value of the widths Wm of one or more trench sections in the first section 201.

[0111] This reduces the influence of the lifetime adjustment region 206 on the transistor section 70. Furthermore, by making the width W1 of the first section 201 at least twice the width Wm of the mesa section 60, it becomes easier to maintain the carrier concentration in the mesa section 60 of the transistor section 70 closest to the boundary region 200, and the decrease in carrier concentration toward the boundary region 200 is suppressed. This suppresses the decrease in the on-voltage of the IGBT in the mesa section 60. Additionally, by making the width W1 of the first section 201 larger than the combined width (Wt + 2Wm) of at least one trench section in the boundary region 200 and the widths (2 × Wm) of the two mesa sections flanking that trench section, it becomes easier to maintain the carrier concentration in the mesa section 60 of the transistor section 70 closest to the boundary region 200, and the decrease in carrier concentration toward the boundary region 200 is suppressed. This suppresses the decrease in the on-voltage of the IGBT in the mesa section 60.

[0112] Figure 5 shows an example of the lifetime killer density distribution 220 along the b-b' line in Figure 3. The b-b' line is a straight line that passes through the lifetime adjustment region 206 in the second section 202 and is parallel to the Z-axis.

[0113] In the second part 202, the density distribution 220 has a density peak 222. The density peak 222 is the portion containing the depth position Zp where the lifetime killer density shows a maximum value k2. The density peak 222 may be the portion of the density distribution that has a bell-shaped form. When charged particles such as helium are irradiated to the depth position Zp, many lifetime killers are formed at the depth position Zp. Also, due to the variation in the range of the charged particles, a density peak 222 with its peak located at the depth position Zp is formed in the density distribution 220. The density distribution 210 shown in Figure 4 is the distribution of lifetime killer density in the X-axis direction at the depth position Zp.

[0114] The density distribution 220 of lifetime killers when the injection surface for charged particles such as helium is the upper surface 21 is shown by a solid line, and the density distribution 220 of lifetime killers when the injection surface is the lower surface 23 is shown by a dashed line. Depending on the injection surface, the density distribution 220 of lifetime killers in the Z-axis direction may be asymmetrical around the depth position Zp. When the injection surface is the upper surface 21, the density distribution 220 of lifetime killers in the Z-axis direction shows a distribution that draws a tail 224 in the -Z direction (towards the upper surface 21) and decreases sharply in the +Z direction (towards the lower surface 23). When the injection surface is the lower surface 23, the density distribution 220 of lifetime killers in the Z-axis direction shows a distribution that draws a tail 224 in the +Z direction (towards the lower surface 23) and decreases sharply in the -Z direction (towards the upper surface 21). The density k1 may or may not coincide with the density value of tail 224 of the lifetime killer density distribution on the injection surface side, as in this example.

[0115] Let W5 be the width (peak width) of the density peak 222 in the Z-axis direction. The full width at half maximum of the density peak 222 may be used as the peak width W5. In another example, the width W6 of the portion of the density peak 222 where the lifetime killer density is α × k1 or greater may be used as the peak width of the density peak 222. α may be 1 or a value greater than 1. For example, α is 1.1. If the density value of the tail 224 of the lifetime killer density distribution on the injection surface side is greater than the density k1, the lifetime killer density α × k1 may be set to be greater than the density value of the tail 224 of the lifetime killer density distribution. However, in this case, the lifetime killer density α × k1 must be set to be less than the density k2.

[0116] figure 3The width W1 of the first part 201 described above may be greater than or equal to the peak width of the density peak 222 (e.g., W5). The larger the peak width of the density peak 222, the greater the variation in the width of the horizontal slope 212 described in Figure 4 tends to be. By setting the width W1 to be greater than or equal to the peak width of the density peak 222, even if there is variation in the width of the horizontal slope 212, it is possible to suppress the horizontal slope 212 from reaching the transistor section 70. The width of the horizontal slope 212 may be smaller than the peak width of the density peak 222. The width W1 of the first part 201 may be twice or more the peak width of the density peak 222, five times or more, or ten times or more. The width W1 of the first part 201 may be greater than or equal to the width W6 of the density peak 222.

[0117] Figure 6 shows another example of the configuration of the boundary region 200. The cross-section shown in Figure 6 is an XZ plane that includes the first part 201 and a portion of the second part 202. The boundary region 200 in this example has more mesa portions 61 than the boundary region 200 shown in Figure 3. As explained in Figure 5, Zp is the distance in the Z-axis direction from the top surface 21 of the semiconductor substrate 10 to the apex of the density peak 222. The width W1 of the first part 201 may be greater than or equal to the distance Zp. The larger the distance Zp, the greater the variation in the width of the lateral slope 212 as explained in Figure 4 tends to be. By making the width W1 greater than or equal to the distance Zp, even if there is variation in the width of the lateral slope 212, it is possible to suppress the lateral slope 212 from reaching the transistor portion 70. The width of the lateral slope 212 may be less than the distance Zp. The width W1 of the first part 201 may be 1.5 times or more the distance Zp, 2 times or more, or 3 times or more.

[0118] The width W2 of the second part 202 may be greater than or equal to the distance Zp. This ensures the area of ​​the second part 202 and suppresses the flow of carriers from the transistor part 70 to the diode part 80. The width W2 may be twice or more the distance Zp, five times or more, ten times or more, or fifteen times or more. The width W1 of the first part 201 may be greater than the width W2 of the second part 202. The width W1 of the first part 201 may be twice or more the width W2 of the second part 202, five times or more, ten times or more, or fifteen times or more.

[0119] In each example described herein, the width W1 of the first part 201 may be 1 μm or more. By making the width W1 1 μm or more, the effect of suppressing fluctuations in the threshold voltage at which the transistor part 70 turns on is obtained. The width W1 may be 5 μm or more, 10 μm or more, or 20 μm or more. The larger the width W1, the easier it is to suppress fluctuations in the threshold voltage. However, if the width W1 is made too large, the effect of suppressing fluctuations in the threshold voltage saturates, but the semiconductor device 100 becomes larger. The width W1 may be 200 μm or less. The width W1 may be 150 μm or less, 100 μm or less, 50 μm or less, or 30 μm or less. Also, the width W1 + W2 of the boundary region 200 may be 200 μm or less. The width W1 + W2 may be 150 μm or less, or 100 μm or less. The width W1 + W2 may be 30 μm or more, 50 μm or more, 70 μm or more, or 100 μm or more.

[0120] The width W1 of the first part 201 may be 10% or more of the width W1 + W2 of the boundary region 200. The width W1 may be 20% or more of the width W1 + W2, or 30% or more. The width W1 may be 50% or less of the width W1 + W2, or 40% or less, or 30% or less. This ensures the area of ​​the second part 202 and suppresses the flow of carriers from the transistor section 70 to the diode section 80.

[0121] Figure 7 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the other examples described herein in the arrangement of the storage region 16. The structure of the semiconductor device 100 other than the storage region 16 is the same as in any of the examples described herein.

[0122] In this example, the storage region 16 is also located in at least some of the mesa portions 61 of the first portion 201. The storage region 16 may be located in one or more mesa portions 61 of the first portion 201 that are closest to the transistor portion 70. In this example, the storage region 16 is not provided in the second portion 202. The storage region 16 and the lifetime adjustment region 206 do not overlap when viewed from above. The storage region 16 and the lifetime adjustment region 206 may be touching or separated when viewed from above.

[0123] By placing the storage region 16 in the mesa region 61 near the transistor region 70, it becomes easier to increase the carrier concentration in the mesa region 60 located near the end of the transistor region 70, making it easier to obtain the IE effect. Since the storage region 16 is not provided in the second region 202, the influence on the diode region 80 caused by providing the storage region 16 in the boundary region 200, such as the increase in electric field strength during reverse recovery, can be suppressed.

[0124] Figure 8 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the other examples described herein in the structure of the mesa portion 61. The structure of the semiconductor device 100 other than the mesa portion 61 is the same as in any of the examples described herein. The diode portion 80 and the boundary region 200 may have a mesa portion 61 of the same structure.

[0125] In this example, the mesa region 61 has an anode region 17 instead of a base region 14. The structure other than the anode region 17 is the same as that of the mesa region 61 in other examples described herein. The anode region 17 is a P-type region with a different doping concentration than the base region 14. In the example in Figure 8, the anode region 17 is a P-type region with a lower doping concentration than the base region 14.

[0126] By adjusting the doping concentration of the anode region 17 to be lower than that of the base region 14, the amount of carriers injected from the anode region 17 can be adjusted to be relatively small. The doping concentration of the anode region 17 may be adjusted according to the density of lifetime killers in the lifetime adjustment region 206. For example, by reducing the density of lifetime killers in the lifetime adjustment region 206, the influence of the lifetime adjustment region 206 on the transistor section 70 can be suppressed. However, if the density of lifetime killers is reduced, the carrier lifetime in the diode section 80 may not be sufficiently reduced. In this case, the doping concentration of the anode region 17 may be reduced to reduce the amount of carriers injected from the anode region 17.

[0127] Figure 9 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the other examples described herein in that it has a lower end region 230. The structure of the semiconductor device 100 other than the lower end region 230 is the same as in any of the examples described herein.

[0128] The lower end region 230 is a P-type region provided in contact with the lower end of at least the trench closest to the boundary region 200 among the multiple trenches of the transistor section 70. The lower end region 230 may have a lower doping concentration than the base region 14 and may also have a lower doping concentration than the anode region 17. The lower end region 230 is a floating region that is not in contact with the emitter electrode 52.

[0129] In the example shown in Figure 9, the trench closest to the boundary region 200 is the gate trench 40 located at the boundary between the transistor section 70 and the boundary region 200. By providing the lower end region 230, the electric field concentration near the lower end of the trench can be mitigated, thereby improving the breakdown voltage of the semiconductor device 100.

[0130] The lower end region 230 may be provided continuously across multiple trenches in the transistor section 70. In the example in Figure 9, the lower end region 230 is provided continuously across all trenches in the transistor section 70. In the transistor section 70, the lower end region 230 is located away from the base region 14. An N-type region is located between the base region 14 and the lower end region 230. This N-type region may be at least one of the storage region 16 and the drift region 18. In the example in Figure 9, the storage region 16, the drift region 18, and the lower end region 230 are arranged in order below the base region. The distance between the lower end region 230 and the upper surface 21 is smaller than the distance between the lifetime adjustment region 206 and the upper surface 21. In other words, the lower end region 230 is located above the lifetime adjustment region 206.

[0131] The lower end region 230 may also be located in the boundary region 200. In this example, the lower end region 230 extends in the X-axis direction from the transistor section 70 to the second section 202. In the X-axis direction, the lower end region 230 may terminate inside the second section 202. In other words, the lower end region 230 does not need to be located in the diode section 80. In a top view, the lower end region 230 and the lifetime adjustment region 206 partially overlap in the boundary region 200. By extending the lower end region 230 to the second section 202, the avalanche withstand capability of the transistor section 70 can be improved, and avalanche breakdown in the transistor section 70 can be suppressed.

[0132] Figure 10 shows another example of the ee cross-section. The semiconductor device 100 in this example differs from the example in Figure 9 in the arrangement of the lower end region 230. The structure of the semiconductor device 100 other than the lower end region 230 is the same as in any of the examples described herein.

[0133] In this example, the lower end region 230 extends in the X-axis direction from the transistor section 70 to the diode section 80. In the X-axis direction, the lower end region 230 may terminate inside the diode section 80. That is, the diode section 80 has a region in the X-axis direction where the lower end region 230 is not provided. In the X-axis direction, the width of the region in which the diode section 80 has the lower end region 230 may be smaller than the width of the region in which the diode section 80 does not have the lower end region 230. The lower end region 230 is provided only in the mesa section 61 located at the end in the X-axis direction of the diode section 80, and does not need to be provided in other mesa sections 61. By extending the lower end region 230 to the diode section 80, the avalanche withstand capability of the transistor section 70 can be improved, and avalanche breakdown in the transistor section 70 can be suppressed.

[0134] Figure 11 shows another example of the ee cross section. The semiconductor device 100 in this example differs from the examples in Figures 9 and 10 in the arrangement of the lower end region 230. The structure of the semiconductor device 100 other than the lower end region 230 is the same as in any of the examples described herein.

[0135] In this example, the lower end region 230 extends in the X-axis direction from the transistor section 70 to the first section 201. In this example, in the X-axis direction, the lower end region 230 terminates inside the first section 201. In other words, the lower end region 230 in this example is not provided in the second section 202 or the diode section 80. In a top view, the lower end region 230 and the lifetime adjustment region 206 do not overlap. In a top view, the lower end region 230 and the lifetime adjustment region 206 may be in contact or separated.

[0136] Extending the lower end region 230 to the boundary region 200 makes it easier for holes in the drift region 18 of the transistor section 70 to pass through the lower end region 230 to the boundary region 200. This reduces the IE effect of the transistor section 70. The further the lower end region 230 is extended in the X-axis direction, the easier it is for holes to pass through to the boundary region 200, thus reducing the IE effect of the transistor section 70. In this example, since the lower end region 230 is terminated at the first portion 201, the avalanche withstand capability of the transistor section 70 can be improved while maintaining the IE effect of the transistor section 70, as explained in Figure 9, etc.

[0137] In the X-axis direction, the distance between the lower end region 230 and the second portion 202 is denoted as W7. The distance W7 may be greater than or equal to the width of the horizontal slope 212 (e.g., W3) as described in Figure 4, etc. The distance W7 may be more than twice the width of the horizontal slope 212, more than five times, or more than ten times. The distance W7 may be greater than or equal to the mesa width Wm as described in Figure 3, etc., or more than twice the mesa width Wm.

[0138] Figure 12 shows an example of the arrangement of the first part 201 and the second part 202 in a top view. In Figure 12, the relative positions of each part of the boundary region 200 with respect to each trench section are shown. In Figure 12, the area where the boundary region 200 is provided is shown by a solid rectangle, and the areas where the second part 202 and the lifetime adjustment region 206 are provided are shown by hatched lines. In the boundary region 200, the area without hatched lines is the first part 201.

[0139] In the example shown in Figure 12, the boundary position in the X-axis direction between the transistor section 70 and the boundary region 200 is X1, the boundary position in the X-axis direction between the diode section 80 and the boundary region 200 is X2, and the boundary position in the X-axis direction between the first section 201 and the second section 202 is X3. Each boundary position is the same as in the example described in Figures 3 to 11.

[0140] In the example shown in Figure 12, the Y-axis positions of both ends of the boundary region 200 are denoted as Y1 and Y2. The contact holes 54 shown in Figure 2, etc., have a longitudinal length in the Y-axis direction. In this example, the Y-axis end position of the contact hole 54 is defined as the Y-axis end position of the boundary region 200. If the Y-axis end positions of the contact holes 54 provided in multiple mesa portions 61 are not constant, the Y-axis end position of the contact hole 54 extending furthest outward may be defined as the Y-axis end position of the boundary region 200.

[0141] In the example shown in Figure 12, the Y-axis positions of the second portion 202 are denoted as Y3 and Y4. The Y-axis positions Y3 and Y4 of the second portion 202 are the Y-axis positions of the lifetime adjustment region 206. At least one of the Y-axis positions Y3 and Y4 may be located inside the boundary region 200, beyond the Y-axis positions Y1 and Y2 of the boundary region 200. In the example shown in Figure 12, the second portion 202 is sandwiched between the first portion 201 in the Y-axis direction. The Y-axis positions Y3 and Y4 of the second portion 202 may be located outside the Y-axis positions Y5 and Y6 of the cathode region 82, as described in Figure 2, etc. In other words, the lifetime adjustment region 206 in the diode portion 80 may be provided over a wider area in the Y-axis direction than the cathode region 82.

[0142] Let Sk be the area of ​​the second portion 202 in the top view, and S be the area of ​​the boundary region 200. The area ratio Sk / S of area Sk and area S may satisfy the following equation. 0.8 ≤ Sk / S < 1 By setting the area ratio Sk / S to 0.8 or higher, the area of ​​the lifetime adjustment region 206 can be secured, thereby suppressing the flow of carriers from the transistor section 70 to the diode section 80. Furthermore, the flow of carriers from the region located outside the second section 202 in the Y-axis direction to the diode section 80 can be suppressed.

[0143] The distance between position Y1 and position Y3, or the distance between position Y2 and position Y4, may be greater than the width W1. The distance between position Y1 and position Y3, or the distance between position Y2 and position Y4, may be greater than the width W2. The distance between position Y1 and position Y3, or the distance between position Y2 and position Y4, may each be 0.3(L1-L2) or greater. As an example, the distance between position Y1 and position Y3, or the distance between position Y2 and position Y4, is 0.5(L1-L2). This prevents the inflow of carriers from the first part 201 through the second part 202 to the diode part 80, especially from the Y-axis direction, and suppresses, for example, a decrease in reverse recovery withstand capability.

[0144] Figure 13 shows the relationship between the area ratio Sk / S and the reverse recovery loss Err of the diode section 80. By suppressing the carrier flow from the transistor section 70 to the diode section 80, the reverse recovery time of the diode section 80 is shortened, and the reverse recovery loss can be reduced. Figure 13 shows comparative example 300, in which the lifetime adjustment region 206 is not provided, and examples 301 and 302, in which the lifetime adjustment region 206 is provided, in the structure shown in Figure 3, etc. In example 302, the dose of charged particles irradiated to form a lifetime killer in the lifetime adjustment region 206 is twice that of example 301. Also, the reverse recovery loss Err when the lifetime adjustment region 206 is not provided in the boundary region 200 (i.e., area ratio Sk / S = 0) is shown by a circle.

[0145] As shown in Figure 13, when the area ratio Sk / S is set to 80% or higher, the reverse recovery loss Err begins to decrease. The area ratio Sk / S may also be 90% or higher. As shown in Figure 13, when the area ratio Sk / S is set to 90% or higher, the reverse recovery loss Err is significantly reduced. The area ratio Sk / S may also be 95% or higher.

[0146] When the area ratio Sk / S approaches 100%, the effect of reducing the reverse recovery loss Err saturates. The area ratio Sk / S may be 99.5% or less, 99% or less, 97% or less, or 95% or less. By reducing the area ratio Sk / S, it becomes easier to secure the width W1 of the first part 201, and fluctuations in the threshold voltage of the transistor part 70 can be suppressed.

[0147] Figure 14 shows the relationship between lifetime killer density, carrier lifetime, and charged particle concentration in the lifetime adjustment region 206. The charged particles are impurities irradiated to form lifetime killers such as lattice defects 204. In this example, the charged particles are helium ions.

[0148] In Figures 4 and 5, the width of the lateral slope 212 (e.g., W3), the peak width of the density peak 222 (e.g., W5), and the depth position Zp of the density peak 222 were determined from the density distribution of the lifetime killer. In other examples, these values ​​may be determined from the distribution of carrier lifetimes (in this example, the lifetime of vacancies), or from the chemical density distribution of charged particles (e.g., helium).

[0149] The distribution of carrier lifetimes may have a shape that is the inversion of the lifetime killer density distribution along the vertical axis. In other words, the higher the density of lifetime killers, the shorter the carrier lifetime, and the lower the density of lifetime killers, the longer the carrier lifetime. When the density of lifetime killers is sufficiently low, the carrier lifetime may saturate to a sufficiently high value. A carrier lifetime that has saturated to a sufficiently high value is sometimes called a saturated carrier lifetime. The value of the saturated carrier lifetime may be 10 μs or more, 30 μs or more, 100 μs or more, or 300 μs or more. The upper limit of the saturated carrier lifetime may be 10,000 μs or less, 3,000 μs or less, or 1,000 μs or less.

[0150] Let LT1 be the carrier lifetime in the first part 201. The carrier lifetime LT1 may be the maximum value of the carrier lifetime of the first part 201 at depth position Zp, or it may be the average value. Let LT2 be the carrier lifetime in the second part 202. The carrier lifetime LT2 may be the minimum value of the carrier lifetime of the second part 202 at that depth, or it may be the average value.

[0151] The chemical concentration distribution of charged particles (e.g., helium) may have a shape similar to the density distribution of lifetime killers. In other words, the higher the chemical concentration distribution of charged particles, the higher the density of lifetime killers, and the lower the chemical concentration distribution of charged particles, the lower the density of lifetime killers.

[0152] Let He1 be the chemical concentration of charged particles in the first part 201. The chemical concentration He1 may be the minimum value of the chemical concentration of charged particles in the first part 201 at depth Zp, or it may be the average value. Let He2 be the chemical concentration in the second part 202. The chemical concentration He2 may be the maximum value of the chemical concentration of charged particles in the second part 202 at that depth, or it may be the average value.

[0153] In the calculations described in Figures 4 and 5, density k1 may be replaced with carrier lifetime LT2, and density k2 with carrier lifetime LT1 to determine the width of the lateral slope 212 (e.g., W3), the peak width of the density peak 222 (e.g., W5), and the depth position Zp of the density peak 222. In the calculations described in Figures 4 and 5, density k1 may be replaced with chemical concentration He1, and density k2 with chemical concentration He2 to determine the width of the lateral slope 212 (e.g., W3), the peak width of the density peak 222 (e.g., W5), and the depth position Zp of the density peak 222.

[0154] Figure 14 illustrates an example of calculating the width (e.g., W3) of the horizontal slope 212 from the carrier lifetime distribution. Carrier lifetime LT1 is greater than carrier lifetime LT2. The position where the carrier lifetime is the average of LT1 and LT2 (i.e., (LT1 + LT2) / 2) may be used as the boundary position in the X-axis direction between the first part 201 and the second part 202.

[0155] The carrier lifetime distribution in the X-axis direction has a lateral slope 213 in which the carrier lifetime increases from the second part 202 to the first part 201. The lateral slope 213 is continuous from LT2 to LT1. Increase This is the part in which the carrier lifetime decreases. In other words, the lateral slope 213 does not have a portion in the direction from the second portion 202 to the first portion 201 where the carrier lifetime decreases.

[0156] Let W3 be the width of the horizontal slope 213 in the X-axis direction. In this example, the width of the horizontal slope 213 is calculated as the width of the horizontal slope 212. The width W3 may be the width of the portion where the carrier lifetime increases from α × LT2 to β × LT1. α and β are the same as in the examples in Figures 4 and 5. The width of the horizontal slope 213 in the X-axis direction may be twice the width W4 of the portion where the carrier lifetime increases from LT2 to the average value of LT1 and LT2.

[0157] In each example described herein, the lifetime adjustment region 206 can be formed by irradiating the semiconductor substrate 10 at a depth position Zp with charged particles such as helium from the upper surface 21 or lower surface 23. When the charged particles are helium ions, the dose of helium ions is 1 × 10⁻⁶ 10 ions / cm 2 The above is 1 x 10 13 ions / cm 2 The following may be true: The dose of helium ions is 1 × 10⁻⁶. 11 ions / cm 2 It may be greater than or equal to the dose of helium ions. 12 ions / cm 2 The following is also acceptable.

[0158] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0159] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0160] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 15...Contact region, 16...Storage region, 17...Anode region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 29...Straight section, 30...Dummy trench section, 31...Tip section, 32...Dummy insulating film, 34...Dummy conductive section, 38...Interlayer insulating film, 39...Straight section, 40...Gate trench section, 41...Tip section, 42...Gate insulating film, 44...Gate conductive section, 52...Emitter electrode, 54...Contact hole, 60, 61 ...Mesa section, 70...Transistor section, 80...Diode section, 81...Extended region, 82...Cathode region, 90...Edge termination structure section, 100...Semiconductor device, 130...Outer periphery gate wiring, 131...Active side gate wiring, 160...Active section, 162...Edge, 164...Gate pad, 200...Boundary region, 201...First section, 202...Second section, 204...Lattice defect, 206...Lifetime adjustment region, 210...Density distribution, 212...Transverse slope, 213...Transverse slope, 220...Density distribution, 222...Density peak, 230...Lower end region, 300...Comparative example, 301...Example, 302...Example

Claims

1. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, A transistor section provided on the semiconductor substrate, A diode portion is provided on the semiconductor substrate and is arranged alongside the transistor portion in a first direction, A boundary region provided on the semiconductor substrate and disposed between the transistor portion and the diode portion Equipped with, The diode portion is located on the upper surface side of the semiconductor substrate and has a lifetime adjustment region including a lifetime killer that adjusts the lifetime of the carriers. The aforementioned boundary region is A first portion that is in contact with the transistor section and does not have the lifetime adjustment region, It has a second portion which is in contact with the diode portion and in which the lifetime adjustment region of the diode portion is extended, The density distribution of the lifetime killer in the first direction has a lateral slope in which the density of the lifetime killer decreases from the second portion of the boundary region toward the first portion. In the first direction, the width of the first portion is smaller than the width of the second portion. In the first direction, the width of the first portion is greater than or equal to the width of the lateral slope. Semiconductor equipment.

2. In the second portion, the density distribution of the lifetime killer in the depth direction of the semiconductor substrate has a density peak. The width of the first portion in the first direction is greater than or equal to the peak width of the density peak in the depth direction. The semiconductor device according to claim 1.

3. The width of the first portion in the first direction is greater than or equal to the distance from the upper surface of the semiconductor substrate to the density peak. The semiconductor device according to claim 2.

4. The transistor section comprises a plurality of trench sections arranged in a line in the first direction, The mesa portion sandwiched between the two trench portions and It has, The width of the first portion in the first direction is at least twice the width of the mesa portion in the first direction. The semiconductor device according to claim 1.

5. The aforementioned transistor section is Multiple trench sections arranged side by side in the first direction, The mesa portion sandwiched between the two trench portions and It has, The width of the first portion in the first direction is greater than the combined width of at least one trench portion in the boundary region and the widths of the two mesa portions flanking the trench portion. The semiconductor device according to claim 1.

6. The width of the first portion in the first direction is 1 μm or more. The semiconductor device according to claim 1.

7. The width of the first portion in the first direction is 10 μm or more. The semiconductor device according to claim 6.

8. The width of the boundary region in the first direction is 200 μm or less. The semiconductor device according to claim 1.

9. The width of the first portion in the first direction is 10% or more of the width of the boundary region in the first direction. The semiconductor device according to claim 1.

10. The width of the second portion in the first direction is greater than or equal to the distance from the upper surface of the semiconductor substrate to the density peak. The semiconductor device according to claim 2.

11. The semiconductor substrate has a drift region of the first conductivity type, The aforementioned transistor section is Displaced between the drift region and the upper surface of the semiconductor substrate, the emitter region has a doping concentration higher than that of the drift region, A base region of a second conductivity type is disposed between the emitter region and the drift region, Displaced between the base region and the drift region, and having a higher doping concentration than the drift region, It has, At least a portion of the first part is provided with the storage area, The storage area is not located in the second part. The semiconductor device according to any one of claims 1 to 10.

12. The semiconductor substrate has a drift region of the first conductivity type, The aforementioned transistor section is Displaced between the drift region and the upper surface of the semiconductor substrate, the emitter region has a doping concentration higher than that of the drift region, A base region of a second conductivity type is disposed between the emitter region and the drift region. It has, The aforementioned diode section is It has a second conductivity type anode region disposed between the drift region and the upper surface of the semiconductor substrate, The doping concentrations in the base region and the anode region are different. The semiconductor device according to any one of claims 1 to 10.

13. The semiconductor substrate has a drift region of the first conductivity type, The aforementioned transistor section is Multiple trench sections arranged side by side in the first direction, Of the plurality of trenches, at least the lower end region of the second conductive type is provided in contact with the lower end of the trench closest to the boundary region. It has, The lower end region extends to the second portion. The semiconductor device according to any one of claims 1 to 3.

14. The semiconductor substrate has a drift region of the first conductivity type, The aforementioned transistor section is Multiple trench sections arranged side by side in the first direction, Of the plurality of trenches, at least the lower end region of the second conductive type is provided in contact with the lower end of the trench closest to the boundary region. It has, The lower end region extends to the first portion and is not provided in the second portion. The semiconductor device according to any one of claims 1 to 3.

15. In the first direction, the distance between the lower end region and the second portion is greater than or equal to the width of the lateral slope. The semiconductor device according to claim 14.

16. An upper electrode positioned above the upper surface of the semiconductor substrate, An interlayer insulating film disposed between the upper electrode and the semiconductor substrate Furthermore, In the boundary region, the interlayer insulating film is provided with a contact hole having a longitudinal dimension in the second direction, connecting the upper electrode and the semiconductor substrate. When the end of the contact hole in the second direction is defined as the end of the boundary region in the second direction, the area Sk of the second portion in a top view and the area S of the boundary region satisfy the following equation. 0.8≦Sk / S<1 The semiconductor device according to any one of claims 1 to 10.

17. A semiconductor device comprising a semiconductor substrate having an upper surface and a lower surface, A transistor section provided on the semiconductor substrate, A diode portion is provided on the semiconductor substrate and is arranged alongside the transistor portion in a first direction, A boundary region provided on the semiconductor substrate and positioned between the transistor portion and the diode portion, An upper electrode positioned above the upper surface of the semiconductor substrate, An interlayer insulating film disposed between the upper electrode and the semiconductor substrate Equipped with, The diode portion is located on the upper surface side of the semiconductor substrate and has a lifetime adjustment region including a lifetime killer that adjusts the lifetime of the carriers. The aforementioned boundary region is A first portion that is in contact with the transistor section and does not have the lifetime adjustment region, It has a second portion which is in contact with the diode portion and in which the lifetime adjustment region of the diode portion is extended, In the boundary region, the interlayer insulating film is provided with a contact hole having a longitudinal dimension in the second direction, connecting the upper electrode and the semiconductor substrate. When the end of the contact hole in the second direction is defined as the end of the boundary region in the second direction, the area Sk of the second portion in a top view and the area S of the boundary region satisfy the following equation. 0.8≦Sk / S<1 Semiconductor equipment.

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