Field-effect transistor

Abstract

To provide a field effect transistor having a trench gate structure and with higher reliability.SOLUTION: The present invention provides a field effect transistor 1 comprising: an n-type first semiconductor layer 10 that is composed of a gallium oxide system semiconductor; a second semiconductor layer 11 that is provided onto the first semiconductor layer 10, and is composed of Si; first and second p-type semiconductor parts 13a and 13b that are embedded into first and second trenches 12a and 12b, respectively; a gate electrode 16 that is embedded into a third trench 14 provided so that one side surface and a part of a bottom surface are formed by a first p-type semiconductor part 13a so as to be covered with a gate insulation film 15; an n-type region 111 that is provided in a part of at least the third trench 14 on a front layer of a trench interval region of the second semiconductive layer 11; and a p-type region 112 that is provided between the first semiconductor layer 10 and the n-type region 111 in the trench interval region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a field-effect transistor. [Background technology]

[0002] Conventionally, field-effect transistors having a trench gate structure are known, in which β-Ga2O3 and Si are used as semiconductor layers (see Patent Document 1). In the field-effect transistor described in Patent Document 1, the bottom of the trench where the electric field is concentrated is located in a β-Ga2O3 layer with a high dielectric breakdown field strength, thus suppressing dielectric breakdown of the semiconductor layer.

[0003] Furthermore, conventional field-effect transistors having a trench gate structure are known in which a p-type region overlapping the gate oxide region is provided in a semiconductor layer made of SiC (see Non-Patent Literature 1). In the field-effect transistor described in Non-Patent Literature 1, the p-type region overlapping the gate oxide region can mitigate the concentration of the electric field at the bottom of the trench. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 6873516 [Non-patent literature]

[0005] [Non-Patent Document 1] D. Peters et, al., “CoolSiC Trench MOSFET Combining SiC Performance with Silicon Ruggedness”, Issue 3 Power electronics Europe 2017. [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In order to obtain a field-effect transistor with particularly excellent reliability, it is ideal to apply a p-type region that overlaps with the gate oxide film region described in Non-Patent Document 1 to the field-effect transistor described in Patent Document 1, thereby mitigating the concentration of the electric field at the bottom of the trench. In this case, not only dielectric breakdown of the semiconductor layer around the bottom of the trench but also dielectric breakdown of the gate insulating film is suppressed, and further improvement in the reliability of the field-effect transistor can be expected.

[0007] However, since p-type β-Ga2O3 with good conductivity does not exist, it is not possible to form a p-type region by converting a portion of the β-Ga2O3 in the field-effect transistor described in Patent Document 1 to p-type, as is the case with the p-type region in SiC in the field-effect transistor described in Non-Patent Document 1. For this reason, it is not possible to apply the p-type region that overlaps with the gate oxide film region described in Non-Patent Document 1 to the field-effect transistor described in Patent Document 1.

[0008] The object of the present invention is to provide a field-effect transistor having a trench gate structure that is more reliable. [Means for solving the problem]

[0009] One aspect of the present invention provides the following field-effect transistors [1] to [5] in order to achieve the above objective.

[0010] [1] An n-type first semiconductor layer made of a gallium oxide-based semiconductor, a second semiconductor layer made of Si provided on the first semiconductor layer, and first and second p-type semiconductor portions respectively embedded in first and second trenches reaching from the upper surface of the second semiconductor layer to the first semiconductor layer, and a third trench reaching from the upper surface of the second semiconductor layer to the first semiconductor layer and provided such that one side surface and a part of the bottom surface are formed by the first p-type semiconductor portion, a gate electrode covered with a gate insulating film and embedded therein, an n-type region provided at least in a part on the third trench side in the surface layer of the trench region between the second trench and the third trench of the second semiconductor layer, and a p-type region provided between the first semiconductor layer and the n-type region in the region between the first semiconductor layer and the n-type region of the trench region so as to isolate the first semiconductor layer and the n-type region, a source electrode connected to the n-type region, and a drain electrode connected to the first semiconductor layer, a field effect transistor. [2] The field effect transistor according to [1] above, in which a second n-type region is provided in a region between the first semiconductor layer and the p-type region of the trench region. [3] The field effect transistor according to [1] above, in which a second p-type region is provided in a region between the n-type region and the second trench in the surface layer of the trench region. [4] The field effect transistor according to any one of [1] to [3] above, in which the p-type semiconductor portion is made of a p-type oxide semiconductor. [5] The field effect transistor according to [4] above, in which the p-type oxide semiconductor is p-type NiO, CuO, or Cu2O.

Effect of the Invention

[0011] According to the present invention, there is provided a field effect transistor having a trench gate structure, and a more reliable field effect transistor can be provided.

Brief Description of the Drawings

[0012] [Figure 1]Figure 1 is a vertical cross-sectional view of a field-effect transistor according to an embodiment of the present invention. [Figure 2] Figures 2(a) to 2(c) are vertical cross-sectional views showing an example of the manufacturing process of a field-effect transistor. [Figure 3] Figures 3(a) to 3(c) are vertical cross-sectional views showing an example of the manufacturing process of a field-effect transistor. [Figure 4] Figures 4(a), (b), and (c) are graphs showing the off-voltage characteristics, gate characteristics, and on-voltage characteristics of a field-effect transistor, respectively. [Modes for carrying out the invention]

[0013] (Configuration of a field-effect transistor) Figure 1 is a vertical cross-sectional view of a field-effect transistor 1 according to an embodiment of the present invention. The field-effect transistor 1 is a vertical field-effect transistor having a trench gate structure.

[0014] The field-effect transistor 1 comprises an n-type first semiconductor layer 10 made of gallium oxide semiconductor, a second semiconductor layer 11 made of Si provided on the first semiconductor layer 10, a first p-type semiconductor portion 13a and a second p-type semiconductor portion 13b embedded in a first trench 12a and a second trench 12b extending from the upper surface of the second semiconductor layer 11 to the first semiconductor layer 10, and a third trench 14 extending from the upper surface of the second semiconductor layer 11 to the first semiconductor layer 10, with one side and part of the bottom surface formed by the first p-type semiconductor portion 13a. The field-effect transistor comprises a gate electrode 16 embedded and covered by a gate insulating film 15, an n-type region 111 provided on the surface of the region between the second trench 12b and the third trench 14 of the second semiconductor layer 11 (hereinafter referred to as the inter-trench region), at least on a part of the third trench 14 side, a p-type region 112 provided in the region between the first semiconductor layer 10 and the n-type region 111 in the inter-trench region to isolate the first semiconductor layer 10 and the n-type region 111, a source electrode 17 connected to the n-type region 111, and a drain electrode 18 connected to the first semiconductor layer 10. Note that the left gate electrode 16 shown in Figure 1 is used in a field-effect transistor adjacent to the left side of the field-effect transistor 1.

[0015] The field-effect transistor 1 may be either normally-off or normally-on, but when used as a power device, it is usually manufactured as a normally-off type for safety reasons. This is to prevent the source electrode 17 and drain electrode 18 from conducting when the gate becomes uncontrollable due to a gate circuit break or the like.

[0016] In the normally-off field-effect transistor 1, by applying a voltage greater than or equal to the gate threshold voltage between the gate electrode 16 and the source electrode 17, a vertical channel is formed in the region on the gate insulating film 15 side of the p-type region 112 in the trench region, allowing current to flow between the source electrode 17 and the drain electrode 18.

[0017] The first semiconductor layer 10 is composed of a single crystal of a gallium oxide-based semiconductor having a β-type crystal structure. Here, the gallium oxide-based semiconductor refers to Ga2O3 or Ga2O3 to which elements such as Al and In are added. For example, the gallium oxide-based semiconductor has a composition represented by (Ga x Al y In (1-x-y) )2O3 (0 < x ≤ 1, 0 ≤ y ≤ 1, 0 < x + y ≤ 1). When Al is added to Ga2O3, the bandgap widens, and when In is added, the bandgap narrows. Further, the n-type first semiconductor layer 10 contains donor impurities such as Si and Sn.

[0018] Also, the first semiconductor layer 10 typically includes, as shown in FIG. 1, a layer 101 with a high donor concentration for ohmic connection to the drain electrode 18 and a layer 102 thereon. For example, layer 101 has a donor concentration of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less, and layer 102 has a donor concentration of 1×10 15 cm -3 or more and 1×10 17 cm -3 or less. Also, for example, the thickness of layer 101 is 30 μm or more and 600 μm or less, and the thickness of layer 102 is 5 μm or more and 50 μm or less.

[0019] The layer 101 of the first semiconductor layer 10 typically consists of a substrate of a gallium oxide-based semiconductor. In this case, the substrate is formed, for example, by slicing a bulk crystal of a gallium oxide-based single crystal grown by a melt growth method such as the FZ (Floating Zone) method or the EFG (Edge Defined Film Fed Growth) method and polishing the surface. Also, the layer 102 of the first semiconductor layer 10 is typically an epitaxial film formed with the upper surface of layer 101 as the bottom surface.

[0020] The second semiconductor layer 11 is a layer made of a single crystal of Si. The n-type region 111 and p-type region 112 formed in the second semiconductor layer 11 are formed, for example, by implanting donor impurities and acceptor impurities into the second semiconductor layer 11.

[0021] The n-type region 111 formed in the second semiconductor layer 11 is the source of the field-effect transistor 1. The n-type region 111 contains donor impurities such as arsenic and, for example, 1 × 10⁻¹⁶, to ohmic connect with the source electrode 17. 18 cm -3 The above is 1 x 10 21 cm -3 The following high donor concentrations are observed.

[0022] The p-type region 112 formed in the second semiconductor layer 11 contains acceptor impurities such as boron, for example, 1 × 10⁻¹⁶ 18 cm -3 The above is 1 x 10 21 cm -3 It has the following acceptor concentrations.

[0023] If the second semiconductor layer 11 is too thin, it becomes difficult to form the n-type region 111 and the p-type region 112. If it is too thick, it becomes necessary to form the first trench 12a, the second trench 12b, and the third trench 14 to a greater depth. For this reason, the thickness D1 of the second semiconductor layer 11 is preferably, for example, 0.6 μm or more and 1.2 μm or less.

[0024] The method for forming the second semiconductor layer 11 is not particularly limited. For example, a Si single crystal may be epitaxially grown on the upper surface of the first semiconductor layer 10 as a substrate. However, in order to form a second semiconductor layer 11 with high crystal quality, it is preferable to bond a Si substrate to the first semiconductor layer 10 using a substrate bonding technique such as surface activation bonding, and then use a thinned Si substrate, such as a smart cut method, to form the second semiconductor layer 11.

[0025] In field-effect transistors with a trench gate structure, it is necessary for the n-type semiconductor layer and the p-type semiconductor layer to form a pn junction for their operation. However, when the semiconductor layer is composed of a gallium oxide-based semiconductor layer and a Si layer, as in field-effect transistor 1, it is difficult to form a pn junction between these dissimilar materials. For example, a layer of SiGa or Ga metal may be formed at the interface between the n-type and p-type semiconductor layers, or Si may act as a donor in the gallium oxide-based semiconductor, leading to the formation of a layer with a very high donor concentration near the interface of the n-type semiconductor layer due to the diffusion of Si from the p-type semiconductor layer, thus preventing the formation of a pn junction.

[0026] Therefore, as shown in Figure 1, it is preferable that a second n-type region 113 is provided in the region between the n-type first semiconductor layer 10 and the p-type region 112 in the trench region of the second semiconductor layer 11. In this case, the pn junction is formed not between the first semiconductor layer 10 made of gallium oxide semiconductor and the p-type region 112 made of Si, but between the second n-type region 113 and the p-type region 112, both made of Si. Therefore, it is sufficient to form an ohmic contact interface, and flatness or steepness of the interface is not required. In other words, a pn junction can be easily formed. The second n-type region 113 contains donor impurities such as phosphorus, for example, 1 × 10 15 cm -3 The above is 1 x 10 17 cm -3 The following donor concentrations are present.

[0027] Furthermore, as shown in Figure 1, it is preferable that a second p-type region 114 is provided in the region between the n-type region 111 and the second trench 12b on the surface of the inter-trench region of the second semiconductor layer 11. This allows the bulk of the field-effect transistor 1 in the p-type region 112 of the inter-trench region to be fixed to the ground potential along with the source potential using the second p-type region 114. The second p-type region 114 contains acceptor impurities such as boron. The acceptor concentration in the second p-type region 114 is higher than the acceptor concentration in the p-type region 112, for example, 1 × 10⁻⁶ 18 cm-3 The above is 1 x 10 21 cm -3 The following applies:

[0028] The first trench 12a and the second trench 12b extend from the upper surface of the second semiconductor layer 11 (the surface opposite the first semiconductor layer 10) to the first semiconductor layer 10. That is, the bottoms of the first trench 12a and the second trench 12b, and the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b embedded therein, are located below the upper surface of the first semiconductor layer 10 (the surface on the second semiconductor layer 11 side).

[0029] The first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b are made of a p-type semiconductor, and preferably they are made of a p-type oxide semiconductor such as NiO, CuO, or Cu2O that does not react well with the gallium oxide-based semiconductor constituting the first semiconductor layer 10. When NiO is used as the material for the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b, a high breakdown voltage can be obtained due to the large band gap of 3.7 eV that NiO has. When CuO or Cu2O is used, the breakdown voltage is lower than that of NiO, but the material cost can be reduced compared to NiO. These materials may be amorphous, polycrystalline, or single crystal, or they may be composites of two or more of these.

[0030] By providing the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b, when a reverse bias is applied between the gate electrode 16 and the source electrode 17 of the field-effect transistor 1 (off state), the electric field is concentrated at the bottom of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b. Since the bottoms of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b are located within the first semiconductor layer 10, which is made of a gallium oxide-based semiconductor with a high dielectric breakdown field strength, dielectric breakdown of the semiconductor layer due to electric field concentration is suppressed, and the breakdown voltage of the field-effect transistor 1 is increased. Furthermore, by providing the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b and concentrating the electric field in the first semiconductor layer 10, it is possible to use Si, which has a lower dielectric breakdown field strength than gallium oxide-based semiconductors but higher electron mobility, as the material for the second semiconductor layer 11 where the channel is formed, thereby reducing the channel resistance and the on-resistance of the device. Furthermore, Ga2O3 and Si are less expensive than SiC, and Ga2O3 has lower loss performance than SiC.

[0031] Furthermore, one side and part of the bottom of the third trench 14 are formed by the first p-type semiconductor portion 13a, and a portion of the bottom of the gate electrode 16 covered by the gate insulating film 15 in the third trench 14, for example, about half of the cross-section shown in Figure 1, is covered by the first p-type semiconductor portion 13a. Therefore, the electric field can be concentrated at the bottom of the first p-type semiconductor portion 13a, thereby reducing the electric field at the bottom of the third trench 14. This suppresses dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14, and improves the reliability of the field-effect transistor 1. However, it is undesirable for the entire bottom of the gate electrode 16 covered by the gate insulating film 15 to be covered by the first p-type semiconductor portion 13a, as this raises concerns about increased resistance due to a phenomenon called parasitic JFET.

[0032] In order to cause a spatial modulation effect of the electric field by narrowing the n-type layer 102, it is preferable that the distance between the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b, i.e., the width D10 of the trench region, be 1.2 μm or more and 2.0 μm or less.

[0033] Furthermore, in order to shield the electric field at the gate electrode terminal due to the spatial modulation effect described above, the depth D7 of the first trench 12a from the interface between the first semiconductor layer 10 and the second semiconductor layer 11 is preferably 1.6 μm or more and 3.0 μm or less.

[0034] Furthermore, in order to achieve electric field relaxation due to further spatial modulation effects of the n-type layer 102, the horizontal distance D14 between the second trench 12b and the third trench 14 is preferably 0.8 μm or more and 1.2 μm or less.

[0035] The gate electrode 16 is made of, for example, polycrystalline Si doped with a high concentration of donor, tungsten, or tungsten silicide, which is a compound of tungsten and Si. The gate electrode 16 has its sides and bottom covered with a gate insulating film 15, and its top surface covered with an insulating film 19.

[0036] The gate insulating film 15 insulates the gate electrode 16 from the first semiconductor layer 10 and the second semiconductor layer 11, and the insulating film 19 insulates the gate electrode 16 from the source electrode 17. The gate insulating film 15 and the insulating film 19 are made of, for example, HfO2, Al2O3, or SiO2. The thickness of the gate insulating film 15 is, for example, 30 nm or more and 100 nm or less. The thickness of the insulating film 19 is, for example, 30 nm or more and 100 nm or less.

[0037] The source electrode 17 is made of a metal such as aluminum and is ohmic-connected to the n-type region 111 of the second semiconductor layer 11. The drain electrode 18 is made of a metal such as titanium or aluminum and is ohmic-connected to the first semiconductor layer 10.

[0038] The horizontal patterns of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b (i.e., the horizontal patterns of the first trench 12a and the second trench 12b), the horizontal patterns of the gate insulating film 15 and the gate electrode 16 (i.e., the horizontal pattern of the third trench 14), and the horizontal patterns of the n-type region 111 and the second p-type region 114 are not particularly limited. For example, the first trench 12a and the second trench 12b may be connected in a portion not shown in the vertical cross-section of Figure 1.

[0039] (Manufacturing of field-effect transistors) Figures 2(a)-(c) and 3(a)-(c) are vertical cross-sectional views showing an example of the manufacturing process for field-effect transistor 1. The manufacturing process shown in Figures 2(a)-(c) and 3(a)-(c) will be described below.

[0040] First, as shown in Figure 2(a), a first n-type semiconductor layer 10, which is a substrate made of gallium oxide-based semiconductor, and an n-type Si substrate 20 containing donor impurities such as phosphorus are prepared, and these are bonded together by a surface activation bonding method.

[0041] Here, a planar ion-implanted region 21 is formed in the Si substrate 20 at a predetermined depth from the junction surface with the first semiconductor layer 10 by ion implantation of hydrogen ions. As will be described later, the Si substrate 20 is divided using the ion-implanted region 21 as the dividing surface, and the film separated from the Si substrate 20 becomes the second semiconductor layer 11. Therefore, the depth of the ion-implanted region 21 from the junction surface of the Si substrate 20 is determined according to the desired thickness of the second semiconductor layer 11.

[0042] The dose of hydrogen ions implanted for the formation of the ion implantation region 21 is, for example, 2 × 10⁻⁶. 16 ~8×10 16 / cm 2Furthermore, the implantation energy for ion implantation is determined by the depth of the ion implantation region 21 from the junction surface. For example, when forming the ion implantation region 21 at a depth of approximately 950 nm from the junction surface, hydrogen ions are implanted with an energy of approximately 110 keV.

[0043] In surface activation bonding, for example, 5 × 10 -6 In an ultra-high vacuum chamber under a pressure of approximately Pa, the outermost surface of the junction between the first semiconductor layer 10, which has been planarized by a planarization process such as CMP (chemical mechanical polishing), and the Si substrate 20 is removed by irradiation with an Ar atomic beam accelerated to an energy of 1.5 keV, and the newly exposed surfaces are brought into contact and bonded together.

[0044] Next, as shown in Figure 2(b), the bonded first semiconductor layer 10 and Si substrate 20 are subjected to heat treatment to induce hydrogen embrittlement in the ion implantation region 21, thereby splitting the Si substrate 20 (smart cut), leaving the second semiconductor layer 11 on top of the first semiconductor layer 10.

[0045] The heat treatment in smart cutting is performed, for example, in an N2 or Ar atmosphere for 1 to 10 minutes. The heat treatment may be performed in a vacuum chamber under reduced pressure, or in a furnace other than a vacuum chamber. After smart cutting, another heat treatment is performed to repair the damage to the second semiconductor layer 11 caused during ion implantation and smart cutting. Subsequently, a planarization treatment such as CMP may be applied to the surface of the second semiconductor layer 11.

[0046] Next, as shown in Figure 2(c), a p-type region 112 and a second p-type region 114 are formed by ion implanting acceptor impurities such as boron into the second semiconductor layer 11, and an n-type region 111 is formed by ion implanting donor impurities such as arsenic into the second semiconductor layer 11. The region of the n-type second semiconductor layer 11 that is not implanted with impurities is defined as the second n-type region 113.

[0047] Next, as shown in Figure 3(a), a first trench 12a and a second trench 12b are formed in the laminate of the first semiconductor layer 10 and the second semiconductor layer 11, and a first p-type semiconductor portion 13a and a second p-type semiconductor portion 13b are formed in the first trench 12a and the second trench 12b, respectively.

[0048] The first trench 12a and the second trench 12b are formed, for example, by photolithography and dry etching. The first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b are formed by depositing material in the first trench 12a and the second trench 12b, for example, by CVD (Chemical Vapor Deposition), vacuum deposition, sputtering, etc.

[0049] Next, as shown in Figure 3(b), a third trench 14 is formed in the laminate of the first semiconductor layer 10 and the second semiconductor layer 11. The third trench 14 is formed such that a portion of it overlaps with the first trench 12a in the width direction. The third trench 14 is formed, for example, by photolithography and dry etching.

[0050] Next, as shown in Figure 3(c), a gate insulating film 15 and a gate electrode 16 are formed in the third trench 14. The gate insulating film 15 and the gate electrode 16 are formed by depositing material in the third trench 14, for example, by CVD, vacuum deposition, sputtering, etc.

[0051] Subsequently, an insulating film 19, a source electrode 17, and a drain electrode 18 are formed to obtain a field-effect transistor 1. The insulating film 19 is formed by depositing material on the gate electrode 16 by means of CVD, vacuum deposition, sputtering, etc. The source electrode 17 and the drain electrode 18 are formed by depositing material on the upper surface of the second semiconductor layer 11 and the lower surface of the first semiconductor layer 10, respectively, by means of sputtering, etc.

[0052] (Characteristics of field-effect transistors) The following describes the simulation results of the electric field distribution, off-voltage characteristics, gate characteristics, and on-voltage characteristics when a reverse bias is applied to the gate electrode 16 of the field-effect transistor 1 (off state).

[0053] Table 1 shows the dimensions D1 to D18 of each part of the field-effect transistor 1 used in this simulation (see Figure 1).

[0054] [Table 1]

[0055] Furthermore, the material for the first semiconductor layer 10 was Ga2O3, the material for the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b was NiO, the material for the gate electrode 16 was polycrystalline Si, and the material for the gate insulating film 15 was SiO2.

[0056] Furthermore, the thickness of the gate insulating film 15 is 50 nm, the thickness of the first semiconductor layer 10 is 5 μm, and the interface trapping level density between the first semiconductor layer 10 and the second semiconductor layer 11 is 2 × 10⁻¹⁶. 12 cm -2 The dielectric constant was set to / eV, the radius of curvature of the corners at both ends of the bottom of the first trench 12a, the second trench 12b, and the third trench 14 shown in the cross-section of Figure 1 was set to 0.3 μm, and the relative permittivity of the insulating film 19 was set to 3.9.

[0057] Table 2 shows the donor or acceptor concentrations for each part of the field-effect transistor 1 used in this simulation.

[0058] [Table 2]

[0059] When a voltage of 1400V was applied to the drain electrode 18 of the field-effect transistor 1 described above (the source electrode 17 was grounded), the electric field strengths at points P1, P2, and P3 (see Figure 1) were approximately 6MV / cm, 4MV / cm, and 0.3MV / cm, respectively. Here, point P1 is a point in the first semiconductor layer 10 around the bottom of the first trench 12a, point P2 is a point in the gate insulating film 15 around the bottom of the third trench 14, and point P3 is a point on the interface between the p-type region 112 and the second n-type region 113.

[0060] The electric field at point P1 was strongest inside the field-effect transistor 1, while the electric field strengths at points P2 and P3 were kept low as described above. From this, it was confirmed that when a reverse bias is applied to the gate electrode 16 of the field-effect transistor 1, the electric field concentrates at the bottom of the first p-type semiconductor portion 13a, and the electric field around the bottom of the third trench 14 and around the interface between the first semiconductor layer 10 and the second semiconductor layer 11 is relaxed. Therefore, dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14, where electric fields are normally prone to concentration, can be suppressed.

[0061] Figure 4(a) is a graph showing the off-voltage characteristics of the field-effect transistor 1. The graph in Figure 4(a) shows the change in drain current when the gate voltage applied to the gate electrode 16 is fixed at -5V and the drain voltage applied to the drain electrode 18 is varied. Figure 4(a) shows that avalanche breakdown occurs when the drain voltage exceeds approximately 1400V.

[0062] Figure 4(b) is a graph showing the gate characteristics of the field-effect transistor 1. The graph in Figure 4(b) shows the change in drain current when the drain voltage applied to the drain electrode 18 is fixed at 1V and the gate voltage applied to the gate electrode 16 is varied. Figure 4(b) shows that the gate threshold voltage is approximately 2V.

[0063] Figure 4(c) is a graph showing the on-characteristics of the field-effect transistor 1. The graph in Figure 4(c) shows the change in drain current when the gate voltage applied to the gate electrode 16 is fixed at 15V and the drain voltage applied to the drain electrode 18 is varied. According to Figure 4(c), for example, when the gate voltage is 15V and the drain voltage is 1V, the on-resistance is approximately 3.2mΩcm. 2 That is the case.

[0064] (Effects of the embodiment) According to the above embodiment of the present invention, the bottom of the third trench 14 into which the gate electrode 16 is embedded is placed in an n-type first semiconductor layer 10 made of a gallium oxide-based semiconductor with a high dielectric breakdown field strength, and the electric field around the bottom of the third trench 14 is mitigated by the first p-type semiconductor portion 13a, thereby suppressing dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14 and improving the reliability of the field-effect transistor 1.

[0065] Although embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention. Furthermore, the components of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

[0066] Furthermore, the embodiments described above do not limit the invention as defined in the claims. It should also be noted that not all combinations of features described in the embodiments are necessarily essential for solving the problem of the invention. [Explanation of symbols]

[0067] 1…Field-effect transistor, 10…First semiconductor layer, 11…Second semiconductor layer, 111…n-type region, 112…p-type region, 113…Second n-type region, 114…Second p-type region, 12a…First trench, 12b…Second trench, 13a…First p-type semiconductor region, 13b…Second p-type semiconductor region, 14…Third trench, 15…Gate insulating film, 16…Gate electrode, 17…Source electrode, 18…Drain electrode

Claims

1. A first n-type semiconductor layer made of a gallium oxide-based semiconductor, A second semiconductor layer made of Si is provided on the first semiconductor layer, First and second p-type semiconductor portions are embedded in first and second trenches, respectively, that extend from the upper surface of the second semiconductor layer to the first semiconductor layer, A gate electrode, covered and embedded in a gate insulating film, is provided in a third trench extending from the top surface of the second semiconductor layer to the first semiconductor layer, such that one side and a portion of the bottom surface are formed by the first p-type semiconductor portion. In the surface layer of the inter-trench region between the second trench and the third trench of the second semiconductor layer, an n-type region is provided on at least a part of the third trench side, A p-type region is provided in the region between the first semiconductor layer and the n-type region of the trench region, so as to isolate the first semiconductor layer and the n-type region. A source electrode connected to the n-type region, A drain electrode connected to the first semiconductor layer, A field-effect transistor equipped with [a specific feature].

2. A second n-type region is provided in the region between the first semiconductor layer and the p-type region in the trench region. The field-effect transistor according to claim 1.

3. A second p-type region is provided in the surface layer of the trench-interval region, in the region between the n-type region and the second trench. The field-effect transistor according to claim 1.

4. The p-type semiconductor portion is made of a p-type oxide semiconductor. A field-effect transistor according to any one of claims 1 to 3.

5. The p-type oxide semiconductor is p-type NiO, CuO, or Cu ２ It is O. The field-effect transistor according to claim 4.

Images