Differential interface circuit and receiver

Abstract

To provide a differential interface circuit capable of receiving a multiple-value PAM signal accurately.SOLUTION: A first stage 420_1 of a differential interface circuit 400A includes a first transistor MN11, a second transistor MN12, a third transistor MN13, and a fourth transistor MN14. Gates of the first transistor MN11 and the second transistor MN12 are connected to input terminals INP, INN. The third transistor MN13 and the fourth transistor MN14 are connected in parallel to the first transistor MN11 and the second transistor MN12. A gate of the third transistor MN13 is connected to a drain of the second transistor MN12, and a gate of the fourth transistor MN14 is connected to a drain of the first transistor MN11.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a differential interface circuit.

Background Art

[0002] In conventional serial data transmission, the NRZ (Non Return to Zero) method was the mainstream. However, in applications that require a higher transmission rate, a multi-level PAM method such as PAM4 is adopted.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The present disclosure has been made in view of such circumstances, and one of its exemplary purposes is to provide a differential interface circuit capable of accurately receiving a multi-level PAM signal.

Means for Solving the Problems

[0005] Aspects of this disclosure relate to a differential interface circuit. The differential interface circuit comprises a first input terminal, a second input terminal, and a first stage. The first stage includes a first transistor whose gate is connected to the first input terminal, a second transistor whose gate is connected to the second input terminal, a first resistor connected to the drain of the first transistor, a second resistor connected to the drain of the second transistor, a first current source connected to the source of the first transistor, a second current source connected to the source of the second transistor, a third resistor connected between the source of the first transistor and the source of the second transistor, a third transistor connected in parallel with the first transistor and whose gate is connected to the drain of the second transistor, a fourth transistor connected in parallel with the second transistor and whose gate is connected to the drain of the first transistor, a first capacitor connected between the second input terminal and the source of the first transistor, and a second capacitor connected between the first input terminal and the source of the second transistor.

[0006] Furthermore, any combination of the above components, or any substitution of components or expressions between methods, apparatus, systems, etc., are also valid as embodiments of the present invention or this disclosure. Moreover, the description in this section (means for solving the problem) does not describe all the indispensable features of the present invention, and therefore, subcombinations of these described features may also constitute the present invention. [Effects of the Invention]

[0007] According to certain aspects of this disclosure, multi-level PAM signals can be accurately received. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a circuit diagram showing the basic configuration of a differential interface circuit. [Figure 2] Figure 2 is a block diagram of a transmission system in which the transmitting and receiving devices are connected in a single-ended configuration. [Figure 3]Figure 3 is a circuit diagram of a differential interface circuit according to Embodiment 1. [Figure 4] Figure 4 is a circuit diagram of a differential interface circuit according to Embodiment 2. [Figure 5] Figure 5 is a block diagram of the transmission system for an N-value PAM (PAM-N) signal according to the embodiment. [Modes for carrying out the invention]

[0009] This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one or more embodiments (examples or variations) disclosed herein.

[0010] In one embodiment, the differential interface circuit includes a first input terminal, a second input terminal, and a first stage. The first stage includes a first transistor whose gate is connected to the first input terminal, a second transistor whose gate is connected to the second input terminal, a first resistor connected to the drain of the first transistor, a second resistor connected to the drain of the second transistor, a first current source connected to the source of the first transistor, a second current source connected to the source of the second transistor, a third resistor connected between the source of the first transistor and the source of the second transistor, a third transistor connected in parallel with the first transistor and whose gate is connected to the drain of the second transistor, a fourth transistor connected in parallel with the second transistor and whose gate is connected to the drain of the first transistor, a first capacitor connected between the second input terminal and the source of the first transistor, and a second capacitor connected between the first input terminal and the source of the second transistor.

[0011] With this configuration, by adding a third and fourth transistor, the potential difference between the differential outputs in the first stage (the drain of the first transistor and the drain of the second transistor) can be reduced when the differential interface circuit is used for single-ended transmission. This reduces distortion of the output waveform of the differential interface circuit.

[0012] Furthermore, by adding the first and second capacitors, the input signal can be fed back to the source side through these capacitors, thereby accelerating signal transmission. This compensates for the effects of phase differences caused by propagation delay.

[0013] In one embodiment, the first stage may further include a third capacitor connected in parallel with the third resistor. The third capacitor can impart a high-frequency emphasis equalizing characteristic to the first stage.

[0014] In one embodiment, the first stage may further include a seventh resistor connected in series with the first capacitor between the second input terminal and the source of the first transistor, and an eighth resistor connected in series with the second capacitor between the first input terminal and the source of the second transistor. With this configuration, when the differential interface circuit is used for single-ended transmission, the phase of the source of the first transistor on the signal input side and the phase of the source of the second transistor on the non-signal input side can be precisely matched by the additional seventh and eighth resistors.

[0015] In one embodiment, the differential interface circuit may further include a second stage connected after the first stage. The second stage may include a fifth transistor whose gate is connected to the drain of the first transistor, a sixth transistor whose gate is connected to the drain of the second transistor, a fourth resistor connected to the drain of the fifth transistor, a fifth resistor connected to the drain of the sixth transistor, a third current source connected to the source of the fifth transistor, a fourth current source connected to the source of the sixth transistor, a sixth resistor connected between the source of the fifth transistor and the source of the sixth transistor, a seventh transistor connected in parallel with the fifth transistor and whose gate is connected to the drain of the sixth transistor, and an eighth transistor connected in parallel with the sixth transistor and whose gate is connected to the drain of the fifth transistor. In this case, the potential difference of the differential output (between the drain of the fifth transistor and the drain of the sixth transistor) can also be reduced in the second stage. This further reduces the distortion of the output waveform of the differential interface circuit.

[0016] In one embodiment, the second stage may further include a fourth capacitor connected in parallel with the sixth resistor. This allows the second stage to be given a high-frequency emphasis equalizing characteristic.

[0017] In one embodiment, the differential interface circuit may be integrated onto a single semiconductor substrate. "Integrated integration" includes cases where all the circuit components are formed on the semiconductor substrate, or where the main components of the circuit are integrated, and some resistors, capacitors, etc., may be provided outside the semiconductor substrate for adjusting circuit constants. Integrating the circuit onto a single chip can reduce the circuit area and maintain uniformity of the characteristics of the circuit elements.

[0018] A receiving device according to one embodiment receives a multi-level PAM signal. The receiving device may include any of the differential interface circuits described above.

[0019] (Embodiment) Hereinafter, preferred embodiments will be described with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Further, the embodiments are illustrative and not restrictive of the disclosure and the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the disclosure and the invention.

[0020] In this specification, the state where "member A is connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0021] Similarly, the state where "member C is connected (provided) between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their connection.

[0022] Also in this specification, the reference numerals assigned to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors represent their respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductance) as appropriate.

[0023] In this embodiment, a differential interface circuit suitable for a multi-value signal receiving device including a PAM4 signal will be described. First, the basic configuration of the differential interface circuit will be described.

[0024] FIG. 1 is a circuit diagram showing the basic configuration of a differential interface circuit 400. The differential interface circuit 400 includes a plurality of stages 410_1 to 410_N. The number of stages N can be 2 or 3 or more, and here a configuration with N = 2 is shown.

[0025] Multiple stages 410_1 to 410_2 have a configuration in which a filter element FIL is added to a differential amplifier DA.

[0026] The differential amplifier DA of stage 410_i, the i-th stage (i=1,2,...N), is equipped with load resistors RDi1, RDi2, input differential pairs MNi1, MNi2, and tail current sources IBi1, IBi2.

[0027] The gates of the input differential pairs MN11 and MN12 are the differential inputs of each stage 410_i, and the drains of the input differential pairs MN11 and MN12 are the differential outputs of each stage 410_i.

[0028] The filter element FIL is connected between the input differential pairs MNi1 and MNi2, respectively. The filter element FIL includes a resistor RSi0 and a capacitor CSi0 connected in parallel.

[0029] The gates of the input differential pairs MN11 and MN12 of the first stage 410_1 are connected to the differential input terminals INP and INN. The gates of the input differential pairs MN21 and MN22 of the second stage 410_2 are connected to the differential output of the preceding first stage 410_1.

[0030] The above describes the basic configuration of the differential interface circuit 400.

[0031] The inventors, after examining the differential interface circuit 400 shown in Figure 1, have come to recognize the following problems.

[0032] While high-speed serial transmission transmitters and receivers have differential interfaces, the cable wiring (transmission path) connecting them may not only use differential wiring such as twisted pair, but also single-wire wiring such as coaxial cable to reduce cable weight and cost.

[0033] Figure 2 is a block diagram of a transmission system in which the transmitter and receiver are connected in a single-ended configuration. The interface terminals of the transmitter 200 and receiver 300 have built-in termination resistors (50Ω), and in the case of a single-ended connection, an external resistor Rpd simulating the termination resistor is placed on the unconnected side of each device.

[0034] If the differential interface circuit 400 in Figure 1 is used as the input interface circuit on the receiving device side of the transmission system 100 in Figure 2, a signal is input to the INP side, but no signal is input to the INN side. As a result, the differential interface circuit 400 operates asymmetrically, with a potential difference between the two input signal waveforms.

[0035] Furthermore, since the non-signal-input INN side operates only after receiving the operation from the signal-input INP side, propagation delay also occurs.

[0036] For these reasons, if the differential interface circuit 400 shown in Figure 1 is used in a single-ended transmission system, the output signal will have a significantly distorted differential waveform.

[0037] In the case of binary serial transmission, even if the differential waveform is distorted, this effect can be reduced by placing a high-gain differential comparator or similar device in the subsequent stage to binarize it. On the other hand, in the case of multi-level serial transmission, placing a high-gain differential circuit will result in the loss of information from the multi-level signal.

[0038] The following describes the configuration of an equalizer circuit that can solve these problems.

[0039] (Embodiment 1) Figure 3 is a circuit diagram of the differential interface circuit 400A according to Embodiment 1. The differential interface circuit 400A comprises a plurality of stages 420_1 to 420_N. The number of stages N can be 2 or 3 or more, but here a configuration of N=2 is shown. If N≧3, the same configuration as the second stage 420_2 may be repeated.

[0040] The first stage 420_1 comprises a first transistor MN11, a second transistor MN12, a third transistor MN13, a fourth transistor MN14, a first resistor RD11, a second resistor RD12, a third resistor RS10, a first current source IB11, a second current source IB12, a first capacitor CI11, a second capacitor CI12, and a third capacitor CS10.

[0041] The first stage 420_1 will be described in detail. The first transistor MN11 and the second transistor MN12 constitute an input differential pair. The gate of the first transistor MN11 is connected to the differential input terminal INP of the differential interface circuit 400A, and the gate of the second transistor MN12 is connected to the differential input terminal INN of the differential interface circuit 400A.

[0042] The first resistor RD11 is connected between the drain of the first transistor MN11 and the power line, and the second resistor RD12 is connected between the drain of the second transistor MN12 and the power line. The first current source IB11 is connected between the source of the first transistor MN11 and ground, and the second current source IB12 is connected between the second transistor MN12 and ground.

[0043] The third transistor MN13 and the fourth transistor MN14 are feedback transistors. They are isomorphic (N-channel) to the first transistor MN11 and the second transistor MN12. The drain of the third transistor MN13 is connected to the drain of the first transistor MN11, and the source of the third transistor MN13 is connected to the source of the first transistor MN11. The gate of the third transistor MN13 is connected to the drain of the second transistor MN12, and one of the differential outputs of the first stage 420_1 is fed back.

[0044] Similarly, the drain of the fourth transistor MN14 is connected to the drain of the second transistor MN12, and the source of the fourth transistor MN14 is connected to the source of the second transistor MN12. The gate of the fourth transistor MN14 is connected to the drain of the first transistor MN11, and one of the differential outputs of the first stage 420_1 is fed back.

[0045] The third resistor RS10 is connected between the source of the first transistor MN11 and the source of the second transistor MN12. The third capacitor CS10 is connected in parallel with the third resistor RS10 between the source of the first transistor MN11 and the source of the second transistor MN12.

[0046] In other words, the first stage 420_1 has the same configuration as the first stage 410_1 in Figure 1, with the addition of the third transistor MN13 and the fourth transistor MN14.

[0047] In the first stage 420_1, in addition to the third transistor MN13 and the fourth transistor MN14, the first capacitor CI11 and the second capacitor CI12 are added. The first capacitor CI11 is connected between the differential input terminal INN and the source of the first transistor MN11. The second capacitor CI12 is connected between the differential input terminal INP and the source of the second transistor MN12.

[0048] Next, I will explain Stage 2, 420_2.

[0049] The second stage 420_2 comprises the fifth transistor MN21, the sixth transistor MN22, the seventh transistor MN23, the eighth transistor MN24, the fourth resistor RD21, the fifth resistor RD22, the sixth resistor RS20, the third current source IB21, the fourth current source IB22, and the fourth capacitor CS20.

[0050] The second stage 420_2 can be understood as having the same configuration as the second stage 410_2 in Figure 1, with the addition of the seventh transistor MN23 and the eighth transistor MN24. Furthermore, the second stage 420_2 can be understood as having the same configuration as the first stage 420_1, but with the first capacitor CI11 and the second capacitor CI12 omitted.

[0051] The above describes the configuration of the differential interface circuit 400A according to the embodiment. Next, its advantages will be explained.

[0052] In the differential interface circuit 400A shown in Figure 3, the potential difference of the differential output for each stage can be reduced by adding feedback transistors MNi3 and MNi4 to each stage 420_i (i=1,2,…N).

[0053] Furthermore, in the first stage 420_1, by adding a first capacitor CI11 between the differential input terminal INN and the source of the first transistor MN11, and adding a second capacitor CI12 between the differential input terminal INP and the source of the second transistor MN12, the input signal can be fed through these capacitors CI11 and CI12 to the source side, thereby accelerating signal transmission. This compensates for the effects of phase difference due to propagation delay.

[0054] (Embodiment 2) Figure 4 is a circuit diagram of the differential interface circuit 400B according to Embodiment 2. The differential interface circuit 400B comprises a plurality of stages 430_1 to 430_N. The number of stages N can be 2 or 3 or more, but here a configuration of N=2 is shown. If N≧3, the same configuration as the second stage 430_2 may be repeated.

[0055] For the second stage and beyond, the configuration of stage 430_i (i=2,...N) is the same as the configuration of stage 420_i (i=2,...N) in Figure 3, while the configuration of the first stage 430_1 differs from that of the first stage 420_1 in Figure 3.

[0056] The first stage 430_1 in Figure 4 further includes a seventh resistor RI11 and an eighth resistor RI12 in addition to the components of the first stage 420_1 in Figure 3. The seventh resistor RI11 is connected in series with the first capacitor CI11 between the differential input terminal INN and the source of the first transistor MN11. The eighth resistor RI12 is connected in series with the second capacitor CI12 between the differential input terminal INP and the source of the second transistor MN12.

[0057] The above describes the configuration of the differential interface circuit 400B. With this differential interface circuit 400B, when used for single-ended transmission, the phase of the source of transistor MN11 on the signal input side and the phase of the source of transistor MN12 on the non-signal input side can be precisely matched by the additional resistors RI11 and RI12.

[0058] Next, we will explain modified versions of the differential interface circuits 400A and 400B.

[0059] (Variation 1) In the embodiments, differential interface circuits 400A and 400B have been described, but the capacitors CS10 and CS20 that constitute the filter element FIL can be omitted. In other words, the equalizing function is not essential in this disclosure, and this disclosure can be applied to a simple differential interface circuit.

[0060] You can omit only the first stage capacitor CS10, while retaining the capacitors CS20 in the second stage and beyond.

[0061] (Modification 2) For the first stage only, the configuration 420_1 and 430_1 is used, while a different configuration may be used for the second stage and beyond.

[0062] (Variation 3) In this embodiment, transistors MN11 and MN12 are NMOS transistors, but this is not limited to them; PMOS transistors may also be used. In this case, the top and bottom (power supply and ground) should be reversed.

[0063] (Application) Figure 5 is a block diagram of a transmission system 100 of an N-value PAM (PAM-N) signal according to an embodiment. The transmission system 100 comprises a transmitting device 200 and a receiving device (deserializer) 300. The transmitting device 200 and the receiving device 300 are connected via a transmission cable 102.

[0064] (Transmitter) The transmitting device 200 is a serializer IC (Integrated Circuit) that receives data S1 to be transmitted to the receiving device 300 from an external circuit (not shown), converts it into an N-value PAM signal S2, and transmits it to the receiving device 300. The type of parallel data S1 is not limited, but examples include image data that requires high-speed transmission of large amounts of data.

[0065] (Receiving device) The receiving device 300 is a deserializer IC that receives a PAM-N signal S2 from the transmitting device 200 and outputs the received data S3 to another external circuit (not shown). Differential signals are used for signal transmission between the transmitting device 200 and the receiving device 300, but single-ended signals may also be used.

[0066] Here, a 4-level (N=4) PAM (PAM4) signal is used as an example of a PAM-N signal, but the number of gradations in a PAM signal is not limited, and this disclosure can also be applied to 8-level, 16-level, and 64-level signals.

[0067] First, the configuration of the transmitting device 200 will be described. The PAM encoder 210 converts data S1a into PAM format data S1b. In the PAM encoder 210, a clock signal is embedded in data S1b. The encoding method in the PAM encoder 210 is not particularly limited, but DC balanced encoding methods such as 8b10b, 10b12b, and 64b66b can be used.

[0068] The P / S converter 220 converts the data S1b generated by the PAM encoder 210 into serial data S1c. The PAM driver 230 converts the serial data S1c into an analog PAM-N signal S2 and outputs it.

[0069] Next, the configuration of the receiving device 300 will be described. The receiving device 300 includes a waveform shaping circuit 310, an A / D converter 320, a PAM phase comparator 330, a clock recovery circuit 340, an S / P converter 350, and a PAM decoder 360.

[0070] While the PAM-N signal S2 is transmitted through the transmission cable 102, the waveform of the PAM-N signal S2 becomes distorted. A waveform shaping circuit 310 is provided to improve this waveform distortion. Examples of waveform distortion include attenuation due to transmission loss and waveform distortion due to the low-pass effect of the transmission cable 102. The waveform shaping circuit 310 shapes the waveform of the PAM-N signal S2 so that it approaches the ideal PAM signal.

[0071] The waveform shaping circuit 310 can be equipped with a VGA (Variable Gain Amplification) function that amplifies the PAM-N signal S2 with a variable gain and adjusts the DC amplitude of the PAM-N signal S2, as well as an equalizing (EQ) function that corrects the frequency characteristics of the PAM-N signal S2.

[0072] The A / D converter 320 quantizes the PAM-N signal S2a, which has been waveform-shaped by the waveform shaping circuit 310, and converts it into a comparison signal S2b.

[0073] The PAM phase comparator 330 receives the comparison signal S2b and, in synchronization with the clock signal CLK (data strobe signal) generated by the clock recovery circuit 340, latches the multiple bits b1 to b3 that make up the comparison signal S2b. The PAM phase comparator 330 converts the comparison signal S2b latched by the clock signal CLK into a 2-bit binary code (symbol data) S2c.

[0074] The S / P converter 350 converts the binary code S2c into parallel data S2e. The PAM decoder 360 performs the reverse processing with the PAM encoder 210 of the transmitter 200, decodes the DC-balanced encoded parallel data S2e, and outputs data S3.

[0075] The differential interface circuits 400A and 400B described above can be used in the first stage of the receiving device 300, and are particularly suitable for use in the input stage of the waveform shaping circuit 310.

[0076] (Note) The technology disclosed herein can be understood in one respect as follows:

[0077] (Item 1) First input terminal and, Second input terminal and, Stage 1 and Equipped with, The aforementioned first stage is, A first transistor whose gate is connected to the first input terminal, The gate of the second transistor is connected to the second input terminal, A first resistor connected to the drain of the first transistor, A second resistor connected to the drain of the second transistor, A first current source connected to the source of the first transistor, A second current source connected to the source of the second transistor, A third resistor connected between the source of the first transistor and the source of the second transistor, A third transistor is connected in parallel with the first transistor, and its gate is connected to the drain of the second transistor, A fourth transistor is connected in parallel with the second transistor, and its gate is connected to the drain of the first transistor, A first capacitor connected between the second input terminal and the source of the first transistor, A second capacitor connected between the first input terminal and the source of the second transistor, A differential interface circuit, including one.

[0078] (Item 2) The differential interface circuit described in item 1 further includes a third capacitor connected in parallel with the third resistor, wherein the first stage further includes the third capacitor.

[0079] (Item 3) The aforementioned first stage is, A seventh resistor connected in series with the first capacitor is placed between the second input terminal and the source of the first transistor, Between the first input terminal and the source of the second transistor, an eighth resistor is connected in series with the second capacitor, A differential interface circuit as described in item 1 or 2, further including the differential interface circuit described in item 1 or 2.

[0080] (Item 4) The system further comprises a second stage connected to the subsequent stage of the first stage, The second stage is, A fifth transistor whose gate is connected to the drain of the first transistor, A sixth transistor whose gate is connected to the drain of the second transistor, The fourth resistor is connected to the drain of the fifth transistor, The fifth resistor connected to the drain of the sixth transistor, A third current source connected to the source of the fifth transistor, A fourth current source connected to the source of the sixth transistor, A sixth resistor connected between the source of the fifth transistor and the source of the sixth transistor, A seventh transistor is connected in parallel with the fifth transistor, and its gate is connected to the drain of the sixth transistor, An eighth transistor is connected in parallel with the sixth transistor, and its gate is connected to the drain of the fifth transistor, A differential interface circuit, including any of the items 1 to 3.

[0081] (Item 5) The differential interface circuit described in item 4 further includes a fourth capacitor connected in parallel with the sixth resistor, the second stage.

[0082] (Item 6) A differential interface circuit described in any of items 1 to 5, which is integrated into a single semiconductor substrate.

[0083] (Item 7) A receiver for multi-level PAM (Pulse Amplitude Modulation) signals, comprising a differential interface circuit as described in any of items 1 to 6.

[0084] While the embodiments described herein have been explained using specific terminology, this explanation is merely illustrative to aid understanding and does not limit the scope of this disclosure or the claims. The scope of the present invention is defined by the claims, and therefore embodiments, examples, and modifications not described herein are also included within the scope of the present invention. [Explanation of Symbols]

[0085] 400 Differential Interface Circuit 420_1,430_1 Stage 1 MN11 First Transistor MN12 Second Transistor MN13 Third Transistor MN14 4th transistor IB11 1st current source IB12 2nd current source CI11 First Capacitor CI12 Second Capacitor CS10 Third Capacitor RD11 1st resistor RD12 2nd resistor RS10 3rd resistor 420_2,430_2 Stage 2 MN21 Fifth Transistor MN22 6th Transistor MN23 7th Transistor MN24 8th Transistor IB21 Third current source IB22 4th current source CS20 4th Capacitor RD21 4th resistor RD22 5th resistor RS20 6th resistor 100 Transmission Systems 102 Transmission Cable 200 Transmitter 210 PAM encoder 220 P / S converter 230 PAM Driver 300 Receiver 310 Waveform shaping circuit 320 A / D converter 330 PAM phase comparator 340 Clock Recovery Circuit 350 S / P converter 360 PAM Decoder S2 Multi-value PAM signal

Claims

1. First input terminal and, Second input terminal and, Stage 1 and Equipped with, The first stage is, A first transistor whose gate is connected to the first input terminal, The gate of the second transistor is connected to the second input terminal, A first resistor connected to the drain of the first transistor, A second resistor connected to the drain of the second transistor, A first current source connected to the source of the first transistor, A second current source connected to the source of the second transistor, A third resistor connected between the source of the first transistor and the source of the second transistor, A third transistor is connected in parallel with the first transistor, and its gate is connected to the drain of the second transistor. A fourth transistor is connected in parallel with the second transistor, and its gate is connected to the drain of the first transistor, A first capacitor connected between the second input terminal and the source of the first transistor, A second capacitor connected between the first input terminal and the source of the second transistor, A differential interface circuit, including one.

2. The differential interface circuit according to claim 1, wherein the first stage further includes a third capacitor connected in parallel with the third resistor.

3. The first stage is, A seventh resistor connected in series with the first capacitor is placed between the second input terminal and the source of the first transistor. Between the first input terminal and the source of the second transistor, an eighth resistor is connected in series with the second capacitor, The differential interface circuit according to claim 1 or 2, further comprising:

4. The system further comprises a second stage connected to the subsequent stage of the first stage, The aforementioned second stage is, A fifth transistor whose gate is connected to the drain of the first transistor, A sixth transistor whose gate is connected to the drain of the second transistor, The fourth resistor connected to the drain of the fifth transistor, The fifth resistor connected to the drain of the sixth transistor, A third current source connected to the source of the fifth transistor, A fourth current source connected to the source of the sixth transistor, A sixth resistor connected between the source of the fifth transistor and the source of the sixth transistor, A seventh transistor is connected in parallel with the fifth transistor, and its gate is connected to the drain of the sixth transistor, An eighth transistor is connected in parallel with the sixth transistor, and its gate is connected to the drain of the fifth transistor, A differential interface circuit according to claim 1 or 2, including the differential interface circuit described in claim 1 or 2.

5. The differential interface circuit according to claim 4, wherein the second stage further includes a fourth capacitor connected in parallel with the sixth resistor.

6. A differential interface circuit according to claim 1 or 2, which is integrated as a single semiconductor substrate.

7. A receiving device for multi-level PAM (Pulse Amplitude Modulation) signals, comprising the differential interface circuit described in claim 1 or 2.

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