Imaging device

Abstract

To provide an imaging device capable of effectively reducing power consumption during moving image shooting without affecting AF processing.SOLUTION: In an imaging device having an FPGA capable of high-speed transfer of image signals of moving images received from an imaging element to an image processing circuit at a predetermined frame rate, the FPGA has at least a communication circuit block that transmits and receives the image signals between the imaging element and the image processing circuit, an image processing block that performs predetermined image processing on the received image signals, an AF processing block that performs arithmetic processing related to AF using the received image signals, and a PLL circuit block that outputs high-speed clock signals to the communication circuit block, the image processing block, and the AF processing block. The FPGA stops driving the PLL circuit block by detecting that both transfer processing of one frame's worth of image signals in the communication circuit block and AF processing in the AF processing block have been completed.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an imaging device capable of capturing moving images and reducing power consumption.

Background Art

[0002] Conventionally, in an imaging device having an intermediate device (FPGA) for image processing, when transmitting captured image data from the FPGA to a subsequent image processing device (DSP) via serial communication, a PLL circuit (Phase-locked loop circuit) is used as a means for generating a high-speed clock signal to enable high-speed transmission.

[0003] However, since the PLL circuit generally consumes a large amount of power, it has been desired to suppress power consumption by appropriately controlling the PLL circuit.

[0004] For example, in the invention disclosed in Patent Document 1, in an imaging device having an image sensor, an intermediate device, and an image processing device, and obtaining a moving image by the image sensor continuously acquiring a plurality of image signals, the intermediate device includes a PLL circuit that adjusts the speed of a clock signal, a synchronization signal generation circuit that notifies the PLL circuit of the start and completion of transmission of the captured image signal to the intermediate device, and a high-speed serial transmission circuit that performs high-speed serial communication with the image processing device using the clock signal adjusted by the PLL circuit. The PLL circuit has a pause period in which it stops operating after the transmission of the image signal for one frame among the image signals of the moving image captured by the image sensor. The pause period of the PLL circuit is a time preset with respect to a predetermined frame rate in the acquisition of a plurality of consecutive image signals. The intermediate device is configured to independently stop and start the PLL circuit by being given a predetermined frame rate.

[0005] According to this invention, it is stated that an imaging device capable of suppressing power consumption without reducing the processing efficiency of the captured image signal during moving image capture can be provided.

Prior Art Documents

Patent Documents

[0006] [Patent Document 1] Patent No. 6042676 [Overview of the project] [Problems that the invention aims to solve]

[0007] On the other hand, in recent years, digital cameras equipped with pixels for on-sensor phase-detection AF have become commonplace in order to meet the need for enhanced autofocus (AF) functionality. Consequently, the burden on the DSP (Digital Signal Processor) responsible for processing on-sensor phase-detection AF has increased. Therefore, it is desirable to configure the system so that some of the processing previously performed by the downstream DSP is transferred to the upstream FPGA (Field-Programmable Gate Array), thereby sharing the load on the DSP with the FPGA.

[0008] Even when a configuration is adopted in which an FPGA handles part of the processing (AF processing), it is still necessary to reduce the power consumption of the PLL circuit. In such a configuration, there are cases where the circuit block for AF processing is operating even during the blanking period of image transfer. Therefore, as disclosed in Patent Document 1, if control is implemented to stop the PLL circuit during the pause period of image transfer, the PLL circuit that is performing AF processing will also stop, leading to a malfunction.

[0009] This invention has been made in view of the above circumstances, and aims to provide an imaging device that can effectively reduce power consumption during video recording without affecting AF processing. [Means for solving the problem]

[0010] To achieve the above objective, an imaging device embodying the present invention has an FPGA (Field-Programmable Gate Array) as an intermediate device capable of high-speed transfer of image signals of moving images received from an image sensor to an image processing circuit at a predetermined frame rate. The FPGA comprises at least a communication circuit block that transmits and receives image signals between the image sensor and the image processing circuit, an image processing block that performs predetermined image processing on the received image signal, an AF processing block that performs calculation processing related to autofocus using the received image signal, and a PLL circuit block that outputs a high-speed clock signal to the communication circuit block, the image processing block, and the AF processing block. The FPGA stops driving the PLL circuit block when it detects that the transfer processing of one frame of image signals in the communication circuit block and the AF processing in the AF processing block have both been completed.

[0011] Furthermore, an imaging device embodying the present invention is preferably characterized in that, after a predetermined waiting period has elapsed since the completion of the transfer of one frame of image signals, the image processing circuit instructs the FPGA to restart the operation of the PLL circuit block, thereby ending the period during which the PLL circuit block is not driven. 。 [Effects of the Invention]

[0013] According to the imaging device embodying the present invention, it is possible to effectively reduce power consumption during video recording without affecting AF processing. [Brief explanation of the drawing]

[0014] [Figure 1] This is a block diagram showing the main components of an imaging device, which is one embodiment of the present invention. [Figure 2] This is a block diagram illustrating the processing within FPGA130 that transfers image signals to DSP140. [Figure 3] This is a timing chart showing the processing flow during video capture. [Figure 4]It is a flowchart for explaining the processing flow of the LV mode including the power management availability determination. [Figure 5] It is a flowchart for explaining the flow of the power management availability determination. [Figure 6] It is a flowchart for explaining the flow of the LV processing loop with power management.

Best Mode for Carrying Out the Invention

[0015] Hereinafter, the best mode for carrying out the present invention will be described with reference to the accompanying drawings. Note that the present invention is not limited by this embodiment.

[0016] The block diagram shown in FIG. 1 shows the main configuration of an imaging device according to an embodiment of the present invention. In this figure, the imaging device 100 includes a photographing optical system 110, an image sensor 120, an FPGA 130, a DSP 140, a main CPU 150, a user interface (I / F) 161, a recording medium interface (I / F) 162, an image display unit 170, and a lens control unit 180.

[0017] The photographing optical system 110 is composed of a plurality of lens groups not shown in the figure, including a focus lens group and a zoom lens group. In this figure, only one lens is shown as an example.

[0018] The image sensor 120 receives the light rays condensed by the photographing optical system 110, performs photoelectric conversion, and outputs an image signal. The image sensor 120 includes a gain variable amplifier and an A / D converter not shown inside, and the image signal is output as digital data. When an image sensor 120 that does not incorporate these gain variable amplifiers and A / D converters is adopted, these devices may be individually mounted.

[0019] The FPGA 130 is an intermediate device that performs predetermined processing on the image signal read from the image sensor 120 and outputs it to the subsequent DSP 140. The FPGA 130 will be described in detail later.

[0020] The DSP 140 performs various signal processes on the image signal output from the FPGA 130. Examples of the signal processes include, for example, color reproduction processing, development processing into image data in JPEG format or TIFF format, and the like.

[0021] The main CPU 150 performs overall control of the entire imaging apparatus 100 by executing the stored program. For example, it performs read control of the imaging element 120. That is, by outputting a signal for determining the driving timing of the imaging element 120 by the main CPU 150, horizontal driving and vertical driving for each pixel are controlled, and the image signal generated at each pixel is read out.

[0022] The lens control unit 180 is connected to the main CPU 150 so as to be mutually communicable, and cooperatively controls the imaging optical system 110.

[0023] The user I / F 161 has operation members such as a release button, a power button, a command dial, a cross key, etc. For example, when the user operates these operation members, the main CPU 150 issues an instruction to perform corresponding operations.

[0024] The recording medium I / F 162 writes and reads RAW data and developed image data to and from a recording medium (not shown). This recording medium is a removable recording medium such as a semiconductor memory.

[0025] The image display unit 170 displays so-called live view (LV) images, image data read from a recording medium (not shown), and the like.

[0026] Next, the function of the FPGA 130 in the imaging apparatus 100 of the present invention described above will be described in detail. FIG. 2 is a block diagram for explaining the processing in the FPGA 130 that functions to pass the image signal read from the imaging element 120 to the DSP 140.

[0027] In this figure, FPGA130 includes a receiving circuit block 131, an image processing block 132, a transmitting circuit block 133, a main clock generation block 134, a PLL circuit block 135, and an AF processing block 136.

[0028] The receiving circuit block 131 receives the image signal output from the image sensor 120.

[0029] The image processing block 132 applies predetermined image processing to the image signal output from the image sensor 120. Examples of image processing include defective pixel correction, white balance processing, and shading correction of the photographic lens. The processed image signal is then output to the transmission circuit block 133.

[0030] The transmission circuit block 133 transfers the image signal output from the image processing block 132 to the DSP 140. This ensures that the processed image signal is delivered from the FPGA 130 to the DSP 140. The transmission circuit block 133 also detects the completion of the image signal transfer to the DSP 140 using a known method. This transfer completion detection is used to stop the PLL circuit block 135, which will be described later.

[0031] The AF processing block 136 receives an image signal from the image processing block 132 as needed and applies predetermined AF processing to it. Examples of AF processing include contrast AF processing and correlation calculation processing using the output of image plane phase-difference pixels. The AF processing block 136 also detects the completion of AF processing by a known method. This processing completion detection is used to stop the drive of the PLL circuit block 135, which will be described later.

[0032] The main clock generation block 134 generates a clock signal. The clock signal generated here is input to the PLL circuit block 135.

[0033] The PLL circuit block 135 takes the clock signal generated by the main clock generation block 134 as an input signal and generates a high-speed clock signal synchronized with it. This high-speed clock signal is input to the image processing block 132, the transmission circuit block 133, and the AF processing block 136. This high-speed clock signal enables each circuit to perform high-speed internal processing.

[0034] Furthermore, when FPGA130 detects that both the image signal transfer in the transmission circuit block 133 and the AF processing in the AF processing block 136 have been completed, it stops driving the PLL circuit block 135.

[0035] Furthermore, regarding the synchronization signals between each circuit within FPGA130 and the image signal transfer from FPGA130 to DSP140, it is assumed that these signals are generated within the receiving circuit block 131 in this embodiment by a synchronization signal generation block (not shown). The synchronization signals generated here are input to the image processing block 132, the transmitting circuit block 133, and the AF processing block 136 via a communication path (not shown). Each circuit, such as the receiving circuit block 131, transfers the image signal to the subsequent circuit in synchronization with this synchronization signal.

[0036] Next, the processing flow when a moving image is captured at a predetermined frame rate (e.g., 30 fps) in the imaging device 100 embodying the present invention will be explained. Figure 3 is an example of a time chart showing the processing flow from the image sensor 120 to the DSP 140 when capturing a moving image.

[0037] In this figure, the signal VAct_In represents the transfer status of one frame of image signal acquired by the image sensor 120 from the image sensor 120 to the FPGA 130. In this embodiment, it corresponds to the signal status input to the receiving circuit block 131 in the FPGA 130. If this signal is Hi, it means that one frame has been transferred, and this period is the vertical active period. On the other hand, if this signal is Low, it means that the frame transfer is inactive.

[0038] The signal VAct_Out represents the transfer status of one frame of image signal processed within FPGA130 to DSP140. In this embodiment, it corresponds to the signal status output from the transmission circuit block 133 within FPGA130. If this signal is Hi, it means that one frame has been transferred, and this period is the vertical active period. On the other hand, if this signal is Low, it means that the frame transfer is inactive.

[0039] FPGA130 sequentially processes the transferred image signal, such as image processing, and then transfers it to DSP140. Therefore, in the following, the period from the start of transfer to FPGA130 (signal VAct_In is Hi) to the completion of transfer to DSP140 (signal VAct_Out is Low) for one frame of image signal may also be referred to as the frame transfer period Ton_Ft. In this figure, period (1) corresponds to this frame transfer period Ton_Ft.

[0040] This frame transfer period, Ton_Ft, is calculated in the DSP140 using a known calculation method based on the frame rate and exposure time in LV mode.

[0041] Furthermore, the period from the completion of transfer to DSP140 (signal VAct_Out is Low) to the start of transfer to FPGA120 for the next frame (signal VAct_In is High) is sometimes called the frame transfer pause period Toff_Ft. In this figure, period (2) corresponds to this frame transfer pause period Toff_Ft.

[0042] In the LV mode of the imaging device 100 in this embodiment, the frame rate is fixed, and the period from when the signal VAct_In rises to Hi until it rises again in the next frame transfer is constant. Therefore, this frame transfer pause period Toff_Ft is calculated in the DSP 140 by the difference between the frame rate in LV mode and the frame transfer period Ton_Ft described above.

[0043] The AF processing signal S_AF is a signal that represents the execution status of a predetermined AF process in the AF processing block 136 within the FPGA 130. If this signal is Hi, it means that AF processing is being performed in the AF processing block 136, while if this signal is Low, it means that AF processing is not being performed. For example, this signal changes from Hi to Low when AF focus determination is successful. Hereafter, the period during which this signal is Hi may also be referred to as the AF processing period Ton_AF. In this figure, period (3) corresponds to this AF processing period Ton_AF.

[0044] This AF processing period Ton_AF can be pre-calculated in the DSP140 by known calculations corresponding to the AF settings of the imaging device 100, such as the position and size of the distance measuring frame.

[0045] Furthermore, the period from the start of data transfer to FPGA130 (signal VAct_In is Hi) to the start of AF processing (signal S_AF is Hi) is sometimes referred to as the AF processing waiting period Toff_AF. In this figure, period (4) corresponds to this AF processing waiting period Toff_AF.

[0046] This AF processing waiting period Toff_AF can be pre-calculated in the DSP140 by known calculations corresponding to the AF settings of the imaging device 100, such as the position and size of the distance measuring frame.

[0047] In this diagram, the AF processing period Ton_AF ends after the frame transfer period Ton_Ft has finished. However, this is not the only case; if the AF processing is light and completed quickly due to settings such as so-called single-point AF (pinpoint AF), the order of these processes may be reversed.

[0048] The PLL drive signal S_PLL represents the drive status of the PLL circuit block 135 within the FPGA 130. If this signal is high, it means that the PLL circuit block 135 is being driven, and that one of the circuits within the FPGA 130 is performing processing. On the other hand, if this signal is low, it means that the PLL circuit block 135 is not being driven.

[0049] In this embodiment, the PLL circuit block 135 is basically in a driven state during the imaging mode of the imaging device 100, and enters a driven-off state in accordance with a command to stop driving from the FPGA 130. Therefore, the period from when the PLL circuit block 135 is driven off (signal S_PLL is Low) to when it returns (signal S_PLL is High) is the power management period Toff_PLL in the imaging device 100 that embodies the present invention. In this figure, period (5) corresponds to this power management period Toff_PLL.

[0050] This power management period, Toff_PLL, starts when both the aforementioned signals VAct_Out and S_AF go low.

[0051] Furthermore, this power management period, Toff_PLL, is calculated in DSP140 based on various related periods. Details of the calculation will be explained later.

[0052] The PLL stabilization period Tstb_PLL represents the period required for the PLL circuit block 135 to stabilize after the power management period Toff_PLL has ended and it has recovered from the drive stop state. In this embodiment, the value obtained from the specifications table of the PLL circuit block 135 is stored in the DSP 140 as a preset value, and the DSP 140 refers to it as needed. In this figure, period (6) corresponds to this PLL stabilization period Tstb_PLL.

[0053] The PLL return trigger signal Strig_PLL represents the signal that DSP140 sends to FPGA130 to instruct the PLL circuit block 135 to return to its normal state. In this embodiment, the timing of the transmission of this PLL return trigger signal Strig_PLL is controlled by DSP140.

[0054] Specifically, when the DSP140 detects that the frame transfer from FPGA130 to DSP140 is complete, it starts counting down the time until it sends the PLL return trigger signal Strig_PLL. When it detects that the predetermined period has elapsed, the DSP140 sends the PLL return trigger signal Strig_PLL to FPGA130 in order to restore the PLL circuit block 135. Hereafter, this period may also be referred to as the PLL return trigger waiting period Ttrig_PLL. In this figure, period (7) corresponds to this PLL return trigger waiting period Ttrig_PLL.

[0055] To achieve an effective reduction in power consumption, it is effective to maintain the PLL return trigger waiting period Ttrig_PLL for as long as possible, thereby increasing the period during which the PLL circuit block 135 is stopped. Therefore, in this embodiment, the DSP 140 should transmit the PLL return trigger signal Strig_PLL at a timing that is the PLL stabilization period Tstb_PLL required for stabilizing the drive of the PLL circuit block 135, prior to the timing when the next frame transfer is initiated from the image sensor 120.

[0056] Specifically, the PLL return trigger waiting period Ttrig_PLL can be calculated using the frame transfer pause period Toff_Ft and the PLL stabilization period Tstb_PLL mentioned above. That is, the PLL return trigger waiting period Ttrig_PLL is calculated using the following formula. Ttrig_PLL=Toff_Ft-Tstb_PLL ··· (Formula 1)

[0057] Next, we will explain how to calculate the power management period Toff_PLL mentioned above. In this embodiment, the calculation method for the power management period Toff_PLL differs depending on whether the end of the frame transfer period Ton_Ft or the end of the AF processing period Ton_AF is later, so we will consider each case separately.

[0058] First, let's consider the case shown in Figure 3, where the AF processing period Ton_AF ends after the frame transfer period Ton_Ft ends, that is, the AF processing is completed after the frame transfer is complete.

[0059] In this case, even after the frame transfer is complete, the PLL circuit block 135 must be kept running until the AF processing is complete. Therefore, the ideal period during which the PLL circuit block can be stopped, ignoring the stabilization period, is the difference between the period from the start of transfer of the image sensor 120 to the start of transfer of the next frame (=frame rate) and the period from the start of transfer of the image sensor 120 to the completion of the AF processing.

[0060] From the above, the actual power management period Toff_PLL can be calculated using the following formula, with respect to the frame transfer period Ton_Ft, the frame transfer pause period Toff_Ft, the AF processing period Ton_AF, the AF processing waiting period Toff_AF, and the PLL stabilization period Tstb_PLL. Toff_PLL=(Ton_Ft+Toff_Ft) -(Toff_AF+Ton_AF) - Tstb_PLL ··· (Formula 2)

[0061] Next, we consider the opposite case described above, where the frame transfer period Ton_Ft ends after the AF processing period Ton_AF ends, that is, the AF processing is completed during frame transfer.

[0062] In this case, there is no need to worry about AF processing; once frame transfer is complete, the PLL circuit block 135 can be stopped. Therefore, the ideal period during which the PLL circuit block can be stopped is the same as the frame transfer pause period Toff_Ft.

[0063] From the above, the actual power management period Toff_PLL can be calculated using the frame transfer pause period Toff_Ft and the PLL stabilization period Tstb_PLL, using the following formula. Toff_PLL=Toff_Ft-Tstb_PLL ··· (Formula 3)

[0064] As explained above, the power management period Toff_PLL of the PLL circuit block 135 in the imaging device 100 implementing the present invention is determined by the respective formulas, depending on whether the frame transfer or AF processing is completed later. However, if the calculated power management period Toff_PLL is too short, the processing of the imaging device 100 may become unstable. Therefore, it is desirable to make a determination as to whether or not to actually perform power management.

[0065] Figure 4 is an example flowchart illustrating the processing flow of the LV mode, including the power management feasibility determination of the PLL circuit block 135. Although not shown in this figure, this flowchart also describes the case where AF processing is included during LV processing.

[0066] This flowchart begins when the imaging device 100 enters LV mode. LV mode is initiated, for example, by the user turning on the power to the imaging device 100 or selecting a shooting mode using LV.

[0067] First, in step S101 of this flowchart, the LV drive settings of the imaging device 100 are checked. Specifically, it is checked whether actions such as zooming in on the LV image to check details or changing the position of the distance measuring frame have been performed, and these changes are reflected.

[0068] Next, in step S102, a determination is made regarding whether the PLL circuit block 135 is power-managed. The power-management capability determination will be explained in more detail later.

[0069] Next, in step S103, the process branches based on the determination result from the previous step. Specifically, if the PLL circuit block 135 is determined to be power-manageable, the process proceeds to step S104. On the other hand, if the PLL circuit block 135 is determined to be power-manageable, the process proceeds to step S106.

[0070] In step S104, the PLL recovery trigger waiting period Ttrig_PLL is calculated. Specifically, as mentioned above, the DSP140 calculates this from the frame transfer pause period Toff_Ft and the PLL stabilization period Tstb_PLL.

[0071] Next, in step S105, the power manager-enabled LV processing loop is executed. This processing loop will be explained in more detail later. Once the power manager-enabled LV processing loop is finished, the process proceeds to step S107.

[0072] Meanwhile, in step S106, a known LV processing loop without power management is executed. Once the LV processing loop without power management finishes, the process proceeds to step S107.

[0073] Next, in step S107, a determination is made as to whether the LV mode of the imaging device 100 will end. Cases in which the LV mode will end include, for example, the user turning off the power of the imaging device 100, selecting a still shooting mode that does not use LV, or transitioning to a menu screen. If the LV mode of the imaging device 100 does not end and continues, the process returns to step S102, where a determination is made again as to whether the power management of the PLL circuit block 13 is enabled or disabled. On the other hand, if the LV mode of the imaging device 100 will end, this flowchart ends there.

[0074] Next, we will explain in detail the power management feasibility determination step S102 of the overall flow described above. Figure 5 is an example of a flowchart illustrating the power management feasibility determination process.

[0075] When the power management feasibility determination S102 in Figure 4 is initiated, in step S201, the DSP140 first calculates the power management period Toff_PLL. As described above, in this embodiment, the calculation formula for this power management period Toff_PLL differs depending on whether the frame transfer or AF processing is completed later. Therefore, the DSP140 first determines which processing will be completed later.

[0076] Specifically, the DSP140 compares the frame transfer period Ton_Ft with the sum of the AF processing waiting period Toff_AF and the AF processing period Ton_AF. If the frame transfer period Ton_Ft is shorter, it uses equation (1) above to calculate the power management period Toff_PLL. Conversely, if the frame transfer period Ton_Ft is longer, it uses equation (2) above to calculate the power management period Toff_PLL.

[0077] Next, in step S202, a determination is made as to whether the power management period Toff_PLL calculated in the previous step is longer than a predetermined period Tth_PLL. This predetermined period Tth_PLL can be, for example, 0, or it can be set to a period that takes into account the stability of the process.

[0078] Based on the judgment, if the power management period Toff_PLL is longer than or equal to the period Tth_PLL, DSP140 is determined to be capable of power management and proceeds to step S203. Conversely, if the power management period Toff_PLL is shorter than the period Tth_PLL, DSP140 is determined to be incapable of power management and proceeds to step S204.

[0079] Next, in step S203, the power management enabled flag is turned ON according to the result of the previous step. On the other hand, in step S204, the power management enabled flag is turned OFF according to the result of the previous step.

[0080] Once each of the above steps is completed, this flowchart ends and proceed to step S103.

[0081] In this way, by having the DSP 140 determine whether or not the PLL circuit block 135 is power-manageable, there is no need for unnecessary communication with the FPGA 130, and therefore it is possible to simplify the configuration for implementing the invention.

[0082] Next, we will explain in detail the power manager-enabled LV processing loop S105 of the overall flow described above. Figure 6 is an example flowchart illustrating the flow of the power manager-enabled LV processing loop. When the process proceeds to step S105 in Figure 4, the power manager-enabled LV processing loop in this flowchart begins.

[0083] Steps S301, S303, S304, S307, S308, and S310 in this flowchart are processes performed by the DSP140. On the other hand, steps S302, S305, S306, and S309 are processes performed by the FPGA130.

[0084] First, in step S301, the DSP140 instructs the FPGA130 to start frame transfer.

[0085] Next, in step S302, the FPGA 130 receives instructions from the DSP 140 and starts frame transfer. This allows the FPGA 130 to receive one frame of image signals generated by the image sensor 120 and transfer one frame of image signals processed within the FPGA 130 to the DSP 140 at a predetermined frame rate. The FPGA 130 then starts AF processing on the image signals received from the image sensor 120.

[0086] Next, in step S303, the DSP140 detects that it has finished receiving one frame from the FPGA130. One way to do this is to embed a synchronization code that signals the start and end of frame transfer within the high-speed serial communication used for transfer, and the DSP140 detects the start and end of the transfer by detecting this synchronization code when it is received.

[0087] Next, in step S304, the DSP 140 detects the completion of frame reception in the preceding step S303 and begins counting the period it must wait before sending the PLL return trigger signal Strig_PLL to restore the PLL circuit block 135, i.e., the PLL return trigger waiting period Ttrig_PLL. Specifically, the DSP 140 starts counting from the end of the frame transfer period Ton_Ft and continues this counting until the PLL return trigger waiting period Ttrig_PLL calculated in step S104 of Figure 4 has elapsed.

[0088] Meanwhile, in step S305, FPGA130 detects that both the frame transfer to DSP140 and the AF processing in AF processing block 136 have been completed.

[0089] Next, in step S306, FPGA 130 detects the completion of frame transfer and AF processing in the preceding step S305, and stops driving the PLL circuit block 135. This triggers the power management period Toff_PLL.

[0090] In this way, by having the FPGA 130 independently stop the PLL circuit block 135 to enter the power management period, communication with the DSP 140 becomes unnecessary, allowing for a quick and time-free entry into the power management period. Furthermore, since the DSP 140 does not need to be involved in stopping the FPGA 130, it is possible to prevent delays in processing within the DSP 140.

[0091] Meanwhile, in step S307, the DSP140 detects that the pre-calculated PLL return trigger waiting period Ttrig_PLL has elapsed in its continuous time count. As a result, the DSP140 stops the count and resets.

[0092] Next, in step S308, the DSP140 detects that the PLL return trigger waiting period Ttrig_PLL has elapsed and sends a PLL return trigger signal Strig_PLL to the FPGA130 to resume driving the PLL circuit block 135.

[0093] In this way, by sending a trigger signal from the DSP 140 to command the PLL circuit block 135 to return to its normal state, the DSP 140 can determine that the transfer of the next frame is unnecessary when an interrupt occurs due to mode switching, etc., enabling more precise stop control of the PLL circuit block 135 compared to when the return decision is made by the FPGA 130.

[0094] Meanwhile, in step S309, FPGA130 receives a command from DSP140 to restart PLL circuit block 135 and resumes operation of PLL circuit block 135. This ends the power management period Toff_PLL.

[0095] Next, in step S310, the DSP140 determines whether this LV loop has ended. Specifically, the DSP140 detects whether the drive mode of the image sensor 120 has been changed. If the drive mode has been changed, it terminates this LV loop and proceeds to step S107 in Figure 4. On the other hand, if the drive mode of the image sensor 120 has not been changed, it returns to step S301 to repeat this loop and executes each step again.

[0096] As described above, with the imaging device described in the present invention, even in a configuration in which AF processing is performed in an FPGA, the PLL circuit block provided in the FPGA can be stopped without affecting the AF processing, and power consumption can be efficiently reduced. [Explanation of symbols]

[0097] 110 Imaging Optics 120 image sensors 130 FPGA 131 Receiving circuit block 132 Image Processing Block 133 Transmitter circuit block 134 Main Clock Generation Block 135 PLL circuit block 136 AF processing block 140 DSP 150 Main CPU 161 User Interface 162 Recording medium interface 170 Image display section 180 Lens Control Unit

Claims

1. In an imaging device having an FPGA (Field-Programmable Gate Array) as an intermediate device capable of high-speed transfer of image signals of moving images received from an image sensor to an image processing circuit at a predetermined frame rate, The FPGA includes at least a communication circuit block that transmits and receives image signals between the image sensor and the image processing circuit, an image processing block that performs predetermined image processing on the received image signal, an AF processing block that performs calculation processing related to autofocus using the received image signal, and a PLL circuit block that outputs a high-speed clock signal to the communication circuit block, the image processing block and the AF processing block. The imaging device is characterized in that the FPGA stops driving the PLL circuit block when it detects that both the transfer processing of one frame of image signals in the communication circuit block and the AF processing in the AF processing block have been completed.

2. The imaging apparatus according to claim 1, characterized in that the image processing circuit, after a predetermined waiting period has elapsed since the completion of the transfer of one frame of image signals, instructs the FPGA to restart the operation of the PLL circuit block, thereby ending the period during which the operation of the PLL circuit block is stopped.

Images