Equalizer circuit and associated power management circuit

Abstract

To provide an equalizer circuit and a related power management circuit capable of reducing distortion in an envelope tracking (ET) voltage in a case where a radio frequency (RF) signal is modulated in a wide modulation band width.SOLUTION: In a power management device 30, a power management circuit 28 has: a power amplifier circuit 34 configured to generate an ET voltage VCC on the basis of a differential target voltage and provide the ET voltage VCC to a power amplifier circuit 32 via a signal path 36 for amplifying an RF signal 38; and an equalizer circuit 40 that equalizes the differential target voltage prior to generating the ET voltage VCC. Specifically, the equalizer circuit 40 is configured to provide a transfer function including a second-order complex-zero term and a real-zero term for offsetting a transfer function of an inherent trace inductance of the signal path and an inherent impedance of a voltage amplifier circuit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] Related applications This application claims the interests of Provisional Patent Application No. 63 / 135,134, filed on 8 January 2021, the disclosures thereof, which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to equalizer circuits, and more particularly to equalizer circuits for power management circuits configured to operate over a wide modulation bandwidth. [Background technology]

[0003] Mobile communication devices are becoming increasingly common in today's society for providing wireless communication services. The proliferation of these mobile communication devices is partly driven by the many features now enabled in such devices. The increased processing power in such devices means that mobile communication devices are evolving from purely communication tools to high-performance mobile multimedia centers that enable more advanced user experiences.

[0004] A redefined user experience requires high data rates offered by wireless communication technologies, such as fifth-generation novel wireless (5G-NR) technology, which are configured to communicate millimeter-wave (mmWave) radio frequency (RF) signals in the mmWave spectrum located above 12 GHz. To achieve higher data rates, mobile communication devices may use power amplifiers to increase the output power of the mmWave RF signal (for example, to maintain sufficient energy per bit). However, increasing the output power of the mmWave RF signal can lead to increased power consumption and heat dissipation in the mobile communication device, thus compromising overall performance and user experience.

[0005] Envelope tracking (ET) is a power management technique designed to improve the efficiency level of power amplifiers, helping to reduce power consumption and heat dissipation in mobile communication devices. In an ET system, the power amplifier amplifies the RF signal based on a time-varying ET voltage generated according to the time-varying amplitude of the RF signal. More specifically, the time-varying ET voltage corresponds to a time-varying voltage envelope that tracks the time-varying power envelope of the RF signal (e.g., rising and falling). Naturally, the more closely the time-varying voltage envelope tracks the time-varying power envelope, the higher the linearity the power amplifier can achieve. [Overview of the project] [Problems that the invention aims to solve]

[0006] However, time-varying ET voltages can be highly susceptible to distortion caused by trace inductance and / or load impedance, especially when the time-varying ET voltage is generated to track the time-varying power envelope of a high modulation bandwidth (e.g., >200 MHz) RF signal. As a result, the time-varying voltage envelope can become misaligned with the time-varying power envelope of the RF signal, thus potentially causing undesirable distortion (e.g., amplitude clipping) in the RF signal. In this regard, it is desirable to reduce the distortion caused by trace inductance and / or load impedance in the time-varying ET voltage. [Means for solving the problem]

[0007] Embodiments of the present disclosure relate to an equalizer circuit and associated power management circuits. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit via a signal path for amplifying a high-frequency (RF) signal. In particular, the voltage amplifier circuit may have an inherent impedance, and the signal path may have an inherent transinductance that can collectively distort the ET voltage. Thus, the power management circuit includes an equalizer circuit for equalizing the differential target voltage before generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function including a quadratic complex zero term and a real zero term for offsetting the transfer function of the inherent trace inductance and inherent impedance. By using a quadratic transfer function with a real zero term to offset the inherent trace inductance and inherent impedance, it is possible to reduce the distortion of the ET voltage, especially when the RF signal is modulated over a wide modulation bandwidth (e.g., >200 MHz).

[0008] In one embodiment, an equalizer circuit is provided. The equalizer circuit includes a voltage input that receives a differential target voltage, which includes a negative target voltage and a positive target voltage. The equalizer circuit also includes a voltage output that outputs an equalization target voltage corresponding to the differential target voltage. The equalizer circuit also includes an equalizer tuning circuit coupled between the voltage input and the voltage output. The equalizer tuning circuit is configured to generate the equalization target voltage from the differential target voltage based on a transfer function that includes a quadratic complex zero term and a real zero term.

[0009] In another embodiment, a power management circuit is provided. The power management circuit includes an equalizer circuit. The equalizer circuit includes a voltage input that receives a differential target voltage, which includes a negative target voltage and a positive target voltage. The equalizer circuit also includes a voltage output that outputs an equalized target voltage corresponding to the differential target voltage. The equalizer circuit also includes an equalizer tuning circuit coupled between the voltage input and the voltage output. The equalizer tuning circuit is configured to generate the equalized target voltage from the differential target voltage based on a transfer function that includes a quadratic complex zero term and a real zero term. The power management circuit also includes a voltage amplifier circuit configured to generate an ET voltage based on the equalized target voltage.

[0010] Those skilled in the art will understand the scope of this disclosure and realize additional embodiments thereof after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings.

[0011] The accompanying figures incorporated herein and forming part thereof illustrate several aspects of this disclosure and, together with the description, serve to illustrate the principles of this disclosure. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic diagram of an exemplary conventional envelope tracking (ET) power amplifier configured to generate an ET voltage. [Figure 2] Figure 1 is a schematic diagram of an exemplary equivalent circuit to illustrate various impedances and / or inductances of a conventional power amplifier that can distort the ET voltage. [Figure 3] This graph provides an example of factors contributing to voltage disturbance in the equivalent circuit of Figure 2, which can distort the ET voltage in Figure 1. [Figure 4] This is a schematic diagram of an exemplary power management circuit configured to implement a quadratic complex zero transfer function with a real zero term to offset voltage disturbances in the ET voltage, according to embodiments of the present disclosure. [Figure 5]The power management circuit in Figure 4 is a graph illustrating how voltage disturbances can be effectively reduced, as shown in Figure 3, based on a quadratic complex zero transfer function with a real zero term, in order to offset voltage disturbances in the ET voltage. [Figure 6] This schematic diagram provides an illustrative example of an equalizer circuit in the power management circuit of Figure 4, configured according to an embodiment of the present disclosure, for implementing a quadratic complex zero transfer function with a real zero term to offset voltage disturbances in the ET voltage. [Figure 7] This is a schematic diagram providing an exemplary diagram of the equalizer tuning circuit provided for the equalizer circuit in Figure 6. [Figure 8A] This is a schematic diagram providing an example of an alternative implementation of the equalizer tuning circuit shown in Figure 7. [Figure 8B] This is a schematic diagram providing an example of an alternative implementation of the equalizer tuning circuit shown in Figure 7. [Modes for carrying out the invention]

[0013] The embodiments described below represent the necessary information and best modes for carrying out the embodiments, enabling those skilled in the art to implement them. By reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and recognize applications of these concepts not specifically addressed herein. It should be understood that these concepts and applications are included within the scope of this disclosure and the accompanying claims.

[0014] Terms such as "first," "second," etc., may be used herein to describe various elements, but it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, the first element may be referred to as the second element without departing from the scope of this disclosure, and similarly, the second element may be referred to as the first element. Where used herein, the term "and / or" includes any and all combinations of one or more of the related enumerated items.

[0015] When an element such as a layer, region, or substrate is said to be "on top of" another element or to extend "upwards" it, it will be understood that there may also be elements that are directly on top of the other element, extend directly upwards, or intervene it. In contrast, when an element is said to be "directly on top of" another element or to extend "directly upwards" it, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is said to be "above" another element or to extend "upwards", it will be understood that there may also be elements that are directly above the other element, extend directly above it, or intervene it. In contrast, when an element is said to be "directly above" or to extend "directly upwards" it, there are no intervening elements. When an element is said to be "connected" or "bonded" to another element, it will be understood that there may also be elements that are directly connected to the other element, bonded to it, or intervene it. In contrast, when an element is said to be "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0016] Relative terms such as "down" or "up" or "top" or "down" or "horizontal" or "vertical" may be used herein to describe the relationship between one element, layer, or region and another, as shown in the figures. It will be understood that these terms and the terms considered above are intended to encompass different orientations of the device, in addition to the orientation depicted in the figures.

[0017] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the disclosure. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context expressly indicates otherwise. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of a described feature, integer, step, action, element, and / or component, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0018] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art in the field to which this disclosure belongs. Terms used herein should be construed as having the meaning consistent with their meaning in the context of this specification and related art, and it will be further understood that they should not be construed in an idealized or overly formal sense unless expressly defined herein.

[0019] Embodiments are described herein with reference to an equalizer circuit and associated power management circuits. The power management circuit includes a voltage amplifier circuit configured to generate an envelope tracking (ET) voltage based on a differential target voltage and provide the ET voltage to a power amplifier circuit via a signal path for amplifying a high-frequency (RF) signal. In particular, the voltage amplifier circuit may have an inherent impedance, and the signal path may have an inherent transinductance that can collectively distort the ET voltage. Thus, the power management circuit includes an equalizer circuit for equalizing the differential target voltage before generating the ET voltage. Specifically, the equalizer circuit is configured to provide a transfer function having a quadratic complex zero term and a real zero term for offsetting the transfer function of the inherent trace inductance and inherent impedance. By using a quadratic transfer function with a real zero term to offset the inherent trace inductance and inherent impedance, it is possible to reduce the distortion of the ET voltage, especially when the RF signal is modulated over a wide modulation bandwidth (e.g., >200 MHz).

[0020] Before discussing the power management circuit and the equalizer circuit incorporated therein according to this disclosure, which begin in Figure 4, we first provide an overview of a conventional ET power management device capable of experiencing ET voltage distortion, referring to Figures 1 to 3.

[0021] Figure 1 shows the ET voltage V CC This is a schematic diagram of an exemplary conventional power management device 10 configured to generate [a certain signal]. The conventional power management device 10 includes a transceiver circuit 12, an ET integrated circuit (ETIC) 14, a power amplifier circuit 16, and a signal line 18 that couples the ETIC 14 to the power amplifier circuit 16.

[0022] The transceiver circuit 12 controls the time-varying power envelope P ENV The transceiver circuit 12 is configured to generate an associated RF signal 20 and provide it to the power amplifier circuit 16. The transceiver circuit 12 is also configured to generate a (also known as) tracking time-varying power envelope P ENV According to the target voltage V TGTconfigured to generate. ETIC14 is based on the target voltage V TGT to generate the ET voltage V CC configured, and the power amplifier circuit 16 is configured to amplify the RF signal 20 based on the ET voltage V CC .

[0023] Those skilled in the art will understand that the power amplifier circuit 16 can operate with improved efficiency and linearity when the ET voltage V CC exactly tracks the power envelope P of the RF signal 20 ENV . This is achieved when the ET voltage V CC is temporally aligned with the target voltage V TGT . However, the temporal alignment between the ET voltage V CC and the target voltage V TGT can be complicated by various impedances and / or inductances presented to the conventional power management device 10.

[0024] To illustrate various impedances and / or inductances, FIG. 2 is a schematic diagram of an exemplary equivalent circuit 22 for illustrating various impedances and / or inductances of the conventional power management device 10 of FIG. 1 that can distort the ET voltage V CC . For elements common between FIGS. 1 and 2, they are denoted by common element numbers and will not be re-described herein.

[0025] In the equivalent circuit 22, ETIC14 has an inherent inductance that can be modeled by an equivalent inductance L ETIC , and the signal line 20 has an inherent transformer inductance that can be modeled by an equivalent transformer inductance L TRACE . Thus, the equivalent circuit 22 has an equivalent total inductance L ETIC equal to the sum of the equivalent inductance L TRACE (L E =L ETIC +L TRACE ) of E .

[0026] The power amplifier circuit 16 controls the modulated current I CC Modeled as a current source having (s), with total equivalent capacitance C PA It may have. Therefore, the equivalent current source impedance Z presented to the current source SOURCE (s) can be determined as shown in the following equation (Equation 1).

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[0027] In equation (Equation 1), s represents the s-transformation notation and can be expressed as s = j²πf. Modulated current I CC (s) is the target voltage V TGT It is proportional to a certain extent and can be expressed as shown in the following equation (Equation 2).

number

[0028] In the above equation (Equation 2), Z ICC (s) represents the impedance at the collector (not shown) of the power amplifier circuit 16, and ΔD is the V at the output stage (not shown) of the power amplifier circuit 16. TGT and time-varying power envelope P EVN This represents the group delay between [the specified point] and [the specified point].

[0029] In particular, the modulated current I CC This can cause a voltage disturbance across the entire collector of the power amplifier circuit 16. The voltage disturbance is Z SOURCE (s)*I CC (s) is approximately equal to (s). As illustrated and discussed in Figure 3, the voltage disturbance is mainly due to the total equivalent inductance L E This can be caused by the following. Figure 3 is a graph illustrating the factors contributing to voltage disturbance in the equivalent circuit 22 of Figure 2, which can distort the ET voltage of Figure 1.

[0030] Figure 3 shows the first transfer function curve 24 and the second transfer function curve 26. Specifically, the first transfer function curve 24 is the ET voltage V CC An equivalent trace inductance L can cause voltage disturbances. TRACE The transfer function is shown. The second transfer function curve 26 is given by the ET voltage V CC Equivalent impedance L can cause voltage disturbances. ETIC The transfer function is shown. As shown in Figure 3, the equivalent trace inductance L TRACE The ET voltage V CC It is possible to make the current peak at frequency A and then decrease sharply. On the other hand, the equivalent inductance L ETIC The frequency B is from the ET voltage V CC This can cause a decrease in equivalent trace inductance L. TRACE and equivalent inductance L ETIC The ET voltage V caused by the transfer function CC A change in the ET voltage (also known as voltage disturbance) is called an ET voltage V CC This can lead to distortion.

[0031] Referring again to Figure 2, the equivalent trace inductance L TRACE and equivalent inductance L ETIC The transfer function can generally be expressed as H(s) in the s-domain by the following equation (Equation 3).

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[0032] In the above equation (Equation 3), N(s) and D(s) are simple polynomials that define one or more zeros and one or more poles of the transfer function, respectively, with s = j2πf. The one or more zeros are roots of the polynomial equation N(s) and can be determined by solving equation N(s) = 0. The degree of the polynomial N(s) determines the number of zeros in the transfer function H(s). Each zero corresponds to a zero output of the transfer function H(s). The polynomial N(s) is a zero-degree polynomial when N(s) represents a constant value, a linear polynomial when N(s) = 1 + b0s (where b0 is a constant), and N(s) = 1 + b0s + b1s 2 This includes quadratic polynomials when (b1 is a constant), etc. In particular, the transfer function H(s) has a real zero term when N(s) is a linear polynomial N(s)=1+b0s, or when N(s) is a quadratic polynomial N(s)=1+b0s+b1s 2 In this case, it is further called the quadratic complex zero transfer function. Therefore, the quadratic complex zero term (1+b0s+b1s 2 A transfer function H(s) that has both a real zero term (1+b0s) and a real zero term (1+b0s) can be called a quadratic complex zero transfer function with a real zero term.

[0033] In contrast to zero, one or more poles are roots of the polynomial D(s) and can be determined by solving equation D(s)=0. The degree of the polynomial D(s) determines the number of poles of the transfer function H(s). Each pole corresponds to an infinite output of the transfer function H(s). The polynomial D(s) is a zero-degree polynomial when D(s) represents a constant value, a linear polynomial when D(s)=1+a0s (where a0 is a constant), and D(s)=1+a0s+a1s 2 This includes quadratic polynomials when (a1 is a constant), etc. In particular, the transfer function H(s) has a real pole term when D(s) is a linear polynomial N(s)=1+a0s, or when D(s) is a quadratic polynomial N(s)=1+a0s+a1s 2 In this case, it is further called the quadratic complex pole transfer function. Therefore, the quadratic complex pole term (1+a0s+a1s 2 A transfer function H(s) that has both a real pole term (1+a0s) can be called a quadratic complex pole transfer function with a real pole term.

[0034] Specifically, the equivalent trace inductance L TRACE The transfer function H(s) can be a quadratic complex pole transfer function, and the equivalent inductance L ETIC The transfer function H(s) can have a real pole transfer term. Therefore, the equivalent trace inductance L TRACE and equivalent inductance L ETIC The overall transfer function H(s) can be a quadratic complex pole transfer function H(s) with a real pole term. In this respect, the ET voltage V CC To reduce or eliminate voltage disturbances, it is necessary to implement a quadratic complex zero transfer function H(s) with a real zero term to offset the quadratic complex pole transfer function H(s) with a real pole term. Next, we will consider a specific embodiment of creating a quadratic complex zero transfer function N(s) for offsetting voltage disturbances from Figure 4.

[0035] Figure 4 shows the ET voltage V according to an embodiment of the present disclosure. CC This is a schematic diagram of an exemplary power management circuit 28 configured to implement a quadratic complex zero transfer function H(s) with a real zero term in order to offset voltage disturbances in V. The power management circuit 28 can be provided in a power management device 30 which also includes a power amplifier circuit 32. The power management circuit 28 controls the differential target voltage V TGT Based on the ET voltage V CC The ET voltage V is generated and amplified via a signal path 36 (e.g., a conductive trace) for the RF signal 38. CC The system includes a voltage amplifier circuit 34 configured to provide power to the power amplifier circuit 32.

[0036] Notably, the voltage amplifier circuit 34 has an equivalent inductance L as shown in Figure 2. ETIC It can have an intrinsic impedance that can be modeled by the same. Similarly, the signal path 36 has an equivalent inductance L as shown in Figure 2. TRACE It can have an intrinsic transinductance that can be modeled by . Therefore, according to the prior considerations in Figures 2 and 3, the equivalent inductance L ETIC and equivalent inductance LTRACE This presents the quadratic complex pole transfer function H(s) collectively with the real poles, and shows how to apply the ET voltage V to voltage disturbances. CC It can be distorted.

[0037] Thus, the power management circuit 28 is configured to include an equalizer circuit 40. As will be discussed in detail below, the equalizer circuit 40 controls the differential target voltage V TGT Equalize the following, equalize target voltage V TGT-E It is configured to generate the target equalization voltage V. Therefore, the voltage amplifier circuit 34 is configured to generate the target equalization voltage V. TGT-E Based on this, ET voltage V CC It can be configured to generate.

[0038] Specifically, the equalizer circuit 40 sets the target voltage V based on a quadratic complex zero transfer function H(s) with a real zero term. TGT-E It is configured to generate the equalization target voltage V. TGT-E This is the equivalent trace inductance L TRACE and equivalent inductance L ETIC The transfer function H(s) can be effectively offset. As a result, the ET voltage V can be adjusted, especially when the RF signal 38 is modulated with a wide modulation bandwidth (e.g., >200MHz). CC It is possible to eliminate voltage disturbances.

[0039] Figure 5 is a graph illustrating how the equalizer circuit 40 of the power management circuit 28 in Figure 4 can effectively reduce voltage disturbances, as shown in Figure 3, based on a quadratic complex zero transfer function H(s) with a real zero term. Elements common to Figures 3 and 5 are indicated by common element numbers and are not described again herein.

[0040] Figure 5 further shows the third transfer function curve 42 and the fourth transfer function curve 44. Specifically, the third transfer function curve 42 represents the quadratic complex zero transfer function H(s) with a real zero term implemented in the equalizer circuit 40. The fourth transfer function curve 44 is the overall transfer function of the power management circuit 28. As shown in the nearly flat fourth transfer function curve 44, the power management circuit 28 implements the quadratic complex zero transfer function H(s) with a real zero term represented by the third transfer function curve 42, resulting in an equivalent trace inductance L TRACE and equivalent inductance L ETIC Voltage disturbances caused by this can be effectively eliminated.

[0041] Figure 6 is a schematic diagram providing an exemplary diagram of the equalizer circuit 40 in the power management circuit 28 of Figure 4, configured according to an embodiment of the present disclosure, for implementing a quadratic complex zero transfer function H(s) having a real zero term. Elements common to Figures 4 and 6 are indicated by common element numbers and are not described again herein.

[0042] U.S. Patent Application No. 17 / 142,350 (hereinafter, "App'350"), titled "EQUALIZER FOR ENVELOPE POWER SUPPLY CIRCUITRY", describes an equivalent trace inductance L TRACE An equalizer circuit is disclosed that can effectively offset the quadratic complex zero transfer function of . The equalizer circuit 40 considered herein has an equivalent inductance L ETIC The equalizer circuit 40 differs from the equalizer circuit of App 350 in that it can further offset the real zero term. The equalizer circuit 40 further differs from the equalizer circuit of Application 350 in that it includes an equalizer tuning circuit 46, which can be controlled to change the transfer function H(s) of the equalizer circuit 40 (for example, based on the modulation bandwidth of the RF signal 38).

[0043] The equalizer circuit 40 controls the negative target voltage V TGT-M and positive target voltage V TGT-PDifferential target voltage V including TGT includes a voltage input 48 that receives. In a non-limiting example, the voltage input 48 is a negative target voltage V TGT-M for receiving a negative target voltage input 50M and a positive target voltage V TGT-P for receiving a positive target voltage input 50P. The equalizer circuit 40 also has a differential target voltage V TGT and includes a voltage output 52 that outputs an equalization target voltage V TGT-E corresponding thereto. The equalizer tuning circuit 46 is coupled between the voltage input 48 and the voltage output 52.

[0044] As will be discussed in detail below, the equalizer circuit 40 is configured to equalize the differential target voltage V TGT-E such that the equalization target voltage V having a second-order complex zero transfer function H(s) with a real zero term can offset a second-order complex pole transfer function H(s) having a real pole term. TGT

[0045] The equalizer circuit 40 includes a first operational amplifier OPA1 and a second operational amplifier OPA2. The first operational amplifier OPA1 includes a first inverting input node 54, a first non-inverting input node 56, and a first output node 58. The first inverting input node 54 is coupled to a positive target voltage input 50P via a first resistor R1 and a first capacitor C1, which are coupled in parallel with each other. A second resistor R2 is coupled between the first inverting input node 54 and the first output node 58. The first non-inverting input node 56 is coupled to ground (GND). The second operational amplifier OPA2 includes a second inverting input node 60, a second non-inverting input node 62, and a second output node 64. The second inverting input node 60 is coupled to the first output node 58 via a second capacitor C2. Furthermore, the second inverting input node 60 may be coupled to a negative target voltage input 50M via a third resistor R3, and further, to a second output node 64 via an equalizer tuning circuit 46. The second non-inverting input node 62 is coupled to ground (GND). The second output node 64 may be coupled to a voltage output 52. Although the equalizer circuit 40 is shown to include only a voltage output 52, in some embodiments the equalizer circuit 40 may also include an inverting voltage output node (not shown), resulting in an equalized target voltage V TGT-E This could be the differential equalization target voltage. Specific details regarding how the first operational amplifier OPA1 and the second operational amplifier OPA2 can implement the quadratic complex zero transfer function can be found in App'350 and are not described again herein.

[0046] In one embodiment, the equalizer tuning circuit 46 may be implemented based on a T-network configuration. Figure 7 is a schematic diagram providing an exemplary diagram of the equalizer tuning circuit 46 in the equalizer circuit 40 of Figure 6. Elements common to Figures 6 and 7 are indicated by common element numbers and will not be re-explained herein.

[0047] The equalizer tuning circuit 46 has a left resistor R connected in series between the negative target voltage input 50M and the voltage output 52. Land the right resistor R R is included. The equalizer tuning circuit 46 also includes a left resistor R L and a tunable capacitor C0 coupled between a coupling node 66 located between the right resistor R R and ground (GND). As shown, the left resistor R L , the right resistor R R , the tunable capacitor C0, and the shunt resistor R S together form a T-network. In one embodiment, the equalizer tuning circuit 46 may further include a shunt resistor R S coupled between the tunable capacitor C0 and ground (GND).

[0048] Referring back to FIG. 6, by incorporating the equalizer tuning circuit 46 as shown in FIG. 7, the equalizer circuit 40 can realize a second-order complex zero transfer function H(s) having a real zero term, as represented by the following equation (Equation 4).

Number

[0049] As shown in Equation (Equation 4), the transfer function H(s) is secondary a complex zero term

Number

Number

[0050] Furthermore, Equation (Equation 4) can change the real zero term by changing the capacitance of the tunable capacitor C0

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[0051] In one embodiment, the LUT 70 may be pre-configured to establish a correlation between various capacitance values ​​of the tunable capacitor C0 and various modulation bandwidths of the RF signal 38. In this regard, a control circuit 68, which may be a field-programmable gate array (FPGA) as an example, may set a differential target voltage V that indicates a specific modulation bandwidth of the RF signal 38. TGT (For example, a negative target voltage V) TGT-M and / or positive target voltage V TGT-P When it receives a signal, the control circuit 68 may obtain the respective capacitances from the LUT 70 corresponding to a specific modulation bandwidth and set the tunable capacitor C0 to each capacitance obtained from the LUT 70 (for example, via the control signal 72). As a result, for example, a real zero term between bursts of symbols or frames

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[0052] Instead of implementing the equalizer tuning circuit 46 based on a T-network configuration as shown in Figure 7, it is also possible to implement the equalizer tuning circuit 46 based on a π-network configuration. In this regard, Figures 8A and 8B are schematic diagrams that provide exemplary illustrations of alternative implementations of the equalizer tuning circuit 46 in Figure 7.

[0053] Figure 8A is a schematic diagram providing an exemplary figure of an equalizer tuning circuit 46A configured according to an alternative embodiment of the present disclosure to realize a transfer function H(s) including a real zero term. The equalizer tuning circuit 46A includes a shunt resistor R S Without it, it can be functionally equivalent to the equalizer tuning circuit 46 in Figure 7. As shown in Figure 8A, the equalizer tuning circuit 46A has an impedance Z a , Z b , and Z c It is configured according to a π network configuration including impedance Z. a , Z b , and Z c This can be determined based on the following formulas (Formulas 5.1 to 5.3).

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[0054] In the above equations (Equations 1 to 3), ZR L , ZR R , and ZC0 are the left resistor R in Figure 7, respectively. L , right resistor R R , and the equivalent impedance of the tunable capacitor C0. In one embodiment, impedance Z c This is the equivalent inductor L EQ (R EQ =R L *R R *Equivalent resistor R connected in series with C0) EQ (R EQ =R L +R R It can be modeled by ). The equalizer tuning circuit 46 has a real zero term [(R L +R R )+(R L -R R Define )*C0*s].

[0055] Figure 8B is a schematic diagram providing an exemplary figure of an equalizer tuning circuit 46B configured according to another alternative embodiment of the present disclosure to realize a real zero term and a real pole transfer function. The equalizer tuning circuit 46B includes a shunt resistor R S The equalizer tuning circuit 46 of Figure 7, which has the following, may be functionally equivalent. The equalizer tuning circuit 46B has a real zero term [(R L +R R )+(R L *R R +(R L +R R )*R S )*C0*s] and the real pole term [1+R S Define *C0*s].

[0056] Referring again to Figure 4, the voltage amplifier circuit 34 includes an offset capacitor C OFF A voltage amplifier 74 (represented as "VA") may be connected in series with it. The voltage amplifier 74 controls the target equalization voltage V TGT-E Based on this, the initial ET voltage V AMP It is configured to generate an offset capacitor C. OFF This is a low-frequency current I DC Charged by, initial ET voltage V AMP offset voltage V OFF This increases the ET voltage V CC (V CC =V AMP +V OFF ) may be generated. The voltage amplifier circuit 34 generates the ET voltage V CC The system may also include a feedback path 76 that can provide feedback to the voltage amplifier 74.

[0057] The power management circuit 28 may include a multilevel charge pump (MCP) 78 coupled in series with the power inductor 80. The MCP 78 operates on the battery voltage V BAT Based on this, low-frequency voltage V is at multiple levels. DC To generate (for example, differential target voltage VTGT It may be controlled based on 0V or V. For example, the MCP78 may be controlled based on 0V or V. BAT low-frequency voltage V DC It may also operate in back mode to generate 2*V. BAT low-frequency voltage V DC It may operate in boost mode to generate the low-frequency voltage V. DC Based on this, low frequency current I DC It is configured to induce [something].

[0058] The power management circuit 28 may further include a processing circuit 82 coupled between the equalizer circuit 40 and the voltage amplifier circuit 34. The processing circuit 82 controls the equalization target voltage V TGT-E Before providing it to the voltage amplifier circuit 34, the target equalization voltage V TGT-E Further signal processing (e.g., anti-aliasing) can be performed on it.

[0059] Those skilled in the art will recognize improvements and modifications to preferred embodiments of this disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the following claims.

Claims

1. It is an equalizer circuit, A voltage input that receives a differential target voltage including a negative target voltage and a positive target voltage, The output voltage of the equalization target voltage corresponding to the differential target voltage, It is equipped with an equalizer tuning circuit, The equalizer tuning circuit comprises a left resistor, a right resistor, and a tunable capacitor having an adjustable capacitance. The equalizer tuning circuit is coupled between the voltage input and the voltage output. The equalizer tuning circuit is configured to generate the equalization target voltage from the differential target voltage based on a transfer function that includes a quadratic complex zero term and a real zero term that is tunable only as a function of the tunable capacitance of the tunable capacitor. Equalizer circuit.

2. The left resistor and the right resistor are connected in series between the voltage input and the voltage output. The equalizer circuit according to claim 1, wherein the tunable capacitor is provided between ground and the connecting node between the left resistor and the right resistor.

3. The equalizer circuit according to claim 2, further comprising a shunt resistor coupled between the tunable capacitor and the ground.

4. The equalizer circuit according to claim 2, further comprising a control circuit configured to adjust the tunable capacitor based on the differential target voltage, thereby adjusting the real zero term in the transfer function.

5. The control circuit, Based on the modulation bandwidth indicated by the differential target voltage, the capacitance is obtained from the lookup table (LUT), The equalizer circuit according to claim 4, further configured to set the tunable capacitor to the capacitance obtained from the LUT.

6. The equalizer circuit according to claim 2, further comprising a first operational amplifier and a second operational amplifier coupled in series between the voltage input and the voltage output.

7. The equalizer circuit according to claim 6, wherein the voltage input comprises a positive target voltage input that receives the positive target voltage and a negative target voltage input that receives the negative target voltage.

8. The first operational amplifier, A first inverting input node coupled to the positive target voltage input, The first non-inverting input node connected to the ground, A first output node is provided, The second operational amplifier, The first output node and the second inverting input node coupled to the negative target voltage input, The non-inverting input node coupled to the ground, The equalizer circuit according to claim 7, further comprising a second output node coupled to the voltage output.

9. The aforementioned equalizer tuning circuit, The second inverting input node of the second operational amplifier and the left node coupled to the negative target voltage input, The right node is further connected to the voltage output, The equalizer circuit according to claim 8, wherein the left resistor and the right resistor are connected in series between the left node and the right node.

10. A power management circuit comprising an equalizer circuit and a voltage amplifier circuit, The equalizer circuit described above is A voltage input that receives a differential target voltage including a negative target voltage and a positive target voltage, The output voltage of the equalization target voltage corresponding to the differential target voltage, It is equipped with an equalizer tuning circuit, The equalizer tuning circuit comprises a left resistor, a right resistor, and a tunable capacitor having an adjustable capacitance. The equalizer tuning circuit is coupled between the voltage input and the voltage output. The equalizer tuning circuit is configured to generate the equalization target voltage from the differential target voltage based on a transfer function that includes a quadratic complex zero term and a real zero term that is tunable only as a function of the tunable capacitance of the tunable capacitor. The voltage amplifier circuit is configured to generate an envelope tracking (ET) voltage based on the equalization target voltage. Power management circuit.

11. The left resistor and the right resistor are connected in series between the voltage input and the voltage output, The power management circuit according to claim 10, wherein the tunable capacitor has a first end connected to a coupling node located between the left resistor and the right resistor, and a second end connected to ground.

12. The power management circuit according to claim 11, wherein the equalizer tuning circuit further comprises a shunt resistor coupled between the second end of the tunable capacitor and the ground.

13. The power management circuit according to claim 11, further comprising a control circuit configured to adjust the tunable capacitor based on the differential target voltage, thereby adjusting the real zero term in the transfer function.

14. The control circuit, Based on the modulation bandwidth indicated by the differential target voltage, the capacitance is obtained from the lookup table (LUT), The power management circuit according to claim 13, further configured to set the tunable capacitor to the capacitance obtained from the LUT.

15. The power management circuit according to claim 11, wherein the equalizer circuit further comprises a first operational amplifier and a second operational amplifier coupled in series between the voltage input and the voltage output.

16. The power management circuit according to claim 15, wherein the voltage input comprises a positive target voltage input that receives the positive target voltage and a negative target voltage input that receives the negative target voltage.

17. The first operational amplifier, A first inverting input node coupled to the positive target voltage input, The first non-inverting input node connected to the ground, A first output node is provided, The second operational amplifier, The first output node and the second inverting input node coupled to the negative target voltage input, The non-inverting input node coupled to the ground, The power management circuit according to claim 16, further comprising a second output node coupled to the voltage output.

18. The aforementioned equalizer tuning circuit, The second inverting input node of the second operational amplifier and the left node coupled to the negative target voltage input, The right node is further connected to the voltage output, The power management circuit according to claim 17, wherein the left resistor and the right resistor are connected in series between the left node and the right node.

19. The aforementioned voltage amplifier circuit A voltage amplifier configured to generate an initial ET voltage based on the aforementioned equalization target voltage, The power management circuit according to claim 10, comprising an offset capacitor configured to generate the ET voltage by increasing the initial ET voltage by an offset voltage.

20. A multilevel charge pump configured to generate low-frequency voltages at multiple voltage levels based on battery voltage, The power management circuit according to claim 10, further comprising a power inductor configured to induce a low-frequency current based on the low-frequency voltage.

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