Semiconductor equipment

Abstract

The present invention provides a semiconductor device with a novel configuration. The semiconductor device comprises a first electrode, a transistor having a back-gate, and a capacitive element having a pair of electrodes, the semiconductor device further comprising a first insulator that may have ferroelectricity between the back-gate of the transistor and a semiconductor. The first insulator overlaps the semiconductor with a second insulator therebetween. One of a source electrode and drain of the transistor is electrically connected to the first electrode. The other of the source and drain of the transistor is electrically connected to one of the pair of electrodes. The pair of electrodes are each in contact with the first insulator, and have regions overlapping each other with the first insulator therebetween. A ferroelectric is used as the first insulator.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.

[0003] Therefore, as an example of the technical field related to one aspect of the present invention, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a storage device, a signal processing device, a processor, an electronic device, a system, a driving method thereof, a manufacturing method thereof, an inspection method thereof, or a usage method thereof, etc. can be cited.

Background Art

[0004] In recent years, the development of semiconductor devices such as LSIs, CPUs, and memories (storage devices) has been progressing. These semiconductor devices are used in various electronic devices such as computers and portable information terminals. In addition, for memories, memories of various storage methods have been developed according to applications such as temporary storage during arithmetic processing execution and long-term data storage. Representative storage method memories include DRAM, SRAM, flash memory, etc.

[0005] Also, as shown in Non-Patent Document 1, research and development of memories using ferroelectrics have been actively carried out. Also, for next-generation ferroelectric memories, research on ferroelectric HfO2-based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4), and demonstration of the integration of FeRAM using ferroelectric Hf 0.5 Zr 0.5 O2 with CMOS (Non-Patent Document 5), etc., research related to hafnium oxide has also been actively carried out.

Prior Art Documents

[0006] [Non-Patent Document 1] TSBoescke,et al,“Ferroelectricity in hafnium oxide thin films”,APL99,2011 [Non-Patent Document 2] Zhen Fan,et al,“Ferroelectric HfO▲2▼-based materials for next-generation ferroelectric memories”,JOURNAL OF ADVANCED DIELECTRICS,Vol.6,No.2,2016 [Non-Patent Document 3] Jun Okuno,et al,“SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼”,VLSI 2020 [Non-Patent Document 4] Akira Toriumi, "Ferroelectricity of HfO₂ Thin Films," Journal of the Japan Society of Applied Physics, Vol. 88, No. 9, 2019. [Non-Patent Document 5] T.Francois,et al,“Demonstration of BEOL-compatible ferroelectric Hf▲0.5▼Zr▲0.5▼O▲2▼ scaled FeRAM co-integrated with 130nm CMOS for embedded NVM applications”,IEDM 2019 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] One aspect of the present invention aims to provide a novel semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a small footprint. Alternatively, one aspect of the present invention aims to provide a highly reliable semiconductor device. Alternatively, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device with a large memory capacity.

[0008] It should be noted that the problems addressed by one aspect of the present invention are not limited to those listed above. The problems listed above do not preclude the existence of other problems. These other problems are those not mentioned in this section, as described below. Those not mentioned in this section can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that the problems addressed by one aspect of the present invention do not need to solve all of the problems listed above and other problems. One aspect of the present invention solves at least one of the problems listed above and other problems. [Means for solving the problem]

[0009] One aspect of the present invention is a semiconductor device comprising a transistor having a first electrode, a first insulator, a second insulator, a gate, a back gate, and a semiconductor, and a capacitive element having a pair of electrodes, wherein the back gate has a region that overlaps with the semiconductor via the first and second insulators, one of the source or drain of the transistor is electrically connected to the first electrode, the other of the source or drain of the transistor is electrically connected to one of the pair of electrodes, each of the pair of electrodes is in contact with the first insulator and has a region that overlaps with each other via the first insulator, and the first insulator is a ferroelectric.

[0010] Another aspect of the present invention is a semiconductor device having a plurality of stacked layers and a first electrode penetrating the plurality of layers, each of the plurality of layers having a transistor having a first insulator, a second insulator, a gate, a back gate, and a semiconductor, and a capacitive element having a pair of electrodes, the back gate having a region that overlaps with the semiconductor via the first and second insulators, one of the source or drain of the transistor being electrically connected to the first electrode, the other of the source or drain of the transistor being electrically connected to one of the pair of electrodes, the pair of electrodes each having a region that is in contact with the first insulator and overlaps with each other via the first insulator, and the first insulator being a ferroelectric.

[0011] The other electrode of the pair described above and the back gate may be provided on the same insulator. Furthermore, the first insulator preferably contains hafnium, zirconium, and oxygen. Alternatively, the first insulator preferably contains aluminum, scandium, and nitrogen. The second insulator may contain silicon and oxygen.

[0012] Preferably, each of the pair of electrodes described above contains titanium and nitrogen. Preferably, the semiconductor described above is an oxide semiconductor. Preferably, the semiconductor described above contains at least one of indium and zinc, and oxygen. [Effects of the Invention]

[0013] According to one aspect of the present invention, a novel semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a small footprint can be provided. Alternatively, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a large memory capacity can be provided.

[0014] The effects of one aspect of the present invention are not limited to those listed above. The listed effects do not preclude the existence of other effects. Therefore, one aspect of the present invention may not have the effects listed above. Other effects are those described below that are not mentioned in this section. Other effects can be derived from the description in the specification or drawings, etc., by those skilled in the art, and can be appropriately extracted from these descriptions. One aspect of the present invention has at least one of the effects listed above and other effects. [Brief explanation of the drawing]

[0015] Figures 1A and 1B show examples of semiconductor device configurations. Figures 1C and 1D are equivalent circuit diagrams of the semiconductor device. Figures 2A and 2B show examples of semiconductor device configurations. Figures 3A and 3B show examples of semiconductor device configurations. Figures 4A and 4B show examples of semiconductor device configurations. Figures 5A and 5B show examples of semiconductor device configurations. Figure 6A shows an example of the configuration of a semiconductor device. Figures 6B and 6C are equivalent circuit diagrams of the semiconductor device. Figure 7A shows an example of the configuration of a semiconductor device. Figure 7B is an equivalent circuit diagram of the semiconductor device. Figure 8A shows an example of the configuration of a semiconductor device. Figure 8B is an equivalent circuit diagram of the semiconductor device. Figure 9A shows an example of the configuration of a semiconductor device. Figure 9B is an equivalent circuit diagram of the semiconductor device. Figure 10A is a diagram illustrating an example of a memory cell circuit configuration. Figure 10B is a graph showing an example of hysteresis characteristics. Figure 10C is a timing chart showing an example of a memory cell driving method. Figures 11A to 11C show examples of storage device configurations. Figure 12A shows an example of a storage device configuration. Figure 12B is a schematic diagram of the memory strings of the storage device. Figure 13A shows an example of a storage device configuration. Figure 13B is a schematic diagram of the memory strings that the storage device has. Figure 14 shows an example of a cross-sectional configuration of a storage device. Figure 15A is a diagram illustrating the classification of crystal structures. Figure 15B is a diagram illustrating the XRD spectrum of the CAAC-IGZO film. Figure 15C is a diagram illustrating the micro-electron diffraction pattern of the CAAC-IGZO film. Figures 16A and 16B are schematic diagrams of a semiconductor device according to one aspect of the present invention. Figures 17A and 17B are perspective views showing examples of electronic components. Figures 18A to 18J illustrate an example of an electronic device. Figures 19A to 19E illustrate an example of an electronic device. Figures 20A to 20C illustrate an example of an electronic device. [Modes for carrying out the invention]

[0016] The embodiments will be described below with reference to the drawings. However, it will be readily apparent to those skilled in the art that the embodiments can be implemented in many different ways, and their form and details can be modified in various ways without departing from the spirit and scope. Therefore, the present invention is not to be construed as being limited to the contents of the following embodiments.

[0017] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may also contain semiconductor devices.

[0018] In the drawings and other illustrations relating to this specification, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the size or aspect ratio is not necessarily limited to those shown. Furthermore, the drawings are schematic representations of ideal examples and are not limited to the shapes or values ​​shown in the drawings.

[0019] In the configuration of the embodiment of the invention, the same reference numerals are used in common across different drawings for parts that are the same or have similar functions, and repeated explanations may be omitted. Also, when referring to similar functions, the hatch patterns may be the same, and no reference numerals may be assigned. Furthermore, in order to make the drawings easier to understand, the description of some components may be omitted in perspective views or top views, etc.

[0020] In drawings and other materials, arrows indicating the X direction (direction along the X-axis), Y direction (direction along the Y-axis), and Z direction (direction along the Z-axis) may be included. In this specification, "X direction" refers to the direction along the X-axis, and unless otherwise specified, there is no distinction between forward and reverse directions. The same applies to "Y direction" and "Z direction." Furthermore, the X, Y, and Z directions are directions that intersect each other. More specifically, the X, Y, and Z directions are directions that are orthogonal to each other. In this specification, one of the X, Y, or Z directions may be referred to as the "first direction" or "first direction." Another may be referred to as the "second direction" or "second direction." The remaining one may be referred to as the "third direction" or "third direction."

[0021] In this specification, the ordinal numbers "1st," "2nd," and "3rd" are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "1st" in one embodiment of this specification may be referred to as "2nd" in another embodiment or in the claims. Also, for example, a constituent element referred to as "1st" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0022] In this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases described in the specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located on the upper surface of the conductor" can be rephrased as "insulator located on the lower surface of the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0023] Furthermore, the terms "above" and "below" do not limit the positional relationship of the components to being directly above or below each other and in direct contact. For example, the expression "electrode B on insulating layer A" does not require electrode B to be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0024] In this specification, terms such as "overlapping" do not limit the stacking order or other states of the constituent elements. For example, the expression "electrode B overlapping insulating layer A" does not exclude not only the state in which electrode B is formed on top of insulating layer A, but also the state in which electrode B is formed below insulating layer A, or the state in which electrode B is formed to the right (or left) of insulating layer A, etc.

[0025] In this specification, the terms "adjacent" and "proximity" are not limited to direct contact between components. For example, the expression "electrode B adjacent to insulating layer A" does not require that insulating layer A and electrode B be formed in direct contact, and does not exclude cases where other components are included between insulating layer A and electrode B.

[0026] In this specification, terms such as "film" and "layer" can be interchanged as appropriate. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer." Alternatively, depending on the circumstances, terms such as "film" and "layer" can be omitted and replaced with other terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor." Or, the term "conductor" may be changed to the term "conductive layer" or "conductive film." Alternatively, for example, the term "insulating layer" or "insulating film" may be changed to the term "insulator." Or, the term "insulator" may be changed to the term "insulating layer" or "insulating film."

[0027] Voltage refers to the potential difference between two points, while electric potential refers to the electrostatic energy (electrical potential energy) of a unit charge in an electrostatic field at a given point. However, generally, the potential difference between the electric potential at a given point and a reference electric potential (e.g., ground potential) is simply called electric potential or voltage, and electric potential and voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, electric potential may be read as voltage, and voltage as electric potential.

[0028] In this specification, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, "electrode" may be used as part of "wiring," and vice versa. Furthermore, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are formed as a single unit. Similarly, for example, "terminal" may be used as part of "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" also includes cases where multiple "electrodes," "wiring," or "terminals" are formed as a single unit. Therefore, for example, an "electrode" can be part of "wiring" or a "terminal," and for example, a "terminal" can be part of "wiring" or an "electrode." In addition, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" depending on the context.

[0029] In this specification, terms such as "wiring," "signal line," and "power line" can be interchanged with each other depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." Similarly, the term "wiring" may be changed to the term "power line," and vice versa. Terms such as "power line" may be changed to the term "wiring." Terms such as "power line" may be changed to the term "signal line," and vice versa. In addition, the term "potential" applied to the wiring may be changed to the term "signal," and vice versa.

[0030] In this specification, "parallel" means that two lines are positioned at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. "Approximately parallel" or "roughly parallel" means that two lines are positioned at an angle of -30° or more and 30° or less. "Perpendicular" means that two lines are positioned at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. "Approximately perpendicular" or "roughly perpendicular" means that two lines are positioned at an angle of 60° or more and 120° or less.

[0031] In this specification and other documents, when we refer to count values ​​and measured values ​​as "identical," "same," "equal," or "uniform" (including synonyms therefor), we mean that they include an error margin of plus or minus 20%, unless otherwise explicitly stated.

[0032] In this specification, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "A", "b", "_1", "[n]", or "[m,n]". For example, conductor 242 may be shown as conductor 242a and conductor 242b.

[0033] (Embodiment 1) A semiconductor device 10A according to one aspect of the present invention will be described. The semiconductor device 10A includes a transistor 100 and a capacitive element 110 containing a ferroelectric material. Figure 1A is a top view of the semiconductor device 10A. Figure 1B is a cross-sectional view of the area shown by the dashed line A1-A2 in Figure 1A, and is also a cross-sectional view of the transistor 100 in the channel length direction.

[0034] Figures 1C and 1D show the equivalent circuit diagram of the semiconductor device 10A. In Figure 1C, one source or drain of transistor 100 is electrically connected to wiring BL, and the other is electrically connected to one electrode of capacitive element 110. The gate of transistor 100 is electrically connected to wiring WL, and the back gate is electrically connected to wiring CL. The other electrode of capacitive element 110 is electrically connected to wiring PL.

[0035] Alternatively, as shown in Figure 1D, the back gate of transistor 100 may be electrically connected to the wiring WL. In other words, the gate and back gate of transistor 100 may be electrically connected.

[0036] Transistor 100 can be considered a type of top-gate transistor with a back gate. The potential of the back gate may be the same as the gate potential, or it may be the ground potential (GND) or any other potential. Furthermore, the threshold voltage of the transistor can be controlled by controlling the back gate potential independently of the gate potential.

[0037] The gate and back gate are positioned so as to overlap each other, with the semiconductor channel formation region in between. Since the gate and back gate are made of a conductor, they have the function of preventing electric fields generated outside the transistor from acting on the semiconductor where the channel is formed (particularly an electric field shielding function against static electricity). The electric field shielding function can be enhanced by making the back gate larger than the semiconductor channel formation region. Furthermore, the electric field shielding function can be further enhanced by making the back gate larger than the semiconductor and covering the entire semiconductor with the back gate.

[0038] Furthermore, Figure 2A is a cross-sectional view of the area indicated by the dashed line A3-A4 in Figure 1A, and is also a cross-sectional view of transistor 100 in the channel width direction. Figure 2B is a cross-sectional view of the area indicated by the dashed line A5-A6 in Figure 1A. Note that some elements have been omitted from the top view of Figure 1A for clarity.

[0039] A semiconductor device 10A according to one aspect of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 100 and a capacitive element 110 on the insulator 214, an insulator 280 on the transistor 100 and the capacitive element 110, an insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 285 on the insulator 283 and on the insulator 274.

[0040] Insulators 212, 214, 216, 280, 282, 283, 285, and 274 function as interlayer films.

[0041] Furthermore, the semiconductor device 10A has a conductor 240 that is electrically connected to the transistor 100 and functions as a plug. An insulator 241 is provided in contact with the side surface of the conductor 240 that functions as a plug. In addition, a conductor 246 that is electrically connected to the conductor 240 and functions as wiring is provided on the insulator 285 and on the conductor 240. The insulator 283 is in contact with a part of the upper surface of the insulator 214, the side surface of the insulator 216, the side surface of the insulator 222, the side surface of the insulator 275, the side surface of the insulator 280, and the side surface and upper surface of the insulator 282.

[0042] Insulator 241 is provided in contact with the inner walls of the openings of insulators 280, 282, 283, and 285, and conductor 240 is provided in contact with the side surface of insulator 241. Insulator 241 has a structure in which a first insulator is provided in contact with the inner wall of the opening, and a second insulator is provided further inside. Similarly, conductor 240 has a structure in which a first conductor is provided in contact with the side surface of insulator 241, and a second conductor is provided further inside. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 285 in the region overlapping with conductor 246 can be made to be approximately the same.

[0043] Although transistor 100 shows a configuration in which a first insulator and a second insulator of insulator 241 are stacked, the present invention is not limited thereto. For example, the insulator 241 may be provided as a single layer or as a stacked structure of three or more layers. Similarly, although transistor 100 shows a configuration in which a first conductor and a second conductor of conductor 240 are stacked, the present invention is not limited thereto. For example, the conductor 240 may be provided as a single layer or as a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers may be assigned to distinguish them according to the order of formation.

[0044] As shown in Figures 1A, 1B, 2A, and 2B, the semiconductor device 10A includes an insulator 216 on an insulator 214, a conductor 205 (conductors 205a, 205b, and 205c) arranged to be embedded in the insulator 216, a conductor 206 (conductors 206a, 206b, and 206c) arranged to be embedded in the insulator 216, an insulator 222 on the insulator 216, a conductor 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, a conductor 242a on the oxide 230b, and a conductor 2 on the conductor 242a. It includes 47a, an insulator 271a on the conductor 247a, a conductor 242b on the oxide 230b, a conductor 247b on the conductor 242b, an insulator 271b on the conductor 247b, an insulator 252 on the oxide 230b, an insulator 250 on the insulator 252, an insulator 254 on the insulator 250, a conductor 260 (conductors 260a and 260b) located on the insulator 254 and overlapping with a part of the oxide 230b, and an insulator 275 arranged on the insulator 222, insulator 224, oxide 230a, oxide 230b, conductor 242a, conductor 242b, conductor 247a, conductor 247b, insulator 271a, and insulator 275.

[0045] Conductor 205 functions as wiring CL, and conductor 206 functions as wiring PL. In addition, conductor 260 functions as wiring WL, and conductor 246 functions as wiring BL.

[0046] Here, as shown in Figures 1B and 2A, the insulator 252 is in contact with the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface and top surface of the oxide 230b, the side surface of the conductor 242 (conductors 242a and 242b), the side surface of the conductor 247 (conductors 247a and 247b), the side surface of the insulator 271 (insulators 271a and 271b), the side surface of the insulator 275, the side surface of the insulator 280, and the bottom surface of the insulator 250.

[0047] Furthermore, the upper surface of the conductor 260 is positioned so as to be roughly the same height as the top of the insulator 254, the top of the insulator 250, the top of the insulator 252, and the upper surface of the insulator 280. In addition, the insulator 282 is in contact with at least a portion of the upper surfaces of the conductor 260, the insulator 252, the insulator 250, the insulator 254, and the insulator 280.

[0048] In the following, oxides 230a and 230b may be collectively referred to as oxide 230.

[0049] Insulators 280 and 275 are provided with openings that reach oxide 230b. Insulators 252, 250, 254, and 260 are arranged within these openings. In addition, in the channel length direction of transistor 100, conductors 260, 252, 250, and 254 are provided between insulators 271a, conductors 247a, and 242a, and insulators 271b, conductors 247b, and conductors 242b. Insulator 254 has a region in contact with the side surface of conductor 260 and a region in contact with the bottom surface of conductor 260.

[0050] Preferably, the oxide 230 has an oxide 230a disposed on top of the insulator 224 and an oxide 230b disposed on top of the oxide 230a. By having oxide 230a below oxide 230b, the diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed.

[0051] In the transistor 100, the oxide 230 is shown as having a configuration in which two layers of oxide 230a and oxide 230b are stacked, but the present invention is not limited to this. For example, a single layer of oxide 230b or a stacked structure of three or more layers may be provided, or oxide 230a and oxide 230b may each have a stacked structure.

[0052] Conductor 260 functions as the first gate (also called the top gate) electrode, and conductor 205 functions as the second gate (also called the back gate) electrode. Insulators 252, 250, and 254 function as the first gate insulators, and insulators 222 and 224 function as the second gate insulators. Note that gate insulators are sometimes also called gate insulating layers or gate insulating films. Conductor 242a functions as either the source or the drain, and conductor 242b functions as either the source or the drain.

[0053] Furthermore, at least a portion of the region of oxide 230 that overlaps with conductor 260 functions as a channel-forming region. In transistor 100, conductor 260 and conductor 205 have regions that overlap each other via insulator 222, insulator 224, oxide 230, insulator 252, insulator 250, and insulator 254.

[0054] Here, Figure 3A shows an enlarged view of the vicinity of the channel-forming region in Figure 1B. When oxygen is supplied to oxide 230b, the oxygen vacancy in oxide 230b is reduced, and the carrier concentration becomes lower. On the other hand, in the region where oxide 230b is in contact with the conductor, the carrier concentration becomes higher and functions as a source region or drain region. Therefore, the region of oxide 230b between conductors 242a and 242b functions as a channel-forming region.

[0055] Therefore, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 100, and regions 230ba and 230bb that function as a source region or a drain region. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided so as to overlap with the conductor 242a, and the region 230bb is provided so as to overlap with the conductor 242b. At least a part of the region 230bc overlaps with the conductor 260.

[0056] The region 230bc that functions as a channel formation region is a high-resistance region with a low carrier concentration because it has less oxygen deficiency or a lower impurity concentration than the regions 230ba and 230bb. Therefore, the region 230bc can be said to be of the i-type (intrinsic) or substantially i-type.

[0057] Also, the regions 230ba and 230bb that function as a source region or a drain region are regions with an increased carrier concentration and a reduced resistance due to a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the regions 230ba and 230bb are n-type regions with a high carrier concentration and a low resistance as compared with the region 230bc.

[0058] Here, the carrier concentration of the region 230bc that functions as a channel formation region is preferably 18 cm -3 or less, more preferably 17 cm -3 less than, even more preferably 16 cm -3 less than, even more preferably 13 cm -3 less than, and even more preferably 12 cm -3 less than. Note that there is no particular limitation on the lower limit value of the carrier concentration of the region 230bc that functions as a channel formation region, but for example, it can be -9 cm -3 .

[0059] Furthermore, a region may be formed between region 230bc and region 230ba or region 230bb, where the carrier concentration is equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. In other words, this region functions as a junction region between region 230bc and region 230ba or region 230bb. The hydrogen concentration in this junction region may be equal to or lower than that of regions 230ba and 230bb, and equal to or higher than that of region 230bc. Also, the oxygen deficiency in this junction region may be equal to or less than that of regions 230ba and 230bb, and equal to or greater than that of region 230bc.

[0060] Although Figure 3A shows an example in which regions 230ba, 230bb, and 230bc are formed in oxide 230b, the present invention is not limited to this. For example, each of the above regions may be formed not only in oxide 230b but also in oxide 230a.

[0061] Furthermore, in oxide 230, it can be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel-forming region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen should be.

[0062] In transistor 100, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor for the oxide 230 (oxide 230a and oxide 230b) which includes the channel formation region.

[0063] Furthermore, the band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0064] As oxide 230, for example, a metal oxide such as In-M-Zn oxide having indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium) may be used. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 230.

[0065] The oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for oxide 230b. Furthermore, in the metal oxide used for oxide 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. This configuration suppresses the diffusion of impurities and oxygen from structures formed below oxide 230a to oxide 230b.

[0066] Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. With this configuration, transistor 100 can obtain a large on-current and high frequency characteristics.

[0067] Furthermore, because oxides 230a and 230b share a common element other than oxygen as their main component, the defect level density at the interface between oxides 230a and 230b can be reduced. Because the defect level density at the interface between oxides 230a and 230b can be reduced, the influence of interfacial scattering on carrier conduction is small, resulting in a high on-current.

[0068] Specifically, for oxide 230a, a metal oxide with a composition of In:M:Zn = 1:3:4 [atomic ratio] or close to it, or In:M:Zn = 1:1:0.5 [atomic ratio] or close to it may be used. For oxide 230b, a metal oxide with a composition of In:M:Zn = 1:1:1 [atomic ratio] or close to it, In:M:Zn = 1:1:1.2 [atomic ratio] or close to it, In:M:Zn = 1:1:2 [atomic ratio] or close to it, or In:M:Zn = 4:2:3 [atomic ratio] or close to it may be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use gallium as element M. Also, when a single layer of oxide 230b is provided as oxide 230, a metal oxide that can be used for oxide 230a may be applied as oxide 230b.

[0069] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0070] It is preferable that oxide 230b is crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as oxide 230b.

[0071] CAAC-OS has a highly crystalline, dense structure, and is free from impurities and defects (e.g., oxygen deficiencies (V)). OIt is a metal oxide with few impurities (such as ). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (for example, between 400°C and 600°C), the CAAC-OS can be made to have a more crystalline and dense structure. By increasing the density of the CAAC-OS in this way, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0072] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0073] Furthermore, by using a crystalline oxide such as CAAC-OS as oxide 230b, the extraction of oxygen from oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from oxide 230b is reduced, making transistor 100 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0074] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Oxygen vacancies (sometimes called H) can form and generate electron carriers. Therefore, if the region where channels are formed in an oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which channels exist and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the region where channels are formed in an oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. OIt is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0075] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter also referred to as "excess oxygen") near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the on-current of transistor 100 or a decrease in field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface will result in variations in the characteristics of the semiconductor device containing the transistor.

[0076] Therefore, in an oxide semiconductor, the region 230bc, which functions as a channel-forming region, preferably has a reduced carrier concentration and is i-type or substantially i-type, while the regions 230ba and 230bb, which function as a source region or drain region, preferably have a high carrier concentration and are n-type. In other words, oxygen vacancies in region 230bc of the oxide semiconductor, and V O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to regions 230ba and 230bb.

[0077] Therefore, in this embodiment, with the conductor 242a and conductor 242b placed on the oxide 230b, microwave treatment is performed in an oxygen-containing atmosphere to eliminate oxygen deficiencies in region 230bc, and V O The aim is to reduce H. Here, microwave processing refers to processing using a device that has a power supply that generates high-density plasma using microwaves, for example.

[0078] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high-frequency waves such as RF, and this oxygen plasma can be applied. At this time, microwaves or high-frequency waves such as RF can also be irradiated into region 230bc. Due to the action of plasma, microwaves, etc., the V of region 230bc O H is oxygen-deficient (V O By separating the oxygen (H) from the oxygen (H), the hydrogen can be removed from region 230bc, and the oxygen deficiency can be compensated for with oxygen. Therefore, the hydrogen concentration in region 230bc, the oxygen deficiency, and V O This can reduce H and lower the carrier concentration.

[0079] Furthermore, when performing microwave processing in an oxygen-containing atmosphere, the effects of microwaves, high frequencies such as RF, and oxygen plasma are shielded by conductors 242a and 242b and do not reach regions 230ba and 230bb. In addition, the effects of oxygen plasma can be reduced by insulators 271 and 280, which are provided covering oxide 230b and conductor 242. As a result, during microwave processing, V O This prevents a decrease in H and avoids excessive oxygen supply, thus preventing a drop in carrier concentration.

[0080] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the deposition of the insulating film that will become the insulator 252, or after the deposition of the insulating film that will become the insulator 250. By performing microwave treatment in an oxygen-containing atmosphere via the insulator 252 or insulator 250 in this way, oxygen can be efficiently injected into region 230bc. In addition, by arranging the insulator 252 in contact with the side surface of the conductor 242 and the surface of region 230bc, the injection of more oxygen than necessary into region 230bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 242. Furthermore, oxidation of the side surface of the conductor 242 can be suppressed when the insulating film that will become the insulator 250 is deposited.

[0081] Furthermore, the oxygen injected into region 230bc can take various forms, such as oxygen atoms, oxygen molecules, and oxygen radicals (also called O radicals, which are atoms or molecules with unpaired electrons, or ions). Note that the oxygen injected into region 230bc may be one or more of the above forms, and oxygen radicals are particularly preferred. Additionally, the film quality of insulators 252 and 250 can be improved, thereby increasing the reliability of transistor 100.

[0082] In this way, oxygen vacancies are selectively created in the oxide semiconductor region 230bc, and V O By removing H, region 230bc can be made i-type or substantially i-type. Furthermore, it is possible to suppress the supply of excess oxygen to regions 230ba and 230bb, which function as source or drain regions, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of transistor 100 and prevents variations in the electrical characteristics of transistor 100 within the substrate plane.

[0083] By adopting the above configuration, it is possible to provide a semiconductor device with minimal variation in transistor characteristics, high reliability, and excellent electrical characteristics.

[0084] Furthermore, as shown in Figure 2A, in a cross-sectional view of the transistor 100 in the channel width direction, there may be a curved surface between the side surface and the top surface of the oxide 230b. In other words, the ends of the side surface and the ends of the top surface may be curved (also referred to as "rounded").

[0085] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm to 15 nm, and more preferably 2 nm to 10 nm. By adopting such a shape, the coverage of the oxide 230b by the insulator 252, insulator 250, insulator 254, and conductor 260 can be improved.

[0086] Furthermore, as shown in Figure 2A and other figures, by providing an insulator 252 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 230, the indium contained in the oxide 230 may be unevenly distributed at and near the interface between the oxide 230 and the insulator 252. As a result, the atomic ratio near the surface of the oxide 230 becomes similar to that of indium oxide, or similar to that of In-Zn oxide. By increasing the atomic ratio of indium near the surface of the oxide 230, particularly oxide 230b, the field-effect mobility of the transistor 100 can be improved.

[0087] By configuring oxides 230a and 230b as described above, the defect level density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 100 can obtain a large on-current and high frequency characteristics.

[0088] It is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 100 into the transistor 100. Therefore, it is preferable that at least one of insulators 212, 214, 271, 275, 282, 283, and 285 is an insulating material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (i.e., the above impurities do not easily permeate it). Alternatively, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen (e.g., at least one such as oxygen atoms or oxygen molecules) (i.e., the above oxygen does not easily permeate it).

[0089] In this specification, a barrier insulating film refers to an insulating film that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0090] For insulators 212, 214, 271, 275, 282, 283, and 285, it is preferable to use insulators that have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, for insulators 212, 275, and 283, it is preferable to use silicon nitride, which has higher hydrogen barrier properties. Also, for example, for insulators 214, 271, 282, and 285, it is preferable to use aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the phenomenon of impurities such as water and hydrogen diffusing from the substrate side to the transistor 100 side via insulators 212 and 214. Alternatively, the phenomenon of impurities such as water and hydrogen diffusing from the interlayer insulating film located outside the insulator 285 towards the transistor 100 can be suppressed. Alternatively, the phenomenon of oxygen contained in the insulator 224, etc. diffusing towards the substrate side via the insulators 212 and 214 can be suppressed. Alternatively, the phenomenon of oxygen contained in the insulator 280, etc. diffusing upward from the transistor 100 via the insulator 282, etc. can be suppressed. Thus, it is preferable to have a structure in which the transistor 100 is surrounded by insulators 212, 214, 271, 275, 282, 283, and 285, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and the function of suppressing the diffusion of oxygen.

[0091] Here, it is preferable to use oxides having an amorphous structure as insulators 212, 214, 271, 275, 282, 283, and 285. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as (y is any number greater than 0). In such an amorphous metal oxide, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. By using such an amorphous metal oxide as a component of the transistor 100, or by providing it around the transistor 100, hydrogen contained in the transistor 100, or hydrogen present around the transistor 100, can be captured or fixed. It is particularly preferable to capture or fix hydrogen contained in the channel formation region of the transistor 100. By using an amorphous metal oxide as a component of the transistor 100, or by providing it around the transistor 100, it is possible to manufacture a transistor 100 and a semiconductor device that have good characteristics and are highly reliable.

[0092] Furthermore, while insulators 212, 214, 271, 275, 282, 283, and 285 are preferably amorphous, they may also have regions of polycrystalline structure. In addition, insulators 212, 214, 271, 275, 282, 283, and 285 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, a stacked structure in which a polycrystalline layer is formed on top of an amorphous layer is also possible.

[0093] The insulators 212, 214, 271, 275, 282, 283, and 285 may be deposited using, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen-containing molecules in the deposition gas, the hydrogen concentration of insulators 212, 214, 271, 275, 282, 283, and 285 can be reduced. Note that the deposition method is not limited to sputtering, and chemical vapor deposition (CVD), molecular beam epitaxy (MBE), pulsed laser deposition (PLD), atomic layer deposition (ALD), etc. may be used as appropriate.

[0094] Furthermore, it may be preferable to lower the resistivity of insulators 212, 275, and 283. For example, the resistivity of insulators 212, 275, and 283 may be approximately 1 × 10⁻⁶. 13 By setting the resistivity to Ωcm, insulators 212, 275, and 283 may be able to mitigate the charge-up of conductors 205, 242, 260, or 246 in processes using plasma or the like during semiconductor device manufacturing. The resistivity of insulators 212, 275, and 283 is preferably 1 × 10⁻⁶. 10 Ωcm or more, 1 × 10 15 The density should be less than or equal to Ωcm.

[0095] Furthermore, it is preferable that insulators 216, 274, 280, and 285 have a lower dielectric constant than insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and porous silicon oxide may be used as insulators 216, 274, 280, and 285 as appropriate.

[0096] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Here, it is preferable that the conductor 205 is embedded in an opening formed in the insulator 216. In some cases, a portion of the conductor 205 may be embedded in the insulator 214.

[0097] The conductor 205 comprises a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the height of the upper surface of the conductor 205b is approximately equal to the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216.

[0098] Here, it is preferable to use a conductive material for the conductor 205a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0099] By using a conductive material that has the function of reducing hydrogen diffusion for the conductor 205a, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224, etc. Furthermore, by using a conductive material that has the function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and the resulting decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. Therefore, the conductive material can be used as a single layer or in a laminate for the conductor 205a. For example, titanium nitride can be used for the conductor 205a.

[0100] Furthermore, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum for the conductor 205b. For example, tungsten may be used for the conductor 205b. Also, it is preferable to use the same conductive material as conductor 205a for conductor 205c. For example, titanium nitride may be used for conductor 205c.

[0101] Conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 100 can be controlled by changing the potential applied to conductor 205 independently of the potential applied to conductor 260, without linking it to the potential applied to conductor 260. In particular, by applying a negative potential to conductor 205, it is possible to increase the Vth of transistor 100 and reduce the off-current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential applied to conductor 260 is 0V compared to not applying a negative potential.

[0102] Furthermore, the electrical resistivity of the conductor 205 is designed considering the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match this electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 as thin as possible within the limits permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 is reduced. Therefore, the diffusion of these impurities into the oxide 230 can also be suppressed.

[0103] Furthermore, as shown in Figure 1A, the conductor 205 should be larger than the size of the region that does not overlap with the conductors 242a and 242b of the oxide 230. That is, it should be larger than region 230bc. In particular, as shown in Figure 2A, it is preferable that the conductor 205 extends to the region outside the ends of the oxide 230a and oxide 230b in the channel width direction. In other words, it is preferable that the conductor 205 and the conductor 260 are superimposed on the outside of the side surface in the channel width direction of the oxide 230 via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 which functions as the first gate electrode and the electric field of the conductor 205 which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0104] In this specification, an S-channel transistor refers to a transistor structure in which the channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. Furthermore, the S-channel structure disclosed in this specification is different from the Fin-type structure and the Planar-type structure. By adopting an S-channel structure, it is possible to create a transistor that has improved resistance to short-channel effects, or in other words, a transistor in which short-channel effects are less likely to occur.

[0105] By setting transistor 100 to normally off and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, transistor 100 can also be considered as having a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making transistor 100 an S-Channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between oxide 230 and the gate insulator can be made to encompass the entire bulk of oxide 230. Consequently, it becomes possible to improve the current density flowing through the transistor, which can be expected to improve the on-current of the transistor or increase the field-effect mobility of the transistor.

[0106] Furthermore, as shown in Figure 2A, the conductor 205 is extended to function as wiring. However, the configuration is not limited to this, and a conductor that functions as wiring may be provided beneath the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0107] In the transistor 100, the conductor 205 is shown as a stacked structure of conductors 205a, 205b, and 205c, but the present invention is not limited to this. For example, the conductor 205 may be a single layer or a stacked structure of two or more layers.

[0108] Insulators 222 and 224 function as gate insulators on the back gate side.

[0109] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as a hydrogen atom or a hydrogen molecule). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as an oxygen atom or an oxygen molecule). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both hydrogen and oxygen more effectively than the insulator 224.

[0110] The insulator 222 may be an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. Preferably, the insulator is an oxide containing aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). Alternatively, an oxide containing hafnium and zirconium, such as hafnium-zirconium oxide, is preferred. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 100 to the oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inside of the transistor 100 can be suppressed, and the generation of oxygen vacancies in the oxide 230 can be suppressed. In addition, the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230 can be suppressed.

[0111] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto these insulators.

[0112] Furthermore, the insulator 222 may be a single-layer or multi-layer insulator containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), and (Ba,Sr)TiO3 (BST), may also be used as the insulator 222.

[0113] Furthermore, in order to make the capacitive element 110 function as a ferroelectric capacitor, it is preferable to use a material that can possess ferroelectric properties as the insulator 222.

[0114] As a material that can possess ferroelectric properties, for example, hafnium oxide is preferred. Alternatively, zirconium oxide, HfZrO are also suitable as materials that can possess ferroelectric properties. X Metal oxides such as (where X is a real number greater than 0; hereafter simply referred to as HfZrOx) can be used. Alternatively, as a material that may possess ferroelectric properties, a material obtained by adding element J1 (where element J1 is one or more elements selected from zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide can be used.

[0115] Here, the ratio of hafnium atoms to element J1 atoms can be set as appropriate. For example, the ratio of hafnium atoms to zirconium atoms can be set to 1:1 or close to it. Alternatively, as a material that can possess ferroelectric properties, a material obtained by adding element J2 (where element J2 is one or more selected from hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide can be used. Again, the ratio of zirconium atoms to element J2 atoms can be set as appropriate; for example, the ratio of zirconium atoms to element J2 atoms can be set to 1:1 or close to it. Furthermore, as a material that can possess ferroelectric properties, lead titanate (PbTiO) can be used. X ), piezoelectric ceramics having a perovskite structure such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate may also be used.

[0116] Furthermore, aluminum scandium nitride (Al) is an example of a material that may possess ferroelectric properties. 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value in its vicinity. Hereinafter simply referred to as AlScN.)) Al-Ga-Sc nitride, Ga-Sc nitride, etc., can be used. In addition, as a material that may possess ferroelectricity, a metal nitride having element M1, element M2, and nitrogen can be used. Here, element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanides (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), actinides (15 elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectric properties even without containing element M2. Additionally, as a material that can exhibit ferroelectric properties, a material to which element M3 is added to the above metal nitride can be used. Element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate. Since the above metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element, such metal nitrides are sometimes called group 13-15 ferroelectrics or group 13 nitride ferroelectrics.

[0117] Furthermore, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure can be used as materials that may possess ferroelectric properties.

[0118] Furthermore, as a material that may possess ferroelectricity, for example, a mixture or compound consisting of multiple materials selected from the materials listed above can be used. Alternatively, as a material that may possess ferroelectricity, a laminated structure consisting of multiple materials selected from the materials listed above can be used. Incidentally, since the crystal structure or properties of the materials listed above may change not only depending on the film deposition conditions but also on various processes, in this specification, materials that exhibit ferroelectricity are not only called ferroelectrics, but are also called materials that may possess ferroelectricity or materials that are made to possess ferroelectricity.

[0119] As a material that can possess ferroelectric properties, hafnium oxide, or a material containing both hafnium oxide and zirconium oxide (typically HfZrOx), is suitable because it can exhibit ferroelectric properties even when processed into thin films of a few nanometers.

[0120] Alternatively, as a material that can possess ferroelectric properties, scandium aluminum nitride (AlScN) is suitable because it can be formed by sputtering, which can reduce the concentration of impurities in the film or form a dense film. When scandium aluminum nitride (AlScN) is used as a material that can possess ferroelectric properties, a highly reliable film can be expected.

[0121] Furthermore, the film thickness of the ferroelectric material can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically, 2 nm to 9 nm). For example, it is preferable to have a film thickness of 8 nm to 12 nm. By making the film thickness of the ferroelectric material as described above, it is possible to thin the film and exhibit ferroelectricity. By thinning the film, the ferroelectric layer can be sandwiched between a pair of electrodes of a capacitive element, and the capacitive element can be combined with a semiconductor element such as a miniaturized transistor to form a semiconductor device. In other words, it becomes easier to realize a semiconductor device with a reduced occupied area.

[0122] In this specification, materials that may possess ferroelectric properties may be referred to as ferroelectric materials. Furthermore, in this specification, a layered structure of materials that may possess ferroelectric properties may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, a device having such a ferroelectric layer, metal oxide film, or metal nitride film may be referred to as a ferroelectric device in this specification.

[0123] Furthermore, when using HfZrOx as a material capable of ferroelectricity, it is preferable to deposit the film using the ALD method, particularly the thermal ALD method. Also, when depositing a material capable of ferroelectricity using the thermal ALD method, it is preferable to use a precursor that does not contain hydrocarbons (also known as Hydrocarbon, HC). If the material capable of ferroelectricity contains either hydrogen or carbon, or both, it may inhibit the crystallization of the material capable of ferroelectricity. Therefore, as described above, it is preferable to reduce the concentration of either hydrogen or carbon, or both, in the material capable of ferroelectricity by using a hydrocarbon-free precursor. For example, chlorine-based materials can be used as hydrocarbon-free precursors. When using a material containing hafnium oxide and zirconium oxide (HfZrOx) as a material capable of ferroelectricity, HfCl4 and / or ZrCl4 may be used as the precursor. Alternatively, dopants (typically silicon, carbon, etc.) to control the polarization state may be added to the material capable of ferroelectricity. In this case, one method for adding carbon as a dopant may be to use a formation method that uses a material containing hydrocarbons as a precursor.

[0124] Furthermore, when forming a film using a material capable of ferroelectricity, a film with high purity and intrinsic ferroelectricity can be formed by thoroughly eliminating impurities in the film, specifically hydrogen, hydrocarbons, and carbon. Moreover, the manufacturing process compatibility between a film with high purity and intrinsic ferroelectricity and the high purity and intrinsic oxide semiconductor shown in the embodiments described later is extremely high. Therefore, a highly productive method for manufacturing semiconductor devices can be provided.

[0125] Furthermore, it is preferable that the impurity concentration of the material capable of ferroelectricity be low. In particular, lower concentrations of hydrogen (H) and carbon (C) are preferable. Specifically, the hydrogen concentration of the material capable of ferroelectricity is 5 × 10⁻¹⁰. 20 atoms / cm 3 The following is preferable: 1 × 10 20 atoms / cm 3 The following is more preferable. Also, the carbon concentration of the material that may have ferroelectric properties is 5 × 10 19 atoms / cm 3 The following is preferable: 1 × 10 19 atoms / cm 3 The following are preferable.

[0126] Furthermore, when using HfZrOx as a material that can possess ferroelectric properties, it is preferable to alternately deposit hafnium oxide and zirconium oxide in a 1:1 composition using the ALD method.

[0127] Furthermore, when depositing a ferroelectric material using the ALD method, H2O or O3 can be used as the oxidizing agent. However, the oxidizing agent for the ALD method is not limited to these. For example, the oxidizing agent for the ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0128] In particular, materials that can exhibit ferroelectricity are preferred if they have an orthorhombic crystal structure, as this is desirable because it allows ferroelectricity to manifest. However, other crystal structures may also be included. For example, in addition to the orthorhombic crystal structure, one or more crystal structures selected from cubic, tetragonal, orthorhombic, and monoclinic systems may be included. Furthermore, a layer to enhance crystallinity may be formed before forming the ferroelectric material. For example, when using HfZrOx as the ferroelectric material, the layer to enhance crystallinity can be a metal oxide such as hafnium oxide or zirconium oxide, or hafnium or zirconium itself.

[0129] Furthermore, when using AlScN as a material that can possess ferroelectric properties, it is preferable that it has a hexagonal crystal structure. In addition to the hexagonal crystal structure, other crystal structures may also be included. As a layer to enhance crystallinity, it is preferable to use a metallic nitride such as aluminum nitride or scandium nitride, or aluminum or scandium.

[0130] Furthermore, the layer that enhances crystallinity may be formed after the formation of a material capable of ferroelectricity. Alternatively, the material capable of ferroelectricity may be a composite structure having both an amorphous structure and a crystalline structure.

[0131] The insulator 224 in contact with the oxide 230 can be, for example, silicon oxide, silicon oxide nitride, or the like, as appropriate.

[0132] Furthermore, during the manufacturing process of the transistor 100, it is preferable to perform a heat treatment with the surface of the oxide 230 exposed. This heat treatment may be performed, for example, at a temperature of 100°C to 600°C, more preferably 350°C to 550°C. The heat treatment should be performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, it is preferable to perform the heat treatment in an oxygen atmosphere. This allows oxygen to be supplied to the oxide 230, thereby reducing oxygen deficiency. Alternatively, the heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replenish the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then continuously in an atmosphere of nitrogen gas or an inert gas.

[0133] Furthermore, by performing an oxygenation treatment on oxide 230, oxygen deficiencies in oxide 230 can be repaired by the supplied oxygen. In addition, the supplied oxygen reacts with the hydrogen remaining in oxide 230, removing the hydrogen as H2O (dehydration). As a result, the hydrogen remaining in oxide 230 recombines with the oxygen deficiencies and V O This can suppress the formation of H.

[0134] Furthermore, the insulators 222 and 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, but may be made of different materials. Also, the insulator 224 may be formed in an island shape by being superimposed with the oxide 230a. In this case, the insulator 275 will be in contact with the side surface of the insulator 224 and the upper surface of the insulator 222.

[0135] Conductors 242a and 242b are provided in contact with the upper surface of oxide 230b. Conductors 242a and 242b function as the source electrode or drain electrode of transistor 100, respectively.

[0136] As the conductor 242 (conductor 242a and conductor 242b), it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0137] Furthermore, hydrogen contained in oxide 230b, etc., may diffuse into conductor 242a or conductor 242b. In particular, by using tantalum-containing nitrides for conductor 242a and conductor 242b, hydrogen contained in oxide 230b, etc., is more likely to diffuse into conductor 242a or conductor 242b, and the diffused hydrogen may combine with nitrogen present in conductor 242a or conductor 242b. In other words, hydrogen contained in oxide 230b, etc., may be absorbed by conductor 242a or conductor 242b.

[0138] Furthermore, it is preferable that no curved surface is formed between the side surface of the conductor 242 and the top surface of the conductor 242. By using a conductor 242 without such a curved surface, the cross-sectional area of ​​the conductor 242 in the channel width direction can be increased, as shown in Figure 2B. This increases the conductivity of the conductor 242 and increases the on-current of the transistor 100.

[0139] Furthermore, when heat treatment is performed with the conductor 242a (conductor 242b) and the oxide 230b in contact, the sheet resistance of the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) may decrease. Also, the carrier concentration may increase. Therefore, the oxide 230b in the region overlapping with the conductor 242a (conductor 242b) can be made to have a self-aligned low resistance.

[0140] The conductor 242 is preferably formed using a conductive film having compressive stress. This makes it possible to form a strain that expands in the tensile direction (hereinafter sometimes referred to as tensile strain) in regions 230ba and 230bb. The tensile strain causes V O By stably forming H, regions 230ba and 230bb can be made into stable n-type regions. The compressive stress of the conductor 242 is a stress that attempts to relax the compressive shape of the conductor 242, and is a stress with a vector direction from the center to the ends of the conductor 242.

[0141] The magnitude of the compressive stress in the conductor 242 should be, for example, 500 MPa or more, preferably 1000 MPa or more, more preferably 1500 MPa or more, and even more preferably 2000 MPa or more. Alternatively, the magnitude of the stress in the conductor 242 may be determined by preparing a sample in which the conductive film used for the conductor 242 is deposited on a substrate, and measuring the stress of the sample.

[0142] The compressive stress present in the conductor 242 causes strain to form in regions 230ba and 230bb, respectively. This strain is a strain (tensile strain) that has been expanded in the tensile direction due to the compressive stress present in the conductor 242. If regions 230ba and 230bb have a CAAC structure, this strain corresponds to elongation in the direction perpendicular to the c-axis of the CAAC structure. As will be described later, when the CAAC structure is elongated in the direction perpendicular to the c-axis of the CAAC structure, this strain causes oxygen deficiency and V O H atoms are easily formed, and these readily adopt stable structures. As a result, regions 230ba and 230bb become stable n-type regions with high carrier concentrations.

[0143] While the strain formed in oxide 230b has been described above, the present invention is not limited thereto. Similar strains may be formed in oxide 230a.

[0144] In this embodiment, a configuration in which the conductor 242 is a single layer is shown, but the present invention is not limited thereto, and a laminated structure of two or more layers may also be used.

[0145] The conductor 247 has a region that overlaps with the conductor 242 and a region that extends beyond the edge of the oxide 230. Furthermore, as shown in Figures 1A, 1B, and 2B, covering the top and sides of the conductor 242, as well as the sides of the oxide 230, with the conductor 247 can reduce the resistance of the source and drain regions of the transistor.

[0146] As the conductor 247, a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements, can be used. In addition, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may be used. Furthermore, conductive materials containing oxygen, such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-added indium tin oxide, may also be used.

[0147] Furthermore, the region where the conductor 247 and the conductor 206 overlap each other via the insulator 222 functions as a capacitive element 110. In addition, it is preferable not to provide an insulator 224 on the insulator 222 in this region. When the conductor 247 and the conductor 206 come into contact with the insulator 222, which is a ferroelectric material, polarization of the insulator 222 is easily generated. Therefore, it is preferable to use a material that easily generates polarization of the insulator 222 as the conductor 247. For example, it is preferable to use titanium nitride as the conductor 247. Similarly, it is preferable to use a material that easily generates polarization of the insulator 222 as the conductor 206c. For example, it is preferable to use titanium nitride as the conductor 206c.

[0148] The conductor 206 can be formed simultaneously in the same process as the conductor 205. Therefore, the capacitive element 110 can be formed without increasing the number of layers and processes of the semiconductor device 10A.

[0149] The insulator 271a is provided in contact with the upper surface of the conductor 247a, and the insulator 271b is provided in contact with the upper surface of the conductor 247b. It is preferable that the insulator 271 functions as at least a barrier insulating film against oxygen. Therefore, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen. For example, it is preferable that the insulator 271 has a function to suppress the diffusion of oxygen more than the insulator 280. As the insulator 271, for example, an insulator such as aluminum oxide or magnesium oxide may be used.

[0150] The insulator 275 is provided so as to cover the insulator 224, oxide 230a, oxide 230b, conductor 242, conductor 247, and insulator 271. Preferably, the insulator 275 has the function of capturing and fixing hydrogen. In that case, it is preferable that the insulator 275 includes silicon nitride or an insulator such as an amorphous metal oxide, for example, aluminum oxide or magnesium oxide. Alternatively, for example, a laminated film of aluminum oxide and silicon nitride on the aluminum oxide may be used as the insulator 275.

[0151] By providing the insulators 271 and 275 described above, the conductor 242 can be surrounded by an insulator that has barrier properties against oxygen. In other words, the phenomenon of oxygen contained in insulators 224 and 280 diffusing into the conductor 242 can be prevented. This suppresses the phenomenon in which the conductor 242 is directly oxidized by the oxygen contained in insulators 224 and 280, increasing its resistivity and reducing the on-current.

[0152] The insulator 252 functions as part of the gate insulator. Preferably, the insulator 252 is a barrier insulating film against oxygen. The insulator 252 can be any insulator that can be used for the insulator 282 described above. The insulator 252 may be an insulator containing an oxide of either or both aluminum and hafnium. Examples of such insulators include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 252. In this case, the insulator 252 is an insulator containing at least oxygen and aluminum.

[0153] As shown in Figure 2A, the insulator 252 is provided in contact with the top and side surfaces of oxide 230b, the side surface of oxide 230a, the side surface of insulator 224, and the top surface of insulator 222. In other words, the regions of oxide 230a, oxide 230b, and insulator 224 that overlap with the conductor 260 are covered by the insulator 252 in the cross-section in the channel width direction. This allows the insulator 252, which has an oxygen barrier property, to block the phenomenon of oxygen desorption in oxide 230a and oxide 230b when heat treatment is performed. Therefore, the formation of oxygen vacancies in oxide 230a and oxide 230b can be reduced. As a result, oxygen vacancies and V formed in region 230bc can be reduced. O H can be reduced. Therefore, the electrical characteristics of transistor 100 can be improved, and its reliability can be enhanced.

[0154] Conversely, even if an excess amount of oxygen is present in the insulator 280 and insulator 250, it is possible to suppress the excessive supply of such oxygen to oxides 230a and 230b. Therefore, it is possible to suppress a decrease in the on-current of transistor 100 or a decrease in the field-effect mobility caused by excessive oxidation of regions 230ba and 230bb via region 230bc.

[0155] Furthermore, as shown in Figure 1B, the insulator 252 is provided in contact with the sides of the conductors 242, 247, 271, 275, and 280. Therefore, the oxidation of the side surface of the conductor 242 and the formation of an oxide film on that side surface can be suppressed. This makes it possible to suppress a decrease in the on-current of the transistor 100 or a decrease in the field-effect mobility.

[0156] Furthermore, the insulator 252, along with the insulator 254, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 100, it is preferable that the film thickness of the insulator 252 be thin. The film thickness of the insulator 252 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and less than 3.0 nm. In this case, it is sufficient that the insulator 252 has a region with the above-mentioned film thickness in at least a part of it. Furthermore, it is preferable that the film thickness of the insulator 252 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 252 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0157] To deposit the insulator 252 with a thin film thickness as described above, it is preferable to use the ALD method. ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. The PEALD method is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0158] The ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Therefore, the insulator 252 can be deposited with good coverage on the sides of openings formed in the insulator 280, etc., with the thin film thickness described above.

[0159] The insulator 250 functions as part of the gate insulator. It is preferable that the insulator 250 is placed in contact with the upper surface of the insulator 252. The insulator 250 can be silicon oxide, silicon oxynitride, silicon nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or porous silicon oxide. Silicon oxide and silicon oxynitride are particularly preferred because they are stable with respect to heat. In this case, the insulator 250 will be an insulator having at least oxygen and silicon.

[0160] Similar to the insulator 224, it is preferable that the insulator 250 has a reduced concentration of impurities such as water and hydrogen. The film thickness of the insulator 250 is preferably 1 nm to 20 nm, and more preferably 0.5 nm to 15.0 nm. In this case, it is sufficient that the insulator 250 has a region with the above-mentioned film thickness in at least a portion of it.

[0161] In this embodiment, a configuration in which the insulator 250 is a single layer is shown, but the present invention is not limited thereto, and a laminated structure of two or more layers may be used. For example, as shown in Figure 3B, the insulator 250 may be a laminated structure of two layers, consisting of an insulator 250a and an insulator 250b on top of the insulator 250a.

[0162] As shown in Figure 3B, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that is easily permeable to oxygen, and the upper insulator 250b is formed using an insulator that has the function of suppressing the diffusion of oxygen. With this configuration, the phenomenon of oxygen contained in the insulator 250a diffusing to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 by oxygen contained in the insulator 250a can be suppressed. For example, the insulator 250a may be made using a material that can be used for the insulator 250 as described above, and the insulator 250b may be an insulator containing an oxide of aluminum and / or hafnium. As such an insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), etc. can be used. In this embodiment, hafnium oxide is used as the insulator 250b. In this case, the insulator 250b is an insulator having at least oxygen and hafnium. The film thickness of the insulator 250b is 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 250b has at least a portion of the above-mentioned film thickness region.

[0163] Furthermore, when silicon oxide or silicon oxynitride is used for insulator 250a, insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. By making the gate insulator a laminated structure of insulator 250a and insulator 250b, a laminated structure that is stable against heat and has a high dielectric constant can be made. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. In addition, it is possible to make the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator thinner. Thus, the dielectric breakdown voltage of insulator 250 can be increased.

[0164] The insulator 254 functions as part of the gate insulator. Preferably, a barrier insulating film against hydrogen is used as the insulator 254. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the insulator 250 and oxide 230b. The insulator 254 can be any insulator that can be used for the insulator 283 described above. For example, silicon nitride deposited by the PEALD method can be used as the insulator 254. In this case, the insulator 254 will be an insulator containing at least nitrogen and silicon.

[0165] Furthermore, the insulator 254 may also have barrier properties against oxygen. This can suppress the phenomenon of oxygen contained in the insulator 250 diffusing into the conductor 260.

[0166] Furthermore, the insulator 254, along with the insulator 252, the insulator 250, and the conductor 260, must be provided in an opening formed in the insulator 280 or the like. In order to miniaturize the transistor 100, it is preferable that the film thickness of the insulator 254 be thin. The film thickness of the insulator 254 is 0.1 nm or more and 5.0 nm or less, preferably 0.5 nm or more and 3.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less. In this case, it is sufficient that the insulator 254 has a region with the above-mentioned film thickness in at least a part of it. Also, it is preferable that the film thickness of the insulator 254 is thinner than the film thickness of the insulator 250. In this case, it is sufficient that the insulator 254 has a region with a thinner film thickness than the insulator 250 in at least a part of it.

[0167] Furthermore, as shown in Figure 3B, when the insulator 250 has a two-layer laminated structure, by using an insulator 250b that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as hafnium oxide, the insulator 250b can also perform the function of the insulator 254. In such a case, by omitting the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0168] The conductor 260 functions as the first gate electrode of the transistor 100. Preferably, the conductor 260 has a conductor 260a and a conductor 260b disposed on top of the conductor 260a. For example, it is preferable that the conductor 260a is arranged to enclose the bottom and sides of the conductor 260b. Also, as shown in Figures 1B and 2A, the top surface of the conductor 260 is roughly the same as the top surface of the insulator 250. In Figures 1B and 2A, the conductor 260 is shown as a two-layer structure of conductor 260a and conductor 260b, but it may also be a single-layer structure or a stacked structure of three or more layers.

[0169] It is preferable to use a conductive material for the conductor 260a that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms or oxygen molecules).

[0170] Furthermore, because the conductor 260a has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250, which would otherwise reduce its conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc.

[0171] Furthermore, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also be in a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0172] Furthermore, in transistor 100, the conductor 260 is formed self-aligningly to fill the openings formed in the insulator 280 and the like. By forming the conductor 260 in this way, the conductor 260 can be reliably positioned in the region between the conductors 242a and 242b without the need for alignment.

[0173] Furthermore, as shown in Figure 2A, in the channel width direction of transistor 100, with reference to the bottom surface of insulator 222, the height of the bottom surface of the conductor 260 in the region where conductor 260 and oxide 230b do not overlap is preferably lower than the height of the bottom surface of oxide 230b. By configuring conductor 260, which functions as a gate electrode, to cover the side and top surfaces of the channel formation region of oxide 230b via insulator 250 or the like, the electric field of conductor 260 can be easily applied to the entire channel formation region of oxide 230b. Therefore, the on-current of transistor 100 can be increased and the frequency characteristics can be improved. With reference to the bottom surface of insulator 222, the difference between the height of the bottom surface of conductor 260 in the region where oxide 230a and oxide 230b and conductor 260 do not overlap and the height of the bottom surface of oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0174] The insulator 280 is provided on the insulator 275, and openings are formed in the regions where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may also be flattened.

[0175] The insulator 280, which functions as an interlayer film, preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance occurring between the wiring can be reduced. The insulator 280 is preferably made of the same material as the insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0176] Preferably, the insulator 280 has reduced concentrations of impurities such as water and hydrogen. For example, the insulator 280 may be made of silicon oxides such as silicon oxide or silicon oxynitride.

[0177] The insulator 282 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above, and preferably has the function of capturing impurities such as hydrogen. Furthermore, the insulator 282 preferably functions as a barrier insulating film that suppresses the permeation of oxygen. As the insulator 282, an amorphous metal oxide, such as aluminum oxide, may be used. In this case, the insulator 282 will be an insulator having at least oxygen and aluminum. By providing an insulator 282 that is in contact with the insulator 280 in the region sandwiched between the insulator 212 and the insulator 283 and has the function of capturing impurities such as hydrogen, impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in that region can be kept constant. In particular, using aluminum oxide with an amorphous structure as the insulator 282 is preferable because it may be possible to capture or fix hydrogen more effectively. This makes it possible to manufacture a transistor 100 and a semiconductor device 10A with good characteristics and high reliability.

[0178] It is preferable to deposit aluminum oxide as the insulator 282 by sputtering, and more preferably by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using pulsed DC sputtering, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 282 can be controlled by the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the layer below the insulator 282, and the amount of oxygen will be more easily saturated even if the film thickness of the insulator 282 is thin. Also, the larger the RF power, the more oxygen is injected into the layer below the insulator 282.

[0179] For example, RF power could be 0 W / cm². 2 The above is 1.86 W / cm². 2 The following applies: In other words, the amount of oxygen injected can be varied depending on the RF power used during the formation of the insulator 282, so as to suit the characteristics of the transistor. Therefore, an amount of oxygen suitable for improving the reliability of the transistor can be injected.

[0180] Furthermore, an RF frequency of 10 MHz or higher is preferable. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be inflicted on the substrate.

[0181] In this embodiment, a configuration in which the insulator 282 is a single layer is shown, but the present invention is not limited thereto, and a laminated structure of two or more layers may also be used.

[0182] The insulator 283 functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen into the insulator 280 from above. The insulator 283 is placed on top of the insulator 282. Preferably, the insulator 283 is a silicon-containing nitride such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by sputtering may be used as the insulator 283. By depositing the insulator 283 by sputtering, a high-density silicon nitride film can be formed. Alternatively, as the insulator 283, silicon nitride deposited by PEALD or CVD may be further laminated on top of the silicon nitride deposited by sputtering.

[0183] The conductor 240 is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 240 may also have a laminated structure.

[0184] Furthermore, when the conductor 240 has a laminated structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged in the vicinity of the insulators 285, 283, 282, 280, 275, and 271. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. The conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a laminate. In addition, it is possible to suppress the phenomenon in which impurities such as water and hydrogen contained in the layer above the insulator 283 mix into the oxide 230 through the conductor 240.

[0185] As the insulator 241, any barrier insulating film that can be used for insulator 275, etc., may be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, or silicon oxide nitride may be used. Since the insulator 241 is provided in contact with insulators 283, 282, and 271, the phenomenon of impurities such as water and hydrogen contained in insulators 280, etc., mixing into the oxide 230 through the conductor 240 can be suppressed. In particular, silicon nitride is preferred because it has high blocking properties for hydrogen. In addition, it can prevent oxygen contained in insulator 280 from being absorbed by the conductor 240.

[0186] When the insulator 241 is made into a laminated structure as shown in Figure 1B, it is preferable that the first insulator in contact with the inner wall of the opening such as the insulator 280 and the second insulator inside it use a combination of an oxygen barrier insulating film and a hydrogen barrier insulating film.

[0187] For example, aluminum oxide deposited by the ALD method can be used as the first insulator, and silicon nitride deposited by the PEALD method can be used as the second insulator. This configuration suppresses oxidation of the conductor 240 and further reduces the phenomenon of hydrogen contamination in the conductor 240.

[0188] Furthermore, a conductor 246 that functions as wiring may be placed in contact with the upper surface of the conductor 240. It is preferable that the conductor 246 be made of a conductive material mainly composed of tungsten, copper, or aluminum. The conductor may also be in a laminated structure, for example, a laminate of titanium or titanium nitride and the conductive material. The conductor may also be formed to be embedded in an opening provided in the insulator.

[0189] <Example 1> Figures 4A and 4B show a modified semiconductor device 10B, which is a modified version of semiconductor device 10A. Figure 4A is a top view of semiconductor device 10B. Figure 4B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 4A.

[0190] The semiconductor device 10B has a configuration similar to that of the semiconductor device 10A, but without the conductor 242. By omitting the conductor 242, the manufacturing process for the semiconductor device 10B is reduced, thereby increasing productivity.

[0191] <Modification 2> Figures 5A and 5B show a modified semiconductor device 10C, which is a modified version of semiconductor device 10B. Figure 5A is a top view of semiconductor device 10C. Figure 5B is a cross-sectional view of the area indicated by the dashed line A1-A2 in Figure 5A.

[0192] The semiconductor device 10C shown in Figure 5 has a configuration that is the same as semiconductor device 10B but without the insulator 224. By not providing the insulator 224, the manufacturing process of semiconductor device 10C is shortened, and the productivity of semiconductor device 10C can be increased. When the insulator 224 is not provided, it is preferable to form an insulator containing excess oxygen as the insulator 222.

[0193] <Variation 3> Two semiconductor devices 10A may share one wiring BL. Figure 6A is a cross-sectional view showing an example configuration in which two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) are connected to one wiring BL. Figures 6B and 6C are equivalent circuit diagrams of the cross-sectional configuration example shown in Figure 6A.

[0194] Semiconductor device 10Aa is electrically connected to wiring WLa, wiring PLa, wiring CLa, and wiring BL. Semiconductor device 10Ab is electrically connected to wiring WLb, wiring PLb, wiring CLb, and wiring BL. By configuring the two semiconductor devices 10A to be electrically connected to one wiring BL, the occupied area of ​​the semiconductor devices, including semiconductor devices 10A, can be reduced.

[0195] The conductor 260 of the semiconductor device 10Aa is electrically connected to the wiring WLa. Furthermore, the conductor 260 of the semiconductor device 10Aa may function as part of the wiring WLa. The conductor 206 of the semiconductor device 10Aa is electrically connected to the wiring PLa. Furthermore, the conductor 206 of the semiconductor device 10Aa may function as part of the wiring PLa. The conductor 205 of the semiconductor device 10Aa is electrically connected to the wiring CLa. Furthermore, the conductor 205 of the semiconductor device 10Aa may function as part of the wiring CLa.

[0196] The conductor 260 of the semiconductor device 10Ab is electrically connected to the wiring WLb. Furthermore, the conductor 260 of the semiconductor device 10Ab may function as part of the wiring WLb. The conductor 206 of the semiconductor device 10Ab is electrically connected to the wiring PLb. Furthermore, the conductor 206 of the semiconductor device 10Ab may function as part of the wiring PLb. The conductor 205 of the semiconductor device 10Ab is electrically connected to the wiring CLb. Furthermore, the conductor 205 of the semiconductor device 10Ab may function as part of the wiring CLb.

[0197] Furthermore, if the same potential is supplied to wiring PLa and wiring PLb, they may be electrically connected. Similarly, if the same potential is supplied to wiring CLa and wiring CLb, they may be electrically connected.

[0198] Alternatively, as shown in Figure 6C, the gate and back gate of transistor 100 may be electrically connected. In this case, the formation of wiring CL (wiring CLa and wiring CLb) becomes unnecessary, which is effective in improving the productivity and reducing the occupied area of ​​the semiconductor device.

[0199] <Modification 4> By stacking multiple semiconductor devices 10A, the area occupied by each semiconductor device 10A can be reduced. For example, by stacking two semiconductor devices 10A, the area occupied by each semiconductor device 10A is halved.

[0200] Figure 7A is a cross-sectional view showing an example of a configuration in which three semiconductor devices 10A (semiconductor device 10A[1], semiconductor device 10A[2], and semiconductor device 10A[3]) are stacked. Figure 7B is an equivalent circuit diagram of the cross-sectional configuration example shown in Figure 7A. In Figures 7A and 7B, the semiconductor device 10A formed in the first layer is shown as semiconductor device 10A[1], the semiconductor device 10A formed in the second layer is shown as semiconductor device 10A[2], and the semiconductor device 10A formed in the third layer is shown as semiconductor device 10A[3]. In this embodiment and others, the first layer may be called the "first layer," the second layer the "second layer," and the third layer the "third layer."

[0201] Semiconductor device 10A[1] is electrically connected to wiring WL[1], wiring PL[1], wiring CL[1], and wiring BL. Semiconductor device 10A[2] is electrically connected to wiring WL[2], wiring PL[2], wiring CL[2], and wiring BL. Semiconductor device 10A[3] is electrically connected to wiring WL[3], wiring PL[3], wiring CL[3], and wiring BL.

[0202] The conductor 260 of the semiconductor device 10A[1] is electrically connected to the wiring WL[1]. The conductor 260 of the semiconductor device 10A[1] may also function as part of the wiring WL[1]. The conductor 206 of the semiconductor device 10A[1] is electrically connected to the wiring PL[1]. The conductor 206 of the semiconductor device 10A[1] may also function as part of the wiring PL[1]. The conductor 205 of the semiconductor device 10A[1] is electrically connected to the wiring CL[1]. The conductor 205 of the semiconductor device 10A[1] may also function as part of the wiring CL[1].

[0203] The conductor 260 of the semiconductor device 10A[2] is electrically connected to the wiring WL[2]. Furthermore, the conductor 260 of the semiconductor device 10A[2] may function as part of the wiring WL[2]. The conductor 206 of the semiconductor device 10A[2] is electrically connected to the wiring PL[2]. Furthermore, the conductor 206 of the semiconductor device 10A[2] may function as part of the wiring PL[2]. The conductor 205 of the semiconductor device 10A[2] is electrically connected to the wiring CL[2]. Furthermore, the conductor 205 of the semiconductor device 10A[2] may function as part of the wiring CL[2].

[0204] The conductor 260 of the semiconductor device 10A[3] is electrically connected to the wiring WL[3]. The conductor 260 of the semiconductor device 10A[3] may also function as part of the wiring WL[3]. The conductor 206 of the semiconductor device 10A[3] is electrically connected to the wiring PL[3]. The conductor 206 of the semiconductor device 10A[3] may also function as part of the wiring PL[3]. The conductor 205 of the semiconductor device 10A[3] is electrically connected to the wiring CL[3]. The conductor 205 of the semiconductor device 10A[3] may also function as part of the wiring CL[3].

[0205] In Figure 7A, semiconductor device 10A[2] is placed on top of semiconductor device 10A[1], and semiconductor device 10A[3] is placed on top of semiconductor device 10A[2]. Furthermore, each of the semiconductor devices 10A[1] to 10A[3] shown in Figure 7A has a conductor 207 in the same layer as conductors 205 and 206. Conductor 207 can be formed simultaneously in the same manufacturing process as conductors 205 and 206.

[0206] Each of the semiconductor devices 10A[1] to 10A[3] shown in Figure 7A has a conductor 240 that functions as a plug. Note that no insulator 241 is provided on the side surface of the conductor 240 that functions as a plug.

[0207] The conductor 240 in each of the semiconductor devices 10A[1] to 10A[3] shown in Figure 7A penetrates the insulators 285, 283, 282, 280, 275, 271a, conductor 247a, conductor 242a, oxide 230, insulator 224, 222, insulator 214, and insulator 212. Therefore, the conductor 240 is in contact with the insulators 285, 283, 282, 280, 275, 271a, conductor 247a, conductor 242a, oxide 230, insulator 224, and insulator 222. In addition, semiconductor devices 10A[1] and 10A[2] are in contact with the insulators 214 and 212.

[0208] By not providing the insulator 241, the conductor 240 is electrically connected to the conductors 247a and 242a.

[0209] Furthermore, the conductors 207 of each of the semiconductor devices 10A[1] to 10A[3] shown in Figure 7A are electrically connected via the conductors 240 of each of the semiconductor devices 10A[1] to 10A[3]. Specifically, in Figure 7A, the conductor 207 of semiconductor device 10A[1] is electrically connected to the conductor 207 of semiconductor device 10A[2] via the conductor 240 of semiconductor device 10A[1]. Also, the conductor 207 of semiconductor device 10A[2] is electrically connected to the conductor 207 of semiconductor device 10A[3] via the conductor 240 of semiconductor device 10A[2]. In addition, the conductor 207 of semiconductor device 10A[3] is electrically connected to the conductor 246 that functions as wiring BL via the conductor 240 of semiconductor device 10A[3].

[0210] Thus, the transistors in each of the semiconductor devices 10A[1] to 10A[3] shown in Figure 7A are electrically connected to the conductor 246, which functions as a wiring BL, via the conductor 240, which functions as a through electrode. Therefore, the conductor 240 also functions as a wiring BL, or functions as part of the wiring BL.

[0211] One of the sources or drains of transistor 100 in semiconductor device 10A[1], one of the sources or drains of transistor 100 in semiconductor device 10A[2], and one of the sources or drains of transistor 100 in semiconductor device 10A[3] are electrically connected to wiring BL (see Figure 7B).

[0212] By electrically connecting multiple semiconductor devices 10A to a single wiring BL, that is, by sharing a single wiring BL among multiple semiconductor devices 10A, the occupied area of ​​the semiconductor devices including the semiconductor devices 10A can be reduced. Furthermore, by stacking multiple semiconductor devices 10A, the occupied area of ​​the semiconductor devices 10A can be reduced. Therefore, the occupied area of ​​the semiconductor devices including the semiconductor devices 10A can be further reduced.

[0213] <Modification 5> By combining Modification 3 and Modification 4, the area occupied per semiconductor device 10A can be further reduced.

[0214] Figure 8A is a cross-sectional view showing an example of a stacked configuration of multiple semiconductor devices 10A. Figure 8B is an equivalent circuit diagram of the configuration example shown in Figure 8A. In Figures 8A and 8B, two semiconductor devices 10A (semiconductor device 10Aa and semiconductor device 10Ab) formed on the same plane are considered as a pair, and an example is shown in which one pair of semiconductor devices 10A is stacked in three layers (also called "stages").

[0215] In Figures 8A and 8B, semiconductor device 10Aa included in the first layer is shown as semiconductor device 10Aa[1], and semiconductor device 10Ab is shown as semiconductor device 10Ab[1]. Similarly, semiconductor device 10Aa included in the second layer is shown as semiconductor device 10Aa[2], and semiconductor device 10Ab is shown as semiconductor device 10Ab[2]. Furthermore, semiconductor device 10Aa included in the third layer is shown as semiconductor device 10Aa[3], and semiconductor device 10Ab is shown as semiconductor device 10Ab[3].

[0216] Furthermore, semiconductor device 10Aa[1] is electrically connected to wiring WLa[1], wiring PLa[1], wiring CLa[1], and wiring BL. Semiconductor device 10Ab[1] is electrically connected to wiring WLb[1], wiring PLb[1], wiring CLb[1], and wiring BL. Semiconductor device 10Aa[2] is electrically connected to wiring WLa[2], wiring PLa[2], wiring CLa[2], and wiring BL. Semiconductor device 10Ab[2] is electrically connected to wiring WLb[2], wiring PLb[2], wiring CLb[2], and wiring BL. Semiconductor device 10Aa[3] is electrically connected to wiring WLa[3], wiring PLa[3], wiring CLa[3], and wiring BL. Semiconductor device 10Ab[3] is electrically connected to wiring WLb[3], wiring PLb[3], wiring CLb[3], and wiring BL.

[0217] By adopting the configuration shown in Figures 8A and 8B, the occupied area of ​​the semiconductor device, including the semiconductor device 10A, can be further reduced.

[0218] <Variation 6> In the modified configuration 5 described using Figure 8, by not forming a conductor 205 that functions as a back gate on the transistor 100 formed in the second layer and subsequent layers, and instead using the gate (conductor 260) of the transistor 100 in the layer below as the back gate, the manufacturing process of the semiconductor device can be reduced. Therefore, the manufacturing cost of the semiconductor device can be reduced.

[0219] Figure 9A is a cross-sectional view showing an example of a stacked configuration of multiple semiconductor devices 10A. Figure 9B is an equivalent circuit diagram of the configuration example shown in Figure 9A.

[0220] In Figure 9A, the transistor 100 formed in the second layer does not have conductors 205, conductors 206, insulators 216, insulators 214, and insulators 212, and the insulator 222 of the second layer is formed on top of the conductors 260 and insulators 280 formed in the first layer.

[0221] Furthermore, a conductor 261 is formed on the insulator 280 of the first layer. The conductor 261 formed on the first layer functions as the other electrode of the capacitive element 110 formed on the second layer. The conductor 261 of the first layer can be formed simultaneously in the same process as the conductor 260 of the first layer.

[0222] Furthermore, in Figure 9A, the transistor 100 formed in the third layer does not have conductors 205, conductors 206, insulators 216, insulators 214, and insulators 212, and the insulator 222 of the third layer is formed on top of the conductors 260 and insulators 280 formed in the second layer.

[0223] Furthermore, a conductor 261 is formed on the insulator 280 of the second layer. The conductor 261 formed on the second layer functions as the other electrode of the capacitive element 110 formed on the third layer. The conductor 261 of the second layer can be formed simultaneously in the same process as the conductor 260 of the second layer.

[0224] Note that the conductive material 261 does not need to be formed in the top layer. Alternatively, if a capacitive element 110 is not formed in the layer directly above it, the conductive material 261 does not need to be formed. In Figure 9A, the conductive material 261 is not formed in the third layer.

[0225] <Component materials for semiconductor devices> The following describes the constituent materials that can be used in semiconductor devices.

[0226] <<Substrate>> As the substrate for forming the semiconductor device 10 (semiconductor device 10A, semiconductor device 10B, and semiconductor device 10C), for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates.

[0227] Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates that have insulating regions within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates.

[0228] Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates containing metal nitrides and substrates containing metal oxides. Furthermore, there are substrates with a conductor or semiconductor mounted on an insulating substrate, substrates with a conductor or insulator mounted on a semiconductor substrate, and substrates with a semiconductor or insulator mounted on a conductive substrate.

[0229] Alternatively, substrates with elements mounted on them may be used. Examples of elements mounted on the substrate include capacitive elements, resistive elements, switch elements, light-emitting elements, and memory elements.

[0230] <<Insulator>> Insulators include insulating oxides, nitrides, oxidized nitrides, nitride oxides, metal oxides, metal oxidized nitrides, and metal nitride oxides.

[0231] For example, as transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, parasitic capacitance between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.

[0232] Furthermore, examples of insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxidized nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxidized nitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0233] Insulators with low dielectric constants include silicon oxide, silicon oxide nitride, silicon oxide nitride, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, or resins.

[0234] Furthermore, the electrical properties of transistors using metal oxides can be stabilized by surrounding them with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. As an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or in a multilayer structure. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxide nitride, and silicon nitride can be used.

[0235] Furthermore, the insulator that functions as a gate insulator is preferably an insulator that has a region containing oxygen that is desorbed by heating. For example, by having a silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0236] <<Conductive material>> As the conductor, it is preferable to use a metallic element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metallic elements, or an alloy combining the above metallic elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements like phosphorus, or silicides such as nickel silicide may be used.

[0237] Furthermore, multiple conductive layers formed from the above materials may be used in a laminated structure. For example, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with a nitrogen-containing conductive material. Alternatively, a laminated structure may be formed by combining the aforementioned metal element material with an oxygen-containing conductive material and a nitrogen-containing conductive material.

[0238] Furthermore, when using an oxide in the channel formation region of a transistor, it is preferable to use a laminated structure for the conductor functioning as the gate electrode, which combines a material containing the aforementioned metal element with a conductive material containing oxygen. In this case, it is preferable to place the conductive material containing oxygen on the channel formation region side. By placing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0239] In particular, it is preferable to use a conductive material containing metal elements and oxygen contained in the metal oxide in which the channel is formed as the conductor that functions as the gate electrode. Alternatively, conductive materials containing the aforementioned metal elements and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon-doped indium tin oxide may be used. In addition, indium gallium zinc oxide containing nitrogen may be used. By using such materials, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen that is mixed in from an external insulator or the like.

[0240] <<Metal Oxides>> It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as "oxide semiconductor") as the oxide 230. Below, metal oxides applicable to the oxide 230 according to the present invention will be described.

[0241] Here, we consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Element M is aluminum, gallium, yttrium, or tin. Other elements that can be used for element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, it is also possible to use a combination of multiple of the aforementioned elements for element M. In particular, it is preferable that element M is one or more elements selected from gallium, aluminum, and tin.

[0242] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as "IGZO") as the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as "IAZO") may be used as the semiconductor layer of the transistor. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as "IAGZO" or "IGAZO") may be used as the semiconductor layer. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) is sometimes called In-Ga-Zn oxide.

[0243] In this specification, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxynitrides.

[0244] Furthermore, metal oxides applicable to the oxide 230 according to the present invention will be described in more detail in other embodiments.

[0245] <<Other Semiconductor Materials>> The semiconductor material that can be used for oxide 230 is not limited to the metal oxides described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used as oxide 230. For example, it is preferable to use semiconductors of elemental elements such as silicon, compound semiconductors such as gallium arsenide, or layered materials that function as semiconductors (also called atomic layer materials, two-dimensional materials, etc.) as semiconductor materials. In particular, it is preferable to use layered materials that function as semiconductors as semiconductor materials.

[0246] In this specification, the term "layered material" refers to a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, it is possible to provide a transistor with a large on-current.

[0247] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens. Chalcogens are a general term for elements belonging to Group 16, and include oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0248] As the oxide 230, for example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor. Specific examples of the transition metal chalcogenide applicable as the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), and the like.

[0249] <Operation Example of Semiconductor Device 10> Subsequently, an operation example of the semiconductor device 10 (semiconductor devices 10A, 10B, and 10C) will be described. FIG. 10A shows an equivalent circuit diagram of the semiconductor device 10. The semiconductor device 10 shown in FIG. 10A is a DRAM type (1Tr1C type) memory element (memory cell) having one transistor M and one capacitor element Cfe.

[0250] Also, the capacitor element Cfe has a material that can have ferroelectricity as a dielectric layer between two electrodes. Therefore, the semiconductor device 10 functions as a FeRAM (Ferroelectric Random Access Memory). The transistor M shown in FIG. 10A corresponds to the transistor 100, and the capacitor element Cfe corresponds to the capacitor element 110.

[0251] Various semiconductor materials can be used as the semiconductor layer in which the channel of the transistor M is formed. For example, as the semiconductor layer in which the channel of the transistor M is formed, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor can be used alone or in combination. Further, as the semiconductor material, for example, silicon or germanium can be used. Also, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, and a nitride semiconductor may be used.

[0252] In particular, it is preferable to use an OS transistor as the transistor M. The OS transistor has the characteristic of high breakdown voltage between the source and the drain. Therefore, by using the transistor M as an OS transistor, even if the transistor M is miniaturized, a high voltage can be applied to the transistor M. By miniaturizing the transistor M, the occupied area of the semiconductor device 10 can be reduced. For example, the occupied area per one of the semiconductor devices 10 shown in FIG. 10A can be made 1 / 3 to 1 / 6 of the occupied area per one cell of SRAM (Static Random Access Memory). Therefore, the semiconductor devices 10 can be arranged at high density. As a result, a storage device with a large storage capacity can be realized.

[0253] When an OS transistor is used for the transistor constituting the memory cell, the memory cell can be called an "OS memory". In particular, a DRAM-type OS memory may be called DOSRAM (registered trademark). Also, FeRAM using an OS transistor for the transistor constituting the memory cell may be called FeDOSRAM.

[0254] The wiring WL has a function as a word line, and by controlling the potential of the wiring WL, the on-state and off-state of the transistor M can be controlled. For example, when the transistor M is an n-channel type transistor, by setting the potential of the wiring WL to a high potential, the transistor M can be turned on, and by setting the potential of the wiring WL to a low potential, the transistor M can be turned off.

[0255] The wiring BL has a function as a bit line, and when the transistor M is in the on-state, the potential of the wiring BL is supplied to one electrode of the capacitive element Cfe.

[0256] The wiring PL has a function as a plate line. The other electrode of the capacitive element Cfe is supplied with a potential via the wiring PL.

[0257] <Hysteresis characteristic> The ferroelectric layer of a capacitive element Cfe exhibits hysteresis characteristics. Figure 10B is a graph showing an example of these hysteresis characteristics. In Figure 10B, the horizontal axis represents the voltage applied to the ferroelectric layer. This voltage can be, for example, the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe.

[0258] Furthermore, in Figure 10B, the vertical axis represents the polarization of the ferroelectric layer. A positive value indicates that the positive charge is biased towards one electrode side of the capacitive element Cfe, and the negative charge is biased towards the other electrode side of the capacitive element Cfe. Conversely, a negative polarization value indicates that the positive charge is biased towards the other electrode side of the capacitive element Cfe, and the negative charge is biased towards one electrode side of the capacitive element Cfe.

[0259] The voltage shown on the horizontal axis of the graph in Figure 10B may be the difference between the potential of the other electrode of the capacitive element Cfe and the potential of the one electrode of the capacitive element Cfe. Furthermore, the polarization shown on the vertical axis of the graph in Figure 10B may be defined as a positive value when the positive charge is biased towards the other electrode of the capacitive element Cfe and the negative charge is biased towards the one electrode, and as a negative value when the positive charge is biased towards the one electrode and the negative charge is biased towards the other electrode.

[0260] As shown in Figure 10B, the hysteresis characteristics of the ferroelectric layer can be represented by curves 51 and 52. The voltages at the intersection of curves 51 and 52 are denoted as VSP and -VSP. VSP and -VSP can be said to have different polarities.

[0261] When a voltage below -VSP is applied to the ferroelectric layer, and then the voltage applied to the ferroelectric layer is increased, the polarization of the ferroelectric layer increases according to curve 51. On the other hand, when a voltage above VSP is applied to the ferroelectric layer, and then the voltage applied to the ferroelectric layer is decreased, the polarization of the ferroelectric layer decreases according to curve 52. Therefore, VSP and -VSP can be called saturation polarization voltages. For example, VSP may be called the first saturation polarization voltage and -VSP may be called the second saturation polarization voltage. Also, although Figure 10B shows the case where the absolute values ​​of the first saturation polarization voltage and the absolute values ​​of the second saturation polarization voltage are equal, their absolute values ​​may be different.

[0262] Here, Vc is the voltage applied to the ferroelectric layer when its polarization is zero, as the polarization of the ferroelectric layer changes according to curve 51. Also, -Vc is the voltage applied to the ferroelectric layer when its polarization is zero, as the polarization of the ferroelectric layer changes according to curve 52. Vc and -Vc can be called resistance voltages. The values ​​of Vc and -Vc can be said to be between -VSP and VSP. For example, Vc may be called the first resistance voltage and -Vc may be called the second resistance voltage. Furthermore, in Figure 10B, the absolute values ​​of the first resistance voltage and the absolute values ​​of the second resistance voltage are assumed to be equal, but their absolute values ​​may be different.

[0263] Furthermore, when no voltage is applied to the ferroelectric layer, the maximum value of polarization is called "residual polarization Pr," and the minimum value is called "residual polarization -Pr." The difference between residual polarization Pr and residual polarization -Pr is called "residual polarization 2Pr."

[0264] As mentioned above, the voltage applied to the ferroelectric layer of a capacitive element Cfe can be expressed as the difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode of the capacitive element Cfe. Also, as mentioned above, the other electrode of the capacitive element Cfe is electrically connected to the wiring PL. Therefore, by controlling the potential of the wiring PL, the voltage applied to the ferroelectric layer of the capacitive element Cfe can be controlled.

[0265] An example of a driving method for a semiconductor device 10 that functions as a memory cell is described below. In the following description, the voltage applied to the ferroelectric layer of the capacitive element Cfe is the potential difference between the potential of one electrode of the capacitive element Cfe and the potential of the other electrode (wiring PL) of the capacitive element Cfe. Also, the transistor M is an n-channel type transistor.

[0266] Figure 10C is a timing chart showing an example of a driving method for the semiconductor device 10. Figure 10C shows an example of writing and reading binary digital data to the semiconductor device 10. Specifically, Figure 10C shows an example in which the data "1" is written to the semiconductor device 10 at times T01 to T02, read and rewrite is performed at times T03 to T05, read and write data "0" to the semiconductor device 10 at times T11 to T13, read and rewrite is performed at times T14 to T16, and read and write data "1" to the semiconductor device 10 at times T17 to T19.

[0267] The sense amplifier electrically connected to wiring BL is supplied with Vref as the reference potential. In the readout operation shown in Figure 10C, etc., if the potential of wiring BL is higher than Vref, the bit line driver circuit reads out the data "1". On the other hand, if the potential of wiring BL is lower than Vref, the bit line driver circuit reads out the data "0".

[0268] Between times T01 and T02, the potential of wiring WL is set to a high potential. This turns on transistor M. Also, the potential of wiring BL is set to Vw. Since transistor M is in the ON state, the potential of one electrode of the capacitive element Cfe becomes Vw. Furthermore, the potential of wiring PL is set to GND. Therefore, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "Vw-GND". This allows the data "1" to be written to the semiconductor device 10. Thus, times T01 and T02 can be said to be the period during which the writing operation is performed.

[0269] Here, Vw is preferably greater than or equal to VSP, for example, it is preferably equal to VSP. Furthermore, although GND is the ground potential in this specification, it does not necessarily have to be the ground potential if the semiconductor device 10 can be driven in a manner that satisfies the spirit of one aspect of the present invention. For example, if the absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage are different, and the absolute value of the first resistance voltage and the absolute value of the second resistance voltage are different, GND can be a potential other than ground.

[0270] Between times T02 and T03, the potential of wiring BL and wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "Vw-GND" applied to the ferroelectric layer of the capacitive element Cfe between times T01 and T02 can be greater than or equal to VSP, the polarization of the ferroelectric layer of the capacitive element Cfe changes according to curve 52 shown in Figure 10B between times T02 and T03. Therefore, between times T02 and T03, no polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe.

[0271] After setting the potentials of wiring BL and wiring PL to GND, the potential of wiring WL is set to a low potential. This turns off transistor M. With the above steps, the writing operation is completed and the data "1" is stored in semiconductor device 10. Note that the potentials of wiring BL and wiring PL can be any potential as long as polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is greater than or equal to the second resistance voltage, -Vc.

[0272] At time T03 to time T04, the potential of the wiring WL is set to a high potential. As a result, the transistor M is turned on. Also, the potential of the wiring PL is set to Vw. By setting the potential of the wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitor element Cfe becomes "GND - Vw". As described above, the voltage applied to the ferroelectric layer of the capacitor element Cfe at time T01 to time T02 is "Vw - GND". Therefore, polarization reversal occurs in the ferroelectric layer of the capacitor element Cfe. During the polarization reversal, a current flows through the wiring BL, and the potential of the wiring BL becomes higher than Vref. Therefore, the bit line driver circuit can read the data "1" held in the semiconductor device 10. Therefore, it can be said that time T03 to time T04 is a period for performing a read operation. Although Vref is higher than GND and lower than Vw, it may be higher than Vw, for example.

[0273] Since the above reading is a destructive read, the data "1" held in the semiconductor device 10 is lost. Therefore, at time T04 to time T05, the potential of the wiring BL is set to Vw, and the potential of the wiring PL is set to GND. Thereby, the data "1" is rewritten in the semiconductor device 10. Therefore, it can be said that time T04 to time T05 is a period for performing a rewrite operation.

[0274] At time T05 to time T11, the potential of the wiring BL and the potential of the wiring PL are set to GND. Then, the potential of the wiring WL is set to a low potential. As described above, the rewrite operation is completed, and the data "1" is held in the semiconductor device 10.

[0275] At time T11 to time T12, the potential of the wiring WL is set to a high potential, and the potential of the wiring PL is set to Vw. Since the data "1" is held in the semiconductor device 10, the potential of the wiring BL becomes higher than Vref, and the data "1" held in the semiconductor device 10 is read out. Therefore, it can be said that time T11 to time T12 is a period for performing a read operation.

[0276] Between times T12 and T13, the potential of wiring BL is set to GND. Since transistor M is in the ON state, the potential of one electrode of the capacitive element Cfe is set to GND. Also, the potential of wiring PL is set to Vw. Therefore, the voltage applied to the ferroelectric layer of the capacitive element Cfe is "GND-Vw". This allows the data "0" to be written to the semiconductor device 10. Thus, it can be said that the period between times T12 and T13 is the period during which the writing operation is performed.

[0277] Between times T13 and T14, the potentials of wiring BL and wiring PL are set to GND. As a result, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes 0V. Since the voltage "GND-Vw" applied to the ferroelectric layer of the capacitive element Cfe between times T12 and T13 can be less than or equal to -VSP, the polarization of the ferroelectric layer of the capacitive element Cfe changes according to the curve 51 shown in Figure 10B between times T13 and T14. Therefore, between times T13 and T14, no polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe.

[0278] After setting the potentials of wiring BL and wiring PL to GND, the potential of wiring WL is set to a low potential. This turns off transistor M. With this, the writing operation is completed and the data "0" is stored in semiconductor device 10. Note that the potentials of wiring BL and wiring PL can be any potential as long as polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe, that is, the voltage applied to the ferroelectric layer of the capacitive element Cfe is less than or equal to the first resistance voltage Vc.

[0279] Between times T14 and T15, the potential of wiring WL is set to a high potential. This turns on transistor M. Also, the potential of wiring PL is set to Vw. By setting the potential of wiring PL to Vw, the voltage applied to the ferroelectric layer of the capacitive element Cfe becomes "GND-Vw". As mentioned above, between times T12 and T13, the voltage applied to the ferroelectric layer of the capacitive element Cfe is "GND-Vw". Therefore, polarization reversal does not occur in the ferroelectric layer of the capacitive element Cfe. Consequently, the amount of current flowing through wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe. As a result, the rise in the potential of wiring BL is smaller than when polarization reversal occurs in the ferroelectric layer of the capacitive element Cfe, and specifically, the potential of wiring BL becomes less than or equal to Vref. Therefore, the bit line driver circuit can read the data "0" held in the semiconductor device 10. Thus, times T14 and T15 can be said to be the period during which the read operation is performed.

[0280] Between times T15 and T16, the potential of wiring BL is set to GND, and the potential of wiring PL is set to Vw. This rewrites the data "0" to the semiconductor device 10. Therefore, times T15 and T16 can be considered the period during which the rewrite operation is performed.

[0281] Between times T16 and T17, the potential of wiring BL and wiring PL are set to GND. Subsequently, the potential of wiring WL is set to a low potential. With these steps completed, the rewrite operation is finished and the data "0" is retained in semiconductor device 10.

[0282] Between times T17 and T18, the potential of wiring WL is set to a high potential, and the potential of wiring PL is set to Vw. Since the semiconductor device 10 holds the data "0", the potential of wiring BL becomes lower than Vref, and the data "0" held in the semiconductor device 10 is read out. Therefore, it can be said that times T17 and T18 are the period during which the read operation is performed.

[0283] Between times T18 and T19, the potential of wiring BL is Vw. Since transistor M is in the ON state, the potential of one electrode of the capacitive element Cfe is Vw. Also, the potential of wiring PL is GND. Therefore, the voltage applied to the ferroelectric layer of the capacitive element Cfe is "Vw-GND". This allows the data "1" to be written to the semiconductor device 10. Thus, times T18 to T19 can be said to be the period during which the writing operation is performed.

[0284] From time T19 onward, the potential of wiring BL and wiring PL are set to GND. Subsequently, the potential of wiring WL is set to a low potential. With these steps completed, the writing operation is finished and the data "1" is stored in semiconductor device 10.

[0285] The semiconductor device 10, which uses a ferroelectric layer in the capacitive element Cfe, functions as a non-volatile memory element that can retain written information even when the power supply is interrupted.

[0286] Furthermore, DRAM (Dynamic Random Access Memory) requires periodic refresh operations, which increases power consumption. The semiconductor device 10, which uses a ferroelectric layer in the capacitive element Cfe, does not require refresh operations, thus reducing power consumption.

[0287] In this specification, a memory element or memory circuit including a ferroelectric layer may be referred to as a "ferroelectric memory" or "FE memory." Therefore, the semiconductor device 10 is both a ferroelectric memory and an FE memory. The FE memory has a capacity of 1 × 10⁻¹⁶ 10 Preferably 1 × 10 12 In summary, 1 × 10 15 The above number of rewrite cycles can be expected to be achieved. Furthermore, the FE memory can be expected to achieve an operating frequency of 10 MHz or higher, preferably 1 GHz or higher.

[0288] Furthermore, in FE memory, there is a correlation between residual polarization 2Pr and data retention capacity; as residual polarization 2Pr decreases, data retention capacity decreases. In this specification, the period until residual polarization 2Pr decreases by 5% (when data retention capacity decreases by 5%) is referred to as the "memory retention period." FE memory can be expected to achieve a memory retention period of 10 days or more, preferably 1 year or more, and more preferably 10 years or more, under ambient temperatures of 150°C or 200°C.

[0289] Furthermore, FE memory can be applied to cache memory and registers of CPUs (Central Processing Units) and GPUs (Graphics Processing Units). By combining FE memory with the CPU's cache memory and registers, Noff-CPU (Normally Off CPU) operation can be achieved. By combining FE memory with the GPU's cache memory and registers, Noff-GPU (Normally Off CPU) operation can be achieved.

[0290] This embodiment can be appropriately combined with other embodiments shown herein.

[0291] (Embodiment 2) In this embodiment, an example configuration of a storage device 300 using a semiconductor device 10 as a memory cell will be described.

[0292] Figure 11A shows a block diagram illustrating an example configuration of a storage device 300 according to one aspect of the present invention. The storage device 300 shown in Figure 11A includes a drive circuit 21 and a memory array 20. The memory array 20 has a plurality of semiconductor devices 10. Figure 11A shows an example in which the memory array 20 has a plurality of semiconductor devices 10 arranged in an m x n matrix (where m and n are integers of 2 or more).

[0293] Note that rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction (direction along the X-axis) is defined as a "row" and the Y direction (direction along the Y-axis) is defined as a "column," but the X direction may be defined as a "column" and the Y direction as a "row."

[0294] In Figure 11A, the semiconductor device 10 in the 1st row and 1st column is shown as semiconductor device 10[1,1], and the semiconductor device 10 in the mth row and nth column is shown as semiconductor device 10[m,n]. In this embodiment, an arbitrary row may be referred to as row i, and an arbitrary column may be referred to as column j. Therefore, i is an integer between 1 and m, and j is an integer between 1 and n. In this embodiment, the semiconductor device 10 in the ith row and jth column is shown as semiconductor device 10[i,j]. In this embodiment, when "i+α" (where α is a positive or negative integer) is used, "i+α" is not less than 1 and not greater than m. Similarly, when "j+α" is used, "j+α" is not less than 1 and not greater than n.

[0295] Furthermore, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment, the first wiring WL (first row) is denoted as wiring WL[1], and the mth wiring WL (mth row) is denoted as wiring WL[m]. Similarly, the first wiring PL (first row) is denoted as wiring PL[1], and the mth wiring PL (mth row) is denoted as wiring PL[m]. Similarly, the first wiring BL (first column) is denoted as wiring BL[1], and the nth wiring BL (nth column) is denoted as wiring BL[n].

[0296] Multiple semiconductor devices 10 located in row i are electrically connected to the wiring WL (wiring WL[i]) and the wiring PL (wiring PL[i]) in row i. Multiple semiconductor devices 10 located in column j are electrically connected to the wiring BL (wiring BL[j]) in column j.

[0297] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0298] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal. Signal CLK is a clock signal.

[0299] Furthermore, signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated by the control circuit 32.

[0300] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 300 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 so that this operating mode is executed.

[0301] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0302] The peripheral circuit 41 is a circuit for writing and reading data to and from the semiconductor device 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0303] The row decoder 42 and column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to access, and the column decoder 44 is a circuit for specifying the column to access. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the function of writing data to the semiconductor device 10, reading data from the semiconductor device 10, and holding the read data.

[0304] The input circuit 47 has the function of holding the signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the semiconductor device 10. The data (Dout) read by the column driver 45 from the semiconductor device 10 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. The output circuit 48 also has the function of outputting Dout to the outside of the storage device 300. The data output from the output circuit 48 is the signal RDA.

[0305] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW22 is controlled by signal PON1, and the on / off state of PSW23 is controlled by signal PON2. In Figure 11A, the number of power supply domains to which VDD is supplied in the peripheral circuit 31 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0306] The drive circuit 21 and the memory array 20 may be provided on the same plane. Alternatively, as shown in Figure 11B, a layer containing the memory array 20 may be placed directly above the layer containing the drive circuit 21. By stacking the drive circuit 21 and the memory array 20, the signal propagation distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, resulting in reduced power consumption and signal delay. Furthermore, the storage device 300 can be miniaturized.

[0307] Furthermore, although Figure 11B shows a single layer of memory array 20 on top of the drive circuit 21, multiple layers of memory array 20 may be stacked on top of the drive circuit 21. Figure 11C shows an example in which k layers (where k is an integer of 2 or more) of memory array 20 are stacked on top of the drive circuit 21. In Figure 11C and other figures, the first layer of memory array 20 is shown as memory array 20[1], the second layer of memory array 20 is shown as memory array 20[2], and the k-th layer of memory array 20 is shown as memory array 20[k].

[0308] Figure 12A shows a schematic diagram illustrating an example configuration of the storage device 300. The storage device 300 shown in Figure 12A has a six-layer memory array 20 provided on the drive circuit 21. As mentioned above, in Figure 12A and other figures, the third-layer memory array 20 is shown as memory array 20[3], the fourth-layer memory array 20 as memory array 20[4], the fifth-layer memory array 20 as memory array 20[5], and the sixth-layer memory array 20 as memory array 20[6].

[0309] Each layer of the memory array 20 has multiple semiconductor devices 10 arranged in a matrix, and wiring WL, wiring CL, and wiring PL extending in the X direction. For the sake of clarity in the drawing, the wiring WL, wiring CL, and wiring PL of each of the memory arrays 20 from the first to the fifth layer have been omitted from the description.

[0310] Furthermore, the storage device 300 shown in Figure 12A has multiple wirings BL extending in the Z direction. The wirings BL are formed through each of the six layers of the memory array 20 and are electrically connected to the drive circuit 21. When viewed from the Z direction, the multiple wirings BL are arranged in a matrix.

[0311] Furthermore, in each layer of the memory array 20, one of the multiple semiconductor devices 10 in the memory array 20 is electrically connected to one of the multiple wiring BLs. Therefore, in the storage device 300 shown in Figure 12A, a total of six semiconductor devices 10, one from each layer of the memory array 20, are electrically connected to one wiring BL.

[0312] A configuration in which multiple memory cells (semiconductor devices 10) are electrically connected to a single wiring BL is also called a "memory string." Therefore, it can be said that the storage device 300 shown in Figure 12A is composed of multiple memory strings.

[0313] Figure 12B shows a schematic diagram of the memory string of the storage device 300 shown in Figure 12A. For clarity, the schematic diagram of the memory string in Figure 12B omits the electrical connections between the memory string and the semiconductor device 10 (wirings WL, CL, and PL). A portion of the equivalent circuit of the memory string is also shown in Figure 12B.

[0314] Figure 13A shows a schematic diagram illustrating an example configuration of the storage device 300. The storage device 300 shown in Figure 13A is a modified version of the storage device 300 shown in Figure 12A. Therefore, to minimize repetition in the explanation, we will mainly describe the differences from the storage device 300 shown in Figure 12A.

[0315] The storage device 300 shown in Figure 13A differs from the storage device 300 shown in Figure 12A in that, in each layer of the memory array 20, two of the multiple semiconductor devices 10 in the memory array 20 are electrically connected to one of the multiple wiring BLs. In other words, a total of 12 semiconductor devices 10 are electrically connected to one wiring BL.

[0316] Figure 13B shows a schematic diagram of the memory string of the storage device 300 shown in Figure 13A. Figure 13B also includes a partial equivalent circuit of the memory string.

[0317] The storage device 300 shown in Figure 13A can reduce the number of wiring lines (BLs) compared to the storage device 300 shown in Figure 12A. Therefore, the occupied area of ​​the storage device 300 is reduced.

[0318] Furthermore, the semiconductor device 10 according to one aspect of the present invention is an FE memory, which can retain written information for a long period of time even if the power supply is interrupted. In addition, since the refresh operation required for DRAM is unnecessary, a storage device 300 with low power consumption can be realized.

[0319] [Example of semiconductor device configuration] Figure 14 shows an example of a cross-sectional configuration of a storage device 300 according to one aspect of the present invention. The storage device 300 shown in Figure 14 has a k-layer memory array 20 above the drive circuit 21. In Figure 14, the configuration shown in Figures 8 and 13 is illustrated as the k-layer memory array 20. To reduce repetition in the explanation, the description of the k-layer memory array 20 is omitted here.

[0320] Figure 14 also illustrates a transistor 400 in the drive circuit 21. The transistor 400 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 400 may be either a p-channel transistor or an n-channel transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0321] In Figure 14, the transistor 400 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 400 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI (Silicon on Insulator) substrate.

[0322] Note that the transistor 400 shown in Figure 14 is just one example, and its structure is not limited to that; any appropriate transistor can be used depending on the circuit configuration or driving method.

[0323] A wiring layer containing interlayer films, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plugs electrically connected to the wiring may be integrated into a single unit. That is, a portion of the conductor may function as wiring, and a portion of the conductor may function as a plug.

[0324] For example, on the transistor 400, insulators 320, 322, 324, and 326 are sequentially stacked as interlayer films. In addition, conductors 328 and 330, which are electrically connected to the conductor 207, are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 function as contact plugs or wiring.

[0325] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment such as chemical mechanical polishing (CMP) to improve its flatness.

[0326] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Figure 14, insulators 350, 352, and 354 are sequentially stacked on the insulator 326 and the conductor 330. Conductors 356 are formed on insulators 350, 352, and 354. The conductor 356 functions as a contact plug or wiring.

[0327] An insulator 357 is provided on the insulator 354 and the conductor 356. A conductor 358 is embedded in the insulator 357. The conductor 358 functions as a contact plug or wiring. Conductors 207 and 356 are electrically connected via the conductor 358.

[0328] This embodiment can be appropriately combined with other embodiments shown herein.

[0329] (Embodiment 3) This embodiment describes metal oxides that can be used in semiconductors in which transistor channels are formed.

[0330] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0331] <Classification of crystal structures> First, we will explain the classification of crystal structures in oxide semiconductors using Figure 15A. Figure 15A is a diagram illustrating the classification of crystal structures in oxide semiconductors, specifically IGZO (a metal oxide containing In, Ga, and Zn).

[0332] As shown in Figure 15A, oxide semiconductors are broadly classified into "Amorphous," "Crystalline," and "Crystal." "Amorphous" includes completely amorphous materials. "Crystalline" includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite) (excluding single crystal and polycrystal). Note that single crystal, polycrystal, and completely amorphous materials are excluded from the "Crystalline" classification. "Crystal" includes single crystal and polycrystal materials.

[0333] The structure within the thick frame shown in Figure 15A represents an intermediate state between "Amorphous" and "Crystal," and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as being completely different from the energetically unstable "Amorphous" and "Crystal" states.

[0334] The crystal structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 15B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or Seemann-Bohlin method. Hereafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 15B may simply be referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 15B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 15B is 500 nm.

[0335] As shown in Figure 15B, the XRD spectrum of the CAAC-IGZO film shows a peak indicating clear crystallinity. Specifically, the XRD spectrum of the CAAC-IGZO film shows a peak indicating c-axis orientation near 2θ=31°. As shown in Figure 15B, the peak near 2θ=31° is asymmetrical with respect to the angle at which the peak intensity was detected.

[0336] Furthermore, the crystal structure of a film or substrate can be evaluated by the diffraction pattern (also called the nano-beam electron diffraction pattern) observed by nano-beam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 15C. Figure 15C shows the diffraction pattern observed by NBED with the electron beam incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 15C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In nano-beam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0337] As shown in Figure 15C, the diffraction pattern of the CAAC-IGZO film shows multiple spots indicating c-axis orientation.

[0338] <<Oxide semiconductor structure>> Note that when focusing on the crystal structure, oxide semiconductors may be classified differently from those shown in Figure 15A. For example, oxide semiconductors can be divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the aforementioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors also include polycrystalline oxide semiconductors, pseudo-amorphous oxide semiconductors (a-like OS), and amorphous oxide semiconductors.

[0339] Here, we will explain the details of the CAAC-OS, nc-OS, and a-like OS mentioned above.

[0340] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, the c-axis of which is oriented in a specific direction. This specific direction is the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If we consider the atomic arrangement as a lattice arrangement, then a crystalline region is also a region with a aligned lattice arrangement. Furthermore, CAAC-OS has regions where multiple crystalline regions are connected in the ab-plane direction, and these regions may exhibit distortion. Distortion refers to a point in the connected region where the orientation of the lattice arrangement changes between a region with a aligned lattice arrangement and another region with a aligned lattice arrangement. In short, CAAC-OS is an oxide semiconductor that is c-axis oriented and does not exhibit clear orientation in the ab-plane direction.

[0341] Each of the multiple crystalline regions described above is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of a single minute crystal, the maximum diameter of that crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of that crystalline region may be around several tens of nanometers.

[0342] Furthermore, in In-M-Zn oxides (where element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), CAAC-OS tends to have a layered crystalline structure (also called a layered structure) consisting of layers containing indium (In) and oxygen (hereinafter referred to as the In layer) and layers containing element M, zinc (Zn), and oxygen (hereinafter referred to as the (M,Zn) layer). Note that indium and element M are mutually substitutable. Therefore, the (M,Zn) layer may contain indium. Also, the In layer may contain element M. Also, the In layer may contain Zn. This layered structure can be observed, for example, as a lattice image in high-resolution TEM images.

[0343] When structural analysis of a CAAC-OS film is performed using an XRD instrument, for example, out-of-plane XRD measurements using θ / 2θ scanning show a peak indicating c-axis orientation at 2θ = 31° or nearby. Note that the position of the c-axis orientation peak (value of 2θ) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0344] Furthermore, for example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film. These spots are observed at point-symmetric positions with respect to the incident electron beam spot (also called the direct spot) that passed through the sample.

[0345] When the crystal region is observed from the specific direction described above, the lattice arrangement within that crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the strain may have lattice arrangements such as pentagons or heptagons. Moreover, in CAAC-OS, clear grain boundaries cannot be observed even near the strain. In other words, it can be seen that the formation of grain boundaries is suppressed by the strain in the lattice arrangement. This is thought to be because CAAC-OS can tolerate strain due to factors such as the non-dense arrangement of oxygen atoms in the ab-plane direction and the change in interatomic bond distances due to the substitution of metal atoms.

[0346] A crystal structure in which clear grain boundaries are observed is called a polycrystal. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in transistor on-current and field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides with a suitable crystal structure for the semiconductor layer of a transistor. In addition, a structure containing Zn is preferred for the composition of CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are preferred because they suppress the generation of grain boundaries more than In oxide.

[0347] CAAC-OS is an oxide semiconductor with high crystallinity and no clearly defined grain boundaries. Therefore, CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. Furthermore, since the crystallinity of oxide semiconductors can decrease due to the inclusion of impurities and the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS have stable physical properties. Therefore, oxide semiconductors containing CAAC-OS are heat-resistant and highly reliable. In addition, CAAC-OS is stable even at high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using CAAC-OS in OS transistors allows for greater flexibility in the manufacturing process.

[0348] [nc-OS] nc-OS exhibits periodicity in atomic arrangement in minute regions (e.g., regions between 1 nm and 10 nm, particularly between 1 nm and 3 nm). In other words, nc-OS contains minute crystals. These minute crystals are also called nanocrystals because their size is, for example, between 1 nm and 10 nm, particularly between 1 nm and 3 nm. Furthermore, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Consequently, depending on the analytical method, nc-OS may be indistinguishable from a-like OS and amorphous oxide semiconductors. For example, when structural analysis of an nc-OS film is performed using an XRD instrument, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Also, when electron diffraction (also called limited-field electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter larger than that of the nanocrystals (e.g., 50 nm or larger), a diffraction pattern resembling a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystal (for example, 1 nm to 30 nm), an electron diffraction pattern may be obtained in which multiple spots are observed within a ring-shaped region centered on a direct spot.

[0349] [a-like OS] a-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has porous or low-density regions. That is, a-like OS has lower crystallinity compared to nc-OS and CAAC-OS. Also, a-like OS has a higher hydrogen concentration in the film compared to nc-OS and CAAC-OS.

[0350] <<Oxide Semiconductor Composition>> Next, we will explain the details of CAC-OS mentioned above. Note that CAC-OS refers to the material composition.

[0351] [CAC-OS] CAC-OS is a material composition in which, for example, the elements constituting the metal oxide are unevenly distributed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide, and the regions containing these metal elements are mixed in sizes of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or close to that size, is also referred to as a mosaic or patchy state.

[0352] Furthermore, CAC-OS is a composite metal oxide having a mosaic-like structure formed by the separation of the material into a first region and a second region, with the first region distributed within the film (hereinafter also referred to as a cloud-like structure). In other words, CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0353] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is the region where [In] is greater than the [In] in the composition of the CAC-OS film. The second region is the region where [Ga] is greater than the [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is the region where [In] is greater than the [In] in the second region, and [Ga] is smaller than the [Ga] in the second region. The second region is the region where [Ga] is greater than the [Ga] in the first region, and [In] is smaller than the [In] in the first region.

[0354] Specifically, the first region described above is a region whose main components are indium oxide, indium zinc oxide, etc. The second region described above is a region whose main components are gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region whose main component is In. Similarly, the second region can be rephrased as a region whose main component is Ga.

[0355] Furthermore, a clear boundary may not be observed between the first region and the second region described above.

[0356] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) confirms that it has a structure in which regions mainly composed of In (first region) and regions mainly composed of Ga (second region) are unevenly distributed and mixed.

[0357] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulation due to the second region work complementaryly to give CAC-OS a switching function (on / off function). In other words, CAC-OS has conductive function in part of the material, insulating function in part of the material, and semiconductor function as a whole. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I) can be achieved. on This enables high field-effect mobility (μ) and good switching operation.

[0358] Oxide semiconductors can take on diverse structures, each possessing different properties. One embodiment of the present invention may include two or more of the following: amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0359] <Transistors containing oxide semiconductors> Next, we will explain the case where the above oxide semiconductor is used in a transistor.

[0360] By using the above-mentioned oxide semiconductor in transistors, it is possible to realize transistors with high field-effect mobility. Furthermore, it is possible to realize highly reliable transistors.

[0361] It is preferable to use an oxide semiconductor with a low carrier concentration for the transistor. For example, the carrier concentration of an oxide semiconductor is 1 × 10⁻⁶. 17 cm -3 The following is preferably 1 × 10 15 cm -3 More preferably 1 × 10 13 cm -3 More preferably 1 × 10 11 cm -3 More preferably 1 × 10 10 cm -3 It is less than 1 × 10 -9 cm-3 This concludes the explanation. Furthermore, when lowering the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film should be lowered to reduce the defect level density. In this specification, a low impurity concentration and low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors with low carrier concentrations may also be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors.

[0362] Furthermore, oxide semiconductor films that are highly pure or substantially highly pure have a low defect level density, which may result in a low trap level density.

[0363] Furthermore, charges trapped in the trap levels of oxide semiconductors can take a long time to disappear, sometimes behaving like fixed charges. Therefore, transistors in which channel formation regions are formed in oxide semiconductors with a high trap level density may exhibit unstable electrical properties.

[0364] Therefore, reducing the impurity concentration in the oxide semiconductor is effective in stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in an oxide semiconductor refer to elements other than the main components that make up the oxide semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0365] <Impurities> Here, we will explain the effects of various impurities in oxide semiconductors.

[0366] In oxide semiconductors, the presence of silicon and carbon, which are Group 14 elements, leads to the formation of defect levels within the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and the concentrations of silicon and carbon near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are compared by 2 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 17 atoms / cm 3 The following applies:

[0367] Furthermore, if an oxide semiconductor contains alkali metals or alkaline earth metals, it may form defect levels and generate carriers. Therefore, transistors using oxide semiconductors containing alkali metals or alkaline earth metals tend to exhibit normally-on characteristics. For this reason, the concentration of alkali metals or alkaline earth metals in the oxide semiconductor obtained by SIMS should be set to 1 × 10⁻⁶. 18 atoms / cm 3 The following is preferably 2 × 10 16 atoms / cm 3 Do the following:

[0368] Furthermore, in oxide semiconductors, the presence of nitrogen generates electrons, which act as carriers, increasing the carrier concentration and making it easier for the semiconductor to become n-type. As a result, transistors using oxide semiconductors containing nitrogen tend to exhibit normally-on characteristics. Alternatively, the presence of nitrogen in oxide semiconductors can lead to the formation of trap levels. As a result, the electrical properties of the transistor may become unstable. For this reason, the nitrogen concentration in oxide semiconductors obtained by SIMS should be set to 5 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 atoms / cm 3 More preferably 1 × 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 Do the following:

[0369] Furthermore, hydrogen contained in oxide semiconductors can react with oxygen bonded to metal atoms to form water, potentially creating oxygen vacancies. Hydrogen can then fill these vacancies, generating electrons, which act as carriers. Additionally, some of the hydrogen can combine with oxygen bonded to metal atoms to generate electrons. Therefore, transistors using oxide semiconductors containing hydrogen tend to exhibit normally-on characteristics. For this reason, it is preferable to reduce the hydrogen content in oxide semiconductors as much as possible. Specifically, in oxide semiconductors, the hydrogen concentration obtained by SIMS should be 1 × 10⁻⁶. 20 atoms / cm 3 Less than 1 × 10 19 atoms / cm 3 Less than 5x10 18 atoms / cm 3 Less than 1 × 10 18 atoms / cm 3 Make it less than.

[0370] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of a transistor, stable electrical characteristics can be provided.

[0371] This embodiment can be appropriately combined with other embodiments shown herein.

[0372] (Embodiment 4) In this embodiment, Figures 16A and 16B show an example of a chip 1200 on which the semiconductor device of the present invention is mounted. Multiple circuits (systems) are mounted on the chip 1200. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0373] As shown in Figure 16A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0374] The chip 1200 is provided with bumps (not shown) that connect to the first surface of the package substrate 1201, as shown in Figure 16B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 that connect to the motherboard 1203.

[0375] The motherboard 1203 may be provided with storage devices such as a storage device 1221 and a flash memory 1222. For example, a semiconductor device 10 can be used as the storage device 1221. Alternatively, for example, a semiconductor device 10 may be used instead of the flash memory 1222.

[0376] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. A semiconductor device 10 can be used for this memory. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing or multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-accumulate operation circuit using an oxide semiconductor, it becomes possible to perform image processing and multiply-accumulate operations with low power consumption.

[0377] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed on the GPU 1212.

[0378] The analog arithmetic unit 1213 includes one or both an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit.

[0379] The memory controller 1214 has a circuit that functions as a controller for the storage device 1221 and a circuit that functions as an interface for the flash memory 1222.

[0380] Interface 1215 has interface circuits for connecting to external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface).

[0381] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

[0382] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0383] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a storage device 1221, and a motherboard 1203 on which flash memory 1222 is provided can be called a GPU module 1204.

[0384] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module.

[0385] This embodiment can be appropriately combined with other embodiments shown herein.

[0386] (Embodiment 5) This embodiment shows an example of an electronic component incorporating the semiconductor device shown in the above embodiment.

[0387] <Electronic Components> Figure 17A shows a perspective view of an electronic component 700 and a circuit board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 17A has a memory device 720 inside a mold 711. Figure 17A is partially omitted to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the memory device 720 by a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted board 704.

[0388] The storage device 720 includes a drive circuit layer 721 and a memory circuit layer 722. A storage device 300 according to one aspect of the present invention can be used in the storage device 720. Therefore, the drive circuit layer 721 can be said to be a layer including a drive circuit 21. Furthermore, a single-layer or multi-layer memory array 20 can be used in the memory circuit layer 722. Therefore, the drive circuit layer 721 can be said to be a layer including a memory array 20.

[0389] Figure 17B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in package) or MCM (Multi-Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple storage devices 720 are provided on the interposer 731.

[0390] Electronic component 730 shows an example where the memory device 720 is used as high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

[0391] The package substrate 732 can be a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like. The interposer 731 can be a silicon interposer, a resin interposer, or the like.

[0392] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can be used as through electrodes.

[0393] It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0394] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0395] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit placed on the silicon interposer and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0396] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the memory device 720 and the semiconductor device 735.

[0397] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 17B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0398] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. For example, mounting methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be used.

[0399] This embodiment can be appropriately combined with other embodiments shown herein.

[0400] (Embodiment 6) This embodiment describes an application example of a semiconductor device according to one aspect of the present invention.

[0401] A semiconductor device according to one aspect of the present invention can be applied to storage devices in various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, game consoles, etc.). It can also be used in image sensors, IoT (Internet of Things), healthcare-related equipment, etc. Here, "computer" includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0402] An example of an electronic device having a semiconductor device according to one aspect of the present invention will be described. Figures 18A to 18J and 19A to 19E illustrate how the electronic component 700 or electronic component 730 having the semiconductor device is included in each electronic device.

[0403] [mobile phone] The information terminal 5500 shown in Figure 18A is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0404] The information terminal 5500 can store temporary files generated during application execution (for example, cache when using a web browser) by applying a semiconductor device according to one aspect of the present invention.

[0405] [Wearable devices] Figure 18B also shows an information terminal 5900, which is an example of a wearable device. The information terminal 5900 includes a housing 5901, a display unit 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0406] Similar to the information terminal 5500 described above, a wearable device can store temporary files generated during application execution by applying a semiconductor device according to one aspect of the present invention.

[0407] [Information terminal] Figure 18C also illustrates a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display unit 5302, and a keyboard 5303.

[0408] The desktop information terminal 5300, like the information terminal 5500 described above, can store temporary files generated during application execution by applying a semiconductor device according to one aspect of the present invention.

[0409] In the above, smartphones, wearable devices, and desktop information terminals were used as examples of electronic devices and illustrated in Figures 18A to 18C, respectively. However, information terminals other than smartphones, wearable devices, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable devices, and desktop information terminals include PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0410] [electric appliances] Furthermore, Figure 18D illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a casing 5801, a refrigerator door 5802, a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0411] A semiconductor device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to an information terminal or the like via the internet. The electric refrigerator 5800 can store temporary files generated when transmitting such information in the semiconductor device.

[0412] In this example, an electric refrigerator was described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0413] [Game console] Figure 18E also shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a casing 5201, a display unit 5202, buttons 5203, etc.

[0414] Furthermore, Figure 18F illustrates a home console 7500, which is an example of a game console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a wired connection. Although not shown in Figure 18F, the controller 7522 may also be equipped with a display unit for displaying game images, and input interfaces other than buttons, such as a touch panel, a joystick, a rotary knob, or a sliding knob. Moreover, the shape of the controller 7522 is not limited to the shape shown in Figure 18F, and its shape may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and shaped like a gun can be used. Also, for example, in music games, a controller shaped like a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be equipped with cameras, depth sensors, microphones, etc., and operated by the game player's gestures or voice.

[0415] Furthermore, the video from the aforementioned game console can be output by display devices such as televisions, personal computer displays, game displays, and head-mounted displays.

[0416] By applying the semiconductor device described in the above embodiment to a portable game console 5200 or a home game console 7500, a low-power portable game console 5200 or a low-power home game console 7500 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0417] Furthermore, by applying the semiconductor device described in the above embodiment to a portable game console 5200 or a home game console 7500, it becomes possible to retain temporary files and other data necessary for calculations that occur during game execution.

[0418] Figure 18E shows a portable game console as an example of a game console. Figure 18F shows a home console for game use. However, the electronic devices of one aspect of the present invention are not limited to these. Examples of electronic devices of one aspect of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0419] [Mobile] The semiconductor device described in the above embodiment can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0420] Figure 18G shows an example of a mobile vehicle, the automobile 5700.

[0421] The driver's seat area of ​​the 5700 automobile is equipped with an instrument panel that provides various information by displaying the speedometer, tachometer, odometer, fuel gauge, gear status, and air conditioning settings. Additionally, a display device for showing this information may be provided around the driver's seat.

[0422] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for obstructed views from pillars and other obstructions, as well as blind spots in the driver's seat, thereby enhancing safety. In other words, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for, and safety can be enhanced.

[0423] The semiconductor device described in the above embodiment can temporarily hold information, and therefore can be used, for example, to hold necessary temporary information in systems that perform autonomous driving, road guidance, and hazard prediction for the automobile 5700. The display device may be configured to display temporary information such as road guidance and hazard prediction. Alternatively, it may be configured to hold video footage from a driving recorder installed in the automobile 5700.

[0424] While the above uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0425] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0426] Figure 18H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, a shutter button 6244, etc., and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. Furthermore, the digital camera 6240 may be configured to allow for the attachment of a strobe device, viewfinder, etc. separately.

[0427] By applying the semiconductor device described in the above embodiment to the digital camera 6240, a low-power digital camera 6240 can be realized. Furthermore, because the low power consumption reduces heat generation from the circuit, the impact of heat on the circuit itself, peripheral circuits, and modules can be minimized.

[0428] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0429] Figure 18I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, etc. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by a connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0430] When recording video captured by the video camera 6300, encoding is required according to the data recording format. By using the semiconductor device described above, the video camera 6300 can retain temporary files generated during encoding.

[0431] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter-defibrillator (ICD).

[0432] Figure 18J is a schematic cross-sectional view showing an example of an ICD. The ICD unit 5400 includes at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0433] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0434] The ICD unit 5400 functions as a pacemaker, pacing the heart if the heart rate falls outside the specified range. If pacing does not improve the heart rate (e.g., in cases of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0435] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store heart rate data acquired by the sensor, the number of times pacing treatment was performed, the duration, etc., in the electronic component 700.

[0436] Furthermore, the antenna 5404 can receive power, which is then used to charge the battery 5401. The ICD unit 5400 also benefits from having multiple batteries, thus enhancing safety. Specifically, even if some of the batteries in the ICD unit 5400 fail, the remaining batteries can still function, thus acting as an auxiliary power source.

[0437] In addition, the system may have an antenna capable of transmitting physiological signals, separate from the power receiving antenna 5404. For example, a system may be configured to monitor cardiac activity so that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0438] [Extension devices for PCs] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0439] Figure 19A shows an example of such an expansion device, an external expansion device 6100 for a PC, equipped with a portable chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to a PC, for example, via USB (Universal Serial Bus). Although Figure 19A illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with, for example, a cooling fan.

[0440] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with circuits for driving semiconductor devices and the like as described in the above embodiment. For example, electronic components 700 and a controller chip 6106 are mounted on the circuit board 6104. The USB connector 6103 functions as an interface for connecting to external devices.

[0441] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card that can be attached to electronic devices such as information terminals and digital cameras.

[0442] Figure 19B is a schematic diagram of the external appearance of an SD card, and Figure 19C is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, an electronic component 700 and a controller chip 5115 are mounted on the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the writing circuit, load driver, and read circuit provided in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 700.

[0443] By providing electronic components 700 on the back side of the circuit board 5113, the capacity of the SD card 5110 can be increased. Alternatively, a wireless chip with wireless communication capabilities may be provided on the circuit board 5113. This allows for wireless communication between an external device and the SD card 5110, enabling the reading and writing of data to and from the electronic components 700.

[0444] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0445] Figure 19D is a schematic diagram of the external appearance of the SSD, and Figure 19E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to external devices. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is equipped with a storage device and a circuit for driving the storage device. For example, electronic components 700, a memory chip 5155, and a controller chip 5156 are mounted on the circuit board 5153. The capacity of the SSD 5150 can be increased by also providing electronic components 700 on the back side of the circuit board 5153. Work memory is incorporated into the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 incorporates a processor, ECC circuitry, etc. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be modified as appropriate depending on the circumstances. For example, the controller chip 5156 may also be provided with memory that functions as work memory.

[0446] [Calculator] The computer 5600 shown in Figure 20A is an example of a large-scale computer. The computer 5600 houses multiple rack-mount type computers 5620 in rack 5610.

[0447] Computer 5620 can have a configuration as shown in the perspective view in Figure 20B, for example. In Figure 20B, computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0448] The PC card 5621 shown in Figure 20C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 20C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, for information on these semiconductor devices, please refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below.

[0449] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and the connector 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0450] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0451] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0452] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the wiring provided on the board 5622 using these terminals. Examples of semiconductor devices 5627 include FPGAs (Field Programmable Gate Arrays), GPUs, and CPUs. For example, an electronic component 730 can be used as the semiconductor device 5627.

[0453] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by soldering these terminals to the wiring on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5628 include memory devices. For example, an electronic component 700 can be used as the semiconductor device 5628.

[0454] Computer 5600 can also function as a parallel computer. By using Computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0455] By using a semiconductor device according to one aspect of the present invention in the various electronic devices described above, it is possible to miniaturize and reduce the power consumption of the electronic devices. Furthermore, because the semiconductor device according to one aspect of the present invention has low power consumption, it is possible to reduce heat generation from the circuit. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using a semiconductor device according to one aspect of the present invention, it is possible to realize electronic devices that operate stably even in high-temperature environments. Therefore, the reliability of electronic devices can be improved.

[0456] This embodiment can be appropriately combined with other embodiments shown herein. [Explanation of Symbols]

[0457] 10: Semiconductor device, 20: Memory array, 21: Drive circuit, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sense amplifier, 47: Input circuit, 48: Output circuit, 51: Curve, 52: Curve, 100: Transistor, 110: Capacitive element

Claims

1. A first electrode, a first insulator, a second insulator, A transistor having a gate, a back gate, and a semiconductor, It has a capacitive element having a pair of electrodes, The back gate has a region that overlaps with the semiconductor via the first insulator and the second insulator. The source or drain of the transistor is electrically connected to the first electrode. The source or drain of the transistor is electrically connected to one of the pair of electrodes. Each of the pair of electrodes is in contact with the first insulator and has a region that overlaps with the first insulator. The first insulator is a ferroelectric, A semiconductor device in which the other electrode of the pair and the back gate are provided on the same insulator.

2. Multiple layers stacked together, A first electrode penetrating the aforementioned multiple layers, It has, Each of the aforementioned layers is A first insulator and a second insulator, A transistor having a gate, a back gate, and a semiconductor, It has a capacitive element having a pair of electrodes, The back gate has a region that overlaps with the semiconductor via the first insulator and the second insulator. The source or drain of the transistor is electrically connected to the first electrode. The source or drain of the transistor is electrically connected to one of the pair of electrodes. Each of the pair of electrodes is in contact with the first insulator and has a region that overlaps with the first insulator. The first insulator is a ferroelectric, A semiconductor device in which the other electrode of the pair and the back gate are provided on the same insulator.

3. In claim 1 or 2, The first insulator is a semiconductor device comprising hafnium, zirconium, and oxygen.

4. In either claim 1 or 2, The first insulator is a semiconductor device comprising aluminum, scandium, and nitrogen.

5. In either claim 1 or 2, The second insulator is a semiconductor device comprising silicon and oxygen.

6. In either claim 1 or 2, Each of the pair of electrodes is a semiconductor device containing titanium and nitrogen.

7. In either claim 1 or 2, The semiconductor is an oxide semiconductor.

8. In either claim 1 or 2, The semiconductor device comprises at least one of indium and zinc, and oxygen.

Images