Method for producing semiconductor devices and semiconductor devices

Abstract

Method for generating a semiconductor device and semiconductor device According to one embodiment, the method includes providing a semiconductor body (1) having an upper surface (10). A mask (2) is deposited on the upper surface of the semiconductor body, and the mask includes at least one first section (21) and at least one second section (22). The at least one second section is laterally adjacent to the at least one first section. The mask is thicker in the at least one second section than in the at least one first section. In a further step, a channel region (11) of a first conductivity type is formed in the semiconductor body (1) within the region of the at least one first section. Forming the channel region includes implanting a dopant of the first type into the semiconductor body through the upper surface. In a further step, an auxiliary layer (3) is deposited on a side surface (22a) of the at least one second section, the side surface facing the at least one first section. Thereby, the lateral extent of the at least one second section is increased and the lateral extent of the at least one first section is decreased. In a further step, a hole is generated in the semiconductor body in the region of the first section with a reduced lateral extent such that the hole extends from the upper surface through the channel region.

Description

[Technical Field]

[0001] This disclosure relates to a method for producing a semiconductor device and to a semiconductor device. [Background technology]

[0002] U.S. Patent Application Publication No. 2012 / 0146090 relates to a transistor device that can be fabricated with an integrated diode using self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulating gate electrodes formed in trenches within the substrate. One or more body regions are formed on the upper surface of the substrate adjacent to each gate trench. One or more source regions are formed self-aligned on the upper surface of the substrate adjacent to each gate trench. One or more thick insulating portions are formed on the gate electrodes on the upper surface of the substrate, spaced apart between adjacent thick insulating portions. A metal is formed on the substrate above the thick insulating portions. The metal forms self-aligned contacts to the substrate through the spaces between the thick insulating portions. An integrated diode is formed beneath the self-aligned contacts.

[0003] U.S. Patent Application Publication No. 2012 / 0164810 relates to a method for manufacturing a silicon carbide semiconductor device. A first impurity region is formed by ion implantation through a first opening formed in a mask layer. A mask portion having a mask layer and a spacer layer is formed by depositing a spacer layer on an etching stop layer on which the mask layer is provided. A second opening surrounded by a second sidewall is formed in the mask portion by anisotropic etching of the spacer layer. A second impurity region is formed by ion implantation through the second opening. The angle of the second sidewall with respect to the surface is 90°±10° over the same height as the second depth. This improves the accuracy of impurity region expansion. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] The objective is to provide an improved method for manufacturing semiconductor devices, such as a method with a reduced number of manufacturing steps and / or a method that enables the manufacturing of smaller structures. A further objective is to provide an improved semiconductor device having, for example, a smaller structure. [Means for solving the problem]

[0005] Embodiments of this disclosure relate to improved methods for producing semiconductor devices and improved semiconductor devices.

[0006] Firstly, a method for producing semiconductor devices is described. According to one embodiment, a method for producing a semiconductor device includes the step of providing a semiconductor body having a top surface. A mask is deposited on the top surface of the semiconductor body, and the mask includes at least one first compartment and at least one second compartment. The at least one second compartment is adjacent to the at least one first compartment in the lateral direction. The mask is thicker in the at least one second compartment than in the at least one first compartment. In a further step, a channel region of a first conductivity type is formed within the semiconductor body in the region of the at least one first compartment. Forming the channel region includes injecting a dopant of the first type into the semiconductor body through the top surface. In a further step, an auxiliary layer is deposited on the side surface of the at least one second compartment, the side surface facing the at least one first compartment. This increases the lateral extension of the at least one second compartment and decreases the lateral extension of the at least one first compartment. In a further step, holes are generated in the semiconductor body in a region of the first section where the lateral extension range is reduced, so that the holes extend from the top surface through the channel region.

[0007] The superior properties of wide-bandgap semiconductors (WBGs), such as high critical field and electron mobility or high-frequency switching, result in a much larger Barriger figure of merit compared to commonly used silicon, making them ideal materials for power switches. This enables several applications for energy efficiency and electrical transport.

[0008] Today, most commercially available power SiC-MOSFETs are based on a cell design with a planar channel aligned to the Si plane, i.e., the surface of the SiC(0001) wafer. However, boosting current density in such switches is hindered by junction-FET (JFET) resistance, which increases with injector downscaling, and low inversion channel mobility. On the other hand, trench MOSFETs exhibiting a dry-etched U-shaped channel allow for low on-resistance due to the absence of a JFET region and higher cell density. Particularly for SiC channel devices, the trench MOSFET architecture allows for optimization of carrier mobility by designing the channel for multiple different crystal planes and improving gate dielectric control.

[0009] Nevertheless, current trench cell designs do not fully utilize the aforementioned advantages. Despite utilizing multiple different crystal planes for carrier transport, the trench pitch and width of the cell remain considerably large, thus hindering the maximum scaled cell density and, consequently, the high current density of the device.

[0010] The method disclosed herein enables self-aligned channel injection and trench etching, thus replacing two separate lithography steps. As a result, fewer manufacturing steps are required, and smaller structures can be produced. This method is suitable for the fabrication of various semiconductor devices such as MOSFTs, IGBTs, JFETs, or MISFETs.

[0011] The semiconductor body may be based on materials such as Si, SiC, GaN, or Ga2O3. The semiconductor body may also be based on a wide-bandgap material. The semiconductor body may comprise a doped substrate and a doped drift layer on the substrate. The upper surface of the semiconductor body may be at least partially formed by the drift layer. For example, the substrate may have a higher doping concentration than the drift layer. The substrate and the drift layer may have the same conductivity type. Both may be either n-doped or p-doped.

[0012] In the step of providing a semiconductor body, the upper surface of the semiconductor body may be a flat surface without interruptions, recesses, or holes.

[0013] The mask may be produced using a lithography process. For example, the mask includes a photoresist. In at least one second section, the mask is thicker than in at least one first section. This could mean that the thickness of the mask in at least one first section is zero, for example, so that the top surface of the semiconductor body is exposed in the area of ​​at least one first section. Alternatively, the mask may have a thickness of at least one first section that is greater than zero but less than the thickness of at least one second section. In either case, a step is formed between at least one first section and at least one second section. This step forms a side of the second section facing at least one first section.

[0014] The thickness of the mask is measured in a direction perpendicular to the top surface. In this specification, “thickness” means the average of the maximum thicknesses. For example, the thickness of the mask in at least one second section is at least twice, at least five times, at least ten times, or at least 100 times greater than the thickness in at least one first section.

[0015] The mask comprises at least one first section, i.e., one or more first sections, and at least one second section, i.e., one or more second sections. All features disclosed herein for one first section are disclosed for all first sections, and similarly, all features disclosed herein for one second section are disclosed for all second sections.

[0016] For simplicity, the expression "at least one" is also referred to herein simply as "the".

[0017] For example, the mask comprises one second section forming a web and several first sections each within the mesh of the web. Alternatively, the mask may comprise one first section forming a web and several second sections each within the mesh of the web. A further alternative is that the mask comprises several first sections and several second sections, with each first section being in the lateral direction between two second sections.

[0018] At least one first section is adjacent in the lateral direction to at least one second section. In particular, at least one second section is adjacent in the lateral direction to at least one first section. The step between the first section and the second section indicates, for example, the boundary between the first section and the second section. The second section may completely surround at least one first section in the lateral direction. Alternatively, the first section may be between two second sections in a first lateral direction. In this specification, the lateral direction is understood as a direction parallel to the upper surface of the semiconductor body and / or parallel to the main extension plane.

[0019] The step of forming the channel region is performed after the step of depositing a mask on the upper surface. Forming the channel region includes implanting a first-type dopant through the upper surface of the semiconductor body. The first-type dopant is either a p-type dopant or an n-type dopant. The second-type dopant is different herein from the first-type dopant, i.e., either an n-type dopant or a p-type dopant. For example, the first-type dopant is boron and the second-type dopant is arsenic or phosphorus.

[0020] Forming the channel region can further include an annealing step that is performed after implanting the first-type dopant. During the annealing step, the implanted first-type dopant further diffuses within the semiconductor body, resulting in the channel region spreading into the semiconductor body.

[0021] The channel region is of the first conduction type. When the first-type dopant is a p-type dopant, the first conduction type is hole conduction. That is, the channel region is p-doped. When the first-type dopant is an n-type dopant, the first conduction type is electron conduction, i.e., the channel region is n-doped. The second conduction type is different herein from the first conduction type.

[0022] The channel region is formed within the region of at least one first section, i.e., under at least one first section. During implantation, the dopant can abut the mask over its entire lateral extent, i.e., also in the region of at least one second section. However, because the thickness of the mask in at least one second section is greater, less dopant is implanted into the semiconductor body in the region of the second section. The amount of the first-type dopant implanted into the region of the second section is, for example, not sufficient to form a region of the first conduction type under the second section.

[0023] The channel region extends, for example, at least 50 nm and / or at most 1 μm into the semiconductor body (depth of the channel region) from the upper surface.

[0024] The step of depositing an auxiliary layer on the side of at least one second compartment is performed after the channel region is formed. As described above, the side of at least one second compartment may be formed by a step between at least one second compartment and at least one first compartment. Thus, the side extends obliquely, for example, perpendicularly or nearly perpendicularly with respect to the top surface.

[0025] Due to the auxiliary layer, the width or lateral extension of the second compartment increases, while the width or lateral extension of the first compartment decreases. In other words, by depositing the auxiliary layer on the sides of the mask (also referred to as the initial mask), the mask is complemented by the deposited auxiliary layer and thus transformed into a new mask comprising the initial mask and the deposited auxiliary layer, having a narrower / smaller first compartment and a wider / larger second compartment.

[0026] The thickness of the auxiliary layer on the side surface of at least one second compartment is, for example, at least 50 nm and at most 1 μm. Thus, the lateral extension of at least one second compartment is increased by at least this thickness, for example by about twice this thickness, and the lateral extension of at least one first compartment is decreased by at least this thickness, for example by about twice this thickness.

[0027] The material of the auxiliary layer is different from, for example, the material of the initial mask. For example, the auxiliary layer contains or consists of SiO2, SiN, or polysilicon.

[0028] The step of generating holes within the semiconductor body is performed after the auxiliary layer is deposited. The holes are generated within the region of the first compartment, which has a reduced lateral extension. During hole generation, the semiconductor body beneath the second compartment, which has an increased lateral extension, may be protected by the second compartment with the increased lateral extension, and as a result, the holes are actually formed only within the region of the first compartment with a reduced lateral extension.

[0029] Due to the reduced lateral extension of the first section, the resulting hole has a smaller lateral extension or width than the previously formed channel region. Therefore, the hole is formed through the channel region. For example, the hole is adjacent to the channel region in the lateral direction. For example, the hole is completely surrounded by the channel region in the lateral direction, or the channel region is adjacent to the hole on both sides with respect to the first lateral direction.

[0030] For example, the generated pores protrude deeper into the semiconductor body than the channel region, for example, at least 1.5 times deeper. As an example, the pore depth is at least 500 nm and / or up to 2 μm.

[0031] In a further embodiment, after forming the channel region and before depositing the auxiliary layer, an additional auxiliary layer is deposited on the side of at least one second compartment, which increases the lateral extension of at least one second compartment and decreases the lateral extension of at least one first compartment. Since the additional auxiliary layer is deposited before the auxiliary layer, the additional auxiliary layer is also referred to herein as the first auxiliary layer, and therefore the auxiliary layer is also referred to herein as the second auxiliary layer.

[0032] Therefore, in this method, the lateral extension of the second section of the mask may be doubled, and the lateral extension of the first section of the mask may be doubled. In other words, the initial mask is transformed twice into each new mask such that the first section becomes narrower / smaller and the second section becomes wider / larger each time.

[0033] The thickness of the additional auxiliary layer on the side of at least one second compartment may be within the same range as the thickness of the auxiliary layer on the side. The additional auxiliary layer may be made of a different material from the auxiliary layer and / or mask. For example, the additional auxiliary layer may contain or consist of SiO2, SiN, or polysilicon.

[0034] According to a further embodiment, a second type of conductive contact region is formed within the semiconductor body in the region of the first compartment after and before the deposition of an additional auxiliary layer. The contact region is formed so as to be located between the channel region and the upper surface of the semiconductor body. The formation of the contact region involves injecting a second type of dopant into the semiconductor body through the upper surface.

[0035] The formation of the contact region may include an annealing process after injection of the second type of dopant. During the annealing process, the second type of dopant further diffuses into the semiconductor body, resulting in the contact region extending further into the semiconductor body.

[0036] The contact region is formed at least partially from the previously formed channel region. Therefore, the amount of the second type of dopant injected is sufficient to convert a portion of the channel region, which is of the first conductivity type, to the second conductivity type.

[0037] During the injection of the second type of dopant, the lateral extension of the first compartment is reduced compared to the lateral extension of the first compartment during the injection of the first type of dopant; therefore, the contact region has a smaller lateral extension than the channel region. Thus, laterally, the contact region is surrounded by or adjacent to the channel region on both sides with respect to the first lateral direction.

[0038] The depth of the contact region is less than the depth of the channel region, for example, so that the contact region is located between the channel region and the top surface. In other words, in the vertical direction perpendicular to the top surface, the contact region is positioned between the channel region and the top surface.

[0039] According to further embodiments, the pore is formed through the contact region. For example, the pore is adjacent to the contact region in the lateral direction. Since the lateral extension of the first compartment during pore formation is smaller than the lateral extension of the first compartment during injection of the second type of dopant, the lateral extension of the pore is smaller than the lateral extension of the contact region. For example, the pore is completely surrounded by the contact region in the lateral direction, or the contact region is adjacent to the pore on both sides with respect to the first lateral direction. For example, in the first lateral direction, the contact region is located between the pore and the channel region.

[0040] By forming a pore, a channel region and / or contact region formed in the region of at least one first compartment may be divided into two channel regions and / or contact regions. All features disclosed herein and below with respect to one channel region or one contact region within the region of at least one first compartment are also disclosed with respect to two contact regions or two channel regions within the region of at least one first compartment.

[0041] In a further embodiment, the auxiliary layer is deposited by a conformal, i.e., undirected deposition process. As a result, the sides of at least one second compartment, the top surface of at least one second compartment, and a region of the first compartment are covered by the auxiliary layer. For example, within the region of the first compartment, the top surface of the semiconductor body is covered by the auxiliary layer. The auxiliary layer may be deposited, for example, by chemical vapor deposition, abbreviated as CVD.

[0042] In a further embodiment, after the deposition of the auxiliary layer, a directional material removal process is applied in which more of the auxiliary layer is removed in the region of the first compartment and the upper surface of the second compartment than in the side surface of at least one second compartment. The removal process may be an etching process, such as a dry etching process, such as a plasma etching process. The directional material removal process is also known as an anisotropic material removal process.

[0043] After the material removal process, at least one side of the second compartment is still covered by at least the remainder of the previously deposited auxiliary layer. However, a region of at least one first compartment having a reduced lateral extension, and / or the upper surface of at least one second compartment, may be exposed after the directional material removal process. Holes are formed, for example, after the directional material removal process is carried out. For example, the specified thickness of the auxiliary layer on the side relates to the thickness after the material removal process.

[0044] The same disclosures made for auxiliary layers with respect to conformal deposition processes are disclosed, and the subsequent directional material removal process may also be performed for further auxiliary layers. The injection of a second type of dopant is performed, for example, after the directional material removal process applied to further auxiliary layers.

[0045] According to at least one embodiment, a protective layer is deposited on the semiconductor body in at least one first compartment region before depositing an auxiliary layer and / or before depositing any further auxiliary layers. The protective layer is configured to protect the semiconductor body when the (further) auxiliary layers are removed by a directional material removal process. For example, the protective layer is an etch stop layer that prevents etchants from reaching the semiconductor body.

[0046] In further embodiments, before the mask is applied, the semiconductor body is of the second conductivity type, at least on its upper surface. For example, the entire upper surface is of the second conductivity type. In particular, the drift layer of the semiconductor body may be of the second conductivity type. The substrate may also be of the second conductivity type.

[0047] According to a further embodiment, during the injection of the first type of dopant, at least one second compartment protects the semiconductor body below from the first type of dopant such that the semiconductor body remains in a second conductivity type on its upper surface within the region of at least one second compartment. In other words, the amount of first type of dopant reaching the semiconductor body in the region of at least one second compartment is not sufficient to change the conductivity type of the semiconductor body.

[0048] According to further embodiments, the method further includes the step of forming an electrically insulating layer on the surface of the pore. The insulating layer is, for example, SiO2. The insulating layer may be formed by filling the pore with an electrically insulating material or by oxidation of the surface of the pore. The surface of the pore is in particular the side and / or bottom surface formed by the semiconductor body that defines the pore.

[0049] According to a further embodiment, the method further includes forming a gate electrode on and / or in at least one hole such that the gate electrode is electrically insulated from the semiconductor body by an electrical insulating layer. The gate electrode may include, or consist of, at least one of metals such as Cu, Al, Au, Ag or alloys thereof, or highly doped polysilicon.

[0050] The formation of the electrical insulating layer and / or gate electrode may be carried out while the mask is still on the upper surface of the semiconductor body.

[0051] According to further embodiments, the method includes the step of removing a mask. During mask removal, auxiliary layers and / or further auxiliary layers may be removed along with the initial mask.

[0052] In a further embodiment, the method includes the step of forming a main electrode on the upper surface such that the main electrode is adjacent to the semiconductor body and electrically connected in a region adjacent to at least one hole in the lateral direction. In particular, this step is performed after removing the mask such that the main electrode is adjacent to the upper surface of the semiconductor body in a region where at least one second section of the mask previously covered the upper surface.

[0053] The main electrode is a metal such as Cu, Al, Au, Ag, or an alloy thereof. For example, the main electrode is electrically insulated from the gate electrode by an electrical insulating layer. The main electrode may be adjacent to the contact region and the channel region, and may be in electrical contact with them. For example, an ohmic contact is formed between the main electrode and the contact region and / or the channel region.

[0054] In a further embodiment, the main electrode is adjacent to at least one diode region of the semiconductor body on its upper surface. The diode region is of a second conductivity type. For example, the diode region is a region of the semiconductor body that has been previously covered and thus protected by at least one second section of the mask. The diode region may be formed by a drift layer. For example, the diode region and the main electrode together form a Schottky diode, which is also referred to as a JBS diode. This forms a Schottky contact between the main electrode and the diode region.

[0055] In the first lateral direction, the contact region and the channel region may be located between the hole and the diode region. The diode region may be adjacent to the channel region in the first lateral direction.

[0056] In a further embodiment, an additional mask is applied to the upper surface of the semiconductor body before the mask is applied. The additional mask may also include a photoresist and may be formed by lithography.

[0057] In a further embodiment, at least one plug region of a first conductivity type is formed within the semiconductor body by using an additional mask. Forming at least one plug region may also involve injecting a dopant of the first type into the semiconductor body through the top surface. After injection, an annealing process may be performed to further expand the plug region within the semiconductor body.

[0058] According to a further embodiment, at least one plug region is formed at least partially in a region adjacent to the upper surface and subsequently covered by at least one second section of the mask.

[0059] The plug region may also be located within the region of the first compartment of the mask to be subsequently applied. For example, during the injection of the second type of dopant, the plug region within the region of the first compartment of the mask is converted to the second conductive type and thus becomes part of the contact region.

[0060] According to further embodiments, the doping concentration in at least one plug region is greater than that in the channel region. When referring to doping concentrations in different regions, in each case, the average or maximum doping concentration of the region is intended.

[0061] For example, at least one plug region has a doping concentration at least one order of magnitude greater than the doping concentration in the channel region. The doping concentration in the plug region is, for example, 10 18 cm -3 ~10 19 cm -3 The doping concentration in the channel region is, for example, 10 16 cm -3 ~10 18 cm -3 That is the case.

[0062] The doping concentration in the contact region is, for example, at least one order of magnitude greater than the doping concentration in the drift layer and / or the diode region and / or the channel region.18 cm -3 ~10 19 cm -3 It is. The doping concentration of the drift layer and / or the diode region is, for example, 10 15 cm -3 ~10 17 cm -3 It is.

[0063] According to a further embodiment, the mask includes a plurality of strip-shaped first sections and a plurality of strip-shaped second sections. For example, the first section is formed between every two second sections. Similarly, the second section may be formed between every two first sections. For example, the first section and the second section are alternately arranged side by side in a first lateral direction.

[0064] The first section and the second section are strip-shaped, that is, elongated. For example, the second section is formed as a rib. The main extension directions of the first section and the second section may extend parallel to each other. For example, each of the first section and the second section extends in a second lateral direction perpendicular to the first lateral direction.

[0065] According to a further embodiment, channel regions and holes are formed in some or each region of the first section. Each channel region may be formed in a strip shape, and each hole may be formed as a trench. The strip-shaped channel regions and trenches may all extend in the second lateral direction. When forming the trenches, each of the strip-shaped channel regions is separated from each other in the first lateral direction and divided into two strip-shaped channel regions.

[0066] Similarly, strip-shaped contact regions may be formed in the region of each first section. The strip-shaped contact regions, for example, extend in the second lateral direction. When forming the trenches, each of the strip-shaped contact regions is separated from each other in the first lateral direction and divided into two strip-shaped contact regions.

[0067] All features disclosed herein for the formation of channel regions and / or contact regions and / or pores within the region of at least one first compartment are also disclosed for the formation of all other channel regions and / or contact regions and / or pores within the region of further first compartments of the mask.

[0068] According to further embodiments, multiple plug regions are formed. All features disclosed in relation to at least one plug region are also disclosed for all other plug regions.

[0069] In a further embodiment, each plug region is formed in a stripe shape, i.e., elongated.

[0070] In a further embodiment, the plug region extends obliquely to the channel region. For example, the plug region extends perpendicularly to the channel region. The plug regions may extend in a first lateral direction, or they may be spaced apart from each other in a second lateral direction. For example, all plug regions extend parallel to each other.

[0071] Next, a semiconductor device is described. The semiconductor device may be produced using a method according to any one of the embodiments disclosed herein. Thus, all the features disclosed in this method are also disclosed for semiconductor devices, and vice versa.

[0072] According to one embodiment, the semiconductor device comprises a semiconductor body having a top surface. At least one hole extends from the top surface into the semiconductor body. The at least one hole defines an active region of the semiconductor body in a first lateral direction parallel to the top surface. The active region includes at least one channel region which is of a first conductivity type and at least one contact region which is of a second conductivity type. The at least one channel region and the at least one contact region are adjacent to the at least one hole in the first lateral direction. The at least one contact region is embedded in the at least one channel region such that, in a vertical direction perpendicular to the top surface, the at least one contact region is positioned between the top surface and the at least one channel region and is adjacent to the top surface in the vertical direction. The width of the active region, measured in the first lateral direction, is up to three times the depth of the at least one hole, measured in the vertical direction.

[0073] Active regions having such an aspect ratio (width / depth) can be generated using the methods described herein. For example, the width of the active region is up to twice the depth of at least one pore, or up to the depth of at least one pore.

[0074] The active region of a semiconductor device is the region where charge carriers are transported during operation. For example, the active region is formed between two pores and is defined by the two pores in a first lateral direction. The active region is, for example, a continuous region of the semiconductor body.

[0075] A semiconductor device may comprise several active regions that are laterally separated from each other by one or more pores. All features disclosed for one active region are also disclosed for all other active regions.

[0076] According to further embodiments, the width of the active region is up to 3 μm, or up to 2.5 μm, or up to 2 μm, or up to 1.5 μm, or up to 1 μm.

[0077] According to a further embodiment, the semiconductor device further comprises a main electrode on the upper surface within the active region.

[0078] In a further embodiment, the active portion includes at least one diode region, the at least one of which is of a second conductivity type. The at least one diode region may be adjacent to the upper surface of the semiconductor body in the vertical direction.

[0079] In a further embodiment, the main electrode is adjacent to and electrically in contact with at least one contact region. Additionally, the main electrode may be adjacent to and electrically in contact with at least one diode region and / or at least one channel region.

[0080] According to a further embodiment, the surface of at least one hole is at least partially covered by an electrical insulating layer. The surface of the hole is formed by a semiconductor body. For example, the sides and bottom of the hole are covered by an electrical insulating layer.

[0081] According to a further embodiment, the gate electrode is formed on and / or in at least one hole and is electrically insulated from the semiconductor body by an insulating layer.

[0082] According to a further embodiment, the active region includes at least one plug region, the at least one plug region being of a first conductivity type and adjacent to the upper surface. For example, the at least one plug region has a higher doping concentration than the at least one channel region.

[0083] According to further embodiments, the semiconductor device is a power semiconductor device. The semiconductor device is, for example, a MOSFET, IGBT, JFET, or MISFET. Further main electrodes may be applied to the bottom surface of the semiconductor body, which is opposite the top surface. The power semiconductor device may be configured such that the voltage difference between the main electrodes and the further main electrodes is at least 1 kV, for example, at least 1.2 kV or at least 3.3 kV.

[0084] In the case of MISFETs, JFETs, or MOSFETs, the contact region is also referred to as the source region. In the case of IGBTs, the contact region is also referred to as the emitter region.

[0085] According to a further embodiment, the semiconductor device comprises a plurality of holes, each formed as a trench. The trenches are spaced apart from one another in a first transverse direction. Each trench extends in a second transverse direction. The first and second transverse directions are, for example, orthogonal to each other.

[0086] According to a further embodiment, the semiconductor device comprises a plurality of active regions, each active region being located between a pair of trenches. Thus, in the first lateral direction, one active region is formed between each pair of trenches.

[0087] In a further embodiment, each active region includes at least two elongated channel regions, for example, striped channel regions. The channel regions extend in a second lateral direction. Furthermore, each active region includes at least two elongated contact regions, for example, striped contact regions. Each contact region extends in a second lateral direction. The contact regions may be spaced apart from each other in a first lateral direction. Similarly, the channel regions may be spaced apart from each other in a first lateral direction.

[0088] The lengths of the trench, contact area, and / or channel area measured along the second lateral direction may all be the same.

[0089] In a further embodiment, the channel region and contact region of each active region are adjacent to a trench defining the active region. Thus, in each active region, one contact region and one channel region are adjacent to a trench defining the active region on one side with respect to the first lateral direction, and further channel regions and further contact regions are adjacent to trenches defining the active region on the other side with respect to the first lateral direction.

[0090] According to a further embodiment, the width of the active region is the distance between two trenches that define the active region in the first lateral direction.

[0091] The following describes, based on exemplary embodiments, a method for producing a semiconductor device and the semiconductor device itself, with reference to the drawings. The accompanying drawings are included for further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to actual size. The description of each of the following drawings will not be repeated to the extent that elements or components correspond to each other in terms of their function in different drawings. For clarity, elements may not be shown with corresponding reference numerals in all drawings. [Brief explanation of the drawing]

[0092] [Figure 1] This is a flowchart illustrating an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 2] This is a flowchart illustrating an exemplary embodiment of a method for manufacturing semiconductor devices. [Figure 3] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 4] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 5]This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 6] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 7] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 8] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 9] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 10] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 11] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 12] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 13] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 14] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 15] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 16] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 17] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 18] This figure shows one of the different locations in an exemplary embodiment of a method for manufacturing a semiconductor device. [Figure 19] This figure shows an exemplary embodiment of a semiconductor device. [Modes for carrying out the invention]

[0093] Figure 1 shows a flowchart of a first exemplary embodiment of a method for producing a semiconductor device. In step S1, a semiconductor body having a top surface is provided. Next, in a second step S2, a mask is deposited on the top surface, the mask comprising at least one first compartment and at least one second compartment laterally adjacent to the at least one first compartment. The mask is thicker in the at least one second compartment than in the at least one first compartment. In step S3, at least one channel region of a first conductivity type is formed in the semiconductor body in the region of the at least one first compartment, and forming the channel region includes injecting a dopant of the first type into the semiconductor body through the top surface. In step S4, an auxiliary layer is deposited on the side of the at least one second compartment facing the at least one first compartment to increase the laterally extending extent of the at least one second compartment and decrease the laterally extending extent of the at least one first compartment. In step S5, holes are formed in the semiconductor body in a region of at least one first compartment in which the lateral extension range is reduced, such that at least one hole extends from the top surface through the channel region.

[0094] Figure 2 shows a flowchart of a second exemplary embodiment of a method for producing a semiconductor device. Steps S1 to S5 are the same as in the first exemplary embodiment. After step S1, step S6 is performed in which an additional mask is applied to the upper surface of the semiconductor body. In step S7, at least one plug region of a first conductivity type is formed in the semiconductor body by using the additional mask. Subsequently, the additional mask is removed and steps S2 and S3 are performed. After step S3 in which the channel region is formed, step S8 is performed in which an additional auxiliary layer is deposited on the side of at least one second compartment of the mask to increase the lateral extension of at least one second compartment and decrease the lateral extension of at least one first compartment. Then, in step S9, a contact region of a second conductivity type is formed in the semiconductor body in the region of the first compartment such that the contact region is between the channel region and the upper surface of the semiconductor body. Forming the contact region involves injecting a dopant of the second type through the upper surface. The contact region is of the second conductivity type. Subsequently, steps S4 and S5 are carried out. After step S5, in which the holes are formed, in step S10, an electrical insulating layer is formed on the surface of at least one hole. Then, in step S11, a gate electrode is formed on and / or inside at least one hole, and the gate electrode is electrically insulated from the semiconductor body by the electrical insulating layer. In step S12, the mask is removed, and in step S13, a main electrode is formed on the upper surface of the semiconductor body.

[0095] Here, Figures 3 to 18 show exemplary embodiments of a method for producing semiconductor devices based on various positions in the method. In this exemplary embodiment, the first type dopant is a p-type dopant, and therefore the first conductivity type is hole conduction. The second type dopant is an n-type dopant, and therefore the second conductivity type is electron conduction. However, the method can also be carried out with the first type dopant being an n-type dopant and the second type dopant being a p-type dopant.

[0096] Figure 3 shows a semiconductor body 1. The semiconductor body 1 is based on a wide bandgap material such as SiC. The semiconductor body 1 comprises an n-doped substrate 19 and an n-doped drift layer 18 on the substrate 19. The doping concentration in the substrate 19 is greater than the doping concentration in the drift layer 18. For example, in the drift layer 18, the doping concentration is 10 15 cm -3 ~10 17 cm -3 The drift layer 18 forms the upper surface 10 of the semiconductor body 1.

[0097] Figure 3 also illustrates several different directions used herein. Hereinafter, the transverse direction is defined as the direction parallel to the top surface 10 or principal extension plane of the semiconductor body 1. In Figure 3, the first transverse direction Q is perpendicular to the plane of paper, and the second transverse direction L is parallel to the plane of paper. The perpendicular direction V is perpendicular to the top surface 10 or principal extension plane and is also parallel to the plane of paper in Figure 3.

[0098] Figure 4 shows the position in the method for which a first mask 8, also referred to herein as a further mask 8, is applied to the upper surface 10 of the semiconductor body 1. The mask 8 comprises a first section 81 in which the upper surface 10 is exposed and a second section 82 in which the upper surface 10 is covered by the mask material. For example, the mask 8 is produced by using photolithography. The mask material of the first mask 8 may be a photoresist.

[0099] Figure 5 shows the location where a first type of dopant, i.e., a p-type dopant such as boron, is injected into the semiconductor body 1 through the top surface 10. This creates a plug region 14 within the region of the first compartment 81 of the first mask 8. Thus, the plug region 14 is a p-doped region. Therefore, the amount of p-type dopant injected is so large that the previously n-doped semiconductor material below the first compartment 81 of the first mask 8 is converted into p-doped semiconductor material.

[0100] A certain amount of p-type dopant may reach through the second compartment 82 of the first mask 8 and be contained within the semiconductor body 1 below the second compartment 82. However, the shielding or protection by the second compartment 82 is efficient enough that the amount of p-type dopant reaching the semiconductor body 1 is not sufficient to convert the n-doped semiconductor material to a p-doped material. As a result, the plug region 14 is formed only within the region of the first compartment 81 of the first mask 8. In the region of the second compartment 82, the semiconductor body 1 remains n-doped.

[0101] The formation of the plug region 14 may include an annealing process after or during the injection process, resulting in further drift of the injected p-type dopant into the semiconductor body 1, causing further expansion of the plug region 14. The doping concentration of the plug region 14 after annealing is, for example, 10 18 cm -3 ~10 19 cm -3 That is the case.

[0102] In contrast to what is shown in Figure 5, the plug region 14 may also be formed within a trench. For this purpose, a trench may be formed within the semiconductor body 1 in the region of the first compartment 81, and then a p-type dopant may be injected into the semiconductor body 1 in the region of the trench. In this way, the plug region 14 is made to extend more deeply within the semiconductor body 1.

[0103] Figure 6 shows the semiconductor body 1 in a plan view relative to the top surface 10 after the first mask 8 has been removed. As can be seen here, the plug regions 14 are elongated stripe-shaped regions, each extending in the first lateral direction Q and spaced apart from one another in the second lateral direction L.

[0104] Figure 7 shows a further position of the method. Here again, a plan view of the top surface 10 of the semiconductor body 1 is shown. In Figure 7, a second mask 2, also referred to herein simply as mask 2, is applied to the top surface 10 of the semiconductor body 1. The second mask 2 comprises a first section 21 and a second section 22. In the first section 21, the top surface 10 of the semiconductor body 1 is exposed. However, in the second section 22, the top surface 10 is covered by the mask material. The second mask 2 may, again, be produced by photolithography. The mask material may be a photoresist.

[0105] The first section 21 and the second section 22 are elongated, stripe-like structures that extend along the second lateral direction L. In the first lateral direction Q, the first section and the second section 22 are arranged alternately.

[0106] Figure 8 again shows a cross-sectional view of the semiconductor body 1, but this is a rotated view compared to Figures 3 to 5, where the second transverse direction L is perpendicular to the plane of the paper, and the first transverse direction Q is parallel to the plane of the paper.

[0107] Figure 8 shows the location where a first type of dopant, i.e., a p-type dopant, is injected through the top surface 10. In the first compartment 21, the semiconductor body 1 is not protected by the mask 2. Therefore, the amount of p-type dopant injected into the semiconductor body 1 is greater in the region of the first compartment 21 than in the region of the second compartment 22. As a result, a channel region 11 is formed within the region of the first compartment 21. The channel region 11 is of the first conductivity type, i.e., hole conduction or p-doping. In other words, the amount of p-type dopant injected is sufficient to convert the previously n-doped semiconductor material in the region of the first compartment 21 to a p-doped semiconductor material. In the region of the second compartment 22, the amount of p-type dopant injected is not sufficient to change the doping type. The formation of the channel region 11 may also involve an additional annealing process.

[0108] Figure 9 shows the location of the method in which the first auxiliary layer 4, also referred to herein as a further auxiliary layer, is deposited on the initial mask 2. The first auxiliary layer 4 covers the upper surface of the semiconductor body 1 in the region of the first compartment 21, the upper surface of the initial mask 2 in the region of the second compartment 22, and also the side surface 22a of the second compartment 22. The side surface 22a extends perpendicularly to the upper surface 10 and is formed by the steps between the first compartment 21 and the second compartment 22 of the initial mask 2, respectively. Conformal or omnidirectional deposition processes, such as CVD, are used to deposit the first auxiliary layer 4. The first auxiliary layer 4 contains, for example, SiN or SiO2, or consists of them.

[0109] Figure 10 shows further locations of the method in which a directional material removal process, such as dry etching, is used to remove material from the first auxiliary layer 4 within the region of the first section 21 and on the upper surface of the second section 22. The directional material removal process does not remove, or does not completely remove, material from the first auxiliary layer 4 on the side surface 22a of the second section 22. As a result, at least a portion of the first auxiliary layer 4 remains on the side surface 22a of the second section 22. Thus, the second section 22 becomes effectively wider, i.e., their lateral extension in the first lateral direction Q increases, and the first section 21 becomes effectively narrower, i.e., their lateral extension in the first lateral direction Q decreases. The thickness of the remaining portion of the first auxiliary layer 4 on the side surface 22a of the second section 22 is, for example, at least 100 nm and at most 1 μm. Therefore, the width of each second section 22 increases by twice this thickness, and the width of each first section decreases by twice this thickness.

[0110] Before applying the further auxiliary layer 4, a protective layer (not shown), such as an etch stop layer, may be applied to the upper surface 10 of the semiconductor body 1. This protective layer can protect the semiconductor body 1 within the area of ​​the first compartment from attacks during the directional material removal process.

[0111] Figure 11 shows the location of the method in which the second type of dopant, i.e., the n-type dopant, is injected into the semiconductor body 1 through the top surface 10. This forms a contact region 12 within the region of the first compartment 21, with a reduced lateral extension. Compared to the embodiment of the first type of dopant for forming the channel region 11, the contact region 12 is narrower than the channel region 11, i.e., the lateral extension of the first lateral direction Q is smaller, due to the reduced lateral extension of the first compartment 21. Again, the formation of the contact region 12 may further include an annealing step, which is not shown.

[0112] The contact region 12 is formed from a portion of the previously formed channel region 11 and is of a second conductivity type, i.e., electron conduction or n-doping. Therefore, the amount of n-type dopant injected is sufficient to convert each portion of the channel region 11 from p-doping to n-doping. For example, the doping concentration of the contact region 12 is 10 18 cm -3 ~10 19 cm -3 That is the case.

[0113] As can be seen further in Figure 11, the depth of the contact region 12 is less than the depth of the channel region 11, and the depth is measured in the vertical direction V. Therefore, the contact region 12 is formed between the top surface 10 and the channel region 11 in the vertical direction V.

[0114] Figure 12 shows the location of the method in which a second auxiliary layer 3, also referred to herein simply as auxiliary layer 3, is deposited on the upper surface 10 of the semiconductor body 1 by conformal deposition. The auxiliary layer 3 covers the upper surface 10 of the region of the first compartment 21, the upper surface of the second compartment 22, and the side surface 22a of the second compartment 22. The second auxiliary layer 3 may be made of a different material from the first auxiliary layer 4. The second auxiliary layer 3 is formed from, for example, SiN or SiO2.

[0115] At the location shown in Figure 13, a directional material removal process, such as dry etching, is used to remove the material of the second auxiliary layer 3 within the region of the first section 21 and on the upper surface of the second section 22. Due to the directional method, the remainder of the second auxiliary layer 3 remains on the side surface 22a of the second section 22, resulting in an effective increase in the width of the second section 22 and an effective decrease in the width of the first section 21. The remaining thickness of the second auxiliary layer 3 on the side surface 22a may be within the same region as the first auxiliary layer 4.

[0116] At the location shown in Figure 14, trench-shaped holes 5 are etched into the semiconductor body 1 in the region of the first section 21 where the width is reduced. The etchant used for etching is preferably selected such that the etching rate of the semiconductor material of the semiconductor body 1 is greater than the etching rate of the mask material and / or the material of the first auxiliary layer 4 and / or the material of the second auxiliary layer 3.

[0117] Trench 5 extends from the top surface 10 through the contact region 12 and the channel region 11, and is deeper than the channel region 11. Each trench 5 divides the previously continuous contact region 12 and channel region 11 into two contact regions 12 and two channel regions 11 adjacent to each trench 5 on both sides with respect to the first lateral direction Q. As an example, the depth of the etched trench 5 is 1 μm or less.

[0118] Figure 15 shows the location of the method in which the electrical insulating layer 51 is formed on the surface of the trench 5. The electrical insulating layer 51 is formed, for example, by oxidizing the surface of the trench 5. Additionally, a gate electrode 7 is formed within the trench 5.

[0119] At the position shown in Figure 16, the second mask 2 and the remaining auxiliary layers 3 and 4 on the side surface 22a of the second compartment 22 are removed. This exposes the top surface 10 of the semiconductor body 1 in the region between the trenches 5. Between each pair of trenches 5, the top surface 10 is partially formed by two contact regions 12, two channel regions 11, and a diode region 13. Thus, the contact regions 12 are embedded in the channel regions 11, and as a result, the contact regions 12 and channel regions 11 are adjacent to the trenches 5 but are electrically insulated from the gate electrodes 7 in the trenches 5 by the electrical insulation layer 51. The diode regions 13 are formed by a drift layer 18 and are therefore n-doped.

[0120] As a result of the method described herein, only one lithography step is required to generate the channel region 11, the contact region 12, and the trench 5. Such a self-aligning process makes it possible to generate very small structures. The distance between two adjacent trenches 5, measured in the first transverse direction Q, is, for example, up to three times the depth of the trench 5. For example, the distance is up to 3 μm. The width of each contact region 12, measured in the first transverse direction Q, is, for example, up to 1 μm or up to 500 nm.

[0121] Figure 17 is a perspective view of the semiconductor body 1 from Figure 16, showing the relative positions of the trench 5, contact region 12, channel region 11, diode region 13, and plug region 14. The plug region 14 extends diagonally to the trench 5 and is adjacent to the upper surface 10 of the region previously covered by the second section 22 of the mask 2.

[0122] In the position shown in Figure 18, the first main electrode 6 is attached to the upper surface 10 of the semiconductor body 1. The main electrode 6 is adjacent to the semiconductor body 1 in the region between the trenches 5 and is in direct contact with the contact region 12, the channel region 11, and the diode region 13. The first main electrode 6 is formed from, for example, a metal. It is electrically insulated from the gate electrode 7 by an electrical insulating layer 51.

[0123] Figure 19 shows the final semiconductor device 100. The semiconductor device 100 is a power semiconductor device, such as a power MOSFET. A second main electrode 9 is attached to the bottom surface of the semiconductor body 1, opposite to the top surface 10. The first main electrode 6 is the source electrode, and the second main electrode 9 is the drain electrode.

[0124] The plug region 14 is used, for example, to make electrical contact with the channel region 11. Due to the high doping concentration of the plug region 14, an ohmic contact may be formed between the plug region 14 and the first main electrode 6. On the other hand, the plug region 14 is electrically connected to the channel region 11, and as a result, at its end, the channel region 11 is electrically well connected to the first main electrode 6.

[0125] During operation, a voltage difference of, for example, more than 1kV is applied between the first main electrode 6 and the second main electrode 9. In the forward operation of the MOSFET, the current flowing between the main electrodes 6 and 9 is controlled by the gate electrode 7. In conduction mode, electrons are injected from the first main electrode 6 into the contact region 12. From there, the electrons pass through the channel region 11, travel along the trench 5, enter the drift layer 18, and flow from there to the second main electrode 9. The diode region 13, together with the first main electrode 6, forms a Schottky diode that is interrupted in conduction mode.

[0126] Therefore, the flow of charge carriers mainly occurs in the region between the trenches 5, and for this reason, this region is referred to herein as the active region A. A very small structure of the active region A can be generated by the method described herein.

[0127] The embodiments shown in Figures 1 to 19 above represent exemplary embodiments of improved methods for producing semiconductor devices and semiconductor devices. Therefore, they do not constitute a complete list of all embodiments of the improved methods and improved semiconductor devices. Actual methods and devices may differ from the embodiments shown in terms of elements, order of method steps, etc. [Explanation of Symbols]

[0128] Reference sign 1. Semiconductor body 2 (Second) Mask 3. (Second) auxiliary layer 4. First / Further Auxiliary Layer 5 holes 6 (First) Main Electrode 7 Airports 8. First Mask / Further Masks 9. Second main electrode 10 Top side 11 Channel Region 12 Contact Area 13 Diode region 14 Plug Area 18 Drift Layer 19 circuit boards 21. First section 22 Second section 22a Side of the second section 22 51 Electrical insulation layer 81 Mask 8, Section 1 82 Mask 8, second section 100 Semiconductor Devices Si Method Steps Q First lateral direction L Second lateral direction V Vertical

Claims

1. A method for producing semiconductor devices, To provide a semiconductor body (1) having an upper surface (10), The mask (2) is attached to the upper surface (10), The mask (2) comprises at least one first section (21) and at least one second section (22) that is laterally adjacent to the at least one first section (21), The mask (2) is thicker in the at least one second section (22) than in the at least one first section (21), and is to be applied. The method involves forming a channel region (11) of a first conductivity type within the semiconductor body (1) in the region of at least one first section (21), Forming the channel region (11) includes injecting a first type of dopant into the semiconductor body (1) through the upper surface (10), An auxiliary layer (3) is deposited on the side surface (22a) of the at least one second section (22) facing the at least one first section (21) to increase the lateral extension range of the at least one second section (22) and decrease the lateral extension range of the at least one first section (21). To generate the holes (5) in the semiconductor body (1) in the region of the at least one first section (21) where the lateral extension range is reduced, such that the holes (5) extend from the upper surface (10) through the channel region (11) Includes, Before the mask (2) is attached, an additional mask (8) is attached to the upper surface (10) of the semiconductor body (1). The first conductive type at least one plug region (14) is formed within the semiconductor body (1) by using the further mask (8), and the at least one plug region (14) is Adjacent to the upper surface (10), It is at least partially formed within the region of the upper surface (10) that is subsequently covered by the at least one second section (22) of the mask (2), The doping concentration in at least one plug region (14) is greater than the doping concentration in the channel region (11). method.

2. After the channel region (11) is formed and before the auxiliary layer (3) is deposited, a further auxiliary layer (4) is deposited on the side surface (22a) of the at least one second section (22) to increase the lateral extension of the at least one second section (22) and decrease the lateral extension of the at least one first section (21). After the deposition of the further auxiliary layer (4) and before the deposition of the auxiliary layer (3), a second conductive type contact region (12) is formed in the semiconductor body (1) in the region of the first compartment (21), and as a result, the contact region (12) is located between the channel region (11) and the upper surface (10), and the formation of the contact region (12) includes injecting a second type dopant into the semiconductor body (1) through the upper surface (10). The hole (5) is formed through the contact region (12). The method according to claim 1.

3. The auxiliary layer (3) is deposited by a conformal deposition process such that the side surface (22a) of the at least one second section (22), the top surface of the at least one second section (22), and the region of the first section (21) are covered by the auxiliary layer (3). Next, a directional material removal process is applied in which the auxiliary layer (3) is removed more from the region of the first section (21) and the upper surface of the second section (22) than from the side surface (22a) of the second section (22). The method according to claim 1 or 2.

4. Before applying the mask (2), the semiconductor body (1) is the second conductive type at least on the upper surface (10). During the injection of the first type of dopant, the at least one second compartment (22) protects the semiconductor body (1) below the first type of dopant so that the semiconductor body (1) remains of the second conductivity type on the upper surface (10) within the region of the at least one second compartment (22). The method according to claim 2.

5. To form an electrical insulating layer (51) on the surface of the hole (5), The steps include forming the gate electrode (7) on and / or in the hole (5) such that the gate electrode (7) is electrically insulated from the semiconductor body (1) by the electrical insulating layer (51), The steps of removing the mask (2) and The method involves forming a main electrode (6) on the upper surface (10) such that the main electrode (6) is electrically connected to the semiconductor body (1) in a region adjacent to the hole (5) in the lateral direction. The method according to claim 4.

6. The main electrode (6) is adjacent to at least one diode region (13) of the semiconductor body (1) which is the second conductivity type on the upper surface (10), The method according to claim 5.

7. The mask (2) comprises a plurality of striped first sections (21) and a plurality of striped second sections (22), Channel regions (11) and holes (5) are formed within the area of ​​several of the first sections (21), each channel region (11) is formed in a stripe pattern, and each hole (5) is formed as a trench. The method according to claim 1 or 2.

8. Multiple plug regions (14) are formed, Each plug region (14) is formed in a stripe pattern. The plug region (14) extends diagonally with respect to the channel region (11). The method according to claim 7.

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