Plasma processing equipment

Abstract

The purpose of the present invention is to provide a technique capable of estimating and accurately controlling the temperature of a wafer for each region.　A representative plasma processing apparatus according to the present invention comprises: a processing chamber in which plasma for processing a wafer to be processed is formed; a sample table that is disposed in the processing chamber and on an upper surface of which the wafer is placed; a plurality of heaters that are disposed in a plurality of regions inside a dielectric film, which is disposed covering the upper surface of a base material inside the sample table; temperature sensors disposed at a first plurality of locations in a refrigerant flow path disposed inside the base material and between the refrigerant flow path and the upper surface of the base material; and a control unit that estimates the wall surface temperature or heat transfer coefficient at a second plurality of locations of the refrigerant flow path using the outputs from the temperature sensors and the temperature of refrigerant, estimates the temperature of the wafer at a third plurality of locations using the estimated wall surface temperature or heat transfer coefficient of the refrigerant flow path and the outputs of the temperature sensors, and controls the operation of the plurality of heaters using the estimated temperature of the wafer so that the wafer reaches a target temperature.

Description

Technical Field

[0001] The present invention relates to a plasma processing apparatus.

Background Art

[0002] In a plasma processing apparatus, an etching process is performed on a so-called multilayer film in which a plurality of films are laminated on the surface of a plate-like sample such as a semiconductor wafer (hereinafter also simply referred to as "wafer"). In order to shorten the time required for the etching process, different processes according to the type of film are performed in a single processing chamber, and the etching process is performed without taking out the wafer outside the processing chamber during the process.

[0003] In such a process, it is important to adjust the temperature of the sample stage disposed in the processing chamber to an appropriate temperature and then process the wafer. Generally, a heater is built in the sample stage of the plasma processing apparatus, and when processing the wafer, it is adjusted to a temperature suitable for processing to improve the processing accuracy.

[0004] As a conventional technique for arranging a heater in the plasma processing apparatus as described above and adjusting it to a temperature suitable for wafer processing, for example, there is JP-A-2021-19066 (Patent Document 1). Patent Document 1 aims to provide a temperature control device, a temperature control method, and an inspection device that can accurately estimate the temperature of a temperature control object and control the temperature even when the temperature control object generates heat, and discloses the following contents as an invention related to the temperature control device, the temperature control method, and the inspection device. "A temperature control device that controls the temperature of a temperature control object includes a heating mechanism having a heating source that heats the temperature control object, a temperature measuring device that measures the ambient temperature of the temperature control object, a temperature estimating unit that dynamically estimates the temperature of the temperature control object based on the power input to the heating source, the power supplied to the temperature control object, and the ambient temperature, and a temperature controller that controls the temperature of the temperature control object by controlling the power input to the heating source based on the estimated temperature of the temperature control object." In this conventional technology, an LED heating mechanism is placed on the sample stage, and a cooling mechanism (refrigerant flow path) is built into the sample stage. The device also includes a temperature controller and a temperature estimation unit (observer). The reason for including the temperature estimation unit is that, due to structural issues with the device, it is difficult to directly measure the temperature of the wafer placed on the sample stage. Therefore, the temperature near the wafer is measured, and the temperature estimation unit estimates the wafer temperature. The temperature controller controls the heat output of the LED heating mechanism and the cooling output of the cooling mechanism (opening and closing of the refrigerant flow path valve) to keep the estimated wafer temperature constant at the target temperature.

[0005] Furthermore, another prior art example relating to temperature control of such plasma processing apparatus is WO2023 / 013637 (Patent Document 2). Patent Document 2 discloses the following invention relating to a wafer temperature control device, a control method for a wafer temperature control device, and a program for a wafer temperature control device: "In order to provide a wafer temperature control device that can estimate the wafer temperature with sufficient accuracy and control the wafer temperature to a target temperature even when the amount of cooling operation input to the cooler is changed, the device comprises: a heater 1 that heats a wafer W according to an input amount of heating operation; a cooler 2 that cools the wafer W according to an input amount of cooling operation; a proximity temperature measuring instrument 3 that measures the temperature near the wafer W; a temperature estimation observer 4 that estimates the wafer temperature based on the proximity temperature measured by the proximity temperature measuring instrument 3 and the amount of cooling input to the cooler 2 or the amount of cooling output by the cooler; and a temperature controller 5 that controls the amount of cooling operation so that the temperature deviation between the set temperature and the estimated wafer temperature becomes small." This conventional technology controls the heating amount of a heater built into the sample stage and the cooling amount of He gas supplied to the back surface of the sample, and controls the wafer temperature with a temperature controller to reach a target temperature. Similar to the aforementioned Patent Document 1, the device is equipped with a temperature estimation unit (observer) that estimates the wafer temperature from the measured temperature near the wafer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2021-19066 [Patent Document 2] International Publication No. 2023 / 013637 [Overview of the project] [Problems that the invention aims to solve]

[0007] Here, the fact that the temperature of the refrigerant flow path is not uniform (for example, the temperature is low near the inlet and high near the outlet) affects the estimation of the wafer temperature. In contrast, neither Patent Document 1 nor Patent Document 2 takes into account the temperature change of the refrigerant flow path or how this temperature change affects the heat transfer conditions, resulting in the problem that it is difficult to control the wafer temperature with high precision in each region. Therefore, the present invention aims to provide a technology that can estimate the temperature of a wafer region by region and control it with high precision. [Means for solving the problem]

[0008] To solve the above problems, one representative plasma processing apparatus of the present invention comprises: a processing chamber disposed inside a vacuum vessel in which plasma for processing a wafer to be processed is formed inside; a sample stage disposed inside the processing chamber on which the wafer is placed on its upper surface; a plurality of heaters arranged in a plurality of regions inside a dielectric film that covers the upper surface of a disc or cylindrical substrate inside the sample stage; a refrigerant flow path disposed inside the substrate and a first plurality of temperature sensors disposed at a plurality of locations between the refrigerant flow path and the upper surface of the substrate; a control unit that estimates the temperature or heat transfer coefficient of the walls at a second plurality of locations in the refrigerant flow path using the output from the temperature sensors and the temperature of the refrigerant, estimates the temperature of the wafer at a third plurality of locations using the estimated temperature or heat transfer coefficient of the walls of the refrigerant flow path and the output of the temperature sensors, and controls the operation of the plurality of heaters so that the wafer reaches a target temperature using the estimated wafer temperature. [Effects of the Invention]

[0009] According to the present invention, the temperature of the wafer can be estimated for each region and controlled with high precision. Other issues, configurations, and effects not mentioned above will be clarified by the description of the embodiments for carrying out the invention below. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 is a schematic cross-sectional view showing the configuration of a plasma processing apparatus according to an embodiment of the present invention. [Figure 2] Figure 2 is a schematic cross-sectional view showing a part of the configuration of the sample stage of the plasma processing apparatus shown in Figure 1. [Figure 3] Figure 3 is a schematic diagram illustrating an example of the correspondence between the refrigerant flow path inside the substrate, the heater film, and the estimated wafer temperature location. [Figure 4] Figure 4 is a data flow diagram showing the processing sequence for wafer temperature control. [Figure 5] Figure 5 is a block diagram illustrating another example of a wafer temperature control processing sequence. [Modes for carrying out the invention]

[0011] Embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to these embodiments. Furthermore, in the drawings, identical parts are denoted by the same reference numerals. When there are multiple components with the same or similar function, they may be described using the same symbol but with different subscripts. Furthermore, when it is not necessary to distinguish between these multiple components, the subscripts may be omitted in the description. The positions, sizes, shapes, and ranges of the components shown in the drawings may not represent their actual positions, sizes, shapes, and ranges in order to facilitate understanding of the invention. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and ranges disclosed in the drawings.

[0012] Furthermore, "upwards" or "upper part" refers to the vertically upward direction when a component is placed horizontally. In addition, "upwards" ("upper part") and its opposite, "downwards" ("lower part"), may be referred to as the "positive z-axis direction" and the "negative z-axis direction," respectively, while the horizontal direction may be referred to as the "x-axis direction," "y-axis direction," or "xy-plane direction," etc. Furthermore, the flat surface of a member that is located above it and faces upwards is called the "top surface." In addition, the flat surface of a member that is located below it and faces downwards is called the "bottom surface." Furthermore, among the structural members, the surfaces that extend in the vertical direction are referred to as "side walls," "wall surfaces," "side wall surfaces," etc.

[0013] (Configuration of the plasma etching system) Embodiments of the present invention will be described below with reference to Figures 1 to 5. Figure 1 is a schematic cross-sectional view showing the configuration of a plasma processing apparatus according to an embodiment of the present invention. The plasma processing apparatus 100 includes a processing chamber 104 located inside a vacuum vessel 101, where plasma for processing a wafer 109 to be processed is formed inside, and a sample stage 120 located inside the processing chamber 104, on which the wafer 109 is placed. The sample stage 120 also includes a dielectric film (201, 203) covering the upper surface of a disc or cylindrical substrate 108, with a plurality of heaters (heater film 204) arranged in a plurality of regions within the dielectric film. Furthermore, a refrigerant flow path 152 located inside the substrate 108 and a first plurality of temperature sensors 202 located between the refrigerant flow path 152 and the upper surface of the substrate 108 are also provided. The control units (170, 171) then use the output from the temperature sensor 202 and the temperature of the refrigerant to estimate the temperature or heat transfer coefficient of the walls at a second number of locations in the refrigerant flow path 152, and use the estimated temperature or heat transfer coefficient of the refrigerant flow path 152 and the output from the temperature sensor 202 to estimate the temperature of the wafer 109 at a third number of locations. Furthermore, the control units (170, 171) use the estimated temperature of the wafer 109 to control the operation of the multiple heaters (heater films 204) so ​​that the wafer 109 reaches the target temperature.

[0014] The control of the plasma processing apparatus 100 is performed by a personal computer 170 and a PLC (Programmable Logic Controller) 171. The personal computer 170 sets the processing sequence of the plasma processing apparatus 100 and sends the set processing sequence and processing conditions to the PLC 171. The PLC 171 sends a control signal to cause the components of the plasma processing apparatus 100 to operate according to the processing sequence. Although the personal computer 170 and the PLC 171 are separately described in the present disclosure, the present disclosure is not limited to this case. It is also possible to apply a configuration that realizes the functions of the personal computer 170 and the PLC 171 as a control unit 172. This will be specifically described below.

[0015] Note that FIG. 1 shows a plasma etching apparatus that forms plasma by generating ECR (Electron Cyclotron Resonance) between a microwave electric field and a magnetic field using the microwave electric field as the electric field for forming plasma, and etches a plate-like sample such as a semiconductor wafer using the plasma. Here, the case of the plasma etching apparatus is described, but the present disclosure is not limited to the case of the plasma etching apparatus, and can also be applied to a processing apparatus in which processing other than plasma etching is performed.

[0016] The plasma processing apparatus 100 has a vacuum chamber 101 that includes a processing chamber 104 in which plasma is formed. The vacuum chamber 101 has a cylindrical shape with an open top, and a dielectric window 103 (for example, made of quartz) for introducing microwaves is disposed as a lid member at the top thereof, and a processing chamber 104 that is hermetically partitioned between the inside and the outside is formed.

[0017] Furthermore, a vacuum exhaust port 110 is located at the bottom of the vacuum vessel 101, and the vacuum vessel 101 is in communication with a vacuum exhaust device (not shown) located below and connected to the vacuum vessel 101. In addition, a shower plate 102, which forms the ceiling surface of the processing chamber 104, is provided below the lower surface of the dielectric window 103, which constitutes the lid member at the top of the vacuum vessel 101. The shower plate 102 has a plurality of gas introduction holes 102a located in the center, and etching gas is introduced into the processing chamber 104 through these gas introduction holes 102a. The shower plate 102 is a disc made of a dielectric material such as quartz.

[0018] Furthermore, an electric field / magnetic field generating unit 160 is located above the outside of the vacuum vessel 101 to form the electric and magnetic fields for generating the plasma 116. A waveguide 105 is positioned between the electric field / magnetic field generating unit 160 and the processing chamber 104. The waveguide 105 is positioned above the dielectric window 103 and transmits the electric field of a predetermined frequency generated in the electric field / magnetic field generating unit 160 to the processing chamber 104. In addition, the electric field transmitted inside the waveguide 105 is formed by oscillation in the electric field generating power supply 106. The frequency of the electric field is not particularly limited, but in this embodiment, a 2.45 GHz microwave is used.

[0019] Furthermore, the magnetic field generating coil 107, which forms the magnetic field, is positioned above the dielectric window 103, surrounding the side wall of the vacuum vessel 101 and the outer circumference of the lower end of the waveguide 105. The electric field oscillated in the electric field generating power supply 106 propagates inside the waveguide 105, passes through the dielectric window 103 and the shower plate 102, and is supplied to the processing chamber 104. In addition, the interaction between the magnetic field generated by the magnetic field generating coil 107 and the electric field supplied into the processing chamber 104 generates ECR (Electron Cyclotron Resonance). By exciting and dissociating the atoms or molecules of the processing gas introduced into the processing chamber 104 through the gas introduction hole 102a of the shower plate 102, a high-density plasma 116 is generated inside the processing chamber 104.

[0020] Next, an overview of the sample stage 120 will be described using Figure 1. The detailed configuration of the sample stage 120 will be described later using Figure 2. Below the processing chamber 104, in other words, below the space where the plasma 116 is formed, is the sample stage 120, which functions as a wafer mounting electrode. The sample stage 120 has a mounting surface 120a on which the wafer 109, which is the sample (to be processed), is placed. The mounting surface 120a of the sample stage 120 faces either the shower plate 102 or the dielectric window 103. As shown in Figure 1, the sample stage 120 is covered with a dielectric film 140 that constitutes the mounting surface 120a. Inside the dielectric film 140, a plurality of conductive films 111 for electrostatic adsorption are arranged, connected to a DC power supply 126 via a high-frequency filter 125 as shown in Figure 1. Here, the conductive films 111 are elements that constitute the mounting surface 120a of the sample stage 120, and are film-shaped electrostatic adsorption electrodes to which DC power is supplied to generate electrostatic force for wafer adsorption. The conductive film 111 may be a bipolar film in which one of the multiple film-like electrodes is assigned different polarities, or it may be a unipolar film in which the same polarity is assigned; however, in this embodiment, it is shown as a unipolar film.

[0021] Furthermore, a high-frequency power supply 124 and a matching unit 129 are positioned closer to the conductive film 111 than the high-frequency filter 125. These high-frequency power supply 124 and matching unit 129 are connected to a conductive electrode substrate (hereinafter also simply referred to as "substrate") 108, which has a circular or cylindrical shape and is located inside the sample stage 120. The high-frequency power supply 124 is connected to ground 112. High-frequency power of a predetermined frequency is supplied to the substrate 108 from the high-frequency power supply 124, and a bias potential is formed above the wafer 109, which is adsorbed and held on the mounting surface 120a of the sample stage 120, during the processing of the wafer 109. In other words, the sample stage 120 has electrodes to which high-frequency power is supplied from the high-frequency power supply 124 while the plasma 116 is being formed. The electrodes for forming the bias potential will be described later.

[0022] Inside the substrate 108, a refrigerant flow path 152 is arranged spirally or concentrically around a central axis, assuming a central axis extending vertically in the substrate 108 or the sample stage 120, in order to remove the transferred heat and cool the sample stage 120. A cooling refrigerant flows through this refrigerant flow path 152 to cool the substrate 108. As will be described later, the sample stage 120 is provided with a heater film 204, and the sample stage 120 (substrate 108) is heated by power supplied from the heater power supply 180.

[0023] Furthermore, a recessed portion 120d is positioned on the outer circumference of the upper part of the sample stage 120. A susceptor ring 113, which is a ring-shaped member made of a dielectric material such as quartz or alumina, is placed on the upper surface of the ring-shaped recessed portion 120d, which is formed to be lower in height than the mounting surface 120a of the sample stage 120. When the susceptor ring 113 is placed on the recessed portion 120d, the upper surface of the susceptor ring 113 is positioned higher than the mounting surface 120a of the sample stage 120. The susceptor ring 113 is positioned on the outer circumference of the mounting surface 120a of the sample stage 120 and covers the surface of the sample stage 120. Specifically, the susceptor ring 113 is configured to cover the upper surface of the recessed portion 120d, the cylindrical side wall surface of the recessed portion 120d, and the cylindrical side wall surface of the sample stage 120 below the recessed portion 120d.

[0024] Next, the process of placing the wafer 109 on the sample stage 120 will be described. For example, the wafer 109 before processing is placed on the tip of the arm of a wafer transport robot located in a vacuum transport chamber, which is a vacuum chamber separate from the vacuum vessel 101. Here, the vacuum transport chamber is connected to the vacuum vessel 101, and the inside of the vacuum transport chamber is depressurized to the same pressure as the processing chamber 104. Then, a gate that demarcates the passage connecting the vacuum transport chamber and the processing chamber 104 is opened by the operation of a valve located in the vacuum transport chamber, and the wafer 109 before processing is transported into the processing chamber 104 while still placed on the tip of the robot arm. Furthermore, the wafer 109, which has been transported to above the mounting surface 120a of the sample stage 120 in the processing chamber 104, is transferred onto the lift pins (not shown) by the vertical movement of the lift pins, and then placed on the mounting surface 120a. After that, it is attracted to and held by the mounting surface 120a of the sample stage 120 by the electrostatic force formed by the DC power applied from the DC power supply 126.

[0025] In this state, the etching gas is introduced into the space between the dielectric window 103 and the quartz shower plate 102, with its flow rate or speed regulated by a mass flow controller (not shown). After diffusing within this space, it is introduced into the processing chamber 104 through the gas inlet hole 102a of the shower plate 102. Subsequently, the vacuum evacuation device operates to exhaust the gas and particles in the processing chamber 104 through the vacuum exhaust port 110. The pressure inside the processing chamber 104 is adjusted to a predetermined value within a range suitable for processing the wafer 109, depending on the balance between the amount of gas supplied from the gas inlet hole 102a of the shower plate 102 and the amount exhausted from the vacuum exhaust port 110.

[0026] Furthermore, while the wafer 109 is held by adsorption, a gas with heat-conducting properties, such as He (helium), is supplied to the gap between the wafer 109 and the upper surface of the dielectric film 140, which is the mounting surface 120a of the sample stage 120, through an opening (not shown) on the upper surface of the dielectric film 140, thereby promoting heat transfer between the wafer 109 and the sample stage 120. A refrigerant adjusted to a temperature within a predetermined range circulates through the refrigerant channel 152, so the temperature of the sample stage 120 or the substrate 108 is pre-adjusted before the wafer 109 is placed on it. Therefore, heat transfer occurs between the sample stage 120 or the substrate 108, which have a large heat capacity, so that the temperature of the wafer 109 is adjusted to be close to the predetermined range before the etching process, and even after the etching process begins, heat from the wafer 109 is transferred, further adjusting the temperature of the wafer 109.

[0027] With the wafer 109 temperature adjusted, microwave electric and magnetic fields are supplied into the processing chamber 104, causing a gas reaction and generating plasma 116. Once the plasma 116 is formed, high-frequency (RF) bias power is supplied to the substrate 108 from the high-frequency power supply 124, creating a bias potential above the upper surface of the wafer 109. Charged particles such as ions in the plasma 116 are attracted to the upper surface of the wafer 109 according to the potential difference between this potential and the potential of the plasma 116. Furthermore, these charged particles collide with the film structure, including the mask and the film layer to be processed, which are pre-placed on the upper surface of the wafer 109, and etching is performed. During the etching process, the etching gas introduced into the processing chamber 104 and the reaction product particles generated during the etching process are exhausted from the vacuum exhaust port 110.

[0028] In the plasma processing apparatus 100 of this embodiment, during plasma processing, high-frequency power is supplied from a high-frequency power supply 127 to a conductive ring 131 located on the upper part of the outer circumference of the sample stage 120 via a power supply connector 161, which will be described later, provided on the sample stage 120 and equipped with an elastic conductive member.

[0029] In the sample stage 120 of this embodiment, the AC high voltage generated from the high-frequency power supply 127 is introduced to a conductive ring 131 made of a conductive material located inside the susceptor ring 113 via a load matching unit 128 and a load impedance variable box 130. This configuration, combined with the load impedance variable box 130 adjusted to a suitable impedance value and a relatively high impedance portion located on top of the susceptor ring 113, relatively lowers the impedance value for high-frequency power from the high-frequency power supply 127 through the substrate 108 to the outer edge of the wafer 109. As a result, high-frequency power is effectively supplied to the outer portion and outer edge of the wafer 109, mitigating the concentration of the electric field in the outer portion or outer edge and attracting charged particles such as ions in the plasma to the upper surface of the wafer 109 in a desired direction. The high-frequency power supply 127 is connected to ground 112. In this embodiment, the frequency of the high-frequency power supply 127 is preferably set to the same value as or a constant multiple of the frequency of the high-frequency power supply 124.

[0030] (Sample stand) Next, the configuration of the sample stage 120 according to this embodiment will be described in detail with reference to Figure 2. Figure 2 is a schematic cross-sectional view showing a part of the configuration of the sample stage of the plasma processing apparatus shown in Figure 1.

[0031] In this embodiment, the substrate 108 shown in Figure 2 is made of a metallic material such as titanium, aluminum, or a compound thereof, and is electrically connected to a ground electrode S (not shown) and electrically connected to the wall surface of the vacuum vessel 101 shown in Figure 1, and is fixed at ground potential. The substrate 108 has a top surface 120b in the center on which a wafer 109 is placed, and a recessed portion 120d arranged in a ring shape on the outer circumference of the top surface 120b, surrounding the top surface 120b and formed to be lower in height than the top surface 120b. Between the top surface 120b and the recessed portion 120d, there is a stepped portion 120e that forms the side wall of the outer circumference of the top surface 120b. A susceptor ring 113 is placed on the ring-shaped recessed portion 120d. The refrigerant flow path 152 has a spiral or concentric shape around the central axis ca of the substrate 108 (sample stage 120).

[0032] The dielectric films (201, 203) are formed by thermal spraying onto the upper surface 120b of the substrate 108 to cover the upper surface 102e. Specifically, a dielectric film 201, which is a film made of a dielectric material such as ceramics, is placed on the upper surface 102e of the substrate 108. Furthermore, a heater film 204, which consists of multiple heaters that are film-like electrodes made of a conductive material and generate heat when DC power is supplied to them, is placed on the upper layer of the dielectric film 201, covering multiple regions of the upper surface 120b of the substrate 108. In other words, a dielectric film 201 is placed on the upper surface 120b of the substrate 108, and a heater film 204, which is a film-like heater, is formed on the upper layer of this dielectric film 201.

[0033] In this embodiment, the sample stage 120 has a structure in which a heater film 204 surrounded by dielectric films 201 and 203 is placed on the upper surface 102e of the base material 108, and is further surrounded (covered) by a shield film 205, which is a film-like conductive member placed on the upper surface of the dielectric film 203, surrounding the upper and peripheral outer edges. In other words, the structure in which the heater film 204 is surrounded by the shield film (conductor film) 205 is contained within the dielectric material that constitutes part of the dielectric films 201 and 203. The shield film 205 is electrically connected to the base material 108, and as a result, the shield film 205 is fixed at the same ground potential as the base material 108, and as a result, the inflow of high-frequency waves into the heater film 204 can be suppressed.

[0034] Furthermore, a dielectric film 206 is positioned on the upper surface of the shield film 205, and an electrode film 207, which is an electrode for electrostatic adsorption and to which high-frequency power for high-frequency bias formation is supplied, is positioned on top of this dielectric material component. In other words, the electrode film 207 is a film made of a conductive material and is connected to a high-frequency power supply 124 that supplies high-frequency power at a predetermined frequency. The electrode film 207 is also electrically connected to the DC power supply 126, and when a DC voltage is applied, the wafer 109 placed on the mounting surface of the sample stage 120 can be attracted by electrostatic force.

[0035] Furthermore, above the upper surface of the electrode film 207, a dielectric film (electrostatic adsorption member) 208, made of a ceramic material that constitutes the uppermost surface of the sample stage 120 and the mounting surface on which the wafer 109 is placed, is positioned to cover the upper surface of the convex portion, the recesses around it, and the stepped portion 120e, which is the side wall of the convex portion. That is, the uppermost surface of the sample stage 120 is positioned on the shield film 205, and the dielectric film 208, which includes an electrode film (electrode) 207 positioned on the upper part of the shield film 205, is positioned on the shield film 205. Note that the dielectric film 140 in Figure 1 shows a configuration that includes dielectric films 201, 203, and 206. In addition, although a case in which the electrode film 207 has two functions, forming a bias potential and electrostatic adsorption of the wafer, and includes the conductive film 111 in Figure 1, has been described, this disclosure is not limited to this case. An electrode for forming a bias potential and an electrode for electrostatic adsorption may be provided separately.

[0036] Furthermore, the sample stage 120 has a temperature sensor 202 positioned on the top of the substrate 108 to detect heat generation from the heater film 204. The temperature sensor 202 is positioned at a first number of locations between the refrigerant flow path 152 located inside the substrate 108 and the upper surface of the substrate 108. In this disclosure, an example is shown in which three temperature sensors 2021 to 2023 are positioned at three locations, as shown in Figure 3, but this disclosure is not limited to three cases. The personal computer 170 has a temperature estimation unit 209 and a control calculation unit 210. The temperature estimation unit 209 estimates the temperature of the wafer 109 (hereinafter also simply referred to as "wafer temperature") based on data acquired by the temperature sensor 202. The PLC 171 controls the heater power supply 180 based on instructions from the control calculation unit 210. The control calculation unit 210 also controls the operation of the refrigerant flow path 152. The temperature sensors 2021 to 2023 are also affected by the refrigerant.

[0037] Next, Figure 3 will be used to explain the target of the thermal analysis when estimating the temperature of wafer 109. Figure 3 is a schematic diagram showing an example of the correspondence between the refrigerant flow path 152 inside the substrate 108, the heater film 204, and the wafer temperature estimation points 305. As will be explained in detail later, the reason for dividing the region of the refrigerant flow path 152 into 301, 302, 303, and 304 is that the thermal analysis results showed that the temperature of each region on the upper wall surface of the refrigerant flow path 152 was different. Wafer 109 temperature estimation points 3051 to 305 13 Since the wall temperature of the refrigerant flow path 152 differs in each region, the heat transfer coefficient when heat is transferred from the refrigerant contained in each of the refrigerant flow path regions 301, 302, 303, and 304 to the wafer 109 also changes. When this heat transfer coefficient is used for temperature control of the wafer 109, it affects the control accuracy.

[0038] To explain Figure 3 in more detail, Figure 3 shows the positional relationship of the wafer 109 (Figure 3(a)), heater film 204 (Figure 3(b)), and refrigerant flow path 152 (Figure 3(c)) extracted from the configuration of the sample stage 120. All of them have a roughly circular shape and are arranged so that their central axes are common. The common central axis is shown as ca. As shown in the order from Figure 3(c) to Figure 3(a), the refrigerant flow path 152 (inside the substrate 108 of the sample stage 120), heater film 204 (above the substrate 108), and wafer 109 (above the heater film 204) are arranged in that order.

[0039] Figure 3(c) shows the results of a thermal analysis of the wall surface of the refrigerant channel 152, assuming that refrigerant is flowing through the refrigerant channel 152. The refrigerant channel 152 has a three-dimensional size in a spiral or concentric shape, and the results of the thermal analysis are shown projected onto the xy plane. In Figure 3(c), temperature differences are indicated by color (hatching), and the temperature and color correspond to the color bars shown in Figure 3(d), respectively.

[0040] When viewed from the positive z-axis direction, the refrigerant flows clockwise from the inlet 152i of the refrigerant flow path 152 along the outer circumference of the base material 108 (the position furthest from the central axis ca), reverses direction just before reaching the inlet 152i, and flows counterclockwise at a position closer to the central axis ca. As it approaches the inlet 152i, it reverses direction again and flows clockwise at a position even closer to the central axis ca. The refrigerant flows in a circular motion from the outside of the base material 108, changing direction as it passes through the inside of the base material 108 fairly evenly, approaching the central axis ca, and flows out of the base material 108 from the outlet 152o of the refrigerant flow path 152.

[0041] The temperature of the wall surface of the refrigerant flow path 152 is 2°C from the inlet 152i to the outermost part of the flow path, and changes to 9°C, 15°C, and 21°C as it approaches the central axis ca. The area where the wall surface temperature is 2°C is designated as region 301, the area where the wall surface temperature is 9°C is designated as region 302, the area where the wall surface temperature is 15°C is designated as region 303, and the area where the wall surface temperature is 21°C is designated as region 304. Through thermal analysis, it was possible to estimate the wall surface temperatures of the refrigerant flow path 152 from region 301 to region 304 (a second set of multiple locations).

[0042] Although the description of the refrigerant flow path 152 has described a case where the inlet of the flow path is located on the outer circumference of the base material 108 and the outlet is located in the central part of the base material 108, this disclosure is not limited to this case. This disclosure can be applied depending on the positions of the inlet and outlet of the refrigerant flow path 152. Furthermore, although the description has described a case where the temperature of the refrigerant flow path 152 is divided into four levels, this disclosure can also be applied when the temperature is divided into a number other than four.

[0043] Figure 3(b) shows the heater film 204 projected onto the xy plane. The heater film 204 is divided into multiple regions, each region denoted by the symbols R1 to R13. In comparison with Figure 3(c), region 301 of the refrigerant flow path 152 roughly corresponds to regions R1 to R4 of the heater film 204, and region 302 of the refrigerant flow path 152 roughly corresponds to regions R5 to R8 of the heater film 204. Furthermore, region 303 of the refrigerant flow path 152 roughly corresponds to regions R9 to R12 of the heater film 204, and region 304 of the refrigerant flow path 152 roughly corresponds to region R13 of the heater film 204. Here, we describe the case where it is divided into 13 regions, but this disclosure is not limited to this case.

[0044] Figure 3(c) shows the wafer 109 projected onto the xy plane. The estimation area 305 indicates the area where the temperature of the wafer 109 is estimated by the temperature estimation unit 209, and is a range with a predetermined area. Compared with Figure 3(b), estimation areas 3051 to 305 13 The (third multiple locations) are located approximately in the central part of each of the regions R1 to R13 of the heater film 204. While the description explains the case where there are 13 estimated locations 305, this disclosure is not limited to this case. A number other than 13 locations may be considered estimated locations.

[0045] Furthermore, the first set of multiple locations is smaller than the second set of multiple locations. Also, the first set of multiple locations is smaller than the third set of multiple locations. Specifically, the range measured by the temperature sensors 2021 to 2023 located at the first set of multiple locations is smaller than the range occupied by the second set of multiple locations (regions 301 to 304 of the refrigerant flow path 152). Also, the range measured by the temperature sensors 2021 to 2023 located at the first set of multiple locations is smaller than the range occupied by the third set of multiple locations (temperature estimation locations 3051 to 305 of the wafer 109). 13 It is smaller than the area occupied by ).

[0046] Thus, because the temperature of the wall surface of the refrigerant flow path 152 differs for each region from 301 to 304, the refrigerant in the refrigerant flow path 152 and the estimated location of the wafer 109 from 3051 to 305 13When considering heat transfer between these regions, it is preferable to set a heat transfer coefficient for each region 301 to 304 of the refrigerant flow path 152, rather than using a single heat transfer coefficient.

[0047] (Example of wafer temperature control) Figure 4 is a data flow diagram showing the processing sequence for temperature control of the wafer 109. In the personal computer 170, the temperature or heat transfer coefficient of the walls of a second set of locations (regions 301 to 304) of the refrigerant flow path 152 is estimated using the output from the temperature sensor 202 and the temperature of the refrigerant, and a third set of locations (estimated locations 3051 to 305) is estimated using the estimated temperature or heat transfer coefficient of the walls of the refrigerant flow path 152 and the output from the temperature sensor 202. 13 The temperature of the wafer 109 is estimated. Then, the operation of the heater (heater film 204) is controlled using the estimated temperature of the wafer 109 so that the wafer 109 reaches the target temperature. In the personal computer 170, the temperature of the wall surface of the refrigerant flow path 152 is estimated using the observer. In the observer, the temperature of the inlet 152i of the refrigerant flow path 152, the temperature of the refrigerant, the thermal conductivity of the substrate 108 or the refrigerant, and the amount of current or power supplied to the heater (heater film 204) are used to estimate the temperature or heat transfer coefficient of the wall surface at a second number of locations in the refrigerant flow path 152. This will be explained in detail below.

[0048] Processing steps S1 to S3 and steps S4 to S5 are performed in the control calculation unit 210. First, in step S1, the control calculation unit 210 obtains a set value for the wafer temperature. The set value may be calculated by the control calculation unit 210 based on the processing conditions, or it may be specified by the user of the plasma processing apparatus 100. Next, in step S2, the control calculation unit 210 calculates the temperature difference between the set value for the wafer temperature and the estimated value for the wafer temperature. The calculated temperature difference is converted into power (electricity) in the control calculation unit 210 in step S3.

[0049] The PLC171 controls the heater power supply 180 based on the converted power, causing the heater film 204 to heat up. With the sample stage 120 heated by the heater film 204, the temperature sensor 202 detects the temperature near the temperature sensor 202. The temperature sensor 202 mainly detects the heat generated by the heater film 204. At this time, P LC Unit 171 controls the supply of refrigerant to the refrigerant flow path 152.

[0050] The temperature estimation unit 209 acquires information indicating the power (power related to the set temperature of the heater film 204) and the temperature near the temperature sensor 202 based on the temperature difference, and estimates the wafer temperature and the temperature of the wall surface of the refrigerant flow path 152. Ta The wafer temperature is notified to the control calculation unit 210 and used to calculate the temperature difference in step S2.

[0051] The control calculation unit 210 classifies the walls of the refrigerant flow path 152 into n (where n is a positive integer of 1 or more; in this disclosure, n=4) according to predetermined temperatures, and obtains tn from the temperature t1 of each wall. In step S4, the control calculation unit 210 calculates hn from the heat transfer coefficient h1 from tn from the temperature t1. Subsequently, in step S5, the control calculation unit 210 calculates pn from the parameter p1 used in the calculation for estimating the wafer temperature in the temperature estimation unit 209.

[0052] Parameters p1 through pn are sent to the temperature estimation unit 209, where the parameters are updated. The processing sequence shown in Figure 4 is repeated at predetermined time intervals, for example, while the plasma etching process is being performed, to control the wafer temperature.

[0053] To summarize the processing sequence described above, the temperature estimation unit 209 estimates the wafer temperature using the nearby temperature, and also estimates the wall temperature of the separated refrigerant flow path 152 region. The estimated wall temperature of the refrigerant flow path 152 is converted into heat transfer conditions or heat transfer coefficients, and the parameters of the temperature estimation unit 209 are updated. The wafer temperature and the wall temperature of the refrigerant flow path 152 at the next sampling time are estimated using the parameters of the temperature estimation unit 209 calculated at the previous sampling time. Note that when calculating the heat transfer conditions and heat transfer coefficients, it is also possible to consider the thermal conductivity of the refrigerant.

[0054] (Other examples of wafer temperature control) Figure 5 is a block diagram showing another example of the temperature control processing sequence for wafer 109. In Figure 5, the temperature of the wall surface of the refrigerant flow path 152 is estimated using a Kalman filter. The example shown in Figure 5 differs from the case shown in Figure 4 in that the processing sequence is set by the control calculation unit 210 in the personal computer 170, while the function of the temperature estimation unit 209 is executed in the PLC 171.

[0055] Figure 5 shows an example of calculating the heat transfer coefficients corresponding to regions 301, 302, 303, and 304, and controlling the wafer 109 to a target temperature. First, the personal computer 170 (particularly the control calculation unit 210) sets the temperature at the inlet 152i of the refrigerant flow path 152 (TCR Temp Setting), the flow velocity of the refrigerant flowing through the refrigerant flow path 152 (Massflow Setting), and the wafer temperature at a predetermined estimated location 305 on the wafer 109 (Temp Setting). The set values ​​are sent to the PLC 171, where calculations are performed. Based on the results of the calculations performed by the PLC 171, the PLC 171 operates the heater film 204 inside the sample stage (Plant) 120.

[0056] The temperature sensor 202 located inside the sample stage 120 detects the heat generation of the heater film 204 and the cooling of the refrigerant flow path 152. The result of this detection is output as a signal St from the sample stage 120 and input again to the Kalman Filter 405 of the PLC 171. Subsequently, the Kalman Filter of the PLC 171lt In er405, the wafer temperature tw and the wall temperature of the refrigerant flow path 152 (temperature t1 in region 301, temperature t2 in region 302, temperature t3 in region 303, and temperature t4 in region 304) are estimated using the detected results. Although the estimation is performed using KalmanFilter405 in Figure 5, the estimation method is not limited to KalmanFilter405 and other methods (observer, machine learning, etc.) may be used. The difference between the wafer temperature tw estimated by PLC171 and the wafer temperature (Temp Setting) set on PC170 is produced and input to PID control unit (PID Controller)406. In PID control unit 406, the amount of heat generated by the heater film 204 necessary to reduce the difference is calculated, and the heater film 204 on the sample stage 120 is operated again based on this calculation result.

[0057] In parallel with the operation of the heater film 204, the heat transfer coefficients for each region 301 to 304 of the refrigerant flow path 152 are calculated using the estimated wall temperatures t1 to t4 and the set refrigerant flow velocity (Massflow Setting), and the wafer temperature estimation model is updated in real time (the parameters for the next sampling time are calculated using the parameters for the previous sampling time). By doing so, the accuracy of wafer temperature estimation can be improved. Note that dividing the region of the refrigerant flow path 152 into four parts is just one example. The division of the region of the refrigerant flow path 152 is not limited to four parts, and the more parts it is divided into, the higher the accuracy of the estimation model can be.

[0058] (Effects / Actions) As described above, according to this disclosure, the heat transfer coefficient is set according to the temperature distribution of the refrigerant flow path, and then the wafer temperature is estimated, so the wafer temperature can be estimated for each region and controlled with high accuracy.

[0059] Although embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure.

[0060] The following describes, but is not limited to, embodiments that may constitute the present invention. (Aspect 1) A processing chamber is located inside a vacuum vessel, and a plasma is formed inside it for processing the wafer to be processed. A sample stage is located in this processing chamber and on which the wafer is placed, Multiple heaters are arranged in multiple regions within a dielectric film that covers the upper surface of a disc-shaped or cylindrical substrate inside this sample stage, A refrigerant flow path is disposed inside the substrate, and a number of temperature sensors are disposed at a first number of locations between the refrigerant flow path and the upper surface of the substrate. A control unit that estimates the temperature or heat transfer coefficient of the walls at a second plurality of locations in the refrigerant flow path using the output from the temperature sensor and the temperature of the refrigerant, estimates the temperature of the wafer at a third plurality of locations using the estimated temperature or heat transfer coefficient of the walls in the refrigerant flow path and the output from the temperature sensor, and controls the operation of the plurality of heaters so that the wafer reaches a target temperature using the estimated wafer temperature. A plasma processing device equipped with [unspecified features]. (Aspect 2) A plasma processing apparatus according to Embodiment 1, The plasma processing apparatus wherein the first plurality of locations is smaller than the second plurality of locations. (Aspect 3) A plasma processing apparatus according to embodiment 1 or embodiment 2, The plasma processing apparatus wherein the first plurality of locations is smaller than the third plurality of locations. (Aspect 4) A plasma processing apparatus according to any one of embodiments 1 to 3, The control unit is a plasma processing apparatus that estimates the temperature of the wall surface of the refrigerant flow path using an observer. (Appendix 5) A plasma processing apparatus according to any one of embodiments 1 to 4, The control unit is a plasma processing apparatus that estimates the temperature of the wall surface of the refrigerant flow path using a Kalman filter. (Aspect 6) A plasma processing apparatus according to any one of embodiments 1 to 5, A plasma processing apparatus comprising a control unit which estimates the temperature or heat transfer coefficient of the walls of the second plurality of locations in the refrigerant flow path using at least one of the temperature of the inlet of the refrigerant flow path, the temperature of the refrigerant, the thermal conductivity of the substrate or the refrigerant, and the amount of current or power supplied to the heater. (Aspect 7) A plasma processing apparatus according to any one of embodiments 1 to 6, The dielectric film is formed by thermal spraying onto the upper surface of the metallic substrate to cover the upper surface of the plasma processing apparatus. [Explanation of Symbols]

[0061] 100: Plasma processing apparatus, 101: Vacuum vessel, 102: Shower plate, 103: Dielectric window, 104: Processing chamber, 105: Waveguide, 106: Power supply for electric field generation, 107: Magnetic field generation coil, 108: Substrate, 109: Wafer, 110: Vacuum exhaust port, 111: Conductive film, 112: Grounding, 113: Susceptor ring, 116: Plasma, 120: Sample stage, 124: High-frequency power supply, 125: High-frequency filter, 126: DC power supply, 127: High-frequency power supply, 128: Matching unit, 129: Matching 130: Variable load impedance box, 131: Conductor ring, 140: Dielectric film, 152: Coolant flow path, 160: Magnetic field forming unit, 161: Power supply connector, 170: PC, 171: PLC, 172: Control unit, 180: Heater power supply, 201: Dielectric film, 202: Temperature sensor, 203: Dielectric film, 204: Heater film, 205: Shield film, 206: Dielectric film, 207: Electrode film, 208: Dielectric film, 209: Temperature estimation unit, 210: Control calculation unit, 406: PID control unit

Claims

1. A processing chamber is located inside a vacuum vessel, and a plasma is formed inside it for processing the wafer to be processed. A sample stage is located in this processing chamber and on which the wafer is placed, Multiple heaters are arranged in multiple regions within a dielectric film that covers the upper surface of a disc-shaped or cylindrical substrate inside this sample stage, A refrigerant flow path is disposed inside the substrate, and a number of temperature sensors are disposed at a first number of locations between the refrigerant flow path and the upper surface of the substrate. A control unit that estimates the temperature or heat transfer coefficient of the walls at a second plurality of locations in the refrigerant flow path using the output from the temperature sensor and the temperature of the refrigerant, estimates the temperature of the wafer at a third plurality of locations using the estimated temperature or heat transfer coefficient of the walls in the refrigerant flow path and the output from the temperature sensor, and controls the operation of the plurality of heaters so that the wafer reaches a target temperature using the estimated wafer temperature. A plasma processing device equipped with [unspecified features].

2. A plasma processing apparatus according to claim 1, The plasma processing apparatus wherein the first plurality of locations is smaller than the second plurality of locations.

3. A plasma processing apparatus according to claim 1 or 2, The plasma processing apparatus wherein the first plurality of locations are smaller than the third plurality of locations.

4. A plasma processing apparatus according to claim 1 or 2, The control unit is a plasma processing apparatus that estimates the temperature of the wall surface of the refrigerant flow path using an observer.

5. A plasma processing apparatus according to claim 1 or 2, The control unit is a plasma processing apparatus that estimates the temperature of the wall surface of the refrigerant flow path using a Kalman filter.

6. A plasma processing apparatus according to claim 1 or 2, A plasma processing apparatus comprising a control unit which estimates the temperature or heat transfer coefficient of the wall surface at a second plurality of locations in the refrigerant flow path using at least one of the temperature of the inlet of the refrigerant flow path, the temperature of the refrigerant, the thermal conductivity of the substrate or the refrigerant, and the amount of current or power supplied to the heater.

7. A plasma processing apparatus according to claim 1 or 2, The dielectric film is formed by thermal spraying onto the upper surface of the metallic substrate to cover the upper surface of the plasma processing apparatus.

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