Method for manufacturing SiC wafers with residual stress control

Abstract

To provide a method for manufacturing a SiC wafer having residual stress control.SOLUTION: A method for manufacturing a SiC wafer comprises steps of: forming a first SiC layer (60) on a support (58); separating the support (58) from the first SiC layer (60); and growing a second SiC layer (68) on the first SiC layer (60). The step of growing the second SiC layer on the first SiC layer includes: introducing the precursor of a first dopant having a first conductive type (N) and generating a first stress in the second SiC layer (68) in a gas phase; and introducing the precursor of a second dopant having a second conductive type (P) opposite to the first conductive type (N) and for generating a second stress opposite to the first stress and balancing the first stress in the second SiC layer (68) in a gas phase, and consequently, the SiC wafer has no warp effect.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] This invention relates to a manufacturing process for SiC wafers that has control over residual stress. [Background technology]

[0002] As is well known, semiconductor devices are typically manufactured on silicon wafers. However, silicon carbide (SiC) wafers are becoming increasingly popular, at least in part, due to their advantageous chemophysical properties. For example, SiC typically has a wider bandgap than silicon. As a result, even at relatively small thicknesses, SiC has a higher breakdown voltage than silicon and can therefore be used beneficially in high-voltage applications such as power devices.

[0003] Silicon carbide can be found in different crystalline forms, or polytypes. The most common polytypes are the cubic polytype (3C-SiC polytype), the hexagonal polytype (4H-SiC and 6H-SiC polytypes), and the rhombohedral polytype (15R-SiC polytype). Of these, the 3C-SiC cubic polytype is currently the subject of detailed study due to its unique properties compared to other wafer polytypes. For example, 3C-SiC wafers typically have a lower trap density at the SiO2 / 3C-SiC interface and a higher mobility of channel electrons. Another property that makes 3C-SiC of interest is its on-state resistance R ON The value may be low, which is particularly useful for devices operating at 650V or higher.

[0004] However, the manufacturing of silicon carbide wafers is more complex than that of silicon wafers, and 3C-SiC substrates are not currently commercially available.

[0005] In particular, the inventors have found that silicon carbide wafers tend to warp, which in fact makes the manufacture of electronic devices unstable. This phenomenon is more pronounced in larger wafers, especially those exceeding 6 inches.

[0006] Patent document EP2782117 describes a SiC epitaxial wafer comprising a SiC substrate and a first P-type SiC epitaxial layer formed on the SiC substrate and containing P-type and N-type impurities. However, the aforementioned problem remains unresolved. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] European Patent EP2782117 [Overview of the project] [Problems that the invention aims to solve]

[0008] The object of the present invention is to provide a silicon carbide wafer manufacturing process that overcomes the shortcomings of known technologies and enables the manufacture of silicon carbide wafers even in large dimensions. [Means for solving the problem]

[0009] According to the present invention, a process for manufacturing silicon carbide wafers is provided, as defined in the claims.

[0010] To better understand the present invention, embodiments thereof are described below with reference to the accompanying drawings, as purely non-limiting examples. [Brief explanation of the drawing]

[0011] [Figure 1]A schematic cross-sectional view showing the state at a certain stage in a manufacturing process, that is, one embodiment of a manufacturing method, of a silicon carbide wafer, particularly a 3C-SiC wafer. [Figure 2] A schematic cross-sectional view showing the state at a certain stage in a manufacturing process, that is, one embodiment of a manufacturing method, of a silicon carbide wafer, particularly a 3C-SiC wafer. [Figure 3] A schematic cross-sectional view showing the state at a certain stage in a manufacturing process, that is, one embodiment of a manufacturing method, of a silicon carbide wafer, particularly a 3C-SiC wafer. [Figure 4] A schematic cross-sectional view showing the state at a certain stage in a manufacturing process, that is, one embodiment of a manufacturing method, of a silicon carbide wafer, particularly a 3C-SiC wafer. [Figure 5] A schematic cross-sectional view showing the state at a certain stage in a manufacturing process, that is, one embodiment of a manufacturing method, of a silicon carbide wafer, particularly a 3C-SiC wafer. [Figure 6] A schematic cross-sectional view showing the state at a certain stage in a manufacturing process, that is, one embodiment of a manufacturing method, of a silicon carbide wafer, particularly a 3C-SiC wafer.

Embodiments for Carrying out the Invention

[0012] The steps or stages in FIGS. 1-3 are of a known type and are described here for the sake of completeness of the description and to better understand the present invention. For example, these processing steps are known from U.S. Patent Publication No. 2020 / 144047.

[0013] In Figure 1-6, a silicon carbide wafer manufacturing process, i.e., a manufacturing method, is illustrated with reference to a CVD growth apparatus 10. The apparatus 10 has a reaction chamber 24 that defines a closed space in which the chemical reactions for SiC wafer growth and doping take place. The apparatus 10 has a heater (not shown), an inlet duct 16, and an outlet duct 18, in a known embodiment. The apparatus 10 further has a support 20 (also referred to as a “susceptor”) and a container 22, for example, cup-shaped. The support 20 and the container 22 are located within the reaction chamber 24. The heater is configured to heat the reaction chamber 24 and what is contained within the reaction chamber 24 (e.g., the support 20, the container 22, gas, substrate, wafer, or other object or substrate). The inlet duct 16 provides a fluid path from the environment outside the apparatus 10 to the reaction chamber 24 and can be used to introduce precursors and gases into the reaction chamber 24. The outlet duct 18 provides a fluid path from the reaction chamber 24 to the outside of the apparatus 10. It can be used to discharge reaction gases formed in the reaction chamber 24 to the outside. The support 20 is placed on the container 22 within the reaction chamber 24. The support 20 constitutes a platform for receiving substrates or wafers and maintaining them inside the reaction chamber 24. In particular, as will be described later, silicon substrates are placed on the support 20 during the manufacturing period of SiC wafers.

[0014] Apparatus of the type described above or similar apparatuses are known, for example, from U.S. Patent Publication 2018 / 090350, which describes a suspender having an inclined shape or formed by a plurality of downward-facing bars. Also, patent document US2020 / 144047 describes an apparatus equipped with a suspender similar to apparatus 10 and usable for carrying out the present invention.

[0015] In detail, in Figure 1, a substrate 58 made of the first material, which is a silicon substrate, is precisely positioned within the reaction chamber 24 and on the seat 48 of the support 20. The substrate 58 is inserted into the seat 48.

[0016] The substrate 58 has the smallest possible thickness to suit the characteristics of the vulnerability. For example, the substrate 58 can have a thickness of at least 60-70 μm, particularly between 200 μm and 300 μm.

[0017] The substrate 58 typically has a crystalline structure. Furthermore, in this step, the reaction chamber 24 is at room temperature.

[0018] Once the substrate 58 is positioned on the support 20, the reaction chamber 24 is sealed and heated to a first temperature by a heater. For example, this first temperature can be between 450°C and 550°C. A first pressure level is also set within the reaction chamber 24, for example, 8 × 10 -5 bar and 12x10 -5 It is possible to place it between the bar and the bar.

[0019] After heating the reaction chamber 24 to the first temperature, it is then raised to a second temperature that is even higher than the first temperature. For example, the second temperature can be between 1050°C and 1150°C. A second pressure level is also set in the reaction chamber 24, which is even higher than the first pressure level, for example, between 75 mbar and 125 mbar.

[0020] The reaction chamber 24 is maintained at the second pressure level for the remainder of the process.

[0021] After heating the reaction chamber 24 to the second temperature, the substrate 58 is immersed in hydrogen (H2). The hydrogen is introduced into the reaction chamber 24 via the inlet duct 16. Furthermore, the substrate 58 is activated by introducing hydrogen chloride (HCl) into the reaction chamber 24 via the inlet duct 16.

[0022] Next, the reaction chamber 24 is heated by the heater to a third temperature even higher than the second temperature. For example, the third temperature can be between 1340°C and 1400°C.

[0023] Referring again to Figure 1, once the reaction chamber 24 is set to the third temperature or after it has reached the third temperature, a carbon-based precursor is introduced into the reaction chamber 24 via the inlet duct 16. The carbon-based precursor carbonizes the surface silicon atoms of the substrate 58 to form a thin SiC layer, particularly a 3C-SiC layer. In one exemplary example, the thin SiC layer has a thickness of several nanometers. This step is also called "ramp carbonization." As will be described later, this thin SiC layer acts as a seed for growing a further, even hotter SiC layer (particularly a 3C-SiC polytype).

[0024] When the reaction chamber 24 is at the third temperature, a silicon-based precursor is added to the carbon-based precursor in the reaction chamber 24. As a result, as illustrated in Figure 2, the first SiC layer 60 begins to grow epitaxially from the thin SiC layer. This step is often defined as "hetero-epitaxial growth." The first SiC layer 60 is the SiC seed layer described above.

[0025] Next, a melting process is carried out. In particular, the melting is performed by maintaining a flow of H2 in the reaction chamber 24 through the inlet duct 16. During the melting period, the reaction chamber 24 is heated by the heater to a fourth temperature that is above the melting temperature of the substrate 58 and even lower than the melting temperature of the first SiC layer 60. For example, the fourth temperature can be between 1550°C and 1650°C. As a result, as illustrated in Figure 3, the substrate 58 melts (indicated by reference numeral 66 in Figure 3) and is deposited in the container 22 and recovered by the absorbent material 33 (e.g., a sponge-like material).

[0026] The reaction chamber 24 can be maintained at the fourth temperature until the entire substrate 58 is removed from the first SiC layer 60, or until a thin residual layer 70 of the substrate 58 remains on the support 20 (the residual layer 70 of the substrate 58 is then removed by an etching process).

[0027] In Figure 4, a silicon and carbon-based precursor is introduced into the reaction chamber 24 via the inlet duct 16. Thus, the first SiC layer 60 continues to increase in thickness, or the second SiC layer 68 begins to grow on the first SiC layer 60 (e.g., by a CVD process). This step is often referred to as "homo-epitaxial growth." The silicon and carbon-based precursor can be supplied during the melting step of the substrate 58. Alternatively, the silicon and carbon-based precursor can be supplied after the melting process of the substrate 58 is complete.

[0028] When the second SiC layer 68 reaches the desired thickness, the flow of silicon and carbon-based precursors is stopped. All reaction gases that may be present in the reaction chamber 24 are removed from the reaction chamber 24 via the outlet duct 18.

[0029] Referring to Figure 5, if the SiC wafer contains residual portions 70 of the substrate 58, these can be removed by an etching process during or at the end of the growth of the second SiC layer 68. In this case, an etching compound such as hydrochloric acid (HCl) (particularly in gaseous form) is introduced into the reaction chamber 24 via the inlet duct 16, which removes the residual portions 70, and the removed residue is discharged from the reaction chamber 24 via the outlet duct 18.

[0030] Thus, a SiC wafer 72 is obtained. This SiC wafer 72 has a diameter between 2 and 12 inches, particularly 6 inches.

[0031] The SiC wafer 72 can be used, for example, as a substrate for the manufacture of electronic devices (for example, by growing additional layers thereon and / or performing steps such as dopant injection and activation, lithography, etc.).

[0032] According to one aspect of the present invention, doping of the SiC layer 68 is carried out during the step period of CVD growth, as shown in Figure 4. This aspect of the present invention is illustrated in Figure 6, which is a replica of Figure 4.

[0033] The doping here has a dual function: setting a desired value for the electrical resistivity of the wafer 72 as a function of subsequent steps in the formation of the electronic component, and regulating the net stress value exposed to the SiC wafer 72 at the end of the manufacturing step.

[0034] More specifically, in one embodiment of the present invention, the doping process of the second SiC layer 69 is carried out by simultaneously supplying two different dopant species, one N-type and one P-type, during the CVD growth period, the dopant species being supplied by using precursors in the gas phase, such as nitrogen (N2) for N-type doping and trimethylaluminum, TMA, or Al2(CH3)6 for P-type doping with aluminum atoms. The supply of these two different dopant species is not simultaneous, but in any case, at some point during the CVD growth, both dopant species may be present in the reaction chamber used for such CVD growth. The same applies to the formation of the seed layer 60.

[0035] As the inventors have learned, it is possible to regulate the tensile and compressive stresses of the SiC wafer 72 by appropriately calibrating the concentrations of N and P dopants in the SiC wafer 72 (or, equivalently, the dose of dopants or precursors introduced into the reaction chamber). In fact, compressive and tensile stresses act in directions perpendicular to the defined planes of the surface of the SiC wafer 72 and tend to warp in mutually opposite directions. N-type doping with N2 allows for regulation of stress in the compressive direction (acting in a first direction), while P-type doping with TMA allows for regulation of stress in the tensile direction (acting in a second direction that is parallel to and opposite to the first direction).

[0036] According to what the inventor has learned, a desired stress balance can be obtained by introducing a precursor in the gas phase in a flow measured in sccm (standard cubic centimeters per minute) that satisfies the following ratio into the reaction chamber 24. When a nitrogen flow equal to "x" sccm, which is selected as a function of the N-type doping desired to be obtained in the SiC wafer 72, is given, the flow "y" of TMA is between 0.01% and 1% of the value of x. For example, about 2100 cm 3 Considering the reaction chamber 24 having an internal volume of, the value of x may be in the range between 500 and 1800 in sccm, and the value of y may be between 0.1 and 5 in sccm, and these values are selected to satisfy the aforementioned ratio.

[0037] It is clear that the values of the flow rate expressed in sccm may vary as a function of the dimensions of the reaction chamber used and the desired dopant concentration at the level of the SiC wafer 72.

[0038] In order to balance the stress at the wafer level, as verified by the inventor, the N-type dopant (N2) concentration can be set within the range of 10 10 atoms / cm 3 -10 20 atoms / cm 3 and the P-type dopant (Al) concentration can be set within the range of 10 17 atoms / cm 3 -10 19 atoms / cm 3 More specifically, as verified by the inventor, the N-type dopant concentration is within the range of 2×10 19 atoms / cm 3 -6×10 19 atoms / cm 3 and the P-type dopant concentration is within the range of 1.5×10 18 atoms / cm 3 -7×10 18 atoms / cm 3It is possible to obtain a substantially flat wafer 72 if the values ​​are within the specified range. The stress balance using the above-mentioned values ​​is particularly effective in the case of 3C-SiC.

[0039] Generally, dopant concentrations may vary depending on the electrical conditions of the wafers manufactured in that manner. For example, 10 18 Number of atoms / cm 3 To obtain a SiC wafer 72 having a net N-type doping level measured at the level of the SiC wafer 72, the concentration of the N-type dopant measured at the level of the wafer 72 is 4 × 10 18 -1.5 × 10 19 Number of atoms / cm 3 The concentration of the P-type dopant measured at the level of wafer 72 was 10 17 Number of atoms / cm 3 Even higher than (for example, 1 x 10 18 Number of atoms / cm 3 ) and 10 19 Number of atoms / cm 3 Even lower than (for example, 8 x 10) 18 Number of atoms / cm 3 ).

[0040] In one embodiment, the above-described manufacturing process is carried out within the same reaction chamber 24, and in particular, the product being manufactured (i.e., the SiC wafer 72 and its intermediate product formed by two or more laminates between the substrate 58 and layers 60 and 68) is not removed from the reaction chamber 24. The inventors have found that if the SiC wafer 72 (or its intermediate product) is removed from the reaction chamber 24 during the intermediate manufacturing steps, there is a high risk that the wafer 72 (or its intermediate product) will be damaged. In particular, if any of the laminates formed in relation to Figures 2 to 4 is removed from the reaction chamber 24 to perform a step to remove the substrate 58 (e.g., using a delamination process), such a laminate is highly likely to be damaged or cracked during the removal step. On the other hand, by performing a melting process of the substrate 58 within the reaction chamber 24, as described with reference to Figure 3, and, if necessary, by completing the etching step described with reference to Figure 4, layers 60 and 68 are not compromised, and the SiC wafer 72 thus obtained does not exhibit cracks or other physical damage.

[0041] Finally, it is clear that various modifications and alterations can be made to the apparatus and methods described and illustrated herein without departing from the scope of the invention as defined in these claims. For example, the present invention can also be applied to balance the stress effect by introducing an N-type dopant species in order to obtain net P-type doping on a SiC wafer. Furthermore, in the case of N-type doping, a dopant species to replace nitrogen, such as phosphorus (P), can be used, and in the case of P-type doping, a dopant species to replace aluminum, such as boron (B), can be used.

Claims

1. In a method for manufacturing a silicon carbide SiC wafer consisting of multiple steps carried out in the same reaction chamber (24), The step of forming a seed SiC layer (60) on a support (58), A step of growing a further SiC layer (68) on the seed SiC layer (60), comprising the substep of introducing a precursor of a first dopant having a first conductivity type (N) and generating a first stress within the further SiC layer (68) into the reaction chamber (24) in a gas phase, and a substep of introducing a precursor of a second dopant having a second conductivity type (P) opposite to the first conductivity type and generating a second stress opposite to the first stress within the further SiC layer (68) into the reaction chamber (24) in a gas phase, and The step of removing the support (58) at least partially from the seed SiC layer (60), A method comprising a substep of introducing the precursor of the first dopant into the reaction chamber (24) in a gas phase, and introducing the precursor of the second dopant into the reaction chamber (24) in a gas phase.

2. The method according to claim 1, wherein the step of removing the support (58) at least partially is performed by melting the support (58) at least partially in the reaction chamber (24).

3. The method according to claim 2, further comprising the step of completing the removal of the support (58) by etching the remaining portion of the support (58) within the reaction chamber (24).

4. The method according to any one of claims 1 to 2, wherein the step of melting the support (58) is performed by heating the reaction chamber (24) to a temperature above the melting temperature of the support (58) and below the melting temperature of the seed SiC layer (60).

5. The method according to any one of claims 1 to 4, wherein the thickness of the further SiC layer (68) is even greater than the thickness of the seed SiC layer (60).

6. The method according to any one of claims 1 to 5, wherein the material of the seed SiC layer (60) is 3C-SiC.

7. The method according to any one of claims 1 to 6, wherein the material of the further SiC layer (68) is 3C-SiC.

8. The precursor of the first dopant is nitrogen N ２ The method according to any one of claims 1 to 7.

9. The method according to any one of claims 1 to 8, wherein the precursor of the second dopant is trimethylaluminum TMA.

10. The method according to any one of claims 1 to 9, wherein the precursor of the second dopant is introduced into the reaction chamber (24) in a flow expressed in sccm, having a value between 0.01% and 1% of the sccm flow of the precursor of the first dopant.

11. The method according to any one of claims 1 to 10, wherein the precursor of the first dopant is introduced into the reaction chamber (24) to generate a concentration of the first dopant in the further SiC layer (68) that is an order of magnitude greater than the respective concentrations of the second dopants.

12. The precursor of the first dopant is introduced into the reaction chamber (68) to generate a concentration of the first dopant between 2×10 １９ atoms / cm ３ and 6×10 １９ atoms / cm ３ in the further SiC layer (68), and the precursor of the second dopant is introduced into the reaction chamber (24) to generate a concentration of the second dopant between 1.5×10 １８ atoms / cm ３ and 7×10 １８ atoms / cm ３ in the further SiC layer (68). The method according to any one of claims 1 to 11.

13. The method according to any one of claims 1 to 12, wherein the first conductivity type is N type, the second conductivity type is P type, the first stress is compression type, and the second stress is tensile type.

14. A method for manufacturing a silicon carbide SiC wafer comprising a plurality of steps carried out in the same reaction chamber (24), The step of forming a seed SiC layer (60) on a support (58), A step of growing a further SiC layer (68) on the seed SiC layer (60), comprising the substep of introducing a precursor of a first dopant having a first conductivity type (N) and generating a first stress within the further SiC layer (68) into the reaction chamber (24) in a gas phase, and a substep of introducing a precursor of a second dopant having a second conductivity type (P) opposite to the first conductivity type and generating a second stress opposite to the first stress within the further SiC layer (68) into the reaction chamber (24) in a gas phase, and The step of removing the support (58) at least partially from the seed SiC layer (60), It has, A method for growing the seed SiC layer (60) by introducing the precursor of the first dopant in the gas phase and the precursor of the second dopant in the gas phase into the reaction chamber (24) simultaneously or at least partially during the respective time intervals in which they are superimposed.

15. The method according to any one of claims 1 to 14, wherein, in order to grow the further SiC layer (68), the precursor of the first dopant in the gas phase and the precursor of the second dopant in the gas phase are introduced into the reaction chamber (24) simultaneously or at least partially during the respective time intervals in which they overlap.

16. The method according to any one of claims 1 to 15, wherein the step of growing the further SiC layer (68) comprises performing CVD growth in the presence of the precursors of the first and second dopants.

17. The method according to any one of claims 1 to 16, wherein the wafer has a diameter of 6 inches.

18. The method according to any one of claims 1 to 17, wherein the support (58) is a silicon substrate.

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