Switch circuits and power supply circuits

Abstract

This switch circuit is equipped with: a first switching element in which the connection state between a power generation element and a power storage device is controlled according to the voltage to be applied to a first control terminal; and a control circuit which outputs a first voltage for keeping the first switching element switched on to the first control terminal from when the voltage difference between ends of the power storage device is in an initial state until the voltage difference, which increases as time passes, reaches a first prescribed value which is larger compared to the initial state, and outputs a second voltage for keeping the first switching element switched off to the first control terminal from when the voltage difference exceeds the first prescribed value until the voltage difference falls below a second prescribed value which is smaller than the first prescribed value.

Description

Technical Field

[0001] The present invention relates to a switch circuit and a power supply circuit.

Background Art

[0002] As power for operating a control circuit in a power conversion circuit that converts power generated from a vibration power generation element, in order to use the power generated from such a vibration power generation element itself, the power generated by a power generation element such as a vibration power generation element is stored in a capacitor such as a capacitor and supplied to the control circuit. It is known. At that time, a cold start switch having a function of directly connecting the output of the power generation element and the capacitor is provided, and the control of the circuit is started by the power stored in the capacitor. After that, when the voltage from the power generation element becomes high, the connection between the output of the power generation element and the capacitor is cut off to reduce the power consumption in the cold start switch. (Fig. 5 of Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is desirable that the cold start switch can supply the necessary power as stably as possible. However, when the output changes greatly due to vibration as in the case of a vibration power generation element, it is difficult to turn on and off the cold start switch at an appropriate timing. In that case, the utilization efficiency of the power generated from the power generation element decreases.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide a switch circuit and a power supply circuit that can control the on and off of a cold start switch at an appropriate timing and improve the utilization efficiency of the power generated from a power generation element. [Means for solving the problem]

[0006] This invention Switch circuit This includes a first switching element whose connection state between the power generation element and the capacitor is controlled according to the voltage applied to the first control terminal, The latch circuit includes a control circuit that controls the voltage of the first control terminal so that the first switching element is turned on or off, and the latch circuit is Is the voltage difference between the two ends of the aforementioned capacitor in its initial state? at time As time passes, it gets bigger 、 Until the voltage difference reaches a first predetermined value that is greater than the initial state. ,before The first voltage that keeps the first switching element turned on is The first control terminal The output is generated, and when the voltage difference exceeds the first predetermined value, until the voltage difference falls below a second predetermined value which is smaller than the first predetermined value. ,before The second voltage that keeps the first switching element off is Output to the first control terminal .

[0007] In the above configuration, the power generation element may be configured to include a power generation unit that outputs an alternating current and a rectifier circuit that rectifies the alternating current.

[0008] In the above configuration, the capacitor has one end connected to a reference potential, and the other end is connected to the power generation element by the first switching element, the first switching element being an enhancement type FET, and the control circuit can be configured to output the voltage at the terminal of the first switching element on the power generation element side as the first voltage, and the reference potential as the second voltage.

[0009] In the above configuration, the rectifier circuit generates a positive voltage relative to the reference potential, and the first switching element can be an enhancement-type NFET.

[0010] In the above configuration, the rectifier circuit generates a negative voltage with respect to the reference potential, and the first switching element can be an enhancement-type PFET.

[0011] In the above configuration, the capacitor has one end connected to a reference potential, and the other end is connected to the power generation element by the first switching element, the first switching element being an enhancement type FET, and the control circuit can be configured to output the reference potential as the first voltage and the voltage at the terminal of the first switching element on the power generation element side as the second voltage.

[0012] In the above configuration, if the first switching element is not an enhancement-type NFET, the rectifier circuit generates a positive voltage with respect to the reference potential, and the first switching element can be an enhancement-type PFET.

[0013] In the above configuration, if the first switching element is not an enhancement-type PFET, the rectifier circuit generates a negative voltage with respect to the reference potential, and the first switching element can be an enhancement-type NFET.

[0014] In the above configuration, the control circuit is configured to include an enhancement-type FET, which has a second switching element whose connection state between the first switching element and the capacitor is controlled according to the voltage applied to the second control terminal, and the control circuit outputs the reference potential to the second control terminal when the voltage difference between the two ends of the capacitor increases over time from an initial state until the voltage difference reaches a first predetermined value, and when the voltage difference exceeds the first predetermined value, it outputs the voltage of the capacitor-side terminal of the second switching element to the second control terminal until the voltage difference falls below the second predetermined value.

[0015] In the above configuration, a third switching element is provided for controlling the connection state between the first control terminal and the reference potential according to the voltage applied to the third control terminal. One end of the capacitor is connected to the reference potential, and the other end thereof is controlled by the first switching element for the connection state with the power generation element. The first control terminal is capacitively coupled to the power generation element. The first switching element is an enhancement-type FET. The control circuit continuously outputs the reference potential to the third control terminal until the voltage difference reaches the first predetermined value, and when the voltage difference exceeds the first predetermined value, the voltage of the other end of the capacitor is output to the third control terminal until the voltage difference is less than the second predetermined value.

[0016] In the above configuration, a fourth switching element with a breakdown voltage lower than that of the first switching element is provided for controlling the connection state between the first switching element and the capacitor according to the voltage applied to the first control terminal, and a limiting element for limiting the voltage between the first switching element and the fourth switching element from exceeding a third predetermined value.

[0018] In the above configuration, the control circuit can be configured to reset the latch state of the latch circuit when the voltage difference is less than the second predetermined value and output the first voltage for turning on the first switching element to the control terminal of the first switching element.

[0019] In the above configuration, in the initial state, the voltage difference between both ends of the capacitor can be 0V.

[0020] The present invention Power supply circuit is The system includes a first switching element that controls the connection state between a power generation element and a capacitor according to the voltage applied to a first control terminal, and a control circuit that controls the voltage at the first control terminal so that the first switching element is turned on or off. provided with a switch circuit and a power conversion circuit for converting the output power of the power generation element ru. The Control circuit is As the voltage difference across the capacitor increases over time from its initial state, a first voltage is output to the first control terminal to keep the first switching element turned on until the voltage difference reaches a first predetermined value greater than the initial state. When the voltage difference exceeds the first predetermined value, a signal for starting the power conversion circuit is output to the power conversion circuit The first switching element is kept off until the voltage difference falls below a second predetermined value which is smaller than the first predetermined value, and a second voltage is output to the first control terminal.

[0021] In the above configuration, the Control circuit can be configured to keep turning off until the voltage difference falls below the second predetermined value when the voltage difference exceeds the first predetermined value. The first switching element

[0022] In the above configuration, the Control circuit can be configured to turn off when the voltage difference exceeds the first predetermined value and output a signal for starting the power conversion circuit to the power conversion circuit. The first switching element

[0023] In the above configuration, the power conversion circuit can be configured to be a voltage conversion circuit that includes an inductor and converts a third voltage input from the power generation element into a fourth voltage.

[0024] In the above configuration, the Control circuit includes a determination circuit that determines whether or not the voltage difference exceeds the first predetermined value, and ,before when it is determined that the recorded voltage difference exceeds the first predetermined value The determination circuit at the time of determination 、 can be configured to include a generation circuit that generates the signal for starting.

Advantages of the Invention

[0025] According to the present invention, it is possible to provide a switch circuit and a power supply circuit that can control the on and off of a cold start switch at an appropriate timing.

Brief Description of the Drawings

[0026] [Figure 1] FIG. 1 is a circuit diagram showing a power supply circuit in which a switch circuit according to an embodiment is used. [Figure 2] FIG. 2 is a diagram showing the on and off of a switch with respect to time, and a current IL flowing through an inductor in a voltage conversion circuit in which a switch circuit according to an embodiment is used. [Figure 3] Figures 3(a) and 3(b) are circuit diagrams of the switch circuit according to Example 1. [Figure 4] Figure 4 is a circuit diagram of the switch circuit according to Example 1. [Figure 5] Figure 5 is a circuit diagram of the control circuit in Example 1. [Figure 6] Figure 6 is a circuit diagram of the determination circuit in Example 1. [Figure 7] Figure 7 shows the time changes of each voltage and the on / off state of the FET in the switch circuit according to Example 1. [Figure 8] Figures 8(a) and 8(b) are circuit diagrams of the latch circuit in Example 1. [Figure 9] Figures 9(a) and 9(b) are circuit diagrams of a switch circuit according to Modification 1 of Example 1. [Figure 10] Figure 10 is a circuit diagram of a switch circuit according to a modified example 1 of Example 1. [Figure 11] Figure 11 shows the time changes of each voltage and the on / off state of the FET in a switch circuit according to a modified example 1 of Example 1. [Figure 12] Figures 12(a) and 12(b) are circuit diagrams of a switch circuit according to a modified example 2 of Example 1. [Figure 13] Figure 13 shows the time changes of each voltage, current, and the on / off state of the FET in the switch circuit according to Example 2. [Figure 14] Figure 14 shows the time changes of each voltage, current, and the on / off state of the FET in the switch circuit according to Modification 1 of Example 2. [Figure 15] Figure 15 is a circuit diagram of the switch circuit according to Example 3. [Figure 16] Figure 16 is a circuit diagram of the switch circuit according to Example 4. [Figure 17] Figure 17 is a circuit diagram of a switch circuit according to a modified example 1 of Example 4. [Figure 18] Figure 18 is a block diagram showing a system in which the switch circuits of Examples 1 to 4 and their modified forms are used. [Modes for carrying out the invention]

[0027] The following describes an embodiment with reference to the drawings. [Examples]

[0028] Figure 1 is a circuit diagram showing a power supply circuit using the switch circuit according to the embodiment. As shown in Figure 1, the power supply circuit includes a voltage conversion circuit 12 and a switch circuit 20. The switch circuit 20 includes a cold start switch CSW and a control circuit 16. The cold start switch CSW is a switch that turns on and off the connection between the input terminal Tin and the output terminal Tout. The control circuit 16 controls the on / off state of the cold start switch CSW. The control circuit 16 also outputs an enable signal Ven to the voltage conversion circuit 12 to start the voltage conversion circuit 12. The output of the power generation element 10 is input to the input terminal Tin of the switch circuit 20 and the input terminal T1 of the voltage conversion circuit 12. The power generation element 10 is composed of a power generation unit 10a, which is an energy harvesting element such as a vibration power generation element, and a rectifier circuit 10b. When the power generation unit (power generation section) 10a outputs an alternating current, the alternating current output by the power generation unit 10a is rectified by the rectifier circuit 10b and input to the input terminal Tin.

[0029] The vibration power generation element is, for example, a piezoelectric element using a piezoelectric material or a MEMS (Micro Electro Mechanical Systems) element using MEMS. The vibration power generation element is installed, for example, on a road or bridge, and generates electricity from vibrations caused by pedestrians or vehicles passing by. The power generated by the power generation element 10 is minute and changes over time. Example 1 is an example in which the output of the power generation element 10 has a rectifier circuit 10b that is positive with respect to ground. In this case, the voltage V2 of the capacitor C2 is positive. Thus, the power generation element 10 is an element that generates a voltage of one polarity with respect to ground (reference potential).

[0030] The output terminal Tout of the switch circuit 20 is connected to one end of the capacitor C2. Capacitor C2 is an electrostatic storage device. The output terminal T2 of the voltage conversion circuit 12 is also connected to one end of the capacitor C2. The voltage Vout at the output terminal Tout of the switch circuit 20 and the voltage V2 at the output terminal T2 of the voltage conversion circuit 12 are both the voltage across capacitor C2 relative to ground. In the following, when explaining the operation of the voltage conversion circuit 12, the voltage V2 will be used as the voltage across capacitor C2, but in other explanations, the voltage Vout will be used as the voltage across capacitor C2.

[0031] The voltage conversion circuit 12 converts the voltage V1 at input terminal T1 to the voltage V2 of capacitor C2 and outputs it to output terminal T2. The value obtained by dividing the voltage V1 by the current input to input terminal T1 corresponds to the input impedance of the voltage conversion circuit 12. The values ​​of each element of the voltage conversion circuit 12 are preset so that the input impedance of the voltage conversion circuit 12 matches the output impedance of the power generation element 10. Each part of the voltage conversion circuit 12, including the control unit 14, operates using the power stored in capacitor C2 from the power generation element 10.

[0032] Nodes N01 to N03 are provided between the input terminal T1 and output terminal T2 of the voltage conversion circuit 12. One end of switch SW1 is connected to node N01 and the other end is connected to node N02. One end of inductor L1 is connected to node N02 and the other end is connected to node N03. One end of switch SW4 is connected to node N03 and the other end is connected to output terminal T2. One end of primary capacitor C1 is connected to node N01 and the other end is connected to ground (reference potential). One end of switch SW2 is connected to node N02 and the other end is connected to ground. One end of switch SW3 is connected to node N03 and the other end is connected to ground. One end of secondary capacitor C2 is connected to output terminal T2 and the other end is connected to ground. Switches SW1 to SW4 are turned on or off based on control signals S1 to S4, respectively. The control unit 14 of the voltage conversion circuit 12 receives an enable signal Ven and a voltage Vout as input, and the control unit 14 outputs control signals S1 to S4. The control unit 14 and the control circuit 16 may be, for example, dedicated circuits or processors.

[0033] Figure 2 shows the on / off state of the switch and the current IL flowing through the inductor as a function of time in a voltage conversion circuit using the switch circuit according to the embodiment.

[0034] Before the power generation element 10 starts generating power, the voltage Vout across capacitor C2 is low, for example, 0V. When the voltage Vout is low, the cold start switch CSW is turned on, and the output of the power generation element 10 is connected to capacitor C2 without going through the voltage conversion circuit 12. Since the voltage conversion circuit 12 is not supplied with enough power to operate in substance, the voltage conversion circuit 12 does not operate. For example, the control signals S1~S4 are 0V, and at this time switches SW1~SW4 are off. When the voltage Vout across capacitor C2 becomes large enough to operate the voltage conversion circuit 12, the control circuit 16 turns off the cold start switch CSW and outputs an enable signal Ven to the voltage conversion circuit 12. As a result, the voltage conversion circuit 12 starts up and begins to operate. The control unit 14 of the voltage conversion circuit 12 begins to control switches SW1~SW4.

[0035] At time t00, the value of voltage V2 is V21. The control unit 14 keeps switches SW1 to SW4 in the off position. The charge stored in capacitor C1 increases due to the current generated by the power generation element 10, and the voltage V1 gradually increases. When the value of voltage V1 exceeds the threshold voltage V11, at time t01, the control unit 14 turns on switches SW1 and SW3 and keeps switches SW2 and SW4 in the off position. As a result, a current IL begins to flow from capacitor C1 to ground through node N01, switch SW1, inductor L1, and switch SW3. Between times t01 and t02, the current IL gradually increases, and the charge in capacitor C1 is released, so the voltage V1 gradually decreases. Magnetic field energy is stored in inductor L1.

[0036] At time t02, the value of voltage V1 is V12. The value of voltage V2 is V21. Current IL is maximum at IL1. The control unit 14 turns off switches SW1 and SW3 and turns on switches SW2 and SW4. Between times t02 and t03, the magnetic field energy stored in inductor L1 causes current IL to flow from ground through switch SW2, inductor L1 and switch SW4, charging capacitor C2. Voltage V2 rises.

[0037] At time t03, the control unit 14 turns off switches SW2 and SW4 and keeps switches SW1 and SW3 off. After time t03, the current IL is 0, the value of voltage V1 is V12, and the value of voltage V2 is V22. Voltage values ​​V21 and V22 may be lower or higher than voltage values ​​V11 and V12. As described above, when current is input from the power generation element 10 to input terminal T1 while switches SW1 to SW4 are off, capacitor C1 is charged. When the voltage V1 of capacitor C1 relative to ground on the node N01 side reaches the threshold voltage V11 and the voltage conversion circuit 12 operates, the charge from capacitor C1 moves to capacitor C2. The voltage of capacitor C2 relative to ground on the output terminal T2 side becomes the voltage V2 of output terminal T2.

[0038] Figures 3(a) and 3(b) are circuit diagrams of the switch circuit according to Embodiment 1. As shown in Figure 3(a), in Embodiment 1, an enhancement mode (normally off mode) NFETM11 is used as the cold start switch CSW. The threshold voltage of the NFETM11 is positive. The source of the NFETM11 is connected to the output terminal Tout, and the drain is connected to the input terminal Tin. Of the source and drain, the terminal connected to the output terminal Tout is the first terminal, and the terminal connected to the input terminal Tin is the second terminal. The gate is the control terminal. The cold start switch CSW is controlled to turn on when the voltage Vout is less than or equal to a predetermined reference voltage Vref, and to turn off when the voltage Vout is greater than the reference voltage Vref. Therefore, when the voltage Vout is less than or equal to the reference voltage Vref, the gate of the NFETM11 is connected to the drain without power supply. As a result, the NFETM11 turns on when the voltage Vin relative to the voltage Vout becomes greater than or equal to the threshold voltage of the NFETM11. As shown in Figure 3(b), when the voltage Vout is higher than the reference voltage Vref, a ground potential is applied to the gate of the NFETM11. This turns off the NFETM11.

[0039] As described above, when the voltage Vout across capacitor C2 is lower than the reference voltage Vref, the cold start switch CSW turns on without power supply and is not controlled by the control circuit. When the voltage Vout is higher than the reference voltage Vref, the cold start switch CSW turns off.

[0040] Figure 4 is a circuit diagram of a switch circuit according to Embodiment 1. As shown in Figure 4, the switch circuit 20 includes an NFETM 11 and a circuit 17. Circuit 17 is a circuit that applies a voltage VG to the gate so that the NFETM 11 turns on when the voltage Vout is less than or equal to the reference voltage Vref, as shown in Figure 3(a), and applies a voltage VG to the gate so that the NFETM 11 turns off when the voltage Vout is greater than the reference voltage Vref, as shown in Figure 3(b).

[0041] The NFETM11 is in enhancement mode, with its source connected to the output terminal Tout and its drain connected to the input terminal Tin. The power supply terminal Tp of the latch circuit 18 is connected to the drain of the NFETM11. The reference potential terminal Tg is connected to ground. The output terminal Tq1 is connected to the gate of the NFETM11. The control circuit 16 outputs voltages Vset and Vrst to the set terminal Tset and reset terminal Trst of the latch circuit 18, respectively, based on the voltage Vout. When a high level is input to terminal Tset as voltage Vset, the latch circuit 18 outputs the voltage Vin of the power supply terminal Tp to the output terminal Tq1 until a high level is input to terminal Trst. Also, when a high level is input to terminal Trst as voltage Vrst, the latch circuit 18 outputs the voltage 0V of the reference potential terminal Tg to the output terminal Tq1 until a high level is input to terminal Tset.

[0042] Figure 5 is a circuit diagram of the control circuit 16 in Embodiment 1. As shown in Figure 5, the voltage Vout is input to the determination circuits 22 and 24. The determination circuits 22 and 24 output the voltage Vout as voltage V01 and V02 when the voltage Vout is equal to or greater than the reference voltages Vref1 and Vref2, respectively, and output the ground potential 0V as voltage V01 and V02 when the voltage Vout is lower than the reference voltages Vref1 and Vref2, respectively.

[0043] The spike generation circuit 26 outputs a spike signal as a reset voltage Vrst when both voltages V01 and V02 are at a high level. The spike generation circuit 28 outputs a spike signal as a set voltage Vset when both voltages V01 and V02 are at a low level. The spike generation circuits 26 and 28 do not require a clock signal, are composed of FETs, and consume power only when generating the output pulse width, resulting in low power consumption. Therefore, they are ideal as circuits for configuring the control circuit of minute electromotive force elements such as piezoelectric elements that generate power from vibration as power generation elements. A spike signal is a single signal, and the interval between spike signals is sufficiently wide relative to the pulse width of the spike signal.

[0044] Figure 6 is a circuit diagram of the determination circuit in Embodiment 1. As shown in Figure 6, in determination circuits 22 and 24, diode D1 is connected in series in the forward direction and diode D2 in the reverse direction between the input terminal and ground where the voltage Vout is input. Although the connection state of the circuit elements is the same in determination circuits 22 and 24, the magnitudes of diodes D1 and D2 are set separately as described later. Node N1 between diodes D1 and D2 outputs voltages V01 and V02 via inverters Iv1 and Iv2. Inverters Iv1 and Iv2 use voltage Vout as the power supply voltage. The reverse current flowing through diode D2 is almost constant regardless of the voltage across its terminals. The forward current flowing through diode D1 depends on the voltage across its terminals. In the low voltage range of Vout, the voltage at node N1 hardly rises even when voltage Vout rises, but in the high voltage range of Vout, the voltage at node N1 rises sharply when voltage Vout rises. When voltage Vout is low, the voltage at node N1 is low, inverter Iv1 outputs voltage Vout, and inverter Iv2 outputs ground potential 0V. When the voltage of voltage Vout rises, the voltage at node N1 rises sharply, and the voltage at node N1 becomes above the threshold voltage of inverter Iv1. Inverter Iv1 outputs ground potential 0V and inverter Iv2 outputs voltage Vout.

[0045] By appropriately setting the sizes of diodes D1 and D2, inverter Iv2 can be configured to output voltage Vout when the voltage Vout is equal to or greater than a specified reference voltage, and to output ground potential 0V when the voltage Vout is lower than the reference voltage. For example, making diode D1 larger than D2 can raise the reference voltage, and making diode D1 smaller than D2 can lower the reference voltage. In the determination circuit 22, the reference voltage is set to Vref1, and in the determination circuit 24, the reference voltage is set to Vref2, which is higher than Vref1, and the sizes of diodes D1 and D2 in determination circuits 22 and 24 are set accordingly. As a result, when the voltage Vout is equal to or greater than the reference voltages Vref1 and Vref2, respectively, the determination circuits 22 and 24 output voltage Vout as voltages V01 and V02, and when the voltage Vout is lower than the reference voltages Vref1 and Vref2, they output ground potential 0V as voltages V01 and V02.

[0046] Figure 7 shows the time variation of each voltage and the on / off state of the FET in the switch circuit according to Embodiment 1. Voltages V01, V02, reset voltage Vrst, and set voltage Vset are shown with dashed lines, and voltage Vout is shown. As shown in Figure 7, at time t11, voltage Vin is near ground potential 0V, and the voltage Vout of capacitor C2 is also near ground potential 0V. Voltages V01, V02, reset voltage Vrst, and set voltage Vset are all at ground potential 0V. The gate voltage VG of NFETM11 is voltage Vin. NFETM11 is off. After time t11, voltage Vin rises. The latch circuit 18 is asymmetric, and the voltage VG at the output terminal Tq1 becomes voltage Vin and rises.

[0047] At time t12, when the voltage VG reaches the threshold voltage Vth of NFETM11, NFETM11 turns on. From time t12 onward, since NFETM11 is on, capacitor C2 begins to charge. This causes the voltage Vout to rise. Note that the rate of increase of voltages Vin and Vout may not be the same.

[0048] At time t13, if the voltage Vout becomes equal to or greater than the reference voltage Vref1, the determination circuit 22 outputs voltage Vout as voltage V01. At time t14, if the voltage Vout becomes equal to or greater than the reference voltage Vref2, the determination circuit 24 outputs voltage Vout as voltage V02. When both voltages V01 and V02 reach a high level, the spike generation circuit 26 outputs a spike signal 30 as a reset voltage Vrst. The height of the spike signal 30 is the same as the voltage Vout. The latch circuit 18 outputs ground potential 0V, which is the voltage of the reference potential terminal Tg, as voltage VG to the output terminal Tq1. NFETM 11 is turned off. When the spike signal 30 is output, the control circuit 16 outputs activation as an enable signal Ven to the control unit 14. As a result, the voltage conversion circuit 12 is activated and starts operating. From time t14 onward, the voltage Vout of capacitor C2 increases due to the output voltage V2 of the voltage conversion circuit 12.

[0049] At time t15, voltage Vin begins to decrease, and voltage Vout begins to decrease. At time t16, when voltage Vout falls below the reference voltage Vref2, the determination circuit 22 outputs ground potential 0V as voltage V02. At time t17, when voltage Vout falls below the reference voltage Vref1, the determination circuit 24 outputs ground potential 0V as voltage V01. When both voltages V01 and V02 reach ground potential 0V, the spike generation circuit 28 outputs a spike signal 32 as the set voltage Vset. The height of the spike signal 32 is the same as voltage Vout. The latch circuit 18 outputs Vin, which is the voltage of the power supply terminal Tp, as voltage VG to the output terminal Tq1. NFETM 11 turns on. When the spike signal 32 is output, the control circuit 16 outputs deactivation as the enable signal Ven to the control unit 14. As a result, the voltage conversion circuit 12 stops operating. At time t18, voltage Vout is approximately 0.

[0050] According to Embodiment 1, as shown in Figure 4, the connection state between the power generation element 10 and the capacitor C2 of the NFETM1 (first switching element) is controlled according to the voltage applied to the gate (first control terminal). Then, as shown from time t11 to t14 in Figure 7, the circuit 17 outputs a first voltage that keeps the gate of the NFETM11 turned ON until the voltage difference Vout-0V across the capacitor C2 becomes larger than the initial state (e.g., 0V) over time.

[0051] As a result, the NFETM11 in the cold start switch CSW turns on without power. At time t14, when the reset voltage Vrst is input to the latch circuit 18, it outputs a ground potential (see Figure 7) to the output terminal Tq1. This allows the NFETM11 to be turned off. In this way, the cold start switch CSW can be controlled stably.

[0052] The control circuit 16 outputs a reset voltage Vrst when the voltage difference between voltage Vout and ground potential increases over time and exceeds the reference voltage Vref2 (first reference voltage). The control circuit 16 also outputs an enable signal Ven to activate the voltage conversion circuit 12. This allows the cold start switch CSW to be turned off when voltage Vout increases and the power stored in capacitor C2 is used, for example, to power the voltage conversion circuit 12. The determination circuits 22 and 24 shown in Figure 5 function as determination circuits that determine whether the voltage difference between voltage Vout and ground potential exceeds the reference voltage Vref2. The spike generation circuit 26 and the control circuit 16 function as generation circuits that generate the enable signal Ven when it is determined that the voltage difference exceeds the reference voltage Vref2.

[0053] The control circuit 16 outputs a set voltage Vset when the voltage difference between voltage Vout and ground potential 0V decreases over time and falls below the reference voltage Vref1 (second reference voltage). The output of the latch circuit 18 switches from the second voltage to the first voltage. In other words, the latch state of the latch circuit is reset. This allows the cold start switch CSW to be turned on when the voltage Vout becomes small and the power stored in capacitor C2 is no longer used to power, for example, the voltage conversion circuit 12.

[0054] Figures 8(a) and 8(b) are circuit diagrams of the latch circuit 18 in Embodiment 1. In Figure 8(a), a NOR-type latch circuit is used as an example to describe the latch circuit 18. PFETM7, M10, M2, and NFETM1 are connected in series between the power supply terminal Tp and the reference potential terminal Tg. PFETM8, M9, M4, and NFETM3 are connected in series in parallel with these FETs between the power supply terminal Tp and the reference potential terminal Tg. The gates of PFETM8 and M7 are connected to the set terminal Tset and the reset terminal Trst, respectively. The gates of PFETM9 and M10 are connected to the reference potential terminal Tg.

[0055] The drains of PFETM2 and NFETM1 are commonly connected to node Q1, and the gates of PFETM2 and NFETM1 are commonly connected to node Q2. The drains of PFETM4 and NFETM3 are commonly connected to node Q2, and the gates of PFETM4 and NFETM3 are commonly connected to node Q1. PFETM4 and NFETM3 form an inverter, and PFETM2 and NFETM1 form an inverter. Nodes Q1 and Q2 are memory nodes and hold complementary voltages to each other.

[0056] Node Q1 is connected to output terminal Tq1, and node Q2 is connected to Tq2. Nodes Q1 and Q2 are connected to reference potential terminal Tg via NFETM5 and M6, respectively. The gates of NFETM5 and M6 are connected to reset terminal Trst and set terminal Tset, respectively.

[0057] When node Q1 is at a high level and node Q2 is at a low level, if voltage Vrst is at a low level, NFETM1 and M5 are off, PFETM2, M10 and M7 are on, NFETM3 and M6 are on, and PFETM4, M9 and M8 are off. When voltage Vrst becomes high, NFETM5 turns on and node Q1 becomes low level. Also, PFETM7 turns off. This switches node Q1 to a low level and node Q2 to a high level. Similarly, when node Q1 is at a low level and node Q2 is at a high level, and voltage Vset becomes high level, node Q1 becomes high level and node Q2 becomes low level.

[0058] As described above, when a high-level voltage Vset is input to the set terminal Tset, the latch circuit 18 outputs the voltage of the power supply terminal Tp to the output terminal Tq1 and the voltage of the reference potential terminal Tg to the output terminal Tq2 until a high-level voltage Vrst is input to the reset terminal Trst. When a high-level voltage Vrst is input to the reset terminal Trst, the latch circuit 18 outputs the voltage of the reference potential terminal Tg to the output terminal Tq1 and the voltage of the power supply terminal Tp to the output terminal Tq2 until a high-level voltage Vset is input to the set terminal Tset.

[0059] Alternatively, the drains of PFETM7 and M8 and the sources of PFETM2 and M4 may be directly connected without PFETM9 and M10. When the levels of nodes Q1 and Q2 invert, current flows from the power supply terminal Tp to the reference potential terminal Tg. PFETM9 and M10 are provided to prevent large currents from flowing when the voltage at power supply terminal Tp is high.

[0060] In a latch circuit where nodes Q1 and Q2 are symmetrical, as the power supply voltage (voltage at power supply terminal Tp relative to the reference potential terminal Tg) rises from 0V, it is not determined which of node Q1 or Q2 will reach the high level at power supply terminal Tp. In latch circuit 18, nodes Q1 and Q2 are asymmetrical, and as the power supply voltage of latch circuit 18 rises from 0V, the voltage at node Q1 becomes high level. To achieve this asymmetry, the gate width of NFETM5 is made narrower than the gate width of NFETM6. For example, the gate length of an NFET is 0.8 μm, the gate length of a PFET is 5 μm, the gate width of a PFET is 0.6 μm, and the gate widths of NFETM1 and M3 are 0.8 μm. In this case, the gate widths of NFETM5 and M6 are set to 15 μm and 60 μm, respectively. As a result, when the power supply voltage rises from 0V, the current I6 flowing through NFETM6 is greater than the current I5 flowing through NFETM5, and the voltage at node Q2 becomes lower than the voltage at node Q1. Therefore, the latch circuit 18 rises so that node Q1 becomes the voltage at power supply terminal Tp. If nodes Q1 and Q2 rise asymmetrically, other parameters may be changed. For example, the gate width of NFETM1 can be made narrower than the gate width of NFETM3. The gate widths of PFETM2, M10, and M7 can be made wider than the gate widths of PFETM4, M9, and M8, respectively. As a result, when the power supply voltage rises from 0V, the voltage at node Q2 becomes lower than the voltage at node Q1. Even if the voltage at power supply terminal Tp rises to, for example, around 5V, the gate widths of NFETM5 and M6 are made larger than the gate widths of the other FETs so that the levels of nodes Q1 and Q2 can be switched by voltages of about 1V Vset and Vrst.

[0061] Figure 8(b) shows an example of a NAND type latch circuit. The latch circuit 18 includes PFETM20a~M20c and M21a~M21c, and NFETM22a~M22d and M23a~M23d. The operation of the latch circuit 18 is the same as in Figure 8(a), so the explanation is omitted. The latch circuit 18 may have a circuit configuration other than those shown in Figures 8(a) and 8(b), as long as it performs the above operation.

[0062] As the circuit for applying the voltage VG to the gate of the FETM11 shown in Figure 4, the latch circuit 18 shown in Figures 8(a) and 8(b) is used. When the reset voltage Vrst (first control signal) is input to the latch circuit 18, it continuously outputs a second voltage to the gate of the NFETM1 that turns off the NFETM1. By using such a latch circuit 18, the latch circuit 18 can output the first voltage to the output terminal Tq1 before the reset voltage Vrst is input, and output the second voltage to the output terminal Tq1 when the reset voltage Vrst is input. This allows for a simple implementation of a circuit that generates the second voltage that turns off the NFETM11.

[0063] The latch circuit 18 outputs a first voltage to the gate of NFETM1 that turns on NFETM1 when the set voltage Vset (second control signal) is input, until the reset voltage Vrst is input. As a result, when the set voltage Vset is input to the latch circuit 18, the gate voltage VG of NFETM11 becomes the first voltage, and NFETM11 can be turned on.

[0064] [Example 1 Modification 1] In Modification 1 of Example 1, a PFET is used as the cold start switch (CSW). In this case, the first terminal and the second terminal are the drain and source of the PFET, respectively.

[0065] Figures 9(a) and 9(b) are circuit diagrams of a switch circuit according to Modification 1 of Embodiment 1. As shown in Figure 9(a), in Modification 1 of Embodiment 1, an enhancement-mode PFETM11a is used as the cold-start switch CSW. The threshold voltage of PFETM11a is negative. The source of PFETM11a is connected to the input terminal Tin, and the drain is connected to the output terminal Tout. When the voltage Vout is less than or equal to the reference voltage Vref, the gate of PFETM11a is connected to ground without power supply. As a result, PFETM11a turns on when the ground potential relative to the voltage Vin becomes less than or equal to the threshold voltage of PFETM11a. As shown in Figure 9(b), when the voltage Vout is higher than the reference voltage Vref, the input terminal Tin is connected to the gate of PFETM11a. As a result, PFETM11a turns off.

[0066] Figure 10 is a circuit diagram of a switch circuit according to Modification 1 of Example 1. As shown in Figure 10, in Modification 1 of Example 1, the NFETM 11 is replaced with an enhancement-type PFETM 11a compared to Figure 4 of Example 1. The source of the PFETM 11a is connected to the input terminal Tin, the drain is connected to the output terminal Tout, and the gate is connected to the output terminal Tq2 of the latch circuit 18a. The configuration of the latch circuit 18a is the same as the latch circuit 18 of Example 1, except that the output terminal Tq2 is connected to the gate of the PFETM 11a. The other circuit configurations are the same as in Figure 4 of Example 1 and will not be described.

[0067] Figure 11 shows the time evolution of each voltage and the on / off state of the FET in the switch circuit according to Modification 1 of Example 1. The gate voltage of PFETM11a with respect to the source voltage is shown as voltage VG-Vin. The threshold voltage of PFETM11a is negative. As shown in Figure 11, the change in voltage Vin with respect to time is the same as in Figure 7. At time t11, the gate voltage VG of PFETM11a is at ground potential 0V. PFETM11a is off. After time t11, the voltage Vin rises. Voltage VG-Vin is -Vin. The latch circuit 18 is asymmetric, and as the power supply voltage of the latch circuit 18 rises from 0V, the voltage at the output terminal Tq2 becomes low level (i.e., ground potential). Even if the voltage Vin rises, the voltage at the output terminal Tq2 remains at ground potential 0V.

[0068] At time t12, when the voltage VG-Vin becomes the threshold voltage Vth of PFETM11a, PFETM11a turns on. After time t12, the voltage Vout rises. At time t14, when the voltage Vout becomes greater than or equal to the reference voltage Vref2, the control circuit 16 outputs a spike signal 30 as a reset voltage Vrst to the reset terminal Trst of the latch circuit 18. The latch circuit 18 outputs the voltage Vin, which is the voltage of the power supply terminal Tp, as the voltage VG to the output terminal Tq2. As a result, the voltage VG-Vin becomes approximately 0V. Therefore, PFETM11a turns off.

[0069] At time t17, when the voltage Vout falls below the reference voltage Vref1, the control circuit 16 outputs a spike signal 32 as the set voltage Vset to the set terminal Tset of the latch circuit 18. The latch circuit 18 outputs the ground potential 0V, which is the voltage of the reference potential terminal Tg, as the voltage VG to the output terminal Tq2. As a result, the voltage VG-Vin becomes -Vin, and the PFETM 11a turns on. The other configurations and operations are the same as in Example 1 and will not be described further.

[0070] In Example 1 and its Modification 1, the input voltage Vin is higher than the ground potential. In this case, when an NFETM11 is used as the cold start switch CSW, as in Example 1, the first voltage that turns on the NFETM11 is the input voltage Vin. When a PFETM11a is used as the cold start switch CSW, as in Modification 1 of Example 1, the first voltage that turns on the PFETM11a is the ground potential voltage. This allows both the NFETM11 and PFETM11a to be turned on stably.

[0071] As in Example 1, when an NFETM11 is used as the cold start switch CSW, the second voltage that turns off the NFETM11 is the voltage at ground potential. As in Modification 1 of Example 1, when a PFETM11a is used as the cold start switch CSW, the second voltage that turns off the PFETM11a is the voltage Vin. This eliminates the need for the extra circuitry used to generate -α or +α in Modifications 2 and 3 of Example 1.

[0072] In Example 1, when the voltage Vout becomes higher than the voltage Vin between times t14 and t17 in Figure 7, the voltage VG is at ground potential 0V and is lower than both the voltage Vout and Vin. Therefore, the gate voltage of NFETM11 is lower than the source voltage. Thus, NFETM11 is off. In Modification 1 of Example 1, when the voltage Vout becomes higher than the voltage Vin between times t14 and t17 in Figure 11, the voltage VG is at voltage Vin and is lower than the voltage Vout. Therefore, when the voltage Vin-Vout becomes lower than the threshold voltage of PFETM11a, PFETM11a turns on, and current flows backward from terminal Tout to terminal Tin. Therefore, it is preferable that the cold start switch CSW is NFETM11 as in Example 1.

[0073] [Modification 2 of Example 1] Modification 2 of Example 1 is an example in which a depletion mode (normally on mode) is used as the cold start switch. Figures 12(a) and 12(b) are circuit diagrams of the switch circuit according to Modification 2 of Example 1. As shown in Figure 12(a), in Modification 2 of Example 1, a depletion mode NFETM11b is used as the cold start switch CSW. The threshold voltage of NFETM11b is negative. The source of NFETM11b is connected to the output terminal Tout, and the drain is connected to the input terminal Tin. When the voltage Vout is less than or equal to the reference voltage Vref, the gate of NFETM11b is connected to ground without power supply. As a result, NFETM11b turns on. As shown in Figure 12(b), when the voltage Vout is higher than the reference voltage Vref, a voltage Vout-α (α is positive) is applied to the gate of NFETM11b. If -α is less than or equal to the threshold voltage of NFETM11b, NFETM11b turns off.

[0074] In Modification 2 of Example 1, which uses a depletion-mode NFET as the cold-start switch (CSW), as shown in Figure 12(b), if -α is not sufficiently lower than the threshold voltage, the leakage current of NFETM11b will increase. When a depletion-mode PFET is used as the cold-start switch (CSW), the threshold voltage of the PFET is positive. When the PFET is off, in order to reduce the leakage current of the PFET, a sufficiently high +α above the threshold voltage must be applied to the gate of the PFET. However, generating a sufficiently low -α or a sufficiently high +α requires extra circuitry, which in turn consumes extra power. In Example 1 and its Modification 1, by using an enhancement-type transistor, extra circuitry is not required to generate -α or +α. This suppresses the consumption of extra power.

[0075] Furthermore, the voltage Vin that the latch circuit 18 outputs to the gates of the NFETM 11 and PFETM 11a may be the voltage obtained by dropping the voltage Vin at the output terminal Tout by the amount of the parasitic resistance of the latch circuit 18. Also, the voltage at ground potential 0V that the latch circuit 18 outputs to the gates of the NFETM 11 and PFETM 11a may be the voltage obtained by raising the voltage at ground potential by the amount of the parasitic resistance of the latch circuit 18. [Examples]

[0076] Example 2 and its modifications are examples where the input voltage Vin is low relative to ground, the output of the power generation element 10 is negative relative to ground, and the voltage V2 across capacitor C2 is negative. In Example 2, an enhancement-mode PFETM11a is used as the cold start switch CSW. The circuit configuration is the same as in Figure 9 of Modification 1 of Example 1, and therefore the explanation is omitted.

[0077] Figure 13 shows the time changes of each voltage, current, and the on / off state of the FET in the switch circuit according to Embodiment 2. As shown in Figure 13, the voltages Vin, Vout, V01, V02, reset voltage Vrst, set voltage Vset, and voltage VG are negative. The threshold voltage Vth of PFETM11a is negative. The reference voltages Vref1 and Vref2 are negative. Between times t12 and t14 and between times t17 and t18, voltage VG is less than or equal to the threshold voltage Vth, so PFETM11a turns on. Between times t14 and t17, voltage VG is higher than the threshold voltage Vth, so PFETM11a turns off. The rest is the same as in Figure 7 of Embodiment 1, so the explanation is omitted.

[0078] [Modification 1 of Example 2] In Modification 1 of Example 2, an enhancement-mode NFETM11 is used as the cold-start switch CSW. The circuit configuration is the same as in Figure 4 of Example 1, and its explanation is omitted. Figure 14 shows the time changes of each voltage, current, and the on / off state of the FET in the switch circuit according to Modification 1 of Example 2. As shown in Figure 14, the threshold voltage Vth of the NFETM11 is positive. The reference voltages Vref1 and Vref2 are negative. Between times t12 and t14 and between times t17 and t18, the voltage VG-Vin is greater than or equal to the threshold voltage Vth, so the NFETM11 turns on. Between times t14 and t17, the voltage VG-Vin is approximately 0V and lower than the threshold voltage Vth, so the NFETM11 turns off. The rest is the same as in Figure 13 of Example 2, and its explanation is omitted.

[0079] In Example 2 and its Modification 1, the input voltage Vin is lower than the ground potential. In this case, when a PFETM11a is used as the cold start switch CSW, as in Example 2, the first voltage that turns on the PFETM11a is the ground potential. When an NFETM11 is used as the cold start switch CSW, as in Modification 1 of Example 2, the first voltage that turns on the NFETM11 is the voltage Vin. This allows both the NFETM11 and the PFETM11a to be stably turned on.

[0080] As in Example 2, when a PFETM11a is used as the cold start switch CSW, the second voltage that turns off the PFETM11a is voltage Vin. As in Modification 1 of Example 2, when an NFETM11 is used as the cold start switch CSW, the second voltage that turns off the NFETM11 is ground potential. This eliminates the need for extra circuitry to generate -α or +α.

[0081] In Example 2, when the voltage Vout becomes higher than the voltage Vin between times t14 and t17 in Figure 13, the voltage VG is at ground potential 0V and is higher than both the voltage Vout and Vin. Therefore, the gate voltage of PFETM11a is higher than the source voltage. Thus, PFETM11a is off. In Modification 1 of Example 2, when the voltage Vout becomes lower than the voltage Vin between times t14 and t17 in Figure 14, the voltage VG is at voltage Vin and is higher than the voltage Vout. Therefore, when the voltage Vin-Vout becomes higher than the threshold voltage of NFETM11, NFETM11 turns on, and current flows backward from terminal Tin to terminal Tout. Thus, it is preferable that the cold start switch CSW is PFETM11a as in Example 2. [Examples]

[0082] In Example 1, when NFETM11 is ON, a voltage drop occurs because NFETM11 is diode-connected. Therefore, as in Modification 1 of Example 1, PFETM11a may be used instead of NFETM11. However, in Modification 1 of Example 1, if the voltage Vout becomes higher than the voltage Vin, current flows in reverse from terminal Tout to terminal Tin. This may cause power loss. Example 3 is an example of a switch circuit that suppresses reverse current flow from terminal Tout to terminal Tin even when the voltage Vout becomes higher than the voltage Vin.

[0083] Figure 15 is a circuit diagram of the switch circuit according to Embodiment 3. Compared to Figure 10 of Modification 1 of Embodiment 1, the switch circuit 20 further includes a PFETM2 and a latch circuit 18c. The source of the PFETM2 is connected to the drain of the PFETM11a, and the drain is connected to the output terminal Tout. The power supply terminal Tp of the latch circuit 18c is connected to the drain of the PFETM2. The reference potential terminal Tg of the latch circuit 18c is connected to ground. The output terminal Tq2 of the latch circuit 18c is connected to the gate of the PFETM2. Voltages Vset and Vrst are input from the control circuit 16 to the set terminal Tset and reset terminal Trst of the latch circuit 18c, respectively. The other circuit configurations are the same as in Figure 10 of Modification 1 of Embodiment 1 and are therefore omitted from description.

[0084] Referring to Figure 11, the operation of the switch circuit in Example 3 will be explained. For simplicity, we will assume that the threshold voltages of PFETM11b and M2 are approximately 0V, and that times t11 and t12 are approximately the same time. In Figure 11, at times t11-t14 and t17-t18, the voltage VG applied to the gate of PFETM11b and the voltage VG2 applied to the gate of PFETM2 are 0V, and at times t14-t17, voltages VG and VG2 are Vout. Therefore, PFETM2 turns on and off when PFETM11a is on and off, respectively. Thus, the switch circuit 20 of Modification 1 of Example 1 operates almost the same as in Figure 11.

[0085] Thus, in Embodiment 3, the connection state between PFETM11a (first switching element) and capacitor C2 is controlled by PFETM2 (second switching element) according to the voltage applied to its gate (second control terminal). Circuit 17 outputs 0V (first voltage) to the gate of PFETM2, keeping PFETM2 ON until the voltage difference Vout-0V across capacitor C2 reaches the reference voltage Vref2. When the voltage difference Vout-0V exceeds the reference voltage Vref2, Circuit 17 outputs Vout (second voltage) to the gate of PFETM2, keeping PFETM2 OFF until the voltage difference Vout-0V falls below the reference voltage Vref1. As a result, even if the voltage Vout becomes higher than the voltage Vin when PFETM11a and PFETM2 are OFF, the gate voltage VG2 of PFETM2 remains Vout, and the OFF state of PFETM2 is maintained. Therefore, reverse current flow from terminal Tout to terminal Tin can be suppressed. Therefore, it is possible to prevent power loss and suppress a decrease in power efficiency.

[0086] In Example 3, an example was described in which enhancement-type PFETs are used as PFETM11a and PFETM2 when the input voltage Vin is higher than the ground potential. However, when the input voltage Vin is lower than the ground potential, enhancement-type NFETs may be used instead of PFETM11a and PFETM2. [Examples]

[0087] Example 4 is an example where the output voltage (i.e., input voltage Vin) of the power generation element 10 is high. For example, when a power generation element is used that has a small capacitive component, such as an organic piezoelectric element or a MEMS (Micro Electro Mechanical Systems) element using an electret, the output voltage of the power generation element 10 becomes high, for example, 35V. In such a case, a high-voltage FET is used as the NFETM11 in Example 1. A high-voltage FET is an FET with a high drain breakdown voltage (the breakdown voltage of the drain relative to the source), and as the NFETM11, for example, an FET with a drain breakdown voltage of 35V or higher is used. However, in Example 1, a high voltage is applied to the power supply terminal Tp of the latch circuit 18. The breakdown voltage of a typical MOSFET is about 5V, and if a voltage of 5V or more is applied to the power supply terminal Tp, the latch circuit 18 will be destroyed. Example 4 is an example in which the destruction of the latch circuit 18 can be suppressed even when the voltage Vin is high.

[0088] Figure 16 is a circuit diagram of the switch circuit according to Embodiment 4. As shown in Figure 16, the gate of NFETM11 is connected to node NG. Capacitor C3 is connected between node NG and input terminal Tin. NFETM11 and capacitor C3 are high-voltage elements, with a voltage rating of, for example, 35V or higher. The source and drain of NFETM3 are connected to ground and node NG, respectively. NFETM3 is an enhancement-type FET. The power supply terminal Tp of latch circuit 18b is connected to the output terminal Tout. The reference potential terminal Tg is connected to ground. The output terminal Tq2 is connected to the gate of NFETM3. Voltages Vset and Vrst are input from control circuit 16 to the set terminal Tset and reset terminal Trst of latch circuit 18b, respectively.

[0089] In Figure 7, at times t11-t14 and t17-t18, the voltage VG3 applied to the gate of NFETM3 is 0V, and at times t14-t17, the voltage VG3 is Vout. If the capacitance of capacitor C3 is made sufficiently large compared to the gate capacitance of NFETM11 and the drain capacitance of NFETM3, then from time t11 onwards, as Vin increases, the voltage VG at the gate of NFETM11 capacitively coupled to the input terminal Tin increases at approximately the same voltage as Vout. At time t14, when the voltage VG3 becomes Vout and NFETM3 turns on, the voltage VG becomes 0V and NFETM11 turns off. At time t17, when the voltage VG3 becomes 0V and NFETM3 turns off, the voltage VG becomes approximately Vin and NFETM11 turns on. The operation of the other switch circuits 20 is the same as in Figure 7 of Embodiment 1 and will not be described.

[0090] According to Embodiment 4, the NFETM3 (third switching element) controls the connection state between node NG and the reference potential according to the voltage VG3 applied to the gate (third control terminal). The latch circuit 18b continues to output the reference potential to the gate of the NFETM3 until the voltage difference Vout-0V across the capacitor C2 reaches the reference voltage Vref1. Once the voltage difference Vout-0V exceeds the reference voltage Vref1, it outputs Vout to the gate of the NFETM3 until the voltage difference Vout-0V falls below the reference voltage Vref2. In this way, since the power supply terminal Tp of the latch circuit 18b is connected to the output terminal Tout, it is possible to suppress the failure of the latch circuit 18b even if the voltage Vin becomes high.

[0091] [Modification 1 of Example 4] In Example 4, when the NFETM11 is off, if the input voltage Vin becomes high, leakage current may flow through the NFETM11, causing current to flow from the input terminal Tin to the output terminal Tout. In particular, if the NFETM11 is a high-voltage FET, the off-resistance may be low and the leakage current may be large. Modification 1 of Example 4 is an example of suppressing the leakage current of the NFETM11.

[0092] Figure 17 is a circuit diagram of a switch circuit according to Modification 1 of Example 4. As shown in Figure 17, the switch circuit 20 further includes an NFETM4 and a Zener diode Zd compared to Figure 16 of Example 4. The source of NFETM4 is connected to the output terminal Tout, the drain is connected to the source of NFETM11, and the gate is connected to node NG. NFETM4 is an enhancement type FET, and the threshold voltage of NFETM4 is approximately the same as the threshold voltage of NFETM11. By not using a high-voltage FET for NFETM4 and using an FET with a lower drain breakdown voltage than NFETM4, the off-resistance of NFETM4 can be made higher than that of NFETM11. The anode of Zener diode Zd is connected to ground, and the cathode is connected to node N4 between NFETM11 and M4. The breakdown voltage of Zener diode Zd is, for example, 5.5V. The other circuit configurations are the same as in Figure 16 of Example 4 and are omitted from the explanation.

[0093] In Figure 7, PFETM2 turns on and off when NFETM11 is on and off, respectively. Since NFETM11 and M4 are connected in series between the input terminal Tin and the output terminal Tout, when NFETM11 and M4 are off, leakage current flowing from the input terminal Tin to the output terminal Tout can be suppressed. However, if the off-resistance of NFETM4 is high, the voltage at node N4 will be high. If the voltage at node N4 relative to the output voltage Vout exceeds the drain breakdown voltage of NFETM4, NFETM4 may be destroyed. Therefore, the breakdown voltage of the Zener diode Zd is set to be less than or equal to (the maximum value of the drain breakdown voltage of NFETM4 minus Vout). This prevents the voltage at node N4 - Vout from exceeding the drain breakdown voltage of NFETM4, thereby suppressing the destruction of NFETM4.

[0094] According to Modification 1 of Example 4, the NFETM4 (fourth switching element) has a lower drain breakdown voltage than the NFETM11 and controls the connection state between the NFETM11 and the output terminal Tout according to the voltage applied to node NG. The Zener diode Zd (limiting element) limits the voltage at node N4 so that it does not exceed the breakdown voltage (third predetermined value). In this way, by providing the NFETM4, leakage current flowing from the input terminal Tin to the output terminal Tout can be suppressed. By providing the Zener diode Zd, it is possible to prevent the NFETM4 from being destroyed by a high voltage being applied to it.

[0095] Furthermore, by placing the Zener diode Zd on the input terminal Tin side of the NFETM11, it is possible to suppress the increase in the input voltage Vin applied to the NFETM11. However, when the cold start switch CSW is off, the output power of the power generation unit 10a may be rectified in a rectifier circuit other than the rectifier circuit 10b in Figure 1 (for example, the rectifier circuit 62 in Figure 18, which will be described later). In this case, if the voltage Vin at the input terminal Tin is limited, a high voltage will not be applied to the other rectifier circuit. Therefore, as in the modified example 1 of Embodiment 4, it is preferable to provide the Zener diode Zd at node N4.

[0096] In Example 4 and its Modification 1, an example was described in which enhancement-type NFETs are used as NFETM11 and M4 when the input voltage Vin is higher than the ground potential. However, when the input voltage Vin is lower than the ground potential, enhancement-type PFETs can be used instead of NFETM11 and M4.

[0097] In Examples 1 to 4 and their modifications, when the transistor is of the enhancement type, NFETM11, M11b, M3, and M4 are off when the gate voltage is at ground potential 0V and turn on when the gate voltage becomes higher than a positive threshold voltage. PFETM11a, M11c, and M2 are off when the gate voltage (gate voltage relative to source) is at ground potential 0V and turn on when the gate voltage becomes lower than a negative threshold voltage. NFETM11, M11b, M3, M4 and PFETM11a, M11c, and M2 are, for example, MOS (Metal Oxide Semiconductor) FETs using silicon.

[0098] The switch circuits of Examples 1 to 4 and their variations are used as the cold start switch CSW of the voltage conversion circuit 12 in Figure 1. When the reset voltage Vrst is output, the voltage conversion circuit 12 (power conversion circuit) starts converting the output power of the power generation element 10. That is, when circuit 17 outputs the reset voltage Vrst, it starts the voltage conversion circuit 12. In Figure 1, an example of a step-down / step-up type voltage conversion circuit is shown as the power supply circuit, but the power supply circuit may also be a step-down type voltage conversion circuit, a step-up type voltage conversion circuit, or an inverting type voltage conversion circuit. The power conversion circuit may also be a voltage conversion circuit (e.g., DC (Direct Current)-DC converter) equipped with an inductor that converts a third voltage (e.g., DC voltage) input from the power generation element 10 to a fourth voltage (e.g., DC voltage). The power supply circuit may also be a power conversion circuit that converts AC to DC, etc.

[0099] Figure 18 is a block diagram showing a system in which the switch circuits of Examples 1 to 4 and their modified versions are used. As shown in Figure 18, the system comprises a power generation element 60, rectifier circuits 61 and 62, matching circuit 63, voltage conversion circuit 64, charge management circuit 65, capacitor 66, cold start circuit 67, and boost circuit 68.

[0100] The power generation element 60 is, for example, the power generation element 10 in Figure 1, and generates alternating current power of a small current. The rectifier circuit 61 is, for example, a diode bridge, and the rectifier circuit 62 is, for example, a synchronous rectifier circuit. The matching circuit 63 matches the output impedance of the rectifier circuits 61 and 62 with the input impedance of the voltage conversion circuit 64. The voltage conversion circuit 64 is, for example, the voltage conversion circuit 12 in Figure 1, and is a DC-DC converter. The charge management circuit 65 stores power in an appropriate capacitor 66 from among a plurality of capacitors 66. The capacitor 66 is, for example, a capacitor. The charge management circuit 65 monitors the voltage across the plurality of capacitors and appropriately charges the capacitors with generated power. The cold start circuit 67 is the switch circuit 20 shown in any of the embodiments 1 to 4 and their variations, and charges the capacitor 66 with the output current of the rectifier circuit 61 when the capacitor 66 is almost uncharged. The boost circuit 68 is, for example, a charge pump, which generates the voltage used by the rectifier circuit 62 and the voltage conversion circuit 64, etc.

[0101] The operation of the system will now be described. When the power generation element 60 generates a small amount of power while the capacitor 66 is almost empty, the rectifier circuit 61 rectifies the small amount of power. The rectifier circuit 61 is preferably a circuit that can perform rectification without an external power supply, such as a diode bridge. In addition to a diode bridge, a rectifier circuit may be configured by combining an FET with its gate and source or drain short-circuited. Such a rectifier circuit configured by combining FETs is suitable for generating small amounts of power because it can reduce the voltage drop compared to a diode bridge. The current rectified by the rectifier circuit 61 goes through the cold start circuit 67 to the charge management circuit 65 and is stored in the capacitor 66. When the capacitor 66 is charged to a sufficient voltage, the boost circuit 68 boosts the voltage from the capacitor 66 to the voltage used by the rectifier circuit 62 and the voltage conversion circuit 64. The voltage of the capacitor 66 is, for example, 1V, and the output voltage of the boost circuit 68 is, for example, 2V. If the rectifier circuit 62 and voltage conversion circuit 64 operate using the voltage from the capacitor 66, the boost circuit 68 may not be necessary.

[0102] The matching circuit 63 changes the input voltages of the rectifier circuits 61 and 62 according to the amount of power generated by the power generation element 60. The input impedance of the rectifier circuits 61 and 62 is obtained by dividing the input voltage by the output current of the power generation element 60. Therefore, the matching circuit 63 increases the input voltage when the output current of the power generation element 60 is large, and decreases the input voltage when the output current of the power generation element 60 is small. This matches the output impedance of the power generation element 60 with the input impedance of the rectifier circuits 61 and 62. The matching circuit 63 switches between the rectifier circuits 61 and 62 depending on the input voltage. For example, if the rectifier circuits 61 and 62 are a diode bridge and a synchronous rectifier circuit, respectively, the loss due to the diode's on-voltage becomes large when the input voltage is 1V or less. For this reason, the rectifier circuit 62 is used. When the input voltage is 1V or higher, the rectifier circuit 61 is used.

[0103] The voltage conversion circuit 64 converts the input voltage set by the matching circuit 63 into a voltage that the capacitor 66 charges. The voltage of the capacitor 66 is, for example, 1V or 3.3V. The charge management circuit 65 monitors the voltages of multiple capacitors 66 and charges the appropriate capacitor 66 with the generated power.

[0104] In a system using a power generation element 60 that generates such minute amounts of power, the cold start circuit 67 turns on without power when no power is stored in the capacitor 66, and turns off after power is stored in the capacitor 66. By using the switch circuits 20 of Examples 1 to 4 and their modified versions in the cold start circuit 67, the cold start switch can be controlled stably.

[0105] In the embodiment described above, a cold start switch CSW (CSW) as shown in Figure 1 was used as a switching element that controls the connection state between the power generation element and the capacitor according to the voltage applied to the control terminal of the present invention. An FET (Field-Emitting Diode) was used as such a switching element. An FET is preferred because it consumes little power, but the switching element of the present invention is not limited to an FET; other switching elements, such as a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor), may also be used. In a bipolar transistor, the first and second terminals are the emitter and collector, and the control terminal is the base. In an IGBT, the first and second terminals are the emitter and collector, and the control terminal is the gate.

[0106] Furthermore, as the voltage difference across the ends of the capacitor increases over time from its initial state, a first voltage is output to the control terminal to keep the transistor ON until the voltage difference reaches a first predetermined value greater than the initial state. When the voltage difference exceeds the first predetermined value, a second voltage is output to the control terminal to keep the switching element OFF until the voltage difference falls below a second predetermined value smaller than the first predetermined value. For example, circuit 17 includes a latch circuit 18 as shown in Figure 4. In the circuit shown in Figure 4, the normal initial state of the voltage difference across the ends of the capacitor is zero volts, but the present invention is not limited to such zero volts. For example, when a small amount of charge remains in the capacitor, the voltage will be in proportion to the amount of charge and the capacity of the capacitor. The present invention is not limited to this configuration and may be configured with a circuit having hysteresis characteristics that does not include a latch circuit. For example, the present invention is also included in a configuration that combines an element whose output voltage has hysteresis characteristics with respect to the input voltage and a control circuit that controls the on / off state of a switch CSW according to the output voltage of that element.

[0107] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention as described in the claims. [Explanation of symbols]

[0108] 10 Power generation element 12 Voltage conversion circuit 14 Control Unit 16 Control circuits 17 circuits 18. Latch Circuit 20 Switch Circuits

Claims

1. A first switching element controls the connection state between the power generation element and the capacitor according to the voltage applied to the first control terminal, The system includes a control circuit that includes a latch circuit and controls the voltage of the first control terminal so that the first switching element is turned on or off, The latch circuit is As the voltage difference across the capacitor increases over time from its initial state, a first voltage is output to the first control terminal to keep the first switching element turned on until the voltage difference reaches a first predetermined value greater than the initial state. When the voltage difference exceeds the first predetermined value, a second voltage is output to the first control terminal to keep the first switching element off until the voltage difference falls below a second predetermined value which is smaller than the first predetermined value. Switch circuit.

2. The switch circuit according to claim 1, wherein the power generation element comprises a power generation unit that outputs an alternating current and a rectifier circuit that rectifies the alternating current.

3. The aforementioned capacitor has one end connected to a reference potential, and the other end is connected to the power generation element by the first switching element, the connection state of which is controlled. The switch circuit according to claim 2, wherein the first switching element is an enhancement-type FET, and the control circuit outputs the voltage at the terminal on the power generation element side of the first switching element as the first voltage, and outputs the reference potential as the second voltage.

4. The rectifier circuit generates a positive voltage relative to the reference potential. The switch circuit according to claim 3, wherein the first switching element is an enhancement-type NFET.

5. The rectifier circuit generates a negative voltage relative to the reference potential. The switch circuit according to claim 3, wherein the first switching element is an enhancement-type PFET.

6. The aforementioned capacitor has one end connected to a reference potential, and the other end is connected to the power generation element by the first switching element, the connection state of which is controlled. The switch circuit according to claim 2, wherein the first switching element is an enhancement-type FET, and the control circuit outputs the reference potential as the first voltage and the voltage at the terminal on the power generation element side of the first switching element as the second voltage.

7. The rectifier circuit generates a positive voltage relative to the reference potential. The switch circuit according to claim 6, wherein the first switching element is an enhancement type PFET.

8. The rectifier circuit generates a negative voltage relative to the reference potential. The switch circuit according to claim 6, wherein the first switching element is an enhancement-type NFET.

9. It is an enhancement-type FET, and includes a second switching element whose connection state between the first switching element and the capacitor is controlled according to the voltage applied to the second control terminal. The control circuit outputs the reference potential to the second control terminal when the voltage difference increases over time from the initial state until the voltage difference reaches a first predetermined value, and when the voltage difference exceeds the first predetermined value, outputs the voltage of the capacitor-side terminal of the second switching element to the second control terminal until the voltage difference falls below the second predetermined value.

10. The system includes a third switching element that controls the connection state between the first control terminal and the reference potential in accordance with the voltage applied to the third control terminal. The aforementioned capacitor has one end connected to the reference potential, and the other end is connected to the power generation element by the first switching element, the connection state of which is controlled. The first control terminal is capacitively coupled to the power generation element. The first switching element is an enhancement-type FET, The switch circuit according to claim 6, wherein the control circuit continues to output the reference potential to the third control terminal until the voltage difference reaches a first predetermined value, and when the voltage difference exceeds the first predetermined value, it outputs the voltage from the other end of the capacitor to the third control terminal until the voltage difference falls below a second predetermined value.

11. A fourth switching element having a lower voltage rating than the first switching element, which controls the connection state between the first switching element and the capacitor according to the voltage applied to the first control terminal, A limiting element that limits the voltage between the first switching element and the fourth switching element so as not to exceed a third predetermined value, The switch circuit according to claim 10, comprising:

12. When the voltage difference falls below the second predetermined value, the control circuit resets the latch state of the latch circuit and outputs the first voltage to the control terminal of the first switching element to turn on the first switching element. The switch circuit according to claim 1.

13. The switch circuit according to any one of claims 1 to 12, wherein in the initial state, the voltage difference between the two ends of the capacitor is 0V.

14. A switch circuit according to any one of claims 1 to 13, A power conversion circuit that converts the output power of the aforementioned power generation element, Equipped with, The switch circuit is a power supply circuit that outputs a signal to the power conversion circuit to activate the power conversion circuit when the voltage difference exceeds the first predetermined value.

15. A switch circuit having a first switching element that controls the connection state between a power generation element and a capacitor according to the voltage applied to a first control terminal, and a control circuit that controls the voltage of the first control terminal so that the first switching element is turned on or off, A power conversion circuit that converts the output power of the aforementioned power generation element, Equipped with, The aforementioned control circuit is As the voltage difference across the capacitor increases over time from its initial state, a first voltage is output to the first control terminal to keep the first switching element turned on until the voltage difference reaches a first predetermined value greater than the initial state. When the voltage difference exceeds the first predetermined value, a signal is output to the power conversion circuit to activate it, and a second voltage is output to the first control terminal to keep the first switching element off until the voltage difference falls below a second predetermined value which is smaller than the first predetermined value. power circuit.

16. The power supply circuit according to claim 14 or 15, wherein the control circuit keeps the first switching element off when the voltage difference exceeds the first predetermined value until the voltage difference falls below the second predetermined value.

17. The power supply circuit according to any one of claims 14 to 16, wherein the control circuit turns off the first switching element and outputs a signal to the power conversion circuit to activate the power conversion circuit when the voltage difference exceeds the first predetermined value.

18. The power supply circuit according to any one of claims 14 to 17, wherein the power conversion circuit is a voltage conversion circuit comprising an inductor that converts a third voltage input from the power generation element into a fourth voltage.

19. The power supply circuit according to any one of claims 14 to 18, further comprising: a determination circuit that determines whether the voltage difference exceeds a first predetermined value; and a generation circuit that generates the activation signal when the determination circuit determines that the voltage difference exceeds a first predetermined value.

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