Data compression API

Abstract

Apparatus, system, and technique for directing storage to be compressed In at least one embodiment, an application programming interface is implemented for directing storage for storing information to be compressed.

Description

【Technical Field】 【0001】 This application claims the benefit of U.S. Provisional Application No. 63 / 188,282, filed May 13, 2021, entitled "BANDWIDTH COMPRESSION," the entire content of which is incorporated herein by reference (Attorney Docket No. 0112912-289PR0). 【0002】 At least one embodiment relates to an application programming interface for performing computing tasks. For example, at least one embodiment relates to an application programming interface for specifying that a memory is compressible. 【Background Art】 【0003】 Parallel computing devices may experience performance degradation due to bandwidth limitations. The performance of such devices can be improved. 【Brief Description of the Drawings】 【0004】 [Figure 1] FIG. shows an example of a device that uses compression for a memory for caching transmissions according to at least one embodiment. [Figure 2] FIG. shows an example of an architecture for parallel computing according to at least one embodiment. [Figure 3] FIG. shows an example of an API for enabling compression for a memory for caching transmissions according to at least one embodiment. [Figure 4] FIG. shows an example of a process for enabling and using data compression on a GPU according to at least one embodiment. [Figure 5] FIG. shows an example of a process for enabling data compression on a GPU according to at least one embodiment. [Figure 6]This figure shows an exemplary data center according to at least one embodiment. [Figure 7] This figure shows a processing system according to at least one embodiment. [Figure 8] This figure shows a computer system according to at least one embodiment. [Figure 9] This figure shows the system according to at least one embodiment. [Figure 10] This figure shows an exemplary integrated circuit according to at least one embodiment. [Figure 11] This figure shows a computing system according to at least one embodiment. [Figure 12] This figure shows an APU according to at least one embodiment. [Figure 13] This figure shows a CPU according to at least one embodiment. [Figure 14] This figure shows an exemplary accelerator integration slice, based on at least one embodiment. [Figure 15A] This figure shows an exemplary graphics processor according to at least one embodiment. [Figure 15B] This figure shows an exemplary graphics processor according to at least one embodiment. [Figure 16A] This figure shows a graphics core according to at least one embodiment. [Figure 16B] This figure shows a GPGPU according to at least one embodiment. [Figure 17A] This figure shows a parallel processor according to at least one embodiment. [Figure 17B] This figure shows a processing cluster according to at least one embodiment. [Figure 17C] This figure shows a graphics multiprocessor according to at least one embodiment. [Figure 18]A diagram showing a graphics processor according to at least one embodiment. [Figure 19] A diagram showing a processor according to at least one embodiment. [Figure 20] A diagram showing a processor according to at least one embodiment. [Figure 21] A diagram showing a graphics processor core according to at least one embodiment. [Figure 22] A diagram showing a PPU according to at least one embodiment. [Figure 23] A diagram showing a GPC according to at least one embodiment. [Figure 24] A diagram showing a streaming multiprocessor according to at least one embodiment. [Figure 25] A diagram showing a software stack of a programming platform according to at least one embodiment. [Figure 26] A diagram showing a CUDA implementation form of the software stack of FIG. 25 according to at least one embodiment. [Figure 27] A diagram showing a ROCm implementation form of the software stack of FIG. 25 according to at least one embodiment. [Figure 28] A diagram showing an OpenCL implementation form of the software stack of FIG. 25 according to at least one embodiment. [Figure 29] A diagram showing software supported by a programming platform according to at least one embodiment. [Figure 30] A diagram showing compiling code for execution on the programming platforms of FIGS. 25-28 according to at least one embodiment. [Figure 31] A diagram showing in more detail compiling code for execution on the programming platforms of FIGS. 25-28 according to at least one embodiment. [Figure 32]A diagram showing translating source code before compiling the source code, according to at least one embodiment. [Figure 33A] A diagram showing a system configured to compile and execute CUDA source code using different types of processing units, according to at least one embodiment. [Figure 33B] A diagram showing a system configured to compile and execute the CUDA source code of FIG. 33A using a CPU and a CUDA-compatible GPU, according to at least one embodiment. [Figure 33C] A diagram showing a system configured to compile and execute the CUDA source code of FIG. 33A using a CPU and a non-CUDA-enabled GPU, according to at least one embodiment. [Figure 34] A diagram showing an exemplary kernel translated by a CUDA-to-HIP translation tool of FIG. 33C, according to at least one embodiment. [Figure 35] A diagram showing a non-CUDA-enabled GPU of FIG. 33C in more detail, according to at least one embodiment. [Figure 36] A diagram showing how threads of an exemplary CUDA grid are mapped to different compute units of FIG. 35, according to at least one embodiment. [Figure 37] A diagram showing how to migrate existing CUDA code to Data Parallel C++ code, according to at least one embodiment. **DETAILED DESCRIPTION OF THE INVENTION** 【0005】 In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one of ordinary skill in the art that the inventive concept may be practiced without one or more of these specific details. 【0006】 Figure 1 shows an example of a processing device that uses compression on memory for caching transmissions, according to at least one embodiment. In at least one embodiment, the processing unit is a device comprising one or more circuits for implementing an application programming interface ("API"). In at least one embodiment, the API may be implemented to instruct storage which is to contain information to be compressed. In at least one embodiment, the storage is referred to as compressible to reflect this instruction. 【0007】 In at least one embodiment, the storage includes, but is not limited to, any of a variety of non-temporary media and devices that potentially include dynamic random access memory ("DRAM"), static random access memory ("SRAM"), cache memory such as L2 cache, registers, flash memory, high-bandwidth memory such as HBM, HBM2, or HBM2e. 【0008】 In at least one embodiment, the storage area is indicated by the API as being compressible, and a processing device hosting the storage, such as processing device 100, is indicated as being able to compress the information stored in its memory to improve device performance. For example, in at least one embodiment, information stored in compressible memory is compressed for transmission from a page buffer maintained in the storage to an L2 cache 104. In at least one embodiment, the compressed information stored in the cache is decompressed by a compression circuit element 110 and forwarded to a client circuit element on the device, such as a streaming multiprocessor 102. In at least one embodiment, the client circuit element, sometimes referred to as a client component, comprises circuit elements for performing functions related to the processing device 100, such as a streaming multiprocessor 102, a copy engine, and components for performing BAR1 mapping. It should be understood that these examples are illustrative and not limiting. In at least one embodiment, transmissions between components utilize bandwidth, such as the bandwidth provided by a communication bus. 【0009】 In at least one embodiment, the compression circuit element 110 comprises circuit elements for compressing and / or decompressing information. In at least one embodiment, the compression circuit element 110 comprises a post-L2 compression circuit element used by a processing device 100 to decompress compressed information stored in an L2 cache. 【0010】 In at least one embodiment, the processing device 100 is a graphics processing unit, a parallel processing unit, or another processing unit. In at least one embodiment, the processing device 100 comprises one or more streaming multiprocessors 102, memory 106, an L2 cache 104, and a memory controller 108. In at least one embodiment, the processing device 100 includes compression circuit elements for compressing data to be written to the L2 cache 104 and for decompressing data to be read from the L2 cache 104. 【0011】 In at least one embodiment, one or more streaming multiprocessors 102 access data stored in storage 106. In at least one embodiment, storage 106 comprises one or more dynamic random access memories ("DRAM"). In at least one embodiment, storage 106 comprises high-bandwidth memory such as HBM, HBM2, or HBM2e. In at least one embodiment, storage 106 comprises double data rate ("DDR") memory such as DDR5. In at least one embodiment, storage 106 comprises one or more static random access memories ("SRAM"), cache memory, registers, or flash memory. It should be understood that these examples of storage are illustrative and not limiting. 【0012】 In at least one embodiment, the L2 cache 104 comprises memory associated with the symmetric multiprocessor 102. In at least one embodiment, the L2 cache 104 is used to reduce the time or energy spent accessing data stored in the storage 106. In at least one embodiment, the L2 cache 104 is included in a processor chip or module that also includes the symmetric multiprocessor 102. 【0013】 In at least one embodiment, the performance of storage 106 is improved by utilizing L2 cache 104. In at least one embodiment, to further improve performance, data stored in L2 cache 104 is transparently compressed. In at least one embodiment, this reduces bandwidth consumption between L2 cache 104 and storage 106, and / or between L2 cache 104 and streaming multiprocessor 102. In at least one embodiment, compression increases the apparent capacity of L2 cache 104. 【0014】 In at least one embodiment, the memory and cache controller 108 facilitates data flow between the symmetric multiprocessor 102 and the storage 106. In at least one embodiment, the memory and cache controller 108 manages the operation of the L2 cache 104, including the transfer of data from the storage 106 to the L2 cache 104. In at least one embodiment, the memory and cache controller 108 facilitates providing the symmetric multiprocessor 102 with access to data stored in the L2 cache 104 and / or the storage 106. In at least one embodiment, the memory and cache controller 108 implements cache residency and eviction policies to control when data from the storage 106 should be stored in the L2 cache 104 and when such data should be evictioned from the L2 cache 104. 【0015】 In at least one embodiment, the memory and cache controller 108 identifies areas of storage 106 that should be loaded into the L2 cache 104 using compression. In at least one embodiment, the memory and cache controller 108 identifies areas of storage 106 that should be sent to another memory or client component using compression. 【0016】 In at least one embodiment, a processing unit, such as a GPU or PPU or other processor, uses data compression to improve bandwidth utilization and eliminate bottlenecks between memory and cache. In at least one embodiment, this is enabled by circuit elements for performing compression and decompression, which are accessible to the kernel model driver. 【0017】 In at least one embodiment, the API facilitates interaction with the processing unit. In at least one embodiment, this API provides functionality for allocating blocks of memory or modifying properties associated with blocks of memory. In at least one embodiment, this functionality is described using names such as create_memory, allocate_memory, memcreate, and memalloc. It should be understood that these examples are illustrative and not limiting. 【0018】 In at least one embodiment, the function for allocating memory includes parameters that allow properties of the allocated memory to be specified. In at least one embodiment, these properties include information indicating whether this memory should be related to compression. For example, in at least one embodiment, the parameters may include flags to control whether or how data should be compressed. In at least one embodiment, the processing unit accesses stored metadata to reflect these parameters. 【0019】 In at least one embodiment, the memory region associated with compression is referred to as compressible memory. In at least one embodiment, the compressible memory is transparently compressed and decompressed for transmission to or from the cache. In at least one embodiment, a write operation targeting the compressible memory is transparently compressed and written to the L2 cache memory. In at least one embodiment, when the data is read again, the memory in L2 is decompressed. In at least one embodiment, this process is transparent to processes writing to or reading from the compressed memory. For example, in at least one embodiment, a client process writes to and reads from a compressible memory region, and the data associated with the write is transparently compressed, stored in the cache, and decompressed without direct involvement from the client process. In at least one embodiment, enabling compressible memory reduces the bandwidth requirements between L2 and DRAM. In at least one embodiment, enabling compressible memory makes L2 capacity appear larger to streaming multiprocessors utilizing L2, thereby improving processor efficiency. 【0020】 In at least one embodiment, compression requires the use of hardware capacity, such as processor utilization or power availability. In at least one embodiment, since compression may not necessarily be beneficial for all types of data, a compression flag is provided by the API to allow the client to indicate that compression should be used for a particular region of memory. In at least one embodiment, this allows some types of data, such as graphics or machine learning data with repetitive content, to be stored in compressible memory, while other types of data are stored in non-compressible memory. 【0021】 In at least one embodiment, a post-L2 compressor enables L2 cache clients to make virtually addressed memory requests with transparent compression. For example, in at least one embodiment, an L2 cache client, such as a streaming multiprocessor on a GPU, leverages transparent compression and decompression of data. In at least one embodiment, this enables streaming multiprocessor instructions, copy engine copying, and "BAR1" remapping to operate on compressible memory. In at least one embodiment, the post-L2 compressor enables L2 to store compressed data and return decompressed data to cache clients, such as streaming multiprocessors, through XBAR, so that applications leveraging parallel computing architectures, such as CUDA applications, can benefit from compressible memory. 【0022】 In at least one embodiment, the post-L2 compressor unit enables L2 cache clients making virtually addressed requests to transparently compress and decompress data. In at least one embodiment, the data includes a significant amount of zeros, such as machine learning data. For example, in machine learning, activation data may include a significant amount of zeros, but the non-zero writes associated with activation originate from different streaming multiprocessors. In at least one embodiment, in the case of deep learning inference, this compressible memory may be used when reading weight data about a pruned network to reduce bandwidth requirements between L2 and DRAM and increase apparent L2 capacity. In at least one embodiment, the post-L2 compressor comprises a variable-width differential compressor and a sparse data compressor. 【0023】 In at least one embodiment, compressible memory is used in deep learning applications that include both training and inference. In at least one embodiment, during training, the activation of the convolutional network is often sparse due to the ReLU activation layer, which can result in DRAM bandwidth savings when compression is used. In at least one embodiment, during inference, decompression on read provides similar savings for both activation and prune weights. 【0024】 In at least one embodiment, compressible memory is used in a gaming application. In at least one embodiment, variable-width differential compression is used to compress data in compressible memory. In at least one embodiment, this technique is used for ray tracing, sampling and filtering, super-resolution, frame interpolation, frame extrapolation, discocclusion, infill, etc. It should be understood that these examples are illustrative and not limiting. 【0025】 In at least one embodiment, GPU-pinned memory is designated as compressible and then transparently compressible, as described herein. In at least one embodiment, the pinned memory comprises virtual memory pages marked to prevent it from being swapped out. 【0026】 In at least one embodiment, the paging memory is designated as compressible and can be transparently compressed, as described herein. In at least one embodiment, the paging memory comprises virtual memory pages that can be swapped to temporary storage to make room for other pages. 【0027】 In at least one embodiment, a kernel-mode driver allocates memory as compressible. In at least one embodiment, this is done by setting a page table in a specific field. In at least one embodiment, a page is marked as compressible by setting a field in the page table entry to indicate that the memory associated with the page table entry is compressible. 【0028】 In at least one embodiment, compression by the processing unit is not directly exposed to the user and is therefore transparent to the user. In at least one embodiment, the memory allocation semantics for the parallel computing architecture, such as a consistent view of memory, operate according to user expectations regardless of the compression settings. In at least one embodiment, a library can transparently pass compressed and uncompressed allocations to other libraries or other user code. In at least one embodiment, an API is included that provides a mechanism for querying compression support. In at least one embodiment, inter-process communication operates with compressible memory. 【0029】 In at least one embodiment, a cache miss may impair the performance of uncompressed access that does not involve an L2 cache slice or cache bank. For example, in at least one embodiment, a compressed bit cache miss is resolved immediately, while an L2 miss may typically be served along with other pending requests. In at least one embodiment, these misses may affect compute preemption recovery time, but this can be mitigated. 【0030】 In at least one embodiment, the API for exposing compression capabilities includes a data structure in which properties describe the characteristics of the storage to be allocated. In at least one embodiment, parameters to the API function include allocation flags which may be set to include a compression type flag. In at least one embodiment, requests for compressible memory are treated as hints. In at least one embodiment, the kernel-mode driver may or may not have been able to allocate compressible memory in all cases, and therefore may sometimes decide to fall back to allocating non-compressible memory. 【0031】 In at least one embodiment, the API is provided to obtain a minimum or preferred allocation granularity before requesting that compressible memory be allocated. In at least one embodiment, this is done because the allocation granularity for compressible allocations may differ from that for non-compressible allocations. In at least one embodiment, multiple allocation granularities are supported, and if the driver is unable to allocate compressible memory, the driver can ensure that the allocation is assisted by an optimal page size instead of accepting a page size that would have been preferable for compressed memory. 【0032】 In at least one embodiment, discontinuous and compressible allocations may have physical pages uniformly distributed across L2 cache slices or banks to improve compression speed and minimize thrashing. In at least one embodiment, physical pages are selected for allocation to be uniformly distributed across L2 cache slices to improve utilization and minimize thrashing. 【0033】 Figure 2 shows one example of architecture 200 for parallel computing, according to at least one embodiment. In at least one embodiment, application 202 utilizes a parallel computing architecture, such as Compute Unified Device Architecture ("CUDA"), to perform calculations on processing device 210. In at least one embodiment, processing unit 210 corresponds to an embodiment of processing device 100 shown in Figure 1. 【0034】 In at least one embodiment, application 202 is any of various computer programs, code, or other software. In at least one embodiment, application 202 utilizes processing device 210 to perform artificial intelligence, such as deep learning training or inference. In at least one embodiment, application 202 utilizes processing device 210 to generate graphics output. It should be understood that these examples are illustrative and not limiting. 【0035】 In at least one embodiment, the exemplary architecture 200 comprises a library 204, a runtime 206, a driver 208, and a processing device 210. In at least one embodiment, the library comprises code or other executable or interpretable programming that enables a device, such as the processing device 100, to perform computing functions. In at least one embodiment, the runtime 206 and the driver 208 also comprise code or other executable or interpretable programming that enables a device, such as the processing device 100, to perform computing functions. In at least one embodiment, the driver 208 comprises code or other instructions for interface between the host device and the processing device 210. In at least one embodiment, the library 204, the runtime 206, and / or the driver 208 are combined into one or more other combinations or subdivided therein. For example, in at least one embodiment, the combined driver 208 is used to interface with the processing device 210. 【0036】 In at least one embodiment, one or more of the library 204, runtime 206, or driver 208 include an application programming interface ("API") method for controlling the compression of the memory of the processing device 210. In at least one embodiment, the processing device 210 includes memory for storing data to be used by the processing device 210. In at least one embodiment, the memory includes a page buffer used to store graphical data generated by the processing device 210. In at least one embodiment, portions of the memory are associated with a compression attribute that controls whether the contents of the portion are compressed for transmission and storage in a cache, such as the L2 cache 104 shown in Figure 1. In at least one embodiment, the API is used to control the attribute. In at least one embodiment, application 202 uses the API to cause portions of the memory to be compressed by associating those portions with the attribute. 【0037】 Figure 3 shows an example of an API for enabling compression of memory for caching transmissions, according to at least one embodiment. In example 300, the API includes a memory allocation function 310, which, when called, is to be reserved on a computing device such as the processing device 100 illustrated in Figure 1. In at least one embodiment, the computing device corresponds to the processing device 210 shown in Figure 2. 【0038】 In at least one embodiment, memory allocation includes a processing device reserving virtual or physical memory to be used by the processing device to perform a computing task. In at least one embodiment, the memory is reserved by storing information in a data structure for instructing the reservation of the memory. In at least one embodiment, the information includes size and address information and information for instructing whether the memory should be compressed. In at least one embodiment, this information is communicated via parameters of a memory allocation function 310. In at least one embodiment, these parameters include size 306 and property 308. In at least one embodiment, the output of the function 310 is a handle 304 pointing to the reserved memory. In at least one embodiment, these property 308 further include a compression flag 302 for instructing whether this memory should be sent to the cache as compressed data and / or stored in the cache as compressed. 【0039】 Figure 4 shows an example of a process for enabling and utilizing data compression on a GPU, based on at least one embodiment. While Figure 4 is illustrated as a sequence of elements, it should be understood that this illustrated sequence is illustrative and not limiting, and that embodiments may include altered orders of operations or perform the illustrated operations in parallel, unless explicitly indicated or logically required. 【0040】 In 402, in at least one embodiment, a library, runtime, or driver receives a request to allocate memory. In at least one embodiment, the library, runtime, or driver is a driver for a parallel computing architecture such as CUDA. In at least one embodiment, the library, runtime, or driver is a user-mode or kernel-mode driver. In at least one embodiment, the library, runtime, or driver corresponds to one or more of those shown in Figure 2. 【0041】 In at least one embodiment, the request for memory allocation is received in response to a call to an API function. In at least one embodiment, the API function corresponds to or is similar to the memory allocation function 310 illustrated in Figure 3. In at least one embodiment, the call to the API function invokes code within the driver to allocate a requested amount of memory having the requested properties. 【0042】 In 404, in at least one embodiment, the driver identifies a value of a compression flag provided via the API function. In at least one embodiment, the flag indicates that compression should be used with respect to the memory allocated in response to the API function. 【0043】 In 406, in at least one embodiment, the driver stores metadata indicating that the memory allocated in response to the API function call should be treated as compressed. In at least one embodiment, the driver interfaces with the processing device to cause the processing device to store the metadata. In at least one embodiment, the metadata is stored in a page table entry. In at least one embodiment, the metadata is stored in a manner accessible to compression circuit elements in the processing device. For example, in at least one embodiment, the metadata is stored in a manner accessible to post-L2 compression circuit elements. 【0044】 In 408, in at least one embodiment, the data is compressed and written to the cache. In at least one embodiment, the data is compressed in this way in response to the processing device determining that the data should be written to a memory area associated with a compression flag. For example, in at least one embodiment, the processing device determines that the data should be written to a memory area associated with a compression flag and then compresses the data for transmission to the cache. In at least one embodiment, this is done when the data is accessed by a streaming multiprocessor, as described with respect to Figure 1. In at least one embodiment, the data is stored in memory in a compressed form prior to transmission to the cache and is sent to the cache while still compressed. 【0045】 In 410, in at least one embodiment, the data read from the cache is decompressed. In at least one embodiment, a processing device reads compressed data from the cache, decompresses it, and provides the decompressed data to a streaming multiprocessor. In at least one embodiment, a processing device reads compressed data from the cache, decompresses it, and writes the decompressed data back to memory. In at least one embodiment, the compression circuit element is an accessible pre-cache for enabling data compression and decompression between memory and the cache. In at least one embodiment, the compression circuit element is an accessible post-cache for enabling decompression and decompression between the cache and the processor. In at least one embodiment, this enables efficient utilization of bandwidth between memory and the cache. 【0046】 Figure 5 shows an example of a process for enabling data compression on a GPU, based on at least one embodiment. Figure 4 is illustrated as a sequence of elements, but it should be understood that this illustrated sequence is illustrative and not limiting, and that embodiments may include a modified order of operations or perform the illustrated operations in parallel, unless explicitly indicated or logically required. 【0047】 In 502, in at least one embodiment, the API receives a call to the API function. In at least one embodiment, the API function is implemented by a layer of the software stack, such as in a library, runtime, or driver, as illustrated in Figure 2. In at least one embodiment, GPU driver software, such as the driver illustrated in Figure 2, receives an indication that this function has been called and responds to the call. 【0048】 In 504, in at least one embodiment, one or more compression relation parameters to the API function are identified. In at least one embodiment, the parameter includes a flag indicating the compression ratio of the memory area. In at least one embodiment, a library, runtime, or driver identifies the parameter and responds by performing or causing to perform the actions described with respect to elements 506-510. 【0049】 In 506, in at least one embodiment, a page table entry is stored to contain data indicating the compression ratio of the associated memory area. In at least one embodiment, the compression ratio indicates that the associated memory area is intended to store data that can be corrected for compression. 【0050】 In 508, in at least one embodiment, the data in the memory region is compressed for transmission to the cache based on the page table entries. In at least one embodiment, the driver or a circuit element on the GPU determines that the memory is instructed to be compressible, causing the data to be compressed. In at least one embodiment, the compression is performed by a compression circuit element on the GPU. In at least one embodiment, the compression is performed by the driver. 【0051】 In 510, in at least one embodiment, the GPU decompresses the data stored in the cache before sending it to the processor. In at least one embodiment, the driver or circuit element includes a post-L2 compression circuit element. In at least one embodiment, the data in the cache is decompressed before being sent to any other onboard client circuit element. 【0052】 In at least one embodiment, the system comprises one or more processors for implementing an API to indicate storage for storing information to be compressed. In at least one embodiment, the API includes parameters for indicating that the information to be stored in the storage is compressible. In at least one embodiment, the compressible storage is storage designated by an application using the storage as potentially containing data suitable for compression. In at least one embodiment, when compressible storage is indicated, the processing device decides to compress the information stored in the storage for transmission between components of the processing device, such as from memory to an L2 cache. In at least one embodiment, the compression is performed by a compression circuit element on the processing device. 【0053】 In at least one embodiment, the API parameters include data indicating that the allocated block of memory is for containing data that should be compressed for transmission between components of the processing device. 【0054】 In at least one embodiment, the API causes a processing device to store a compressed version of the information. In at least one embodiment, this information is stored in an L2 cache. In at least one embodiment, the API causes the processing device to decompress the compressed version of this information before sending the information to a client circuit element on the processing device. For example, in at least one embodiment, the compressed data is read from the L2 cache, decompressed by a post-L2 compression circuit element, and sent to a streaming multiprocessor. 【0055】 Data center Figure 6 shows an exemplary data center 600 according to at least one embodiment. In at least one embodiment, the data center 600 includes, but is not limited to, a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640. 【0056】 In at least one embodiment, as shown in Figure 6, the data center infrastructure layer 610 may include a resource orchestrator 612, grouped computing resources 614, and node computing resources ("node CRs") 616(1) to 616(N), where "N" represents any positive integer. In at least one embodiment, nodes CR616(1) to CR616(N) may include, but not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field-programmable gate arrays ("FPGA"), data processing units ("DPU") in network devices, graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules. In at least one embodiment, one or more nodes CR from among nodes CR616(1) to CR616(N) may be servers having one or more of the computing resources described above. 【0057】 In at least one embodiment, the grouped computing resources 614 may include separate groupings of node CRs housed in one or more racks (not shown), or many racks housed in a data center at various geographical locations (also not shown). A separate grouping of node CRs within the grouped computing resources 614 may include grouped compute resources, network resources, memory resources, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped in one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination. 【0058】 In at least one embodiment, the resource orchestrator 612 may configure or otherwise control one or more nodes CR616(1) to 616(N) and / or a grouped computing resource 614. In at least one embodiment, the resource orchestrator 612 may include a software design infrastructure ("SDI") management entity for the data center 600. In at least one embodiment, the resource orchestrator 612 may include hardware, software, or any combination thereof. 【0059】 In at least one embodiment, as shown in Figure 6, the framework layer 620 includes, but is not limited to, a job scheduler 632, a configuration manager 634, a resource manager 636, and a distributed file system 638. In at least one embodiment, the framework layer 620 may include a framework for supporting software 652 of the software layer 630 and / or one or more applications 642 of the application layer 640. In at least one embodiment, the software 652 or (one or more) applications 642 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure, respectively. In at least one embodiment, the framework layer 620 may be a type of free and open-source software web application framework, such as Apache Spark® ("Spark"), which can leverage the distributed file system 638 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 632 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 600. In at least one embodiment, the configuration manager 634 may be able to configure different layers, such as the software layer 630 and the framework layer 620, which includes Spark and a distributed file system 638 to support large-scale data processing. In at least one embodiment, the resource manager 636 may be able to manage clustered or grouped computing resources that are mapped or allocated to support the distributed file system 638 and the job scheduler 632. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 614 in the data center infrastructure layer 610.In at least one embodiment, the resource manager 636 may work in conjunction with the resource orchestrator 612 to manage these mapped or allocated computing resources. 【0060】 In at least one embodiment, the software 652 contained within the software layer 630 may include software used by nodes CR616(1) to 616(N), grouped computing resources 614, and / or at least a portion of the distributed file system 638 of the framework layer 620. One or more types of software may include, but are not limited to, internet web page search software, email virus scanning software, database software, and streaming video content software. 【0061】 In at least one embodiment, one or more applications 642 contained within the application layer 640 may include one or more types of applications used by nodes CR616(1) to 616(N), grouped computing resources 614, and / or at least a portion of the distributed file system 638 of the framework layer 620. At least one or more types of applications may include, but are not limited to, CUDA applications. 【0062】 In at least one embodiment, any of the configuration manager 634, resource manager 636, and resource orchestrator 612 may implement any number and type of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may relieve the data center operator of data center 600 of the task of determining potentially faulty configurations and potentially avoiding underutilized and / or underperforming portions of the data center. 【0063】 Computer-based systems The following diagrams illustrate exemplary computer-based systems that may be used to implement at least one embodiment, but are not limited to it. 【0064】 Figure 7 shows a processing system 700 according to at least one embodiment. In at least one embodiment, the processing system 700 includes one or more processors 702 and one or more graphics processors 708, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 702 or processor cores 707. In at least one embodiment, the processing system 700 is a processing platform embedded in a system-on-a-chip ("SoC") integrated circuit for use in a mobile device, handheld device, or embedded device. 【0065】 In at least one embodiment, the processing system 700 may include, or be incorporated into, a server-based gaming platform, game console, media console, mobile gaming console, handheld game console, or online game console. In at least one embodiment, the processing system 700 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, the processing system 700 may also include, be coupled to, or be incorporated into wearable devices such as a smartwatch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, the processing system 700 is a television or set-top box device having one or more processors 702 and a graphical interface produced by one or more graphics processors 708. 【0066】 In at least one embodiment, one or more processors 702 each include one or more processor cores 707 for processing instructions that, when executed, perform actions for the system and user software. In at least one embodiment, each of the one or more processor cores 707 is configured to process a particular instruction set 709. In at least one embodiment, the instruction set 709 may facilitate computing via complex instruction set computing ("CISC"), reduced instruction set computing ("RISC"), or very long instruction word ("VLIW"). In at least one embodiment, each processor core 707 may process a different instruction set 709, and the instruction set 709 may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, the processor core 707 may also include other processing devices, such as a digital signal processor ("DSP"). 【0067】 In at least one embodiment, the processor 702 includes a cache memory ("cache") 704. In at least one embodiment, the processor 702 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of the processor 702. In at least one embodiment, the processor 702 also uses an external cache (e.g., a Level 3 ("L3") cache or a Last Level Cache ("LLC")) (not shown), and the external cache may be shared among processor cores 707 using known cache coherency techniques. In at least one embodiment, additionally, a register file 706 may be included in the processor 702, and the register file 706 may contain different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). In at least one embodiment, the register file 706 may contain general-purpose registers or other registers. 【0068】 In at least one embodiment, one or more processors 702 are coupled with one or more interface buses 710 to transmit communication signals, such as addresses, data, or control signals, between the processors 702 and other components in the processing system 700. In at least one embodiment, the interface bus 710 in one embodiment may be a processor bus, such as a version of the Direct Media Interface ("DMI") bus. In at least one embodiment, the interface bus 710 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., "PCI": Peripheral Component Interconnect, PCI Express ("PCIe")), memory buses, or other types of interface buses. In at least one embodiment, the (one or more) processors 702 include an integrated memory controller 716 and a platform controller hub 730. In at least one embodiment, the memory controller 716 facilitates communication between the memory device and other components of the processing system 700, and the platform controller hub ("PCH") 730 provides connectivity to I / O devices via a local input / output ("I / O") bus. 【0069】 In at least one embodiment, the memory device 720 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase-change memory device, or any other memory device having performance suitable for acting as processor memory. In at least one embodiment, the memory device 720 may act as system memory for the processing system 700 to store data 722 and instructions 721 for use when one or more processors 702 execute an application or process. In at least one embodiment, the memory controller 716 may also be coupled to an optional external graphics processor 712, which may communicate with one or more graphics processors 708 in the processor 702 to perform graphics and media operations. In at least one embodiment, a display device 711 may be connected to one or more processors 702. In at least one embodiment, the display device 711 may include one or more internal display devices, such as those found in mobile electronic devices or laptop devices, or external display devices attached via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 711 may include a head-mounted display (HMD), such as a stereoscopic display device for use in virtual reality ("VR") or augmented reality ("AR") applications. 【0070】 In at least one embodiment, the platform controller hub 730 enables peripherals to connect to the memory device 720 and processor 702 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 746, a network controller 734, a firmware interface 728, a wireless transceiver 726, a touch sensor 725, and a data storage device 724 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 724 may be connected via a storage interface (e.g., SATA) or via a peripheral bus such as PCI or PCIe. In at least one embodiment, the touch sensor 725 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 726 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 728 enables communication with system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, the network controller 734 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 710. In at least one embodiment, the audio controller 746 is a multi-channel high-definition audio controller.In at least one embodiment, the processing system 700 includes an optional legacy I / O controller 740 for connecting legacy devices (e.g., Personal System 2 ("PS / 2")) to the processing system 700. In at least one embodiment, the platform controller hub 730 may also connect to one or more Universal Serial Bus ("USB") controller 742-connected input devices, such as a keyboard and mouse combination 743, a camera 744, or other USB input devices. 【0071】 In at least one embodiment, instances of the memory controller 716 and the platform controller hub 730 may be incorporated into a sophisticated external graphics processor, such as an external graphics processor 712. In at least one embodiment, the platform controller hub 730 and / or the memory controller 716 may be external to one or more processors 702. For example, in at least one embodiment, the processing system 700 may include an external memory controller 716 and a platform controller hub 730, which may be configured as a memory controller hub and peripheral controller hub within a system chipset communicating with (one or more) processors 702. 【0072】 Figure 8 shows a computer system 800 according to at least one embodiment. In at least one embodiment, the computer system 800 may be a system, a SOC, or any combination of interconnected devices and components. In at least one embodiment, the computer system 800 is formed together with a processor 802 which may include an execution unit for executing instructions. In at least one embodiment, the computer system 800 may include components such as the processor 802 for employing an execution unit which includes logic for implementing algorithms for processing data. In at least one embodiment, the computer system 800 may include a processor such as the PENTIUM® processor family, Xeon®, Itanium®, XScale®, and / or StrongARM®, Intel® Core®, or Intel® Nervana® microprocessors, available from Intel Corporation in Santa Clara, California, but other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 800 may run a version of the WINDOWS® operating system available from Microsoft Corporation in Redmond, Washington, but other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used. 【0073】 In at least one embodiment, the computer system 800 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (DSP), a SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system capable of executing one or more instructions. 【0074】 In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 that can be configured to run Compute Unified Device Architecture ("CUDA") (CUDA® is a registered trademark developed by NVIDIA Corporation in Santa Clara, California). In at least one embodiment, the CUDA program is at least part of a software application written in the CUDA programming language. In at least one embodiment, the computer system 800 is a single-processor desktop or server system. In at least one embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800. 【0075】 In at least one embodiment, the processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, the processor 802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside outside the processor 802. In at least one embodiment, the processor 802 may also include a combination of both internal and external caches. In at least one embodiment, the register file 806 may store different types of data in various registers, including, but is not limited to, integer registers, floating-point registers, status registers, and instruction pointer registers. 【0076】 In at least one embodiment, but not limited to, an execution unit 808 containing logic for performing integer and floating-point arithmetic may also be present in the processor 802. The processor 802 may also include a microcode ("u-code") read-only memory ("ROM") for storing microcode for several macro instructions. In at least one embodiment, the execution unit 808 may include logic for handling a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809, along with the associated circuit elements for executing the instructions, in the instruction set of the general-purpose processor 802, arithmetic used by many multimedia applications can be performed using packed data in the general-purpose processor 802. In at least one embodiment, many multimedia applications may be accelerated and run more efficiently by using the full width of the processor's data bus to perform arithmetic on packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more arithmetic operations, one data element at a time. 【0077】 In at least one embodiment, the execution unit 808 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuits. In at least one embodiment, the computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a DRAM device, SRAM device, flash memory device, or other memory device. Memory 820 may store (one or more) instructions 819 and / or data 821, which are represented by data signals that can be executed by the processor 802. 【0078】 In at least one embodiment, a system logic chip may be coupled to the processor bus 810 and memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide memory 820 with a high-bandwidth memory path 818 for instruction and data storage, as well as for the storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 may directly transmit data signals between the processor 802, memory 820, and other components in the computer system 800, and may bridge data signals between the processor bus 810, memory 820, and system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH816 may be coupled to memory 820 through a high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH816 via an Accelerated Graphics Port ("AGP") interconnect 814. 【0079】 In at least one embodiment, the computer system 800 may use a system I / O 822, which is a proprietary hub interface bus for coupling the MCH 816 to the I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripherals to memory 820, a chipset, and a processor 802. Examples may include, but is not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, data storage 824, a legacy I / O controller 823 including a user input interface 825 and a keyboard interface, a serial expansion port 827 such as USB, and a network controller 834. The data storage 824 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. 【0080】 In at least one embodiment, Figure 8 shows a system including interconnected hardware devices or “chips.” In at least one embodiment, Figure 8 may show an exemplary SoC. In at least one embodiment, the devices shown in Figure 8 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or any combination thereof. In at least one embodiment, one or more components of system 800 are interconnected using a Compute Express Link (“CXL”) interconnect. 【0081】 Figure 9 shows System 900 according to at least one embodiment. In at least one embodiment, System 900 is an electronic device utilizing Processor 910. In at least one embodiment, System 900 may be, for example, a notebook, a tower server, a rack server, a blade server, an edge device communicatively coupled to one or more on-premises service providers or cloud service providers, a laptop, a desktop, a tablet, a mobile device, a telephone, an embedded computer, or any other suitable electronic device. 【0082】 In at least one embodiment, the system 900 may include a processor 910 communicably coupled to any preferred number or type of components, peripherals, modules, or devices, but not limited to these. In at least one embodiment, the processor 910 is I 2The devices are coupled using buses or interfaces such as the C-bus, System Management Bus ("SMBus"), Low Pin Count ("LPC") bus, Serial Peripheral Interface ("SPI"), High Definition Audio ("HDA") bus, Serial Advance Technology Attachment ("SATA") bus, USB (versions 1, 2, and 3), or Universal Asynchronous Receiver / Transmitter ("UART") bus. In at least one embodiment, Figure 9 shows a system including interconnected hardware devices or "chips." In at least one embodiment, Figure 9 may show an exemplary SoC. In at least one embodiment, the devices shown in Figure 9 may be interconnected by proprietary interconnects, standard interconnects (e.g., PCIe), or any combination thereof. In at least one embodiment, one or more components of Figure 9 are interconnected using CXL interconnects. 【0083】 In at least one embodiment, Figure 9 includes a display 924, a touchscreen 925, a touchpad 930, a Near Field Communication ("NFC") unit 945, a sensor hub 940, a thermal sensor 946, an Express Chipset ("EC") 935, a Trusted Platform Module ("TPM") 938, a BIOS / firmware / flash memory ("BIOS, FW flash") 922, a DSP 960, a Solid State Disk ("SSD") or Hard Disk Drive ("HDD") 920, a Wireless Local Area Network ("WLAN") unit 950, a Bluetooth unit 952, a Wireless Wide Area Network ("WWAN") unit 956, and a Global Positioning System ("GPS") This may include a Positioning System (955), a camera such as a USB 3.0 camera ("USB 3.0 Camera") (954), or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") (915) implemented, for example, in the LPDDR3 standard. Each of these components may be implemented in any preferred manner. 【0084】 In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components described above. In at least one embodiment, the accelerometer 941, the ambient light sensor ("ALS") 942, the compass 943, and the gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, the thermal sensor 939, the fan 937, the keyboard 936, and the touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, the speaker 963, the headphones 964, and the microphone ("mic") 965 may be communicatively coupled to an audio unit ("audio codec and class D amplifier") 962, and the audio unit 962 may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 962 may include, for example, an audio coder / decoder ("codec") and a class D amplifier, without limitation. In at least one embodiment, a SIM card ("SIM") 957 may be communicatively coupled to a WWAN unit 956. In at least one embodiment, components such as a WLAN unit 950 and a Bluetooth unit 952, as well as the WWAN unit 956, may be implemented in a Next Generation Form Factor ("NGFF"). 【0085】 Figure 10 shows an exemplary integrated circuit 1000 according to at least one embodiment. In at least one embodiment, the exemplary integrated circuit 1000 is a SoC that can be fabricated using one or more IP cores. In at least one embodiment, the integrated circuit 1000 includes one or more application processors 1005 (e.g., CPU, DPU), at least one graphics processor 1010, and additionally, an image processor 1015 and / or a video processor 1020, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1000 includes a USB controller 1025, a UART controller 1030, an SPI / SDIO controller 1035, and I 2 S / I 2 The integrated circuit includes peripherals or bus logic, including a C controller 1040. In at least one embodiment, the integrated circuit 1000 may include a display device 1045 coupled to one or more of the following: a high-definition multimedia interface ("HDMI"®) controller 1050 and a mobile industry processor interface ("MIPI") display interface 1055. In at least one embodiment, storage may be provided by a flash memory subsystem 1060, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1065 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits may additionally include an embedded security engine 1070. 【0086】 Figure 11 shows a computing system 1100 according to at least one embodiment. In at least one embodiment, the computing system 1100 includes a processing subsystem 1101 having one or more processors 1102 and system memory 1104 communicating via an interconnection path which may include a memory hub 1105. In at least one embodiment, the memory hub 1105 may be a separate component within a chipset component or may be integrated within one or more processors 1102. In at least one embodiment, the memory hub 1105 is coupled to an I / O subsystem 1111 via a communication link 1106. In at least one embodiment, the I / O subsystem 1111 includes an I / O hub 1107 which can enable the computing system 1100 to receive input from one or more input devices 1108. In at least one embodiment, the I / O hub 1107 can enable a display controller, which may be included in one or more processors 1102, to provide output to one or more display devices 1110A. In at least one embodiment, one or more display devices 1110A coupled with the I / O hub 1107 may include local, internal, or embedded display devices. 【0087】 In at least one embodiment, the processing subsystem 1101 includes one or more parallel processors 1112 coupled to a memory hub 1105 via a bus or other communication link 1113. In at least one embodiment, the communication link 1113 may be one of any number of standards-based communication link technologies or protocols, such as PCIe, or it may be a vendor-specific communication interface or communication fabric. In at least one embodiment, one or more parallel processors 1112 may form a computation-focused parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a many-integrated-core processor. In at least one embodiment, one or more parallel processors 1112 may form a graphics processing subsystem, which may output pixels to one of one or more display devices 1110A coupled via an I / O hub 1107. In at least one embodiment, one or more parallel processors 1112 may also include a display controller and a display interface (not shown) for enabling direct connection to one or more display devices 1110B. 【0088】 In at least one embodiment, the system storage unit 1114 can be connected to the I / O hub 1107 to provide storage functionality for the computing system 1100. In at least one embodiment, an I / O switch 1116 may be used to provide an interface mechanism for enabling connectivity between the I / O hub 1107 and other components such as a network adapter 1118 and / or a wireless network adapter 1119 that may be incorporated into the platform, as well as various other devices that may be added via one or more add-in devices 1120. In at least one embodiment, the network adapter 1118 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1119 may include one or more other network devices, including Wi-Fi, Bluetooth, NFC, or one or more wireless radios. 【0089】 In at least one embodiment, the computing system 1100 may include other components, not explicitly shown, which may also be connected to the I / O hub 1107, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the communication paths interconnecting the various components in Figure 11 may be implemented using any preferred protocol, such as a PCI-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols, such as NVLink High Speed ​​Interconnection, or one or more protocols, or interconnection protocols. 【0090】 In at least one embodiment, one or more parallel processors 1112 incorporate circuit elements optimized for graphics and video processing, such as video output circuit elements, to constitute a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processors 1112 incorporate circuit elements optimized for general-purpose processing. In at least one embodiment, components of the computing system 1100 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1112, a memory hub 1105, one or more processors 1102, and an I / O hub 1107 may be incorporated into a SoC integrated circuit. In at least one embodiment, components of the computing system 1100 may be incorporated into a single package to form a system-in-package ("SIP") configuration. In at least one embodiment, at least a portion of the components of the computing system 1100 may be incorporated into a multi-chip module ("MCM"), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, the I / O subsystem 1111 and the display device 1110B are omitted from the computing system 1100. 【0091】 Processing system The following diagram illustrates an exemplary processing system that may be used to implement at least one embodiment, but is not limited to it. 【0092】 Figure 12 shows an accelerated processing unit ("APU") 1200 according to at least one embodiment. In at least one embodiment, the APU 1200 is developed by AMD Corporation in Santa Clara, California. In at least one embodiment, the APU 1200 may be configured to run application programs, such as CUDA programs. In at least one embodiment, the APU 1200 includes, but is not limited to, a core complex 1210, a graphics complex 1240, a fabric 1260, an I / O interface 1270, a memory controller 1280, a display controller 1292, and a multimedia engine 1294. In at least one embodiment, the APU 1200 may include, but is not limited to, any number of core complexes 1210, any number of graphics complexes 1250, any number of display controllers 1292, and any number of multimedia engines 1294 in any combination. For illustrative purposes, multiple instances of similar objects are shown herein with a reference number identifying the object and, where necessary, a number in parentheses identifying the instance. 【0093】 In at least one embodiment, the core complex 1210 is a CPU, the graphics complex 1240 is a GPU, and the APU 1200 is a processing unit that incorporates the 1210 and 1240 on a single chip, but is not limited to this. In at least one embodiment, some tasks may be assigned to the core complex 1210, and other tasks may be assigned to the graphics complex 1240. In at least one embodiment, the core complex 1210 is configured to run main control software related to the APU 1200, such as the operating system. In at least one embodiment, the core complex 1210 is the master processor of the APU 1200, controlling and coordinating the operation of the other processors. In at least one embodiment, the core complex 1210 issues commands that control the operation of the graphics complex 1240. In at least one embodiment, the core complex 1210 may be configured to run host executable code derived from CUDA source code, and the graphics complex 1240 may be configured to run device executable code derived from CUDA source code. 【0094】 In at least one embodiment, the core complex 1210 includes, but is not limited to, cores 1220(1) to 1220(4) and an L3 cache 1230. In at least one embodiment, the core complex 1210 may include, but is not limited to, any number of cores 1220 and any number and type of caches in any combination. In at least one embodiment, the cores 1220 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 1220 is a CPU core. 【0095】 In at least one embodiment, each core 1220 includes, but is not limited to, a fetch / decode unit 1222, an integer execution engine 1224, a floating-point execution engine 1226, and an L2 cache 1228. In at least one embodiment, the fetch / decode unit 1222 fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate microinstructions to the integer execution engine 1224 and the floating-point execution engine 1226. In at least one embodiment, the fetch / decode unit 1222 can simultaneously dispatch one microinstruction to the integer execution engine 1224 and another microinstruction to the floating-point execution engine 1226. In at least one embodiment, the integer execution engine 1224 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1226 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decoder unit 1222 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1224 and the floating-point execution engine 1226. 【0096】 In at least one embodiment, each core 1220(i), where i is an integer representing a particular instance of core 1220, can access the L2 cache 1228(i) contained within core 1220(i). In at least one embodiment, each core 1220 contained within core complex 1210(j), where j is an integer representing a particular instance of core complex 1210, is connected to other cores 1220 contained within core complex 1210(j) via the L3 cache 1230(j) contained within core complex 1210(j). In at least one embodiment, a core 1220 contained within core complex 1210(j), where j is an integer representing a particular instance of core complex 1210, can access all of the L3 cache 1230(j) contained within core complex 1210(j). In at least one embodiment, the L3 cache 1230 may contain any number of slices, but is not limited to any number. 【0097】 In at least one embodiment, the graphics complex 1240 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the graphics complex 1240 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering an image to a display. In at least one embodiment, the graphics complex 1240 is configured to perform non-graphics operations. In at least one embodiment, the graphics complex 1240 is configured to perform both graphics-related and non-graphics operations. 【0098】 In at least one embodiment, the graphics complex 1240 includes, but not limited to, any number of compute units 1250 and an L2 cache 1242. In at least one embodiment, the compute units 1250 share the L2 cache 1242. In at least one embodiment, the L2 cache 1242 is partitioned. In at least one embodiment, the graphics complex 1240 includes, but not limited to, any number of compute units 1250 and any number and type of cache (including zero). In at least one embodiment, the graphics complex 1240 includes, but not limited to, any amount of dedicated graphics hardware. 【0099】 In at least one embodiment, each compute unit 1250 includes, but not limited to, any number of SIMD units 1252 and shared memory 1254. In at least one embodiment, each SIMD unit 1252 may implement a SIMD architecture and be configured to perform operations in parallel. In at least one embodiment, each compute unit 1250 may execute any number of thread blocks, but each thread block executes on a single compute unit 1250. In at least one embodiment, a thread block includes, but not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 1252 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process a different set of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 1254. 【0100】 In at least one embodiment, Fabric 1260 is a system interconnect that facilitates data and control transmissions across the core complex 1210, graphics complex 1240, I / O interface 1270, memory controller 1280, display controller 1292, and multimedia engine 1294. In at least one embodiment, APU 1200 may include, but not limited to, any number and type of system interconnects in addition to or instead of Fabric 1260, which facilitate data and control transmissions across any number and type of directly or indirectly linked components that may be inside or outside APU 1200. In at least one embodiment, I / O interface 1270 represents any number and type of I / O interface (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 1270. In at least one embodiment, peripheral devices coupled to the I / O interface 1270 may include, but are not limited to, a keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, and the like. 【0101】 In at least one embodiment, the display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, the multimedia engine 1294 includes, but is not limited to, any amount and type of circuit elements related to multimedia, such as video decoders, video encoders, and image signal processors. In at least one embodiment, the memory controller 1280 facilitates data transfer between the APU 1200 and the unified system memory 1290. In at least one embodiment, the core complex 1210 and the graphics complex 1240 share the unified system memory 1290. 【0102】 In at least one embodiment, the APU 1200 implements a memory subsystem including any amount and type of memory controllers 1280 and memory devices (e.g., shared memory 1254) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the APU 1200 implements a cache subsystem including one or more cache memories (e.g., L2 cache 1328, L3 cache 1230, and L2 cache 1242), each of which may be private to any number of components (e.g., core 1220, core complex 1210, SIMD unit 1252, compute unit 1250, and graphics complex 1240) or shared among any number of components. 【0103】 Figure 13 shows a CPU 1300 according to at least one embodiment. In at least one embodiment, the CPU 1300 is developed by AMD Corporation in Santa Clara, California. In at least one embodiment, the CPU 1300 may be configured to run application programs. In at least one embodiment, the CPU 1300 is configured to run main control software, such as an operating system. In at least one embodiment, the CPU 1300 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 1300 may be configured to run host executable code derived from CUDA source code, and the external GPU may be configured to run device executable code derived from such CUDA source code. In at least one embodiment, the CPU 1300 includes, but is not limited to, any number of core complexes 1310, a fabric 1360, an I / O interface 1370, and a memory controller 1380. 【0104】 In at least one embodiment, the core complex 1310 includes, but is not limited to, cores 1320(1) to 1320(4) and an L3 cache 1330. In at least one embodiment, the core complex 1310 may include, but is not limited to, any number of cores 1320 and any number and type of caches in any combination. In at least one embodiment, the cores 1320 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 1320 is a CPU core. 【0105】 In at least one embodiment, each core 1320 includes, but is not limited to, a fetch / decode unit 1322, an integer execution engine 1324, a floating-point execution engine 1326, and an L2 cache 1328. In at least one embodiment, the fetch / decode unit 1322 fetches instructions, decodes such instructions, generates micro-operations, and dispatches separate microinstructions to the integer execution engine 1324 and the floating-point execution engine 1326. In at least one embodiment, the fetch / decode unit 1322 can simultaneously dispatch one microinstruction to the integer execution engine 1324 and another microinstruction to the floating-point execution engine 1326. In at least one embodiment, the integer execution engine 1324 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 1326 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decoder unit 1322 dispatches microinstructions to a single execution engine that replaces both the integer execution engine 1324 and the floating-point execution engine 1326. 【0106】 In at least one embodiment, each core 1320(i), where i is an integer representing a particular instance of core 1320, can access the L2 cache 1328(i) contained within core 1320(i). In at least one embodiment, each core 1320 contained within core complex 1310(j), where j is an integer representing a particular instance of core complex 1310, is connected to other cores 1320 in core complex 1310(j) via the L3 cache 1330(j) contained within core complex 1310(j). In at least one embodiment, a core 1320 contained within core complex 1310(j), where j is an integer representing a particular instance of core complex 1310, can access all of the L3 cache 1330(j) contained within core complex 1310(j). In at least one embodiment, the L3 cache 1330 may contain any number of slices, but is not limited to any number. 【0107】 In at least one embodiment, the fabric 1360 is a system interconnect that facilitates data and control transmissions across the core complexes 1310(1) to 1310(N) (where N is an integer greater than 0), the I / O interface 1370, and the memory controller 1380. In at least one embodiment, the CPU 1300 may include, but not limited to, any number and type of system interconnects in addition to or instead of the fabric 1360, which facilitates data and control transmissions across any number and type of directly or indirectly linked components that may be inside or outside the CPU 1300. In at least one embodiment, the I / O interface 1370 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to the I / O interface 1370. In at least one embodiment, peripheral devices coupled to the I / O interface 1370 may include, but are not limited to, a display, keyboard, mouse, printer, scanner, joystick or other type of game controller, media recording device, external storage device, network interface card, and the like. 【0108】 In at least one embodiment, the memory controller 1380 facilitates data transfer between the CPU 1300 and the system memory 1390. In at least one embodiment, the core complex 1310 and the graphics complex 1340 share the system memory 1390. In at least one embodiment, the CPU 1300 implements a memory subsystem including any number and type of memory controllers 1380 and memory devices, which may be dedicated to one component or shared among multiple components, but are not limited. In at least one embodiment, the CPU 1300 implements a cache subsystem including one or more cache memories (e.g., L2 cache 1328 and L3 cache 1330), each of which may be private to any number of components (e.g., core 1320 and core complex 1310) or shared among any number of components. 【0109】 Figure 14 shows an exemplary accelerator integration slice 1490 according to at least one embodiment. As used herein, a “slice” comprises a designated portion of the processing resources of an accelerator integration circuit. In at least one embodiment, the accelerator integration circuit provides cache management, memory access, context management, and interrupt management services on behalf of multiple graphics processing engines contained within a graphics acceleration module. Each graphics processing engine may comprise a separate GPU. Alternatively, the graphics processing engine may comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU with multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip. 【0110】 The application effective address space 1482 in system memory 1414 stores process elements 1483. In one embodiment, process element 1483 is stored in response to a GPU call 1481 from an application 1480 running on processor 1407. Process element 1483 contains the process state of the corresponding application 1480. The work descriptor ("WD") 1484 contained in process element 1483 may be a single job requested by the application or may contain a pointer to a queue of jobs. In at least one embodiment, WD 1484 is a pointer to a job request queue in the application effective address space 1482. 【0111】 The graphics acceleration module 1446 and / or individual graphics processing engines may be shared by all or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD1484 to the graphics acceleration module 1446 to start jobs in a virtualized environment. 【0112】 In at least one embodiment, the dedicated process programming model is implementation-specific. In this model, a single process owns the graphics acceleration module 1446 or an individual graphics processing engine. Since the graphics acceleration module 1446 is owned by a single process, the hypervisor initializes the accelerator integration circuitry for the owning partition, and when the graphics acceleration module 1446 is allocated, the operating system initializes the accelerator integration circuitry for the owning process. 【0113】 During operation, the WD fetch unit 1491 in the accelerator integrated slice 1490 fetches the next WD 1484 containing instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1446. As shown, the data from WD 1484 is stored in register 1445 and can be used by the memory management unit ("MMU") 1439, the interrupt management circuit 1447, and / or the context management circuit 1448. For example, one embodiment of the MMU 1439 includes a segment / page walk circuit element for accessing the segment / page table 1486 in the OS virtual address space 1485. The interrupt management circuit 1447 may process an interrupt event ("INT") 1492 received from the graphics acceleration module 1446. When performing graphics operations, the effective address 1493 generated by the graphics processing engine is translated to a real address by the MMU 1439. 【0114】 In one embodiment, the same set of registers 1445 may be duplicated for each graphics processing engine and / or graphics acceleration module 1446 and initialized by the hypervisor or operating system. Each of these duplicated registers may be included in the accelerator integration slice 1490. Exemplary registers that may be initialized by the hypervisor are shown in Table 1. [Table 1] 【0115】 Table 2 shows exemplary registers that can be initialized by the operating system. [Table 2] 【0116】 In one embodiment, each WD1484 is specific to a particular graphics acceleration module 1446 and / or a particular graphics processing engine. The WD1484 contains all the information required by the graphics processing engine to perform the work, or the WD1484 may be a pointer to a memory location set by the application for a command queue of work to be completed. 【0117】 Figures 15A and 15B show exemplary graphics processors according to at least one embodiment. In at least one embodiment, any of the exemplary graphics processors may be fabricated using one or more IP cores. In addition to those shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processors are intended for use within a SoC. 【0118】 Figure 15A shows an exemplary graphics processor 1510 of an SoC integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. Figure 15B shows an additional exemplary graphics processor 1540 of an SoC integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 1510 of Figure 15A is a low-power graphics processor core. In at least one embodiment, the graphics processor 1540 of Figure 15B is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1510 and 1540 may be a variation of the graphics processor 1010 of Figure 10. 【0119】 In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D-1515N-1, and 1515N). In at least one embodiment, the graphics processor 1510 can execute different shader programs via separate logic, thereby optimizing the vertex processor 1505 to perform operations for a vertex shader program, and the one or more fragment processors 1515A-1515N to perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. In at least one embodiment, the vertex processor 1505 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1515A-1515N use primitive and vertex data generated by the vertex processor 1505 to create a frame buffer that is displayed on a display device. In at least one embodiment, one or more fragment processors 1515A-1515N are optimized to execute fragment shader programs such as those provided in the OpenGL API, and the OpenGL API may be used to perform operations similar to those of pixel shader programs such as those provided in the Direct 3D API. 【0120】 In at least one embodiment, the graphics processor 1510 additionally includes one or more MMUs 1520A-1520B, (one or more) caches 1525A-1525B, and (one or more) circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide virtual-physical address mappings for the graphics processor 1510, including vertex processors 1505 and / or (one or more) fragment processors 1515A-1515N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 1005, image processor 1015, and / or video processor 1020 in Figure 10, thereby allowing each processor 1005-1020 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable the graphics processor 1510 to interface with other IP cores in the SoC, either via the SoC's internal bus or via a direct connection. 【0121】 In at least one embodiment, the graphics processor 1540 includes one or more MMUs 1520A to 1520B of the graphics processor 1510 in Figure 15A, caches 1525A to 1525B, and circuit interconnects 1530A to 1530B. In at least one embodiment, the graphics processor 1540 includes one or more shader cores 1555A-1555N (for example, 1555A, 1555B, 1555C, 1555D, 1555E, 1555F-1555N-1, and 1555N), where one or more shader cores 1555A-1555N provide a unified shader core architecture in which a single core, or type, or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1540 includes an intercore task manager 1545 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1555A-1555N, and a tiling unit 1558 for accelerating tiling operations for tile-based rendering, where rendering operations for a scene are subdivided in image space, for example, to take advantage of local space coherence within the scene or to optimize the use of an internal cache. 【0122】 Figure 16A shows a graphics core 1600 according to at least one embodiment. In at least one embodiment, the graphics core 1600 may be contained within the graphics processor 1010 in Figure 10. In at least one embodiment, the graphics core 1600 may be a unified shader core 1555A-1555N, as in the case of Figure 15B. In at least one embodiment, the graphics core 1600 includes a shared instruction cache 1602, a texture unit 1618, and a cache / shared memory 1620, which are common to the execution resources within the graphics core 1600. In at least one embodiment, the graphics core 1600 may include multiple slices 1601A-1601N, or partitions for each core, and the graphics processor may include multiple instances of the graphics core 1600. Slices 1601A to 1601N may contain supporting logic including local instruction caches 1604A to 1604N, thread schedulers 1606A to 1606N, thread dispatchers 1608A to 1608N, and register sets 1610A to 1610N. In at least one embodiment, slices 1601A to 1601N may include a set of additional function units ("AFU") 1612A to 1612N, floating-point units ("FPU") 1614A to 1614N, integer arithmetic logic units ("ALU") 1616 to 1616N, address computational units ("ACU") 1613A to 1613N, double-precision floating-point units ("DPFPU") 1615A to 1615N, and matrix processing units ("MPU") 1617A to 1617N. 【0123】 In at least one embodiment, the FPU1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPU1615A-1615N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU1616A-1616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and may be configured for mixed-precision operations. In at least one embodiment, the MPU1617A-1617N may also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU1617-1617N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general-purpose matrix-to-matrix multiplication ("GEMM"). In at least one embodiment, AFU1612A~1612N can perform additional logical operations not supported by the floating-point unit or integer unit, including trigonometric function operations (e.g., sine, cosine, etc.). 【0124】 Figure 16B shows a general-purpose graphics processing unit ("GPGPU") 1630 according to at least one embodiment. In at least one embodiment, the GPGPU 1630 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, the GPGPU 1630 may be configured to allow highly parallel compute operations to be performed by an array of GPUs. In at least one embodiment, the GPGPU 1630 may be directly linked to other instances of the GPGPU 1630 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, the GPGPU 1630 includes a host interface 1632 for enabling connectivity with a host processor. In at least one embodiment, the host interface 1632 is a PCIe interface. In at least one embodiment, the host interface 1632 may be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 1630 receives commands from the host processor and uses the global scheduler 1634 to distribute the execution threads associated with those commands across a set of compute clusters 1636A–1636H. In at least one embodiment, the compute clusters 1636A–1636H share a cache memory 1638. In at least one embodiment, the cache memory 1638 can act as a higher-level cache for the cache memory within the compute clusters 1636A–1636H. 【0125】 In at least one embodiment, the GPGPU 1630 includes memory 1644A-1644B coupled to compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, the memory 1644A-1644B may include various types of memory devices, including graphics random access memory such as DRAM or synchronous graphics random access memory ("SGRAM") including graphics double data rate ("GDDR") memory. 【0126】 In at least one embodiment, compute clusters 1636A to 1636H each include a set of graphics cores, such as the graphics core 1600 in Figure 16A, and the set of graphics cores may include multiple types of integer and floating-point logic units capable of performing computational operations at varying precisions, including those suitable for computations related to CUDA programs. For example, in at least one embodiment, at least a subset of floating-point units in each of compute clusters 1636A to 1636H may be configured to perform 16-bit or 32-bit floating-point operations, and different subsets of floating-point units may be configured to perform 64-bit floating-point operations. 【0127】 In at least one embodiment, multiple instances of GPGPU1630 may be configured to operate as a compute cluster. Compute clusters 1636A-1636H may implement any technically feasible communication techniques for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU1630 communicate via a host interface 1632. In at least one embodiment, GPGPU1630 includes an I / O hub 1639, which couples GPGPU1630 with a GPU link 1640 that enables direct connections to other instances of GPGPU1630. In at least one embodiment, the GPU link 1640 is coupled to a dedicated GPU-GPU bridge that enables communication and synchronization between multiple instances of GPGPU1630. In at least one embodiment, the GPU link 1640 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPU1630s or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1630 are located on separate data processing systems and communicate via network devices accessible through the host interface 1632. In at least one embodiment, the GPU link 1640 may be configured to enable connectivity to a host processor in addition to, or as an alternative to, the host interface 1632. In at least one embodiment, the GPGPU 1630 may be configured to run CUDA programs. 【0128】 Figure 17A shows a parallel processor 1700 according to at least one embodiment. In at least one embodiment, various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit ("ASIC"), or an FPGA. 【0129】 In at least one embodiment, the parallel processor 1700 includes a parallel processing unit 1702. In at least one embodiment, the parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of the parallel processing unit 1702. In at least one embodiment, the I / O unit 1704 may be directly connected to other devices. In at least one embodiment, the I / O unit 1704 connects to other devices via the use of a hub or switch interface, such as a memory hub 1705. In at least one embodiment, the connection between the memory hub 1705 and the I / O unit 1704 forms a communication link. In at least one embodiment, the I / O unit 1704 connects to a host interface 1706 and a memory crossbar 1716, the host interface 1706 receiving commands intended to perform processing operations and the memory crossbar 1716 receiving commands intended to perform memory operations. 【0130】 In at least one embodiment, when the host interface 1706 receives a command buffer via the I / O unit 1704, the host interface 1706 can direct work operations to the front end 1708 to execute those commands. In at least one embodiment, the front end 1708 is coupled with a scheduler 1710, which is configured to distribute commands or other work items to the processing array 1712. In at least one embodiment, the scheduler 1710 ensures that the processing array 1712 is properly configured and enabled before tasks are distributed to the processing array 1712. In at least one embodiment, the scheduler 1710 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, enabling rapid preemption and context switching of threads running on the processing array 1712. In at least one embodiment, host software can prove workloads for scheduling on the processing array 1712 via one of several graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 1712 by scheduler 1710 logic within a microcontroller, including the scheduler 1710. 【0131】 In at least one embodiment, the processing array 1712 may contain up to "N" clusters (e.g., cluster 1714A, cluster 1714B to cluster 1714N). In at least one embodiment, each cluster 1714A to 1714N of the processing array 1712 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1710 may allocate work to clusters 1714A to 1714N of the processing array 1712 using various scheduling and / or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1710 or partially assisted by compiler logic during the compilation of program logic configured for execution by the processing array 1712. In at least one embodiment, different clusters 1714A to 1714N of the processing array 1712 may be allocated to process different types of programs or to perform different types of computations. 【0132】 In at least one embodiment, the processing array 1712 may be configured to perform various types of parallel processing operations. In at least one embodiment, the processing array 1712 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, the processing array 1712 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations including physical operations, and performing data transformations. 【0133】 In at least one embodiment, the processing array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing array 1712 may include, but is not limited to, additional logic to support the execution of such graphics processing operations, including texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing array 1712 may be configured to execute graphics processing-related shader programs, such as vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1702 may transfer data from system memory via the I / O unit 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory. 【0134】 In at least one embodiment, when the parallel processing unit 1702 is used to perform graphics processing, the scheduler 1710 may be configured to divide the processing workload into tasks of approximately equal size in order to better enable the distribution of graphics processing operations across multiple clusters 1714A to 1714N of the processing array 1712. In at least one embodiment, the parts of the processing array 1712 may be configured to perform different types of processing. For example, in at least one embodiment, to produce a rendered image for display, a first part may be configured to perform vertex shading and topology generation, a second part may be configured to perform tessellation and geometry shading, and a third part may be configured to perform pixel shading or other screen-space operations. In at least one embodiment, intermediate data produced by one or more of the clusters 1714A to 1714N may be stored in a buffer to enable the intermediate data to be transmitted between clusters 1714A to 1714N for further processing. 【0135】 In at least one embodiment, the processing array 1712 may receive processing tasks to be executed via a scheduler 1710, which receives commands defining the processing tasks from a front-end 1708. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program should be executed). In at least one embodiment, the scheduler 1710 may be configured to fetch the index corresponding to the task or to receive the index from the front-end 1708. In at least one embodiment, the front-end 1708 may be configured to ensure that the processing array 1712 is configured to a valid state before the workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is started. 【0136】 In at least one embodiment, each of one or more instances of the parallel processing unit 1702 can be coupled to a parallel processor memory 1722. In at least one embodiment, the parallel processor memory 1722 can be accessed via a memory crossbar 1716, which can receive memory requests from the processing array 1712 and the I / O unit 1704. In at least one embodiment, the memory crossbar 1716 can access the parallel processor memory 1722 via a memory interface 1718. In at least one embodiment, the memory interface 1718 can include a plurality of partition units (for example, partition unit 1720A, partition units 1720B to 1720N), each of which can be coupled to a portion of the parallel processor memory 1722 (for example, a memory unit). In at least one embodiment, the number of partition units 1720A to 1720N is configured to be equal to the number of memory units, such that the first partition unit 1720A has a corresponding first memory unit 1724A, the second partition unit 1720B has a corresponding memory unit 1724B, and the nth partition unit 1720N has a corresponding nth memory unit 1724N. In at least one embodiment, the number of partition units 1720A to 1720N may not be equal to the number of memory devices. 【0137】 In at least one embodiment, memory units 1724A-1724N may include various types of memory devices, including DRAM or graphics random access memory, such as SGRAM including GDDR memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory ("HBM"). In at least one embodiment, to efficiently use the available bandwidth of parallel processor memory 1722, render targets such as frame buffers or texture maps may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each render target in parallel. In at least one embodiment, local instances of parallel processor memory 1722 may be excluded to favor a unified memory design that utilizes system memory in conjunction with local cache memory. 【0138】 In at least one embodiment, any one of the clusters 1714A to 1714N of the processing array 1712 can process data that will be written to any of the memory units 1724A to 1724N in the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 may be configured to forward the output of each cluster 1714A to 1714N to any partition unit 1720A to 1720N that can perform additional processing operations on the output, or to another cluster 1714A to 1714N. In at least one embodiment, each cluster 1714A to 1714N can communicate with the memory interface 1718 through the memory crossbar 1716 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 1716 has connections to a memory interface 1718 for communicating with the I / O unit 1704, as well as to a local instance of the parallel processor memory 1722, which allows processing units in different clusters 1714A-1714N to communicate with system memory or other memory that is not local to the parallel processing unit 1702. In at least one embodiment, the memory crossbar 1716 can use virtual channels to isolate traffic streams between clusters 1714A-1714N and partition units 1720A-1720N. 【0139】 In at least one embodiment, multiple instances of the parallel processing unit 1702 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1702 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1702 may include higher-precision floating-point units than other instances. In at least one embodiment, a system incorporating one or more instances of the parallel processing unit 1702 or parallel processor 1700 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems. 【0140】 Figure 17B shows a processing cluster 1794 according to at least one embodiment. In at least one embodiment, processing cluster 1794 is contained within a parallel processing unit. In at least one embodiment, processing cluster 1794 is one of the processing clusters 1714A to 1714N in Figure 17. In at least one embodiment, processing cluster 1794 may be configured to run many threads in parallel, the term “thread” refers to a particular instance of a program running on a particular set of input data. In at least one embodiment, a single instruction, multiple data ("SIMD") instruction issuing technique is used to support the parallel execution of many threads without providing multiple independent instruction units. In at least one embodiment, a single instruction, multiple thread ("SIMT") technique is used to support the parallel execution of many threads with a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster 1794. 【0141】 In at least one embodiment, the operation of the processing cluster 1794 may be controlled via a pipeline manager 1732 that distributes processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 receives instructions from the scheduler 1710 in Figure 17 and manages the execution of those instructions via the graphics multiprocessor 1734 and / or texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 1794. In at least one embodiment, one or more instances of the graphics multiprocessor 1734 may be included within the processing cluster 1794. In at least one embodiment, the graphics multiprocessor 1734 may process data, and a data crossbar 1740 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1732 can facilitate the distribution of processed data by specifying destinations for the processed data that will be distributed via the data crossbar 1740. 【0142】 In at least one embodiment, each graphics multiprocessor 1734 within the processing cluster 1794 may contain an identical set of function execution logic (e.g., arithmetic logic units, load / store units ("LSU"), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner in which a new instruction can be issued before the previous instruction is completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and the computation of various algebraic functions. In at least one embodiment, the same function unit hardware may be utilized to perform different operations, and any combination of function units may exist. 【0143】 In at least one embodiment, instructions sent to processing cluster 1794 constitute a thread. In at least one embodiment, a set of threads running across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program for different input data. In at least one embodiment, each thread in a thread group may be assigned to a different processing engine in the graphics multiprocessor 1734. In at least one embodiment, a thread group may contain fewer threads than the number of processing engines in the graphics multiprocessor 1734. In at least one embodiment, when a thread group contains fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. In at least one embodiment, a thread group may also contain more threads than the number of processing engines in the graphics multiprocessor 1734. In at least one embodiment, when a thread group contains more threads than the number of processing engines in the graphics multiprocessor 1734, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may run simultaneously on the graphics multiprocessor 1734. 【0144】 In at least one embodiment, the graphics multiprocessor 1734 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1734 may abandon its internal cache and use cache memory in the processing cluster 1794 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 also has access to a Level 2 ("L2") cache in a partition unit (e.g., partition units 1720A-1720N in Figure 17A), and these L2 caches may be shared among all processing clusters 1794 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1734 may also have access to off-chip global memory, which may include one or more of the local parallel processor memory and / or system memory. In at least one embodiment, any memory outside the parallel processing unit 1702 may be used as global memory. In at least one embodiment, the processing cluster 1794 includes multiple instances of a graphics multiprocessor 1734, the graphics multiprocessor 1734 can share common instructions and data, and the common instructions and data can be stored in an L1 cache 1748. 【0145】 In at least one embodiment, each processing cluster 1794 may include an MMU 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1745 may reside within the memory interface 1718 in Figure 17. In at least one embodiment, the MMU 1745 includes a set of page table entries ("PTEs") used to map virtual addresses to physical addresses of tiles and optionally cache line indices. In at least one embodiment, the MMU 1745 may include an address translation lookaside buffer ("TLB") or cache, which may reside within the graphics multiprocessor 1734 or the L1 cache 1748 or the processing cluster 1794. In at least one embodiment, physical addresses are processed to distribute surface data access locality and enable efficient request interleaving between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or a miss. 【0146】 In at least one embodiment, the processing cluster 1794 may be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734 and, if necessary, fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1734 outputs the processed tasks to a data crossbar 1740 to provide the processed tasks to another processing cluster 1794 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1716. In at least one embodiment, a pre-raster operation unit ("pre-ROP") 1742 is configured to receive data from a graphics multiprocessor 1734 and direct the data to a ROP unit, which may be located with partition units as described herein (for example, partition units 1720A-1720N in Figure 17). In at least one embodiment, the pre-ROP 1742 can perform optimizations for color blending, organize pixel color data, and perform address translation. 【0147】 Figure 17C shows a graphics multiprocessor 1796 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 1796 is the graphics multiprocessor 1734 in Figure 17B. In at least one embodiment, the graphics multiprocessor 1796 is coupled with a pipeline manager 1732 of the processing cluster 1794. In at least one embodiment, the graphics multiprocessor 1796 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more GPGPU cores 1762, and one or more LSUs 1766. The GPGPU cores 1762 and LSUs 1766 are coupled with cache memory 1772 and shared memory 1770 via a memory and cache interconnect 1768. 【0148】 In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, the instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In at least one embodiment, the instruction unit 1754 can dispatch the instructions as a thread group (e.g., a warp), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 1762. In at least one embodiment, the instructions can access either the local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 may be used to translate an address in the unified address space to a separate memory address that can be accessed by the LSU 1766. 【0149】 In at least one embodiment, the register file 1758 provides a set of registers to the functional units of the graphics multiprocessor 1796. In at least one embodiment, the register file 1758 provides temporary storage for operands connected to the data paths of the functional units of the graphics multiprocessor 1796 (e.g., GPGPU core 1762, LSU 1766). In at least one embodiment, the register file 1758 is divided among the functional units such that each functional unit is allocated a dedicated portion of the register file 1758. In at least one embodiment, the register file 1758 is divided among different thread groups being executed by the graphics multiprocessor 1796. 【0150】 In at least one embodiment, each GPGPU core 1762 may include an FPU and / or an integer ALU used to execute instructions of the graphics multiprocessor 1796. The GPGPU cores 1762 may have a similar architecture or a different architecture. In at least one embodiment, a first part of the GPGPU core 1762 includes a single-precision FPU and an integer ALU, and a second part of the GPGPU core 1762 includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1796 may additionally include one or more fixed-function units or special-function units for performing specific functions such as rectangular copy operations or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1762 may also include fixed or special-function logic. 【0151】 In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction for multiple sets of data. In at least one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core 1762 may be generated at compile time by the shader compiler or automatically generated when running a program written and compiled for a single program multiple data ("SPMD") or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operation may be executed in parallel via a single SIMD8 logic unit. 【0152】 In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network connecting each functional unit of the graphics multiprocessor 1796 to the register file 1758 and shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a crossbar interconnect that enables the LSU 1766 to implement load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 can operate at the same frequency as the GPGPU core 1762, and therefore data transfer between the GPGPU core 1762 and the register file 1758 has very low latency. In at least one embodiment, the shared memory 1770 may be used to enable communication between threads running on functional units within the graphics multiprocessor 1796. In at least one embodiment, the cache memory 1772 may be used as a data cache to cache texture data communicated between functional units and texture unit 1736, for example. In at least one embodiment, shared memory 1770 may also be used as a cached managed program. In at least one embodiment, a thread running on the GPGPU core 1762 may programmatically store data in shared memory in addition to automatically cached data stored in cache memory 1772. 【0153】 In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to a host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated as a core on the same package or chip and communicatively coupled to the core via a processor bus / interconnection located within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuit elements / logic to efficiently process these commands / instructions. 【0154】 Figure 18 shows a graphics processor 1800 according to at least one embodiment. In at least one embodiment, the graphics processor 1800 includes a ring interconnect 1802, a pipeline front end 1804, a media engine 1837, and graphics cores 1880A to 1880N. In at least one embodiment, the ring interconnect 1802 connects the graphics processor 1800 to other graphics processors or other processing units including one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1800 is one of many processors incorporated within a multicore processing system. 【0155】 In at least one embodiment, the graphics processor 1800 receives batches of commands via a ring interconnect 1802. In at least one embodiment, incoming commands are interpreted by a command streamer 1803 in a pipeline front end 1804. In at least one embodiment, the graphics processor 1800 includes scalable execution logic for performing 3D geometry processing and media processing via one or more graphics cores 1880A-1880N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1803 feeds the commands to a geometry pipeline 1836. In at least one embodiment, for at least some media processing commands, the command streamer 1803 feeds the commands to a video front end 1834, which then couples with a media engine 1837. In at least one embodiment, the media engine 1837 includes a Video Quality Engine ("VQE") 1830 for video and image post-processing and a multi-format encode / decode ("MFX") engine 1833 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1836 and the media engine 1837 each generate execution threads for thread execution resources provided by at least one graphics core 1880A. 【0156】 In at least one embodiment, the graphics processor 1800 includes a scalable thread execution resource featuring modular graphics cores 1880A to 1880N (sometimes called core slices), each having multiple subcores 1850A to 550N, 1860A to 1860N (sometimes called core sub-slices). In at least one embodiment, the graphics processor 1800 may have any number of graphics cores 1880A to 1880N. In at least one embodiment, the graphics processor 1800 includes a graphics core 1880A having at least a first subcore 1850A and a second subcore 1860A. In at least one embodiment, the graphics processor 1800 is a low-power processor having a single subcore (e.g., subcore 1850A). In at least one embodiment, the graphics processor 1800 includes a plurality of graphics cores 1880A to 1880N, each including a first set of subcores 1850A to 1850N and a second set of subcores 1860A to 1860N. In at least one embodiment, each subcore in the first set of subcores 1850A to 1850N includes at least a first set of execution units ("EUs") 1852A to 1852N and media / texture samplers 1854A to 1854N. In at least one embodiment, each subcore in the second set of subcores 1860A to 1860N includes at least a second set of execution units 1862A to 1862N and samplers 1864A to 1864N. In at least one embodiment, each sub-core 1850A-1850N, 1860A-1860N shares a set of shared resources 1870A-1870N. In at least one embodiment, the shared resource 1870 includes shared cache memory and pixel operation logic. 【0157】 Figure 19 shows a processor 1900 according to at least one embodiment. In at least one embodiment, the processor 1900 may include, but is not limited to, logic circuits for executing instructions. In at least one embodiment, the processor 1900 may execute instructions including x86 instructions, AMR instructions, special instructions for ASICs, etc. In at least one embodiment, the processor 1910 may include registers for storing packed data, such as 64-bit wide MMX registers in a microprocessor enabled by MMX™ technology from Intel Corporation, Santa Clara, California. In at least one embodiment, MMX registers available in both integer and floating-point formats may operate with packed data elements accompanied by SIMD and streaming SIMD extension ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher technologies (collectively referred to as "SSEx") may hold such packed data operands. In at least one embodiment, the processor 1910 may implement instructions to accelerate the CUDA program. 【0158】 In at least one embodiment, the processor 1900 includes an in-order front-end ("front-end") 1901 for fetching instructions to be executed and preparing instructions to be used later in the processor pipeline. In at least one embodiment, the front-end 1901 may include several units. In at least one embodiment, an instruction prefetcher 1926 fetches instructions from memory and feeds the instructions to an instruction decoder 1928, which decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 1928 decodes the received instruction into one or more operations called "microinstructions" or "microoperations" (also called "microops" or "uops") for execution. In at least one embodiment, the instruction decoder 1928 parses the instruction into opcodes and corresponding data and control fields that can be used by the microarchitecture to perform the operation. In at least one embodiment, the trace cache 1930 may assemble the decoded uops into a program-order sequence or trace in the uop queue 1934 for execution. In at least one embodiment, when the trace cache 1930 encounters a complex instruction, the microcode ROM 1932 provides the uops necessary to complete the operation. 【0159】 In at least one embodiment, some instructions can be converted to a single micro-op, while others require several micro-ops to complete the entire operation. In at least one embodiment, if five or more micro-ops are required to complete the instruction, the instruction decoder 1928 may access the microcode ROM 1932 to execute the instruction. In at least one embodiment, an instruction can be decoded into a small number of micro-ops for processing in the instruction decoder 1928. In at least one embodiment, if several micro-ops are required to accomplish the operation, the instruction can be stored in the microcode ROM 1932. In at least one embodiment, the trace cache 1930 refers to the entry-point programmable logic array ("PLA") to determine the correct microinstruction pointer for reading the microcode sequence in order to complete one or more instructions from the microcode ROM 1932. In at least one embodiment, after the microcode ROM 1932 has finished sequencing the micro-ops for the instructions, the machine's front-end 1901 may resume fetching the micro-ops from the trace cache 1930. 【0160】 In at least one embodiment, the out-of-order execution engine ("out-of-order engine") 1903 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has several buffers to smooth and reorder the flow of instructions in order to optimize performance as instructions move down the pipeline and are scheduled for execution. The out-of-order execution engine 1903 includes, but is not limited to, an allocator / register renamer 1940, a memory uop queue 1942, an integer / floating-point uop queue 1944, a memory scheduler 1946, a fast scheduler 1902, a slow / general-purpose floating-point scheduler ("slow / general-purpose FP (floating point) scheduler") 1904, and a simple floating-point scheduler ("simple FP scheduler") 1906. In at least one embodiment, the fast scheduler 1902, the slow / general-purpose floating-point scheduler 1904, and the simple floating-point scheduler 1906 are collectively referred to herein as "uop schedulers 1902, 1904, and 1906." The allocator / register renamer 1940 allocates the machine buffers and resources that each uop needs to run. In at least one embodiment, the allocator / register renamer 1940 renames logical registers upon entry into the register file. In at least one embodiment, the allocator / register renamer 1940 also allocates entries for each uop in one of two uop queues, namely the memory uop queue 1942 for memory operations and the integer / floating-point uop queue 1944 for non-memory operations, prior to the memory scheduler 1946 and the uop schedulers 1902, 1904, 1906. In at least one embodiment, the uop schedulers 1902, 1904, 1906 determine when a uop is ready to execute based on whether their dependent input register operand sources are prepared and the availability of execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 1902 of at least one embodiment may schedule every half of the main clock cycle, while the slow / general-purpose floating-point scheduler 1904 and the simple floating-point scheduler 1906 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 1902, 1904, and 1906 arbitrate dispatch ports to schedule uops for execution. 【0161】 In at least one embodiment, execution block 1911 includes, but is not limited to, an integer register file / bypass network 1908, a floating-point register file / bypass network ("FP register file / bypass network") 1910, address generation units ("AGUs") 1912 and 1914, fast ALUs 1916 and 1918, slow ALU 1920, a floating-point ALU ("FP") 1922, and a floating-point move unit ("FP move") 1924. In at least one embodiment, the integer register file / bypass network 1908 and the floating-point register file / bypass network 1910 are also referred to herein as "register files 1908, 1910". In at least one embodiment, AGUs 1912 and 1914, high-speed ALUs 1916 and 1918, low-speed ALU 1920, floating-point ALU 1922, and floating-point movement unit 1924 are also referred to herein as “execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924”. In at least one embodiment, the execution block may include, but is not limited to, any number and type of register files (including zeros), bypass networks, address generation units, and execution units in any combination. 【0162】 In at least one embodiment, register files 1908 and 1910 may be located between the uop schedulers 1902, 1904, and 1906 and the execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, the integer register file / bypass network 1908 performs integer arithmetic. In at least one embodiment, the floating-point register file / bypass network 1910 performs floating-point arithmetic. In at least one embodiment, each of the register files 1908 and 1910 may include, but not limited to, a bypass network that can bypass or forward recently completed results that have not yet been written to the register file to a new dependent uop. In at least one embodiment, the register files 1908 and 1910 may communicate data with each other. In at least one embodiment, the integer register file / bypass network 1908 may include, but not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, since floating-point instructions typically have operands of 64 to 128 bits in width, the floating-point register file / bypass network 1910 may include, but not limited to, 128-bit wide entries. 【0163】 In at least one embodiment, execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924 may execute instructions. In at least one embodiment, register files 1908 and 1910 store integer and floating-point data operand values ​​that microinstructions must execute. In at least one embodiment, processor 1900 may include, but not limited to, any number and combination of execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, floating-point ALU 1922 and floating-point movement unit 1924 may perform floating-point, MMX, SIMD, AVX, and SSE, or other operations. In at least one embodiment, the floating-point ALU 1922 may include, but is not limited to, 64-bit floating-point dividers for performing division, square root, and remainder micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 1916 and 1918. In at least one embodiment, the high-speed ALUs 1916 and 1918 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the slow ALU 1920 may include, but is not limited to, integer execution hardware for high-latency types of operations such as multipliers, shifts, flag logic, and branching, so that most complex integer operations are passed to the slow ALU 1920. In at least one embodiment, memory load / store operations may be performed by the ALUs 1912 and 1914. In at least one embodiment, the high-speed ALU 1916, high-speed ALU 1918, and low-speed ALU 1920 may perform integer arithmetic with 64-bit data operands. In at least one embodiment, the high-speed ALU 1916, high-speed ALU 1918, and low-speed ALU 1920 may be implemented to support various data bit sizes, including 16, 32, 128, 256, and so on. In at least one embodiment, the floating-point ALU 1922 and floating-point movement unit 1924 may be implemented to support various operands with various bit widths.In at least one embodiment, the floating-point ALU 1922 and the floating-point movement unit 1924 may operate with 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions. 【0164】 In at least one embodiment, the uop schedulers 1902, 1904, and 1906 dispatch dependent operations before the parent load has finished executing. In at least one embodiment, since uops may be speculatively scheduled and executed in processor 1900, processor 1900 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be ongoing dependent operations in the pipeline that have passed the scheduler with temporarily inaccurate data. In at least one embodiment, a replay mechanism tracks and redelivers instructions that use inaccurate data. In at least one embodiment, dependent operations may need to be replayed, allowing independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations. 【0165】 In at least one embodiment, the term “register” may refer to an onboard processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be something that can be accessed from outside the processor (from the programmer’s perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuit elements within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, an integer register stores 32-bit integer data. The register file in at least one embodiment also includes eight multimedia SIMD registers for packed data. 【0166】 Figure 20 shows a processor 2000 according to at least one embodiment. In at least one embodiment, the processor 2000 includes, but is not limited to, one or more processor cores ("cores") 2002A to 2002N, an integrated memory controller 2014, and an integrated graphics processor 2008. In at least one embodiment, the processor 2000 may include additional cores up to additional processor cores 2002N, represented by dashed boxes. In at least one embodiment, each of the processor cores 2002A to 2002N includes one or more internal cache units 2004A to 2004N. In at least one embodiment, each processor core also has access to one or more shared cache units 2006. 【0167】 In at least one embodiment, the internal cache units 2004A–2004N and the shared cache unit 2006 represent the cache memory hierarchy within the processor 2000. In at least one embodiment, the cache memory units 2004A–2004N may include at least one level of instruction and data cache within each processor core, and one or more levels of shared intermediate level caches such as L2, L3, level 4 ("L4"), or other levels of cache, where the highest level cache prior to external memory is classified as LLC. In at least one embodiment, cache coherency logic maintains coherency among the various cache units 2006 and 2004A–2004N. 【0168】 In at least one embodiment, the processor 2000 may also include a set of one or more bus controller units 2016 and a system agent core 2010. In at least one embodiment, one or more bus controller units 2016 manage a set of peripheral buses, such as one or more PCI or PCI Express buses. In at least one embodiment, the system agent core 2010 provides management functionality for various processor components. In at least one embodiment, the system agent core 2010 includes one or more integrated memory controllers 2014 for managing access to various external memory devices (not shown). 【0169】 In at least one embodiment, one or more of the processor cores 2002A to 2002N include support for simultaneous multithreading. In at least one embodiment, the system agent core 2010 includes components for coordinating and operating the processor cores 2002A to 2002N during multithreaded processing. In at least one embodiment, the system agent core 2010 may additionally include a power control unit ("PCU"), the PCU including logic and components for regulating the power states of one or more of the processor cores 2002A to 2002N and the graphics processor 2008. 【0170】 In at least one embodiment, the processor 2000 additionally includes a graphics processor 2008 for performing graphics processing operations. In at least one embodiment, the graphics processor 2008 is coupled with a system agent core 2010 which includes a shared cache unit 2006 and one or more integrated memory controllers 2014. In at least one embodiment, the system agent core 2010 also includes a display controller 2011 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2011 may also be a separate module coupled with the graphics processor 2008 via at least one interconnection, or it may be incorporated within the graphics processor 2008. 【0171】 In at least one embodiment, a ring-based interconnect unit 2012 is used to connect the internal components of the processor 2000. In at least one embodiment, alternative interconnect units such as point-to-point interconnects, switching interconnects, or other techniques may be used. In at least one embodiment, the graphics processor 2008 is connected to the ring interconnect 2012 via an I / O link 2013. 【0172】 In at least one embodiment, I / O link 2013 represents at least one of several types of I / O interconnects, including on-package I / O interconnects that facilitate communication between various processor components and a high-performance embedded memory module 2018, such as an eDRAM module. In at least one embodiment, each of the processor cores 2002A to 2002N and the graphics processor 2008 use the embedded memory module 2018 as a shared LLC. 【0173】 In at least one embodiment, the processor cores 2002A-2002N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2002A-2002N are heterogeneous in terms of ISA, where one or more of the processor cores 2002A-2002N execute a common instruction set, and one or more other cores of the processor cores 2002A-2002N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2002A-2002N are heterogeneous in terms of microarchitecture, where one or more cores with relatively high power consumption are coupled with one or more cores with lower power consumption. In at least one embodiment, the processor 2000 may be implemented on one or more chips or as an SoC integrated circuit. 【0174】 Figure 21 shows a graphics processor core 2100 according to at least one embodiment described. In at least one embodiment, the graphics processor core 2100 is contained within a graphics core array. In at least one embodiment, the graphics processor core 2100, sometimes referred to as a core slice, may be one or more graphics cores in a modular graphics processor. In at least one embodiment, the graphics processor core 2100 is an example of one graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2100 may include a fixed-function block 2130 coupled with a plurality of sub-cores 2101A to 2101F, also referred to as sub-slices, which include modular blocks of general-purpose and fixed-function logic. 【0175】 In at least one embodiment, the fixed-function block 2130 includes a geometry / fixed-function pipeline 2136 which may be shared by all subcores in the graphics processor 2100, for example, in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2136 includes a 3D fixed-function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer. 【0176】 In at least one embodiment, the fixed-function block 2130 also includes a graphics SoC interface 2137, a graphics microcontroller 2138, and a media pipeline 2139. The graphics SoC interface 2137 provides an interface between the graphics core 2100 and other processor cores within the SoC integrated circuit. In at least one embodiment, the graphics microcontroller 2138 is a programmable sub-processor configurable to manage various functions of the graphics processor 2100, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2139 includes logic to facilitate decoding, encoding, preprocessing, and / or postprocessing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2139 implements media operations via requests to compute logic or sampling logic within sub-cores 2101-2101F. 【0177】 In at least one embodiment, the SoC interface 2137 enables the graphics core 2100 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, the other components within the SoC include memory hierarchy elements such as shared LLC memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, the SoC interface 2137 can also enable communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enable and / or implement the use of a global memory atomic that may be shared between the graphics core 2100 and the CPU within the SoC. In at least one embodiment, the SoC interface 2137 can also implement power management controls for the graphics core 2100 and enable facilitating between the clock domain of the graphics core 2100 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2137 enables the reception of command buffers from a command streamer and a global thread dispatcher configured to provide commands and instructions to each of the one or more graphics cores in the graphics processor. In at least one embodiment, commands and instructions can be dispatched to the media pipeline 2139 when media operations should be performed, or to the geometry and fixed-function pipelines (e.g., geometry and fixed-function pipeline 2136, geometry and fixed-function pipeline 2114) when graphics processing operations should be performed. 【0178】 In at least one embodiment, the graphics microcontroller 2138 may be configured to perform various scheduling and management tasks for the graphics core 2100. In at least one embodiment, the graphics microcontroller 2138 may perform graphics and / or calculate workload scheduling for various graphics parallel engines in the execution unit (EU) arrays 2102A-2102F and 2104A-2104F within the sub-cores 2101A-2101F. In at least one embodiment, host software running on the CPU core of the SoC, including the graphics core 2100, may submit a workload to one of several graphics processor doorbells, which then invokes scheduling operations for the appropriate graphics engine. In at least one embodiment, the scheduling operation includes determining which workload should run next, submitting the workload to a command streamer, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, the graphics microcontroller 2138 can also facilitate a low-power or idle state for the graphics core 2100, providing the graphics core 2100 with the ability to save and restore registers within the graphics core 2100 during transitions to low-power states, independently of the operating system and / or graphics driver software on the system. 【0179】 In at least one embodiment, the graphics core 2100 may have up to N modular subcores, more or less than the subcores 2101A-2101F shown. For each set of N subcores, in at least one embodiment, the graphics core 2100 may also include shared function logic 2110, shared and / or cache memory 2112, geometry / fixed function pipeline 2114, and additional fixed function logic 2116 for accelerating various graphics and calculating processing operations. In at least one embodiment, the shared function logic 2110 may include logic units (e.g., sampler, mathematical, and / or inter-thread communication logic) that can be shared by each of the N subcores in the graphics core 2100. The shared and / or cache memory 2112 may be LLC for the N subcores 2101A-2101F in the graphics core 2100, and may also function as shared memory accessible by multiple subcores. In at least one embodiment, the geometry / fixed function pipeline 2114 may be included in place of the geometry / fixed function pipeline 2136 within the fixed function block 2130 and may include the same or similar logical units. 【0180】 In at least one embodiment, the graphics core 2100 includes an additional fixed-function logic 2116 which can include various fixed-function acceleration logic for use by the graphics core 2100. In at least one embodiment, the additional fixed-function logic 2116 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines: a full geometry pipeline in geometry / fixed-function pipeline 2116, 2136, and a cull pipeline, the cull pipeline being an additional geometry pipeline which may be included within the additional fixed-function logic 2116. In at least one embodiment, the cull pipeline is a reduced version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can run different instances of the application, each instance having a separate context. In at least one embodiment, position-only shading can hide long cull runs of truncated triangles, which allows shading to complete faster in some instances. For example, in at least one embodiment, the sorting pipeline fetches and shades the vertex position attributes without performing rasterization and rendering of pixels into a frame buffer, so that the sorting pipeline logic within the additional fixed-function logic 2116 can run the position shader in parallel with the main application and produce critical results faster overall than the full pipeline. In at least one embodiment, the sorting pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are sorted or not. In at least one embodiment, the full pipeline (sometimes called the replay pipeline in this instance) can consume the visibility information to skip the sorted triangles and shade only the visible triangles, which are then passed to the rasterization phase. 【0181】 In at least one embodiment, additional fixed-function logic 2116 may also include general-purpose processing acceleration logic, such as fixed-function matrix multiplication logic, to accelerate CUDA programs. 【0182】 In at least one embodiment, each graphics sub-core 2101A-2101F includes a set of execution resources which may be used to perform graphics operations, media operations, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics sub-cores 2101A-2101F include a plurality of EU arrays 2102A-2102F, 2104A-2104F, thread dispatch and inter-thread communication ("TD / IC") logic 2103A-2103F, 3D (e.g., texture) samplers 2105A-2105F, media samplers 2106A-2106F, shader processors 2107A-2107F, and shared local memory ("SLM") 2108A-2108F. EU arrays 2102A-2102F and 2104A-2104F each include multiple execution units, which are GPGPUs capable of performing floating-point and integer / fixed-point logical operations in graphics operations, media operations, or compute operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2103A-2103F perform local thread dispatch and thread control operations for execution units within a subcore, facilitating communication between threads running on the execution units in the subcore. In at least one embodiment, 3D samplers 2105A-2105F can read texture or other 3D graphics-related data into memory. In at least one embodiment, the 3D sampler can read texture data in different ways based on a configured sample state and texture format associated with a given texture. In at least one embodiment, the media samplers 2106A to 2106F can perform similar reading operations based on the type and format associated with the media data.In at least one embodiment, each graphics sub-core 2101A-2101F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads running on the execution units within each of the sub-cores 2101A-2101F may utilize shared local memory 2108A-2108F within each sub-core to enable threads running within a thread group to run using a common pool of on-chip memory. 【0183】 Figure 22 shows a parallel processing unit ("PPU") 2200 according to at least one embodiment. In at least one embodiment, the PPU 2200 consists of machine-readable code that, when executed by the PPU 2200, causes the PPU 2200 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2200 is a multithreaded processor, which is implemented on one or more integrated circuit devices and utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also called machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by the PPU 2200. In at least one embodiment, the PPU2200 is a GPU configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device such as an LCD device. In at least one embodiment, the PPU2200 is used to perform calculations such as linear algebra and machine learning operations. Figure 22 shows an exemplary parallel processor for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture that may be implemented in at least one embodiment. 【0184】 In at least one embodiment, one or more PPUs 2200 are configured to accelerate high-performance computing ("HPC"), data center, and machine learning applications. In at least one embodiment, one or more PPUs 2200 are configured to accelerate CUDA programs. In at least one embodiment, the PPU 2200 includes, but is not limited to, an I / O unit 2206, a front-end unit 2210, a scheduler unit 2212, a work distribution unit 2214, a hub 2216, a crossbar ("X-bar") 2220, one or more general-purpose processing clusters ("GPC") 2218, and one or more partition units ("memory partition units") 2222. In at least one embodiment, the PPU 2200 is connected to a host processor or other PPU 2200 via one or more high-speed GPU interconnects ("GPU interconnects") 2208. In at least one embodiment, the PPU 2200 is connected to a host processor or other peripheral devices via a system bus or interconnect 2202. In at least one embodiment, the PPU 2200 is connected to local memory comprising one or more memory devices ("memory") 2204. In at least one embodiment, the memory devices 2204 include, but are not limited to, one or more dynamic random-access memory (DRAM) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high-bandwidth memory ("HBM") subsystem in which multiple DRAM dies are stacked within each device. 【0185】 In at least one embodiment, the high-speed GPU interconnect 2208 may refer to a wire-based multi-lane communication link, which is used by the system to scale and include one or more PPUs 2200 in combination with one or more CPUs, and supports cache coherence and CPU mastering between the PPUs 2200 and the CPUs. In at least one embodiment, data and / or commands are transmitted by the high-speed GPU interconnect 2208 through the hub 2216 to / from other units of the PPUs 2200, such as one or more copy engines, video encoders, video decoders, power management units, and other components that may not be explicitly shown in Figure 22. 【0186】 In at least one embodiment, the I / O unit 2206 is configured to send and receive communications (e.g., commands, data) from a host processor (not shown in Figure 22) via the system bus 2202. In at least one embodiment, the I / O unit 2206 communicates with the host processor directly via the system bus 2202 or through one or more intermediate devices such as a memory bridge. In at least one embodiment, the I / O unit 2206 may communicate with one or more other processors, such as one or more of the PPU 2200, via the system bus 2202. In at least one embodiment, the I / O unit 2206 implements a PCIe interface for communication via the PCIe bus. In at least one embodiment, the I / O unit 2206 implements an interface for communicating with external devices. 【0187】 In at least one embodiment, I / O unit 2206 decodes packets received via system bus 2202. In at least one embodiment, at least some packets represent commands configured to cause the PPU 2200 to perform various operations. In at least one embodiment, I / O unit 2206 transmits the decoded commands to various other units of the PPU 2200 specified by the commands. In at least one embodiment, the commands are transmitted to the front-end unit 2210 and / or to the hub 2216, or to one or more copy engines, video encoders, video decoders, power management units, etc. (not explicitly shown in Figure 22). In at least one embodiment, I / O unit 2206 is configured to route communication between and between various logical units of the PPU 2200. 【0188】 In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides the workload to the PPU 2200 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory accessible (e.g., readable / writable) by both the host processor and the PPU 2200, and the host interface unit may be configured to access the buffer in system memory connected to the system bus 2202 via memory requests sent by the I / O unit 2206 over the system bus 2202. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2200, thereby the front-end unit 2210 receives a pointer to one or more command streams, manages one or more command streams, reads commands from the command streams, and forwards the commands to various units of the PPU 2200. 【0189】 In at least one embodiment, the front-end unit 2210 is coupled to a scheduler unit 2212 that configures various GPCs 2218 to handle tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2212 is configured to track state information relating to various tasks managed by the scheduler unit 2212, which may indicate which of the GPCs 2218 a task is assigned to, whether the task is active or inactive, the priority level associated with the task, etc. In at least one embodiment, the scheduler unit 2212 manages the execution of multiple tasks on one or more of the GPCs 2218. 【0190】 In at least one embodiment, the scheduler unit 2212 is coupled to a work distribution unit 2214 configured to dispatch tasks for execution on the GPC 2218. In at least one embodiment, the work distribution unit 2214 tracks the number of scheduled tasks received from the scheduler unit 2212, and the work distribution unit 2214 manages a pending task pool and an active task pool for each of the GPCs 2218. In at least one embodiment, the pending task pool may have several slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 2218, and the active task pool may have several slots (e.g., 4 slots) for tasks being actively processed by the GPCs 2218, so that when one of the GPCs 2218 completes the execution of a task, that task is removed from the active task pool for the GPC 2218, and one of the other tasks from the pending task pool is selected and scheduled for execution on the GPC 2218. In at least one embodiment, if an active task is idle on GPC2218, such as while waiting for data dependencies to be resolved, the active task is removed from GPC2218 and returned to the pending task pool, during which time another task is selected from the pending task pool and scheduled for execution on GPC2218. 【0191】 In at least one embodiment, the work distribution unit 2214 communicates with one or more GPCs 2218 via the X-bar 2220. In at least one embodiment, the X-bar 2220 is an interconnection network that connects many units of the PPU 2200 to other units of the PPU 2200 and may be configured to connect the work distribution unit 2214 to a specific GPC 2218. In at least one embodiment, one or more other units of the PPU 2200 may also be connected to the X-bar 2220 via the hub 2216. 【0192】 In at least one embodiment, tasks are managed by a scheduler unit 2212 and dispatched to one of the GPCs 2218 by a work distribution unit 2214. The GPC 2218 is configured to process tasks and produce results. In at least one embodiment, the results may be consumed by other tasks within the GPC 2218, routed to a different GPC 2218 via the X-bar 2220, or stored in memory 2204. In at least one embodiment, the results may be written to memory 2204 via a partition unit 2222, which implements a memory interface for reading and writing data to and from memory 2204. In at least one embodiment, the results may be sent to another PPU 2204 or CPU via a high-speed GPU interconnect 2208. In at least one embodiment, the PPU 2200 includes, but is not limited to, U partition units 2222 equal to the number of separate individual memory devices 2204 coupled to the PPU 2200. 【0193】 In at least one embodiment, the host processor runs a driver kernel, which implements an Application Programming Interface ("API") that enables one or more applications running on the host processor to schedule their operations for execution on the PPU2200. In at least one embodiment, multiple compute applications run concurrently on the PPU2200, and the PPU2200 provides isolation, quality of service ("QoS"), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution on the PPU2200, and the driver kernel outputs the tasks to one or more streams being processed by the PPU2200. In at least one embodiment, each task comprises one or more groups of relational threads, which may be called warps. In at least one embodiment, a warp comprises multiple relational threads (e.g., 32 threads) that may run in parallel. In at least one embodiment, linked threads can refer to multiple threads that include instructions for performing tasks and exchange data through shared memory. 【0194】 Figure 23 shows a GPC2300 according to at least one embodiment. In at least one embodiment, the GPC2300 is the GPC2218 in Figure 22. In at least one embodiment, each GPC2300 includes, but is not limited to, several hardware units for processing tasks, and each GPC2300 includes, but is not limited to, a pipeline manager 2302, a pre-raster operation unit ("PROP") 2304, a raster engine 2308, a work distribution crossbar ("WDX") 2316, an MMU 2318, one or more data processing clusters ("DPC") 2306, and any preferred combination of parts. 【0195】 In at least one embodiment, the operation of the GPC2300 is controlled by a pipeline manager 2302. In at least one embodiment, the pipeline manager 2302 manages the configuration of one or more DPC2306 for handling tasks assigned to the GPC2300. In at least one embodiment, the pipeline manager 2302 configures at least one of the one or more DPC2306 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, the DPC2306 is configured to run a vertex shader program on a programmable streaming multiprocessor ("SM": streaming multiprocessor) 2314. In at least one embodiment, the pipeline manager 2302 is configured to route packets received from work distribution units to appropriate logical units within the GPC 2300, and in at least one embodiment, some packets may be routed to fixed-function hardware units and / or raster engine 2308 in PROP 2304, and other packets may be routed to DPC 2306 for processing by primitive engine 2312 or SM 2314. In at least one embodiment, the pipeline manager 2302 configures at least one of the DPC 2306 to implement a compute pipeline. In at least one embodiment, the pipeline manager 2302 configures at least one of the DPC 2306 to execute at least a portion of a CUDA program. 【0196】 In at least one embodiment, the PROP unit 2304 is configured to route data generated by the raster engine 2308 and DPC 2306 to raster operation ("ROP") units in partition units, such as the memory partition unit 2222, which is described in more detail above in conjunction with Figure 22. In at least one embodiment, the PROP unit 2304 is configured to perform tasks such as performing optimization for color blending, organizing pixel data, and performing address translation. In at least one embodiment, the raster engine 2308 includes, but is not limited to, several fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2308 includes, but is not limited to, a setup engine, a coarse raster engine, a sorting engine, a clipping engine, a fine raster engine, a tile merging engine, and any preferred combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates a plane equation related to the geometric primitives defined by the vertices, which is sent to a coarse raster engine to generate coverage information about the primitives (e.g., x, y coverage mask for tiles), the output of the coarse raster engine is sent to a sorting engine to sort out fragments related to primitives that have fallen into the z test, and the output is sent to a clipping engine to clip fragments that are outside the view frustum. In at least one embodiment, the fragments that have passed clipping and sorting are passed to a fine raster engine to generate attributes about the pixel fragments based on the plane equation generated by the setup engine. In at least one embodiment, the output of the raster engine 2308 contains fragments to be processed by any preferred entity, such as a fragment shader implemented within the DPC2306. 【0197】 In at least one embodiment, each DPC2306 contained within the GPC2300 includes, but is not limited to, an M-Pipe Controller ("MPC") 2310, a primitive engine 2312, one or more SM2314s, and any preferred combination thereof. In at least one embodiment, the MPC2310 controls the operation of the DPC2306 to route packets received from the pipeline manager 2302 to the appropriate unit in the DPC2306. In at least one embodiment, packets related to vertices may be routed to the primitive engine 2312, which is configured to fetch vertex attributes related to the vertices from memory, while packets related to shader programs may be sent to the SM2314. 【0198】 In at least one embodiment, the SM2314 includes a programmable streaming processor configured to handle tasks represented by several threads, but not limited to these. In at least one embodiment, the SM2314 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a particular group of threads concurrently, implementing a SIMD architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same set of instructions. In at least one embodiment, all threads in a group of threads execute the same instruction. In at least one embodiment, the SM2314 implements a SIMT architecture where each thread in a group of threads is configured to process a different set of data based on the same set of instructions, but individual threads in a group of threads are allowed to diverge during execution. In at least one embodiment, program counters, call stacks, and execution states are maintained for each warp to enable concurrent processing between warps and serial execution within warps when threads in a warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread to enable equal concurrent processing among all threads, within warps, and between warps. In at least one embodiment, the execution state is maintained for each individual thread, and threads executing the same instruction may converge and execute in parallel for better efficiency. At least one embodiment of the SM2314 is described in further detail in conjunction with Figure 24. 【0199】 In at least one embodiment, the MMU2318 provides an interface between the GPC2300 and a memory partition unit (for example, partition unit 2222 in Figure 22), and the MMU2318 provides virtual address-to-physical address translation, memory protection, and memory request arbitration. In at least one embodiment, the MMU2318 provides one or more translation lookaside buffers (TLBs) for performing virtual address-to-physical address translation in memory. 【0200】 Figure 24 shows a streaming multiprocessor ("SM") 2400 according to at least one embodiment. In at least one embodiment, the SM2400 is the SM2314 in Figure 23. In at least one embodiment, the SM2400 includes, but is not limited to, an instruction cache 2402, one or more scheduler units 2404, a register file 2408, one or more processing cores ("cores") 2410, one or more special function units ("SFUs") 2412, one or more LSUs 2414, an interconnect network 2416, a shared memory / L1 cache 2418, and any preferred combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on a GPC of parallel processing units (PPUs), each task is assigned to a specific data processing cluster (DPC) within the GPC, and if the task is related to a shader program, the task is assigned to one of the SM2400s. In at least one embodiment, a scheduler unit 2404 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to the SM2400s. In at least one embodiment, the scheduler unit 2404 schedules thread blocks for execution as warps of parallel threads, each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 2404 manages multiple different thread blocks, allocates warps to different thread blocks, and then dispatches instructions from multiple different interlocking groups to various functional units (e.g., processing core 2410, SFU 2412, and LSU 2414) during each clock cycle. 【0201】 In at least one embodiment, “dependency group” may refer to a programming model for organizing groups of communicating threads, and the programming model allows developers to express the granularity at which threads are communicating, enabling a richer and more efficient representation of parallel decomposition. In at least one embodiment, the dependent invocation API supports synchronization between thread blocks for the execution of parallel algorithms. In at least one embodiment, the API of the conventional programming model provides a single, simple construct for synchronizing dependent threads, namely a barrier across all threads in a thread block (e.g., the syncthreads() function). However, in at least one embodiment, the programmer may define groups of threads at a granularity smaller than a thread block and synchronize them within the defined group, enabling higher performance, design flexibility, and software reuse in the form of a functional interface across the collective group as a whole. In at least one embodiment, dependent groups allow programmers to explicitly define groups of threads at sub-block and multi-block granularity and perform collective actions such as synchronization for threads in the dependent group. In at least one embodiment, the sub-block granularity is as small as a single thread. In at least one embodiment, the programming model supports clean composition across software boundaries, thereby allowing libraries and utility functions to be safely synchronized within their local contexts without the need to make assumptions about convergence. In at least one embodiment, the interdependent group primitive enables new patterns of interdependent parallelism, including, but not limited to, producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire grid of thread blocks. 【0202】 In at least one embodiment, the dispatch unit 2406 is configured to send instructions to one or more of the functional units, and the scheduler unit 2404 includes, but is not limited to, two dispatch units 2406 that enable two different instructions from the same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit 2404 includes a single dispatch unit 2406 or an additional dispatch unit 2406. 【0203】 In at least one embodiment, each SM2400 includes a register file 2408 that provides a set of registers to the functional units of the SM2400, in at least one embodiment, but not limited to. In at least one embodiment, the register file 2408 is divided among the functional units such that each functional unit is allocated a dedicated portion of the register file 2408. In at least one embodiment, the register file 2408 is divided among different warps being executed by the SM2400, and the register file 2408 provides temporary storage for operands connected to the data paths of the functional units. In at least one embodiment, each SM2400 includes, but not limited to, a plurality of L processing cores 2410. In at least one embodiment, the SM2400 includes, but not limited to, a large number (e.g., 128 or more) individual processing cores 2410. In at least one embodiment, each processing core 2410 includes, but is not limited to, fully pipelining, single-precision, double-precision, and / or mixed-precision processing units, which include, but is not limited to, floating-point arithmetic logic units and integer arithmetic logic units. In at least one embodiment, the floating-point arithmetic logic units implement the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 2410 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores, and 8 tensor cores. 【0204】 In at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 2410. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4x4 matrix and performs a matrix multiply and accumulate operation D = A × B + C, where A, B, C, and D are 4x4 matrices. 【0205】 In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating-point matrices, and the addition matrices C and D are either 16-bit floating-point or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core operates with 16-bit floating-point input data with a 32-bit floating-point sum. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations, resulting in a full-precision product, which is then added using a 32-bit floating-point addition with other intermediate products for a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform much larger 2D or even higher-dimensional matrix operations built from these smaller elements. In at least one embodiment, APIs such as the CUDA-C++ API expose special matrix load, matrix multiplicative sum, and matrix store operations to efficiently use the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp-level interface assumes a 16x16 matrix that spans all 32 threads of the warp. 【0206】 In at least one embodiment, each SM2400 includes M SFU2412s that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFU2412 includes a tree traversal unit configured to traverse a hierarchical tree data structure (e.g.,). In at least one embodiment, the SFU2412 includes a texture unit configured to perform texture map filtering operations (e.g., texture map filtering). In at least one embodiment, the texture unit is configured to load a texture map (e.g., a 2D array of texels) from memory and sampled texture maps to produce sampled texture values ​​for use in a shader program executed by the SM2400. In at least one embodiment, the texture map is stored in shared memory / L1 cache 2418. In at least one embodiment, the texture unit implements texture operations such as filtering operations using mip maps (e.g., texture maps with different levels of detail). In at least one embodiment, each SM2400 includes, but is not limited to, two texture units. 【0207】 In at least one embodiment, each SM2400 includes, but is not limited to, N LSUs 2414 that implement load and store operations between the shared memory / L1 cache 2418 and the register file 2408. In at least one embodiment, each SM2400 includes, but is not limited to, an interconnection network 2416 that connects each of the functional units to the register file 2408 and connects the LSUs 2414 to the register file 2408 and the shared memory / L1 cache 2418. In at least one embodiment, the interconnection network 2416 may be a crossbar that connects any of the functional units to any of the registers in the register file 2408 and connects the LSUs 2414 to memory locations in the register file 2408 and the shared memory / L1 cache 2418. 【0208】 In at least one embodiment, the shared memory / L1 cache 2418 is an array of on-chip memory that enables data storage and communication between the SM2400 and the primitive engine and between threads in the SM2400. In at least one embodiment, the shared memory / L1 cache 2418 has a storage capacity of 128KB, but is not limited to, and lies on the path from the SM2400 to the partition unit. In at least one embodiment, the shared memory / L1 cache 2418 is used to cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 2418, the L2 cache, and the memory are auxiliary stores. 【0209】 In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used or made available as a cache by programs that do not use shared memory, such as when shared memory is configured to use half of the capacity and texture and load / store operations can use the remaining capacity. In at least one embodiment, integration within the shared memory / L1 cache 2418 allows the shared memory / L1 cache 2418 to function as a high-throughput tube for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration may be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a fixed-function GPU is bypassed to create a much simpler programming model. In at least one embodiment and in the general-purpose parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to the DPC. In at least one embodiment, a blocked thread runs the same program, uses a unique thread ID in the computation to ensure that each thread produces a unique result, executes the program using the SM2400, performs computations, communicates between threads using the shared memory / L1 cache 2418, and reads and writes global memory through the shared memory / L1 cache 2418 and the memory partition unit using the LSU2414. In at least one embodiment, when configured for general-purpose parallel computation, the SM2400 writes commands that the scheduler unit 2404 can use to start new work on the DPC. 【0210】 In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless handheld device), PDA, digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is embodied on a single semiconductor substrate. In at least one embodiment, the PPU is included in an SoC together with one or more other devices such as additional PPUs, memory, RISC CPU, MMU, digital-to-analog converter ("DAC"). 【0211】 In at least one embodiment, the PPU may be contained on a graphics card that includes one or more memory devices. In at least one embodiment, the graphics card may be configured to interface with a PCIe slot on the motherboard of a desktop computer. In at least one embodiment, the PPU may be an integrated GPU ("iGPU") contained within the chipset of the motherboard. 【0212】 Software constructs for general-purpose computing The following diagrams illustrate exemplary software constructs for implementing at least one embodiment, though they are not limiting. 【0213】 Figure 25 shows a software stack for a programming platform according to at least one embodiment. In at least one embodiment, the programming platform is a platform for leveraging hardware on a computing system to accelerate computational tasks. In at least one embodiment, the programming platform may be accessible to software developers through libraries, compiler directives, and / or extensions to programming languages. In at least one embodiment, the programming platform may be, but is not limited to, CUDA, Radeon Open Compute Platform (“ROCm”), OpenCL (OpenCL® is developed by the Khronos group), SYCL, or Intel One API. 【0214】 In at least one embodiment, the programming platform's software stack 2500 provides an execution environment for application 2501. In at least one embodiment, application 2501 may include any computer software that can be launched on the software stack 2500. In at least one embodiment, application 2501 may include, but is not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high-performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads. 【0215】 In at least one embodiment, application 2501 and software stack 2500 run on hardware 2507. In at least one embodiment, hardware 2507 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of compute devices that support programming platforms. In at least one embodiment, such as in the case of CUDA, software stack 2500 may be vendor-specific and compatible only with devices from a specific vendor (one or more). In at least one embodiment, such as in the case of OpenCL, software stack 2500 may be used with devices from different vendors. In at least one embodiment, hardware 2507 includes a host connected to another device that may be accessed to perform compute tasks via application programming interface ("API") calls. In at least one embodiment, the device in hardware 2507 may include, but is not limited to, a GPU, FPGA, AI engine, or other compute device (which may also include a CPU) and its memory, in contrast to the host in hardware 2507, which may include a CPU and its memory. 【0216】 In at least one embodiment, the software stack 2500 of the programming platform includes, but is not limited to, several libraries 2503, a runtime 2505, and a device kernel driver 2506. In at least one embodiment, each of the libraries 2503 may include data and programming code that can be used by computer programs and utilized during software development. In at least one embodiment, the library 2503 may include, but is not limited to, prewritten code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the library 2503 includes functionality optimized for execution on one or more types of devices. In at least one embodiment, the library 2503 may include, but is not limited to, functionality for performing mathematical, deep learning, and / or other types of operations on a device. In at least one embodiment, the library 2503 may relate to a corresponding API 2502 that includes one or more APIs that expose functionality implemented in the library 2503. 【0217】 In at least one embodiment, application 2501 is written as source code that is compiled into executable code, as will be described in more detail below in conjunction with Figures 30-32. In at least one embodiment, the executable code of application 2501 may run, at least partially, on an execution environment provided by the software stack 2500. In at least one embodiment, during the execution of application 2501, it may be possible to reach code that needs to run on the device, as opposed to the host. In at least one embodiment, in such a case, runtime 2505 may be called to load and start the code required on the device. In at least one embodiment, runtime 2505 may include any technically feasible runtime system capable of supporting the execution of application S01. 【0218】 In at least one embodiment, runtime 2505 is implemented as one or more runtime libraries relating to the corresponding APIs, indicated as API 2504 (one or more). In at least one embodiment, one or more of such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, copying device memory, and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for invoking functions on a device (sometimes called "kernels" when the functions are global functions callable from the host) and setting attribute values ​​in buffers maintained by runtime libraries for given functions to be executed on the device. 【0219】 In at least one embodiment, the runtime library and the corresponding API(s) 2504 may be implemented in any technically feasible manner. In at least one embodiment, some (or any number) APIs may expose a low-level set of functions for fine-grained control of the device, while other (or any number) APIs may expose a higher-level set of such functions. In at least one embodiment, high-level runtime APIs may be built on top of low-level APIs. In at least one embodiment, one or more of the runtime APIs may be language-specific APIs layered on top of language-independent runtime APIs. 【0220】 In at least one embodiment, the device kernel driver 2506 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 2506 may provide low-level functionality on which APIs and / or other software, such as API 2504, rely. In at least one embodiment, the device kernel driver 2506 may be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 2506 may compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (with caching of the compiled binary code), which is sometimes referred to as "finalizing" the code. In at least one embodiment, doing so may allow the finalized code to run on the target device, which may not have existed when the source code was first compiled into PTX code. Alternatively, in at least one embodiment, the device source code may be compiled into binary code offline without requiring the device kernel driver 2506 to compile the IR code at runtime. 【0221】 Figure 26 shows a CUDA implementation of the software stack 2500 of Figure 25 according to at least one embodiment. In at least one embodiment, the CUDA software stack 2600, from which application 2601 can be launched, includes a CUDA library 2603, a CUDA runtime 2605, a CUDA driver 2607, and a device kernel driver 2608. In at least one embodiment, the CUDA software stack 2600 runs on hardware 2609, which may include a GPU that supports CUDA and is developed by NVIDIA Corporation in Santa Clara, California. 【0222】 In at least one embodiment, application 2601, CUDA runtime 2605, and device kernel driver 2608 may implement functionality similar to that of application 2501, runtime 2505, and device kernel driver 2506, respectively, as described above in conjunction with Figure 25. In at least one embodiment, CUDA driver 2607 includes a library (libcuda.so) that implements the CUDA driver API 2606. In at least one embodiment, the CUDA driver API 2606 may expose functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability, but not limited to these functions. In at least one embodiment, the CUDA driver API 2606 differs from the CUDA runtime API 2604 in that it simplifies device code management by providing implicit initialization, context management (similar to a process), and module management (similar to a dynamically loaded library). In at least one embodiment, in contrast to the high-level CUDA runtime API 2604, the CUDA driver API 2606 is a low-level API that provides finer-grained control of the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 2606 may expose functionality for context management that is not exposed by the CUDA runtime API 2604. In at least one embodiment, the CUDA driver API 2606 is also language-independent and supports OpenCL, for example, in addition to the CUDA runtime API 2604. Furthermore, in at least one embodiment, the development library containing the CUDA runtime 2605 may be considered separate from the driver components, which include the user-mode CUDA driver 2607 and the kernel-mode device driver 2608 (sometimes referred to as the "display" driver). 【0223】 In at least one embodiment, the CUDA library 2603 may include, but is not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be used by parallel computing applications such as application 2601. In at least one embodiment, the CUDA library 2603 may include mathematical libraries such as the cuBLAS library, which is an implementation of Basic Linear Algebra Subprograms ("BLAS") for performing linear algebra operations; the cuFFT library for calculating the Fast Fourier Transform ("FFT"); and the cuRAND library for generating random numbers. In at least one embodiment, the CUDA library 2603 may include deep learning libraries such as the cuDNN library of primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference. 【0224】 Figure 27 shows an ROCm implementation of the software stack 2500 of Figure 25 according to at least one embodiment. In at least one embodiment, the ROCm software stack 2700, from which application 2701 can be launched, includes a language runtime 2703, a system runtime 2705, a thunk 2707, and a ROCm kernel driver 2708. In at least one embodiment, the ROCm software stack 2700 runs on hardware 2709, which may include a GPU that supports ROCm and is developed by AMD Corporation in Santa Clara, California. 【0225】 In at least one embodiment, application 2701 may perform similar functionality to application 2501 as described above in conjunction with Figure 25. In at least one embodiment, the language runtime 2703 and system runtime 2705 may further perform similar functionality to runtime 2505 as described above in conjunction with Figure 25. In at least one embodiment, the language runtime 2703 and system runtime 2705 differ in that system runtime 2705 is a language-independent runtime that implements the ROCr system runtime API 2704 and utilizes the Heterogeneous System Architecture ("HSA") runtime API. In at least one embodiment, the HSA runtime API is a thin user-mode API that exposes an interface for accessing and interacting with the AMD GPU, including, among other things, functions for memory management, execution control via kernel-designed dispatch, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, as opposed to the system runtime 2705, the language runtime 2703 is an implementation of a language-specific runtime API 2702 layered on top of the ROCr system runtime API 2704. In at least one embodiment, the language runtime API may include, but is not limited to, a Heterogeneous compute Interface for Portability ("HIP") language runtime API, a Heterogeneous Compute Compiler ("HCC") language runtime API, or an OpenCL API. The HIP language, in particular, is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes, among other things, functions similar to those of the CUDA runtime API 2604 described above in conjunction with Figure 26, such as functions for memory management, execution control, device management, error handling, and synchronization. 【0226】 In at least one embodiment, the thunk (ROCt) 2707 is an interface 2706 that may be used to interact with the underlying ROCm driver 2708. In at least one embodiment, the ROCm driver 2708 is a ROCk driver, which is a combination of the AMDGPU driver and the HSA kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that implements similar functionality to the device kernel driver 2506 described above in conjunction with Figure 25. In at least one embodiment, the HSA kernel driver is a driver that allows different types of processors to share system resources more effectively through hardware features. 【0227】 In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 2700 above the language runtime 2703, providing a functional similarity to the CUDA library 2603 described above, in conjunction with Figure 26. In at least one embodiment, the various libraries may include, but are not limited to, a hipBLAS library that implements functionality similar to that of CUDA cuBLAS, a rocFFT library for calculating FFTs similar to those of CUDA cuFFT, and other libraries for mathematics, deep learning, and / or other purposes. 【0228】 Figure 28 shows an OpenCL implementation of the software stack 2500 of Figure 25 in at least one embodiment. In at least one embodiment, the OpenCL software stack 2800, from which application 2801 can be invoked, includes the OpenCL framework 2810, the OpenCL runtime 2806, and the driver 2807. In at least one embodiment, the OpenCL software stack 2800 runs on vendor-non-vendor specific hardware 2609. In at least one embodiment, since OpenCL is supported by devices developed by different vendors, a specific OpenCL driver may be required to interact with hardware from such vendors. 【0229】 In at least one embodiment, application 2801, OpenCL runtime 2806, device kernel driver 2807, and hardware 2808 may perform similar functionality to application 2501, runtime 2505, device kernel driver 2506, and hardware 2507, respectively, as described above in conjunction with Figure 25. In at least one embodiment, application 2801 further includes an OpenCL kernel 2802 having code to be executed on the device. 【0230】 In at least one embodiment, OpenCL defines a “platform” that enables a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides platform layer APIs and runtime APIs, shown as platform API 2803 and runtime API 2805. In at least one embodiment, runtime API 2805 uses contexts to manage kernel execution on devices. In at least one embodiment, each identified device may be associated with its own context, and runtime API 2805 may use its respective context to manage, among other things, command queues, program objects, and kernel objects, and share memory objects for that device. In at least one embodiment, platform API 2803 exposes functionality that allows device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In at least one embodiment, the OpenCL framework further provides a variety of built-in functions (not shown), among other things, including mathematical functions, relational functions, and image processing functions. 【0231】 In at least one embodiment, compiler 2804 is also included in the OpenCL framework 2810. In at least one embodiment, source code may be compiled offline before the application is executed or compiled online during the application's execution. In contrast to CUDA and ROCm, in at least one embodiment, an OpenCL application may be compiled online by compiler 2804, which is included to represent any number of compilers that can be used to compile source code and / or IR code into binary code, such as Standard Portable Intermediate Representation ("SPIR-V") code. Alternatively, in at least one embodiment, an OpenCL application may be compiled offline before such application is executed. 【0232】 Figure 29 shows software supported by a programming platform in at least one embodiment. In at least one embodiment, the programming platform 2904 is configured to support various programming models 2903, middleware and / or libraries 2902, and frameworks 2901 on which application 2900 may rely. In at least one embodiment, application 2900 may be an AI / ML application implemented using a deep learning framework such as MXNet, PyTorch, or TensorFlow, which may rely on libraries such as cuDNN, NVIDIA Collective Communications Library (“NCCL”), and / or NVIDIA Developer Data Loading Library (“DALI”) CUDA libraries to provide accelerated computing on the underlying hardware. 【0233】 In at least one embodiment, the programming platform 2904 may be one of the CUDA, ROCm, or OpenCL platforms described above in conjunction with Figures 26, 27, and 28, respectively. In at least one embodiment, the programming platform 2904 supports a plurality of programming models 2903, which are abstractions of the underlying computing system that allow representation of algorithms and data structures. In at least one embodiment, the programming model 2903 may expose the features of the underlying hardware to improve performance. In at least one embodiment, the programming model 2903 may include, but is not limited to, CUDA, HIP, OpenCL, C++ Accelerated Massive Parallelism ("C++AMP"), Open Multi-Processing ("OpenMP"), Open Accelerators ("OpenACC"), and / or Vulcan Compute. 【0234】 In at least one embodiment, the library and / or middleware 2902 provides an implementation of the abstraction of the programming model 2904. In at least one embodiment, such a library includes data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, such middleware includes software that provides services to the application in addition to the software available from the programming platform 2904. In at least one embodiment, the library and / or middleware 2902 may include, but is not limited to, cuBLAS, cuFFT, cuRAND, and other CUDA libraries, or rocBLAS, rocFFT, rocRAND, and other ROCm libraries. Furthermore, in at least one embodiment, the library and / or middleware 2902 may include libraries of NCCL and ROCm Communication Collectives Library ("RCCL") providing communication routines for the GPU, the MIOpen library for deep learning acceleration, and / or the Eigen library for linear algebra, matrix and vector operations, geometric transformations, numerical solvers, and related algorithms. 【0235】 In at least one embodiment, the application framework 2901 depends on libraries and / or middleware 2902. In at least one embodiment, each of the application frameworks 2901 is a software framework used to implement a standard structure of application software. In at least one embodiment, returning to the AI / ML example described above, the AI / ML application may be implemented using a framework such as Caffe, Caffe2, TensorFlow, Keras, PyTorch, or the MxNet deep learning framework. 【0236】 Figure 30 illustrates the compilation of code for execution on one of the programming platforms shown in Figures 25–28, according to at least one embodiment. In at least one embodiment, compiler 3001 receives source code 3000, which includes both host code and device code. In at least one embodiment, compiler 3001 is configured to convert source code 3000 into host executable code 3002 for execution on a host and device executable code 3003 for execution on a device. In at least one embodiment, source code 3000 may be compiled offline before application execution or online during application execution. 【0237】 In at least one embodiment, source code 3000 may include code in any programming language supported by compiler 3001, such as C++, C, or Fortran. In at least one embodiment, source code 3000 may be contained in a single source file having a mixture of host code and device code, in which the location of the device code is indicated. In at least one embodiment, the single source file may be a .cu file containing CUDA code or a .hip.cpp file containing HIP code. Alternatively, in at least one embodiment, source code 3000 may include multiple source code files rather than a single source file in which host code and device code are separated. 【0238】 In at least one embodiment, the compiler 3001 is configured to compile the source code 3000 into host executable code 3002 for execution on a host and device executable code 3003 for execution on a device. In at least one embodiment, the compiler 3001 performs operations including parsing the source code 3000 into an abstract system tree (AST), performing optimizations, and generating executable code. In at least one embodiment in which the source code 3000 comprises a single source file, the compiler 3001 may separate the device code from the host code in such a single source file, as will be described in more detail below with respect to Figure 31, and compile the device code and the host code into device executable code 3003 and host executable code 3002, respectively, and link the device executable code 3003 and the host executable code 3002 to each other in a single file. 【0239】 In at least one embodiment, the host executable code 3002 and the device executable code 3003 may be in any preferred format, such as binary code and / or IR code. In at least one embodiment, for CUDA, the host executable code 3002 may contain native object code, and the device executable code 3003 may contain code in the PTX intermediate representation. In at least one embodiment, for ROCm, both the host executable code 3002 and the device executable code 3003 may contain target binary code. 【0240】 Figure 31 is a more detailed diagram of compiling code for execution on one of the programming platforms shown in Figures 25–28, according to at least one embodiment. In at least one embodiment, compiler 3101 is configured to receive source code 3100, compile source code 3100, and output executable file 3110. In at least one embodiment, source code 3100 is a single source file, such as a .cu file, a .hip.cpp file, or a file of another format, containing both host code and device code. In at least one embodiment, compiler 3101 may be, but is not limited to, an NVIDIA CUDA compiler ("NVCC": NVIDIA CUDA compiler) for compiling CUDA code in a .cu file, or an HCC compiler for compiling HIP code in a .hip.cpp file. 【0241】 In at least one embodiment, compiler 3101 includes a compiler front-end 3102, a host compiler 3105, a device compiler 3106, and a linker 3109. In at least one embodiment, compiler front-end 3102 is configured to separate device code 3104 from host code 3103 in source code 3100. In at least one embodiment, device code 3104 is compiled by device compiler 3106 into device executable code 3108, which may include binary code or IR code as described. In at least one embodiment, separately, host code 3103 is compiled by host compiler 3105 into host executable code 3107. In at least one embodiment, for NVCC, the host compiler 3105 may be a general-purpose C / C++ compiler that outputs native object code, but is not limited to that which, while the device compiler 3106 may be a Low-Level Virtual Machine ("LLVM") based compiler that forks the LLVM compiler infrastructure and outputs PTX code or binary code, but is not limited to that which. In at least one embodiment, for HCC, both the host compiler 3105 and the device compiler 3106 may be LLVM-based compilers that output target binary code, but is not limited to that which. 【0242】 In at least one embodiment, after compiling the source code 3100 into host executable code 3107 and device executable code 3108, the linker 3109 links the host executable code 3107 and device executable code 3108 together in an executable file 3110. In at least one embodiment, the native object code for the host and the PTX or binary code for the device may be linked together in an Executable and Linkable Format ("ELF") file, which is a container format used to store the object code. 【0243】 Figure 32 shows, in at least one embodiment, that the source code is translated before compiling the source code. In at least one embodiment, the source code 3200 is passed through a translation tool 3201, which translates the source code 3200 into translated source code 3202. In at least one embodiment, the compiler 3203 is used to compile the translated source code 3202 into host executable code 3204 and device executable code 3205 in a process similar to the compilation of the source code 3000 by the compiler 3001 into host executable code 3002 and device executable code 3003, as described above in conjunction with Figure 30. 【0244】 In at least one embodiment, the translation performed by the translation tool 3201 is used to port the source code 3200 for execution in an environment different from the environment in which it was originally intended to run. In at least one embodiment, the translation tool 3201 may include, but is not limited to, a HIP translator used to "hipify" CUDA code targeting the CUDA platform into HIP code that can be compiled and executed on the ROCm platform. In at least one embodiment, the translation of the source code 3200 may include parsing the source code 3200 and converting calls to one or more APIs provided by one programming model (e.g., CUDA) to corresponding calls to one or more APIs provided by another programming model (e.g., HIP), as will be described in more detail below in conjunction with Figures 33A to 34. In at least one embodiment, returning to the example of hipify CUDA code, calls to the CUDA runtime API, CUDA driver API, and / or CUDA libraries can be converted to corresponding HIP API calls. In at least one embodiment, the automated translation performed by the translation tool 3201 is sometimes incomplete and may require additional manual effort to fully port the source code 3200. 【0245】 Configuring GPUs for general-purpose computing The following diagram illustrates, but is not limited to, an exemplary architecture for compiling and executing compute source code, in at least one embodiment. 【0246】 Figure 33A shows a system 33A00 configured to compile and execute CUDA source code 3310 using different types of processing units according to at least one embodiment. In at least one embodiment, system 33A00 includes, but is not limited to, CUDA source code 3310, CUDA compiler 3350, host executable code 3370(1), host executable code 3370(2), CUDA device executable code 3384, CPU 3390, CUDA-enabled GPU 3394, GPU 3392, CUDA-to-HIP translation tool 3320, HIP source code 3330, HIP compiler driver 3340, HCC 3360, and HCC device executable code 3382. 【0247】 In at least one embodiment, CUDA source code 3310 is a collection of human-readable code in the CUDA programming language. In at least one embodiment, CUDA code is human-readable code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, a mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that can be executed in parallel on a device after compilation. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU 3390, GPU 33192, or another GPGPU. In at least one embodiment, host code is source code that can be executed on a host after compilation. In at least one embodiment, the host may be a processor optimized for sequential instruction processing, such as a CPU 3390. 【0248】 In at least one embodiment, the CUDA source code 3310 includes, but is not limited to, any number of global functions 3312 (including zero), any number of device functions 3314 (including zero), any number of host functions 3316 (including zero), and any number of host / device functions 3318 (including zero). In at least one embodiment, the global functions 3312, device functions 3314, host functions 3316, and host / device functions 3318 may be mixed in the CUDA source code 3310. In at least one embodiment, each of the global functions 3312 is executable on a device and callable from a host. In at least one embodiment, one or more of the global functions 3312 can therefore act as an entry point to a device. In at least one embodiment, each of the global functions 3312 is a kernel. In at least one embodiment, and in a technique known as dynamic parallelism, one or more of the global functions 3312 define a kernel, which is executable on a device and callable from such a device. In at least one embodiment, the kernel is executed N times in parallel by N (where N is any positive integer) different threads on the device during execution. 【0249】 In at least one embodiment, each of the device functions 3314 runs on a device and is callable only from such a device. In at least one embodiment, each of the host functions 3316 runs on a host and is callable only from such a host. In at least one embodiment, each of the host / device functions 3316 defines both a host version of the function that is run on a host and is callable only from such a host, and a device version of the function that is run on a device and is callable only from such a device. 【0250】 In at least one embodiment, CUDA source code 3310 may also include any number of calls to any number of functions defined via CUDA runtime API 3302, without limiting it. In at least one embodiment, CUDA runtime API 3302 may include any number of functions that run on the host, such as allocating and deallocating device memory, transferring data between host memory and device memory, and managing a system with multiple devices. In at least one embodiment, CUDA source code 3310 may also include any number of calls to any number of functions specified in any number of other CUDA APIs. In at least one embodiment, a CUDA API can be any API designed for use by CUDA code. In at least one embodiment, a CUDA API may include, but is not limited to, CUDA runtime API 3302, CUDA driver APIs, APIs for any number of CUDA libraries, etc. In at least one embodiment, and with respect to the CUDA runtime API 3302, the CUDA driver API is a lower-level API but provides finer-grained control of the device. In at least one embodiment, examples of CUDA libraries include, but are not limited to, cuBLAS, cuFFT, cuRAND, cuDNN, etc. 【0251】 In at least one embodiment, the CUDA compiler 3350 compiles input CUDA code (e.g., CUDA source code 3310) to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, the CUDA compiler 3350 is an NVCC. In at least one embodiment, the host executable code 3370(1) is a compiled version of the host code contained in the input source code, which is executable on the CPU 3390. In at least one embodiment, the CPU 3390 may be any processor optimized for sequential instruction processing. 【0252】 In at least one embodiment, CUDA device executable code 3384 is a compiled version of device code contained in input source code that is executable on a CUDA-enabled GPU 3394. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, CUDA device executable code 3384 includes, but is not limited to, IR code such as PTX code, which is further compiled at runtime by the device driver into binary code for a specific target device (e.g., a CUDA-enabled GPU 3394). In at least one embodiment, the CUDA-enabled GPU 3394 can be any processor optimized for parallel instruction processing and supporting CUDA. In at least one embodiment, the CUDA-enabled GPU 3394 is developed by NVIDIA Corporation in Santa Clara, California. 【0253】 In at least one embodiment, the CUDA-to-HIP translation tool 3320 is configured to translate CUDA source code 3310 into functionally similar HIP source code 3330. In at least one embodiment, HIP source code 3330 is a collection of human-readable code in the HIP programming language. In at least one embodiment, HIP code is human-readable code in the HIP programming language. In at least one embodiment, the HIP programming language is an extension of the C++ programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, the HIP programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, for example, a HIP programming language includes (one or more) mechanisms for defining global functions 3312, but such a HIP programming language may not support dynamic parallelism, and therefore global functions 3312 defined in the HIP code may only be callable from the host. 【0254】 In at least one embodiment, HIP source code 3330 includes, but is not limited to, any number of global functions 3312 (including zero), any number of device functions 3314 (including zero), any number of host functions 3316 (including zero), and any number of host / device functions 3318 (including zero). In at least one embodiment, HIP source code 3330 may also include any number of calls to any number of functions specified in the HIP runtime API 3332. In at least one embodiment, the HIP runtime API 3332 includes, but is not limited to, functionally similar versions of a subset of functions included in the CUDA runtime API 3302. In at least one embodiment, HIP source code 3330 may also include any number of calls to any number of functions specified in any number of other HIP APIs. In at least one embodiment, a HIP API can be any API designed for use by HIP code and / or ROCm. In at least one embodiment, the HIP API includes, but is not limited to, the HIP runtime API 3332, the HIP driver API, APIs for any number of HIP libraries, APIs for any number of ROCm libraries, and so on. 【0255】 In at least one embodiment, the CUDA-to-HIP translation tool 3320 converts each kernel call in CUDA code from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in CUDA code to any number of other functionally similar HIP calls. In at least one embodiment, a CUDA call is a call to a function specified in the CUDA API, and a HIP call is a call to a function specified in the HIP API. In at least one embodiment, the CUDA-to-HIP translation tool 3320 converts any number of calls to functions specified in the CUDA runtime API 3302 to any number of calls to functions specified in the HIP runtime API 3332. 【0256】 In at least one embodiment, the CUDA-to-HIP translation tool 3320 is a tool known as hipify-perl that performs a text-based translation process. In at least one embodiment, the CUDA-to-HIP translation tool 3320 is a tool known as hipify-clang, which performs a more complex and robust translation process than hipify-perl, involving parsing the CUDA code using clang (a compiler front-end) and then translating the resulting symbols. In at least one embodiment, properly converting CUDA code to HIP code may require modifications (e.g., manual editing) in addition to the modifications performed by the CUDA-to-HIP translation tool 3320. 【0257】 In at least one embodiment, the HIP compiler driver 3340 is a front-end that determines the target device 3346 and then configures a compiler compatible with the target device 3346 to compile the HIP source code 3330. In at least one embodiment, the target device 3346 is a processor optimized for parallel instruction processing. In at least one embodiment, the HIP compiler driver 3340 may determine the target device 3346 in any technically feasible manner. 【0258】 In at least one embodiment, if the target device 3346 is compatible with CUDA (for example, a CUDA-enabled GPU 3394), the HIP compiler driver 3340 generates a HIP / NVCC compile command 3342. In at least one embodiment, and as described in more detail in conjunction with Figure 33B, the HIP / NVCC compile command 3342 configures the CUDA compiler 3350 to compile the HIP source code 3330 using, but not limited to, HIP-to-CUDA translation headers and CUDA runtime libraries. In at least one embodiment, and in response to the HIP / NVCC compile command 3342, the CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384. 【0259】 In at least one embodiment, if the target device 3346 is not CUDA compatible, the HIP compiler driver 3340 generates a HIP / HCC compile command 3344. In at least one embodiment, and as described in more detail in conjunction with Figure 33C, the HIP / HCC compile command 3344 configures HCC3360 to compile HIP source code 3330 using, but not limited to, HCC headers and HIP / HCC runtime libraries. In at least one embodiment, and in response to the HIP / HCC compile command 3344, HCC3360 generates host executable code 3370(2) and HCC device executable code 3382. In at least one embodiment, HCC device executable code 3382 is a compiled version of the device code contained in HIP source code 3330, which is executable on GPU 3392. In at least one embodiment, the GPU3392 could be any processor optimized for parallel instruction processing, incompatible with CUDA, and compatible with HCC. In at least one embodiment, the GPU3392 is developed by AMD Corporation in Santa Clara, California. In at least one embodiment, the GPU3392 is a non-CUDA-enabled GPU3392. 【0260】 For illustrative purposes only, three different flows that may be implemented in at least one embodiment to compile CUDA source code 3310 for execution on CPU 3390 and different devices are illustrated in Figure 33A. In at least one embodiment, a direct CUDA flow compiles CUDA source code 3310 for execution on CPU 3390 and CUDA-enabled GPU 3394 without translating CUDA source code 3310 to HIP source code 3330. In at least one embodiment, an indirect CUDA flow translates CUDA source code 3310 to HIP source code 3330 and then compiles HIP source code 3330 for execution on CPU 3390 and CUDA-enabled GPU 3394. In at least one embodiment, the CUDA / HCC flow translates CUDA source code 3310 into HIP source code 3330, and then compiles the HIP source code 3330 for execution on CPU 3390 and GPU 3392. 【0261】 A direct CUDA flow, which can be implemented in at least one embodiment, is illustrated via a dashed line and a series of bubbles annotated A1-A3. In at least one embodiment, and as illustrated by the bubble annotated A1, the CUDA compiler 3350 receives CUDA source code 3310 and a CUDA compile command 3348 that configures the CUDA compiler 3350 to compile the CUDA source code 3310. In at least one embodiment, the CUDA source code 3310 used in the direct CUDA flow is written in a CUDA programming language based on a programming language other than C++ (e.g., C, Fortran, Python, Java, etc.). In at least one embodiment, and in response to the CUDA compile command 3348, the CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384 (illustrated by the bubble annotated A2). In at least one embodiment, and as illustrated in the bubble annotated with A3, the host executable code 3370(1) and the CUDA device executable code 3384 may run on the CPU 3390 and the CUDA-enabled GPU 3394, respectively. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code which is further compiled at runtime into binary code for a particular target device. 【0262】 An indirect CUDA flow that can be implemented in at least one embodiment is illustrated via a series of bubbles annotated with dotted lines and B1~B6. In at least one embodiment, as illustrated by the bubble annotated with B1, the CUDA-to-HIP translation tool 3320 receives the CUDA source code 3310. In at least one embodiment, as illustrated by the bubble annotated with B2, the CUDA-to-HIP translation tool 3320 translates the CUDA source code 3310 into HIP source code 3330. In at least one embodiment, as illustrated by the bubble annotated with B3, the HIP compiler driver 3340 receives the HIP source code 3330 and determines that the target device 3346 is CUDA-compatible. 【0263】 In at least one embodiment, and as illustrated in the bubble annotated as B4, the HIP compiler driver 3340 generates a HIP / NVCC compile command 3342 and sends both the HIP / NVCC compile command 3342 and the HIP source code 3330 to the CUDA compiler 3350. In at least one embodiment, and as described in more detail in conjunction with Figure 33B, the HIP / NVCC compile command 3342 configures the CUDA compiler 3350 to compile the HIP source code 3330 using, but not limited to, a HIP-to-CUDA translation header and CUDA runtime libraries. In at least one embodiment, and in response to the HIP / NVCC compile command 3342, the CUDA compiler 3350 generates host executable code 3370(1) and CUDA device executable code 3384 (illustrated in the bubble annotated as B5). In at least one embodiment, and as illustrated in the bubble annotated as B6, the host executable code 3370(1) and the CUDA device executable code 3384 may run on the CPU 3390 and the CUDA-enabled GPU 3394, respectively. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a particular target device. 【0264】 The CUDA / HCC flow that can be implemented in at least one embodiment is illustrated via a series of bubbles annotated with solid lines and C1 - C6. In at least one embodiment, as illustrated by the bubble annotated with C1, the CUDA - to - HIP translation tool 3320 receives the CUDA source code 3310. In at least one embodiment, as illustrated by the bubble annotated with C2, the CUDA - to - HIP translation tool 3320 translates the CUDA source code 3310 into HIP source code 3330. In at least one embodiment, as illustrated by the bubble annotated with C3, the HIP compiler driver 3340 receives the HIP source code 3330 and determines that the target device 3346 is not CUDA - compatible. 【0265】 In at least one embodiment, the HIP compiler driver 3340 generates a HIP / HCC compile command 3344 and sends both the HIP / HCC compile command 3344 and the HIP source code 3330 to HCC3360 (illustrated by the bubble annotated with C4). In at least one embodiment, as will be described in more detail in conjunction with FIG. 33C, the HIP / HCC compile command 3344 configures HCC3360 to compile the HIP source code 3330 using, without limitation, the HCC header and the HIP / HCC runtime library. In at least one embodiment, in response to the HIP / HCC compile command 3344, HCC3360 generates host - executable code 3370(2) and HCC device - executable code 3382 (illustrated by the bubble annotated with C5). In at least one embodiment, as illustrated by the bubble annotated with C6, the host - executable code 3370(2) and the HCC device - executable code 3382 can be executed on the CPU3390 and the GPU3392, respectively. 【0266】 In at least one embodiment, after the CUDA source code 3310 has been translated into HIP source code 3330, the HIP compiler driver 3340 may then be used to generate executable code for either the CUDA-enabled GPU 3394 or GPU 3392 without re-running the CUDA-to-HIP translation tool 3320. In at least one embodiment, the CUDA-to-HIP translation tool 3320 translates the CUDA source code 3310 into HIP source code 3330, which is then stored in memory. In at least one embodiment, the HIP compiler driver 3340 then configures the HCC 3360 to generate host executable code 3370(2) and HCC device executable code 3382 based on the HIP source code 3330. In at least one embodiment, the HIP compiler driver 3340 then configures the CUDA compiler 3350 to generate host executable code 3370(1) and CUDA device executable code 3384 based on the stored HIP source code 3330. 【0267】 Figure 33B shows a system 3304 configured to compile and run the CUDA source code 3310 of Figure 33A using a CPU 3390 and a CUDA-enabled GPU 3394, according to at least one embodiment. In at least one embodiment, system 3304 includes, but is not limited to, the CUDA source code 3310, a CUDA-to-HIP translation tool 3320, HIP source code 3330, a HIP compiler driver 3340, a CUDA compiler 3350, host executable code 3370(1), CUDA device executable code 3384, a CPU 3390, and a CUDA-enabled GPU 3394. 【0268】 In at least one embodiment, and as previously described herein in conjunction with Figure 33A, the CUDA source code 3310 includes, but is not limited to, any number of global functions 3312 (including zero), any number of device functions 3314 (including zero), any number of host functions 3316 (including zero), and any number of host / device functions 3318 (including zero). In at least one embodiment, the CUDA source code 3310 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs. 【0269】 In at least one embodiment, the CUDA-to-HIP translation tool 3320 translates CUDA source code 3310 into HIP source code 3330. In at least one embodiment, the CUDA-to-HIP translation tool 3320 converts each kernel call in the CUDA source code 3310 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the CUDA source code 3310 into any number of other functionally similar HIP calls. 【0270】 In at least one embodiment, the HIP compiler driver 3340 determines that the target device 3346 is CUDA-enabled and generates a HIP / NVCC compile command 3342. In at least one embodiment, the HIP compiler driver 3340 then configures the CUDA compiler 3350 via the HIP / NVCC compile command 3342 to compile the HIP source code 3330. In at least one embodiment, as part of configuring the CUDA compiler 3350, the HIP compiler driver 3340 provides access to a HIP-to-CUDA translation header 3352. In at least one embodiment, the HIP-to-CUDA translation header 3352 translates any number of mechanisms (e.g., functions) specified in any number of HIP APIs to any number of mechanisms specified in any number of CUDA APIs. In at least one embodiment, the CUDA compiler 3350 uses a HIP-to-CUDA translation header 3352, in conjunction with a CUDA runtime library 3354 corresponding to the CUDA runtime API 3302, to generate host executable code 3370(1) and CUDA device executable code 3384. In at least one embodiment, the host executable code 3370(1) and CUDA device executable code 3384 may then be executed on a CPU 3390 and a CUDA-enabled GPU 3394, respectively. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, binary code. In at least one embodiment, the CUDA device executable code 3384 includes, but is not limited to, PTX code, which is further compiled at runtime into binary code for a specific target device. 【0271】 Figure 33C shows a system 3306 configured to compile and run the CUDA source code 3310 of Figure 33A using a CPU 3390 and a non-CUDA-enabled GPU 3392, according to at least one embodiment. In at least one embodiment, system 3306 includes, but is not limited to, the CUDA source code 3310, a CUDA-to-HIP translation tool 3320, HIP source code 3330, a HIP compiler driver 3340, an HCC 3360, host executable code 3370(2), HCC device executable code 3382, a CPU 3390, and a GPU 3392. 【0272】 In at least one embodiment, and as previously described herein in conjunction with Figure 33A, the CUDA source code 3310 includes, but is not limited to, any number of global functions 3312 (including zero), any number of device functions 3314 (including zero), any number of host functions 3316 (including zero), and any number of host / device functions 3318 (including zero). In at least one embodiment, the CUDA source code 3310 also includes, but is not limited to, any number of calls to any number of functions specified in any number of CUDA APIs. 【0273】 In at least one embodiment, the CUDA-to-HIP translation tool 3320 translates CUDA source code 3310 into HIP source code 3330. In at least one embodiment, the CUDA-to-HIP translation tool 3320 converts each kernel call in the CUDA source code 3310 from CUDA syntax to HIP syntax, and converts any number of other CUDA calls in the source code 3310 into any number of other functionally similar HIP calls. 【0274】 In at least one embodiment, the HIP compiler driver 3340 then determines that the target device 3346 is not CUDA-enabled and generates a HIP / HCC compilation command 3344. In at least one embodiment, the HIP compiler driver 3340 then configures the HCC 3360 to execute the HIP / HCC compilation command 3344 to compile the HIP source code 3330. In at least one embodiment, the HIP / HCC compilation command 3344 configures the HCC 3360 to use the HIP / HCC runtime library 3358 and the HCC header 3356 to generate the host executable code 3370(2) and the HCC device executable code 3382, but is not limited to this. In at least one embodiment, the HIP / HCC runtime library 3358 corresponds to the HIP runtime API 3332. In at least one embodiment, the HCC header 3356 includes, but is not limited to, any number and type of interoperability mechanisms for HIP and HCC. In at least one embodiment, the host executable code 3370(2) and the HCC device executable code 3382 may be executed on the CPU 3390 and the GPU 3392, respectively. 【0275】 Figure 34 shows an exemplary kernel translated by the CUDA-to-HIP translation tool 3320 of Figure 33C, according to at least one embodiment. In at least one embodiment, the CUDA source code 3310 divides an overall problem, which a given kernel is designed to solve, into relatively coarse subproblems that can be solved independently using thread blocks. In at least one embodiment, each thread block contains any number of threads, but is not limited. In at least one embodiment, each subproblem is divided into relatively fine pieces that can be solved in parallel and in conjunction by threads within a thread block. In at least one embodiment, threads within a thread block can be coordinated by sharing data through shared memory and by synchronizing their execution to coordinate memory access. 【0276】 In at least one embodiment, the CUDA source code 3310 organizes thread blocks associated with a given kernel into a one-dimensional grid, a two-dimensional grid, or a three-dimensional grid of thread blocks. In at least one embodiment, each thread block contains any number of threads, but is not limited, and the grid contains any number of thread blocks, but is not limited. 【0277】 In at least one embodiment, the kernel is a function in device code defined using the declaration specifier "__global__". In at least one embodiment, the grid dimensions on which the kernel runs for a given kernel call and associated streams are specified using CUDA kernel launch syntax 3410. In at least one embodiment, CUDA kernel launch syntax 3410 is "KernelName<<<GridSize,BlockSize,SharedMemorySize,Stream> It is specified as >>(KernelArguments);. In at least one embodiment, the run configuration syntax is a "<<<...>>>" construct inserted between the kernel name ("KernelName") and the parenthetical list of kernel arguments ("KernelArguments"). In at least one embodiment, the CUDA kernel boot syntax 3410 includes, but is not limited to, the CUDA boot functionality syntax instead of the run configuration syntax. 【0278】 In at least one embodiment, "GridSize" is of type dim3 and specifies the dimensions and size of the grid. In at least one embodiment, type dim3 is a CUDA-defined structure containing, but not limited to, unsigned integers x, y, and z. In at least one embodiment, if z is not specified, z defaults to 1. In at least one embodiment, if y is not specified, y defaults to 1. In at least one embodiment, the number of thread blocks in the grid is equal to the product of GridSize.x, GridSize.y, and GridSize.z. In at least one embodiment, "BlockSize" is of type dim3 and specifies the dimensions and size of each thread block. In at least one embodiment, the number of threads per thread block is equal to the product of BlockSize.x, BlockSize.y, and BlockSize.z. In at least one embodiment, each thread executing the kernel is given a unique thread ID accessible within the kernel through an intrinsic variable (e.g., "threadIdx"). 【0279】 In at least one embodiment, and with respect to CUDA kernel boot syntax 3410, “SharedMemorySize” is an optional argument specifying the number of bytes in shared memory dynamically allocated per thread block for a given kernel call, in addition to statically allocated memory. In at least one embodiment, and with respect to CUDA kernel boot syntax 3410, SharedMemorySize defaults to 0. In at least one embodiment, and with respect to CUDA kernel boot syntax 3410, “Stream” is an optional argument specifying the associated stream, and defaults to 0 to specify a default stream. In at least one embodiment, a stream is a sequence of commands to be executed in order (possibly issued by different host threads). In at least one embodiment, different streams may execute commands out of order or simultaneously with each other. 【0280】 In at least one embodiment, the CUDA source code 3310 includes, but is not limited to, a kernel definition and a main function for an exemplary kernel "MatAdd". In at least one embodiment, the main function is host code that runs on the host and includes, but is not limited to, kernel calls that cause the kernel MatAdd to run on the device. In at least one embodiment, and as shown, the kernel MatAdd adds two matrices A and B of size N×N, where N is a positive integer, and stores the result in matrix C. In at least one embodiment, the main function defines the threadsPerBlock variable as 16×16 and the numBlocks variable as N / 16×N / 16. In at least one embodiment, the main function then makes the kernel call "MatAdd<<<numBlocks,threadsPerBlock> Specify >>(A,B,C);. In at least one embodiment, and according to the CUDA kernel boot syntax 3410, the kernel MatAdd is executed using a grid of thread blocks having dimensions N / 16 × N / 16, where each thread block has dimensions 16 × 16. In at least one embodiment, each thread block contains 256 threads, and the grid is made up of enough blocks to have one thread per matrix element, and each thread in such a grid executes the kernel MatAdd to perform one pairwise addition. 【0281】 In at least one embodiment, while translating CUDA source code 3310 to HIP source code 3330, the CUDA-to-HIP translation tool 3320 translates each kernel call in the CUDA source code 3310 from the CUDA kernel launch syntax 3410 to the HIP kernel launch syntax 3420, and converts any number of other CUDA calls in the source code 3310 to any number of other functionally similar HIP calls. In at least one embodiment, the HIP kernel launch syntax 3420 is specified as "hipLaunchKernelGGL(KernelName,GridSize,BlockSize,SharedMemorySize,Stream,KernelArguments);". In at least one embodiment, each of KernelName, GridSize, BlockSize, ShareMemorySize, Stream, and KernelArguments has the same meaning in HIP kernel boot syntax 3420 as it does in CUDA kernel boot syntax 3410 (as previously described herein). In at least one embodiment, the arguments SharedMemorySize and Stream are required in HIP kernel boot syntax 3420 but optional in CUDA kernel boot syntax 3410. 【0282】 In at least one embodiment, a portion of the HIP source code 3330 shown in Figure 34 is identical to a portion of the CUDA source code 3310 shown in Figure 34, except for the kernel call that causes the kernel MatAdd to execute on the device. In at least one embodiment, the kernel MatAdd is defined in the HIP source code 3330 using the same "__global__" declaration specifier that the kernel MatAdd is defined in the CUDA source code 3310. In at least one embodiment, the kernel call in the HIP source code 3330 is "hipLaunchKernelGGL(MatAdd,numBlocks,threadsPerBlock,0,0,A,B,C);", while the corresponding kernel call in the CUDA source code 3310 is "MatAdd<<<numBlocks,threadsPerBlock> >>(A,B,C);" 【0283】 Figure 35 shows in more detail the CUDA-less GPU 3392 of Figure 33C according to at least one embodiment. In at least one embodiment, the GPU 3392 is developed by AMD Corporation in Santa Clara. In at least one embodiment, the GPU 3392 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, the GPU 3392 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric calculations, and other operations related to rendering images to a display. In at least one embodiment, the GPU 3392 is configured to perform non-graphics-related operations. In at least one embodiment, the GPU 3392 is configured to perform both graphics-related and non-graphics-related operations. In at least one embodiment, the GPU 3392 may be configured to execute device code contained in the HIP source code 3330. 【0284】 In at least one embodiment, the GPU 3392 includes, but not limited to, any number of programmable processing units 3520, a command processor 3510, an L2 cache 3522, a memory controller 3570, a DMA engine 3580(1), a system memory controller 3582, a DMA engine 3580(2), and a GPU controller 3584. In at least one embodiment, each programmable processing unit 3520 includes, but not limited to, a workload manager 3530 and any number of compute units 3540. In at least one embodiment, the command processor 3510 reads commands from one or more command queues (not shown) and distributes the commands to the workload manager 3530. In at least one embodiment, for each programmable processing unit 3520, the associated workload manager 3530 distributes the work to the compute units 3540 contained within the programmable processing unit 3520. In at least one embodiment, each compute unit 3540 may execute any number of thread blocks, but each thread block executes on a single compute unit 3540. In at least one embodiment, a workgroup is a thread block. 【0285】 In at least one embodiment, each compute unit 3540 includes, without limitation, any number of SIMD units 3550 and a shared memory 3560. In at least one embodiment, each SIMD unit 3550 may implement a SIMD architecture and be configured to perform operations in parallel. In at least one embodiment, each SIMD unit 3550 includes, without limitation, a vector ALU 3552 and a vector register file 3554. In at least one embodiment, each SIMD unit 3550 executes different warps. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in the warp belongs to a single thread block and is configured to process different sets of data based on a single set of instructions. In at least one embodiment, predication may be used to disable one or more threads in a warp. In at least one embodiment, a lane is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via the shared memory 3560. 【0286】 In at least one embodiment, the programmable processing unit 3520 is referred to as a "shader engine". In at least one embodiment, each programmable processing unit 3520 includes, without limitation, in addition to the compute unit 3540, any amount of dedicated graphics hardware. In at least one embodiment, each programmable processing unit 3520 includes, without limitation, any number (including zero) of geometry processors, any number (including zero) of rasterizers, any number (including zero) of render back-ends, a workload manager 3530, and any number of compute units 3540. 【0287】 In at least one embodiment, compute unit 3540 shares L2 cache 3522. In at least one embodiment, L2 cache 3522 is partitioned. In at least one embodiment, GPU memory 3590 is accessible by all compute units 3540 in GPU 3392. In at least one embodiment, memory controller 3570 and system memory controller 3582 facilitate data transfer between GPU 3392 and the host, and DMA engine 3580(1) enables asynchronous memory transfer between GPU 3392 and such host. In at least one embodiment, memory controller 3570 and GPU controller 3584 facilitate data transfer between GPU 3392 and other GPU 3392, and DMA engine 3580(2) enables asynchronous memory transfer between GPU 3392 and other GPU 3392. 【0288】 In at least one embodiment, the GPU3392 includes any amount and type of system interconnects that facilitate data and control transmissions across any number and type of directly or indirectly linked components, which may be internal to or external to the GPU3392. In at least one embodiment, the GPU3392 includes any number and type of I / O interfaces (e.g., PCIe) that are coupled to any number and type of peripheral devices, which may not be limited. In at least one embodiment, the GPU3392 may include any number of display engines (including zero) and any number of multimedia engines (including zero), which may not be limited. In at least one embodiment, the GPU3392 implements a memory subsystem that includes any amount and type of memory controllers (e.g., memory controller 3570 and system memory controller 3582) and memory devices (e.g., shared memory 3560) that may be dedicated to one component or shared among multiple components. In at least one embodiment, the GPU 3392 implements a cache subsystem including, but not limited to, one or more cache memories (e.g., L2 cache 3522), each of which may be private to any number of components (e.g., SIMD unit 3550, compute unit 3540, and programmable processing unit 3520) or shared among any number of components. 【0289】 Figure 36 shows how threads of an exemplary CUDA grid 3620 are mapped to different compute units 3540 in Figure 35, according to at least one embodiment. In at least one embodiment, and for illustrative purposes only, the grid 3620 has a GridSize of BX × BY × 1 and a BlockSize of TX × TY × 1. In at least one embodiment, the grid 3620 thus includes, but not limited to, (BX * BY) thread blocks 3630, and each thread block 3630 includes, but not limited to, (TX * TY) threads 3640. The threads 3640 are illustrated in Figure 36 as squiggly arrows. 【0290】 In at least one embodiment, grid 3620 is mapped to a programmable processing unit 3520(1) including, but not limited to, compute units 3540(1) to 3540(C). In at least one embodiment, and as shown, (BJ*BY) thread blocks 3630 are mapped to compute unit 3540(1), and the remaining thread blocks 3630 are mapped to compute unit 3540(2). In at least one embodiment, each thread block 3630 may contain, but not limited to, any number of warps, each warp being mapped to a different SIMD unit 3550 in Figure 35. 【0291】 In at least one embodiment, warps in a given thread block 3630 can synchronize with each other and communicate through a shared memory 3560 contained in the associated compute unit 3540. For example, and in at least one embodiment, warps in thread block 3630(BJ,1) can synchronize with each other and communicate through a shared memory 3560(1). For example, and in at least one embodiment, warps in thread block 3630(BJ+1,1) can synchronize with each other and communicate through a shared memory 3560(2). 【0292】 Figure 37 shows how to migrate existing CUDA code to Data Parallel C++ code using at least one embodiment. Data Parallel C++ (DPC++) can refer to an open, standards-based alternative to a single-architecture, proprietary language, which allows developers to reuse code across hardware targets (CPUs as well as accelerators such as GPUs and FPGAs) and to implement custom adjustments for specific accelerators. DPC++ uses similar and / or identical C and C++ constructs that adhere to ISO C++, which developers may be familiar with. DPC++ incorporates the standard SYCL from the Khronos Group to support data parallelism and heterogeneous programming. SYCL refers to a cross-platform abstraction layer based on the underlying concepts, portability, and efficiency of OpenCL, which allows code for heterogeneous processors to be written in a “single-source” style using standard C++. SYCL enables single-source development where C++ template functions contain both host and device code, allowing for the construction of complex algorithms that utilize OpenCL acceleration, and then enabling their reuse across their entire source code for different types of data. 【0293】 In at least one embodiment, a DPC++ compiler is used to compile DPC++ source code that can be deployed across a variety of hardware targets. In at least one embodiment, a DPC++ compiler is used to generate a DPC++ application that can be deployed across a variety of hardware targets, and DPC++ compatibility tools may be used to migrate a CUDA application into a DPC++ multi-platform program. In at least one embodiment, a DPC++ base toolkit includes a DPC++ compiler for deploying applications across a variety of hardware targets, DPC++ libraries for increasing productivity and performance across CPUs, GPUs, and FPGAs, DPC++ compatibility tools for migrating CUDA applications into multi-platform applications, and any preferred combination thereof. 【0294】 In at least one embodiment, the DPC++ programming model is used for one or more aspects related to simply programming CPUs and accelerators by using modern C++ features to represent parallel processing using a programming language called Data Parallel C++. The DPC++ programming language is used for code reuse for hosts (e.g., CPUs) and accelerators (e.g., GPUs or FPGAs), using a single source language, and execution and memory dependencies can be clearly communicated. Mappings within DPC++ code can be used to migrate applications to run on the hardware or set of hardware devices that best accelerate the workload. Even on platforms without available accelerators, the host may be available to simplify the development and debugging of device code. 【0295】 In at least one embodiment, CUDA source code 3700 is provided as input to a DPC++ compatibility tool 3702 to generate human-readable DPC++ 3704. In at least one embodiment, human-readable DPC++ 3704 includes inline comments generated by the DPC++ compatibility tool 3702, which guide the developer on how and / or where to modify the DPC++ code to complete the coding and adjustments to the desired performance 3706, thereby generating DPC++ source code 3708. 【0296】 In at least one embodiment, CUDA source code 3700 is a collection of human-readable source code in the CUDA programming language, or includes such a collection. In at least one embodiment, CUDA source code 3700 is human-readable source code in the CUDA programming language. In at least one embodiment, the CUDA programming language is an extension of the C++ programming language that includes, but is not limited to, a mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, device code is source code that, after compilation, is executable on a device (e.g., a GPU or FPGA) and may run on one or more processor cores of the device, or may include a more parallelizable workflow. In at least one embodiment, the device may be a processor optimized for parallel instruction processing, such as a CUDA-enabled GPU, a GPU, or another GPGPU. In at least one embodiment, host code is source code that, after compilation, is executable on a host. In at least one embodiment, some or all of the host code and device code may be executed in parallel across the CPU and GPU / FPGA. In at least one embodiment, the host is a processor optimized for sequential instruction processing, such as a CPU. The CUDA source code 3700 described with respect to Figure 37 may conform to the CUDA source code described elsewhere in this specification. 【0297】 In at least one embodiment, DPC++ Compatibility Tool 3702 refers to an executable tool, program, application, or any other suitable type of tool used to facilitate the migration of CUDA source code 3700 to DPC++ source code 3708. In at least one embodiment, DPC++ Compatibility Tool 3702 is a command-line based code migration tool available as part of a DPC++ toolkit used to port existing CUDA source to DPC++. In at least one embodiment, DPC++ Compatibility Tool 3702 converts some or all of the source code of a CUDA application from CUDA to DPC++ and generates a resulting file, called Human-Readable DPC++ 3704, which is at least partially written in DPC++. In at least one embodiment, Human-Readable DPC++ 3704 includes comments generated by DPC++ Compatibility Tool 3702 to indicate where user intervention may be required. In at least one instance, user intervention is required when CUDA source code 3700 calls a CUDA API that does not have a similar DPC++ API; other instances where user intervention is required will be described in more detail later. 【0298】 In at least one embodiment, the workflow for migrating CUDA source code 3700 (e.g., an application or a portion thereof) includes creating one or more compile database files, migrating CUDA to DPC++ using the DPC++ compatibility tool 3702, completing and validating the migration to thereby generate DPC++ source code 3708, and compiling DPC++ source code 3708 using the DPC++ compiler to generate a DPC++ application. In at least one embodiment, the compatibility tool provides a utility that intercepts the commands used when a Makefile is executed and stores them in a compile database file. In at least one embodiment, the file is stored in JSON format. In at least one embodiment, the intercept-built command converts Makefile commands into DPC-compatible commands. 【0299】 In at least one embodiment, intercept-build is a utility script that intercepts the build process to capture compile options, macro definitions, and include paths, and writes this data to a compile database file. In at least one embodiment, the compile database file is a JSON file. In at least one embodiment, the DPC++ compatibility tool 3702 parses the compile database and applies the options when migrating the input sources. In at least one embodiment, the use of intercept-build is optional but highly recommended for Make or CMake-based environments. In at least one embodiment, the migration database includes commands, directories, and files, where commands may include required compile flags, directories may include paths to header files, and files may include paths to CUDA files. 【0300】 In at least one embodiment, the DPC++ Compatibility Tool 3702 migrates CUDA code written in CUDA (e.g., an application) to DPC++ by generating DPC++ whenever possible. In at least one embodiment, the DPC++ Compatibility Tool 3702 is available as part of a toolkit. In at least one embodiment, the DPC++ toolkit includes the intercept-build tool. In at least one embodiment, the intercept-built tool creates a compilation database that captures compilation commands to migrate CUDA files. In at least one embodiment, the compilation database generated by the intercept-built tool is used by the DPC++ Compatibility Tool 3702 to migrate CUDA code to DPC++. In at least one embodiment, non-CUDA C++ code and files are migrated as is. In at least one embodiment, the DPC++ Compatibility Tool 3702 generates human-readable DPC++ 3704, which may be DPC++ code that, when generated by the DPC++ Compatibility Tool 3702, may not compile with the DPC++ compiler and may require additional plumbing to identify the parts of the code that were not migrated correctly, potentially involving manual intervention by the developer. In at least one embodiment, the DPC++ Compatibility Tool 3702 provides hints or tools embedded in the code to help the developer manually migrate additional code that may not be automatically migrated. In at least one embodiment, migration is a one-time activity for a source file, project, or application. 【0301】 In at least one embodiment, the DPC++ compatibility tool 37002 is capable of successfully migrating all parts of CUDA code to DPC++, with only optional steps for manually verifying and adjusting the performance of the generated DPC++ source code. In at least one embodiment, the DPC++ compatibility tool 3702 directly generates DPC++ source code 3708 that is compiled by a DPC++ compiler without requiring or utilizing human intervention to modify the DPC++ code generated by the DPC++ compatibility tool 3702. In at least one embodiment, the DPC++ compatibility tool generates compilable DPC++ code that can be optionally adjusted by the developer for performance, readability, maintainability, various other considerations, or any combination thereof. 【0302】 In at least one embodiment, one or more CUDA source files are migrated to DPC++ source files using the DPC++ compatibility tool 3702, at least partially. In at least one embodiment, the CUDA source code includes one or more header files, which may include CUDA header files. In at least one embodiment, the CUDA source files are<cuda.h> Header files and can be used to print text.<stdio.h> This includes a header file. In at least one embodiment, a portion of the vector addition kernel CUDA source file may be written as follows, or relating to the following: 【number】 【number】 【0303】 In at least one embodiment, and with respect to the CUDA source files presented above, the DPC++ compatibility tool 3702 parses the CUDA source code and replaces the header files with appropriate DPC++ and SYCL header files. In at least one embodiment, the DPC++ header file includes helper declarations. In CUDA, there is the concept of thread IDs, and correspondingly, in DPC++ or SYCL, there is a local identifier for each element. 【0304】 In at least one embodiment, and with respect to the CUDA source file presented above, there are two vectors A and B to be initialized, and the result of vector addition is placed into vector C as part of VectorAddKernel(). In at least one embodiment, as part of migrating the CUDA code to DPC++ code, the DPC++ compatibility tool 3702 converts the CUDA thread IDs used to index work elements to SYCL standard addressing for work elements via local IDs. In at least one embodiment, the DPC++ code generated by the DPC++ compatibility tool 3702 may be optimized, for example, by reducing the dimension of nd_item, thereby increasing memory and / or processor utilization. 【0305】 In at least one embodiment, and with respect to the CUDA source files presented above, memory allocation is migrated. In at least one embodiment, cudaMalloc() is migrated to malloc_device(), a unified shared memory SYCL call to which the device and context are passed, relying on the SYCL concept, including platform, device, context, and queues. In at least one embodiment, the SYCL platform may have multiple devices (e.g., host and GPU devices), each device may have multiple queues to which jobs can be submitted, each device may have a context, and a context may have multiple devices and manage shared memory objects. 【0306】 In at least one embodiment, and with respect to the CUDA source file presented above, the main() function calls or calls VectorAddKernel() to add two vectors A and B to each other and store the result in vector C. In at least one embodiment, the CUDA code for calling VectorAddKernel() is replaced by DPC++ code for submitting the kernel to a command queue for execution. In at least one embodiment, the command group handler cgh passes the data, synchronization, and computation to be submitted to the queue, and parallel_for is called for the number of global elements and the number of work items in the work group where VectorAddKernel() is called. 【0307】 In at least one embodiment, and with respect to the CUDA source files presented above, CUDA calls to copy device memory and then free memory for vectors A, B, and C are migrated to corresponding DPC++ calls. In at least one embodiment, C++ code (e.g., standard ISO C++ code for printing a vector of floating-point variables) is migrated as is without modification by DPC++ compatibility tool 3702. In at least one embodiment, DPC++ compatibility tool 3702 modifies the CUDA API for memory setup and / or host calls to run the kernel on an accelerating device. In at least one embodiment, and with respect to the CUDA source files presented above, the corresponding human-readable DPC++ 3704 (e.g., one that can be compiled) is written as follows or relates to the following: 【number】 【number】 【number】 【0308】 In at least one embodiment, human-readable DPC++ 3704 refers to the output generated by DPC++ Compatibility Tool 3702, which may be optimized in one or another manner. In at least one embodiment, human-readable DPC++ 3704 generated by DPC++ Compatibility Tool 3702 may be manually edited by a developer after migration to make it more maintainable, for performance, or for other considerations. In at least one embodiment, DPC++ code generated by DPC++ Compatibility Tool 37002, such as the disclosed DPC++, may be optimized by removing repeated calls to get_current_device() and / or get_default_context() for each malloc_device() call. In at least one embodiment, the DPC++ code generated above uses a three-dimensional nd_range, which may be refactored to use only a single dimension, thereby reducing memory usage. In at least one embodiment, a developer may manually edit the DPC++ code generated by DPC++ Compatibility Tool 3702 and replace the use of unified shared memory with accessors. In at least one embodiment, the DPC++ compatibility tool 3702 has an option to change how it migrates CUDA code to DPC++ code. In at least one embodiment, the DPC++ compatibility tool 3702 is redundant because it uses a generic template for migrating CUDA code to DPC++ code that works for a large number of cases. 【0309】 In at least one embodiment, the CUDA to DPC++ migration workflow includes steps of preparing for migration using an intercept-build script, performing the migration of a CUDA project to DPC++ using the DPC++ compatibility tool 3702, manually reviewing and editing the migrated source files for completion and validity, and compiling the final DPC++ code to generate a DPC++ application. In at least one embodiment, manual review of the DPC++ source code may be required in one or more scenarios, but not limited to, that the migrated API does not return error codes (CUDA code can return error codes, which can then be consumed by the application, whereas SYCL uses exceptions to report errors and therefore does not use error codes to surface errors), that CUDA compute capability-dependent logic is not supported by DPC++, and that statements may not be deleted. In at least one embodiment, scenarios in which DPC++ code requires manual intervention may include, but are not limited to, error code logic being replaced with (*,0) code or commented out, an equivalent DPC++ API not being available, CUDA compute capability-dependent logic, hardware-dependent APIs (clock()), missing features, unsupported APIs, execution time measurement logic, dealing with built-in vector type conflicts, and migration of cuBLAS APIs. 【0310】 In at least one embodiment, one or more techniques described herein utilize the oneAPI programming model. In at least one embodiment, the oneAPI programming model refers to a programming model for interacting with various compute accelerator architectures. In at least one embodiment, oneAPI refers to an application programming interface (API) designed to interact with various compute accelerator architectures. In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language refers to a high-level language for data-parallel programming productivity. In at least one embodiment, the DPC++ programming language is at least partially based on the C and / or C++ programming languages. In at least one embodiment, the oneAPI programming model is a programming model such as one developed by Intel Corporation in Santa Clara, California. 【0311】 In at least one embodiment, oneAPI and / or the oneAPI programming model are used to interact with various accelerator architectures, GPU architectures, processor architectures, and / or variations thereof. In at least one embodiment, oneAPI includes a set of libraries that implement various functionalities. In at least one embodiment, oneAPI includes at least the oneAPI DPC++ library, the oneAPI mass kernel library, the oneAPI data analysis library, the oneAPI deep neural network library, the oneAPI aggregate communication library, the oneAPI threading building block library, the oneAPI video processing library, and / or variations thereof. 【0312】 In at least one embodiment, the oneAPI DPC++ library, also known as oneDPL, is a library that implements algorithms and functions to accelerate DPC++ kernel programming. In at least one embodiment, oneDPL implements one or more standard template library (STL) functions. In at least one embodiment, oneDPL implements one or more parallel STL functions. In at least one embodiment, oneDPL provides a set of library classes and functions, such as parallel algorithms, iterators, function object classes, range-based APIs, and / or variations thereof. In at least one embodiment, oneDPL implements one or more classes and / or functions from the C++ standard library. In at least one embodiment, oneDPL implements one or more random number generator functions. 【0313】 In at least one embodiment, the oneAPI math kernel library, also known as oneMKL, is a library that implements various optimized and parallelized routines for various mathematical functions and / or operations. In at least one embodiment, oneMKL implements one or more basic linear algebra subprograms (BLAS) and / or linear algebra package (LAPACK) high-density linear algebra routines. In at least one embodiment, oneMKL implements one or more sparse BLAS linear algebra routines. In at least one embodiment, oneMKL implements one or more random number generators (RNGs). In at least one embodiment, oneMKL implements one or more vector mathematics (VM) routines for mathematical operations on vectors. In at least one embodiment, oneMKL implements one or more Fast Fourier Transform (FFT) functions. 【0314】 In at least one embodiment, the oneAPI data analysis library, also known as oneDAL, is a library that implements various data analysis applications and distributed computations. In at least one embodiment, oneDAL implements various algorithms for data preprocessing, transformation, analysis, modeling, verification, and decision-making for data analysis in batch, online, and distributed processing modes of computation. In at least one embodiment, oneDAL implements various C++ and / or Java APIs and various connectors to one or more data sources. In at least one embodiment, oneDAL implements a DPC++ API extension to the legacy C++ interface, enabling GPU use for various algorithms. 【0315】 In at least one embodiment, the oneAPI deep neural network library, also known as oneDNN, is a library that implements various deep learning functions. In at least one embodiment, oneDNN implements various neural networks, machine learning, and deep learning functions, algorithms, and / or variations thereof. 【0316】 In at least one embodiment, the oneAPI collective communication library, also known as oneCCL, is a library that implements various applications for deep learning and machine learning workloads. In at least one embodiment, oneCCL is built on top of lower-level communication middleware such as the Message Passing Interface (MPI) and libfabric. In at least one embodiment, oneCCL enables a set of deep learning-specific optimizations, such as priority, persistent behavior, out-of-order execution, and / or variations thereof. In at least one embodiment, oneCCL implements various CPU and GPU capabilities. 【0317】 In at least one embodiment, the oneAPI threading building block library, also known as oneTBB, is a library that implements various parallelized processes for various applications. In at least one embodiment, oneTBB is used for task-based shared parallel programming on a host. In at least one embodiment, oneTBB implements a general parallel algorithm. In at least one embodiment, oneTBB implements a concurrent container. In at least one embodiment, oneTBB implements a scalable memory allocator. In at least one embodiment, oneTBB implements a work-stealing task scheduler. In at least one embodiment, oneTBB implements low-level synchronization primitives. In at least one embodiment, oneTBB is compiler-independent and usable on a variety of processors, including GPUs, PPUs, CPUs, and / or variations thereof. 【0318】 In at least one embodiment, the oneAPI video processing library, also known as oneVPL, is a library used to accelerate video processing in one or more applications. In at least one embodiment, oneVPL implements various video decoding, encoding, and processing functions. In at least one embodiment, oneVPL implements various functions for media pipelines on CPUs, GPUs, and other accelerators. In at least one embodiment, oneVPL implements device discovery and selection in media-centric and video analytics workloads. In at least one embodiment, oneVPL implements API primitives for zero-copy buffer sharing. 【0319】 In at least one embodiment, the oneAPI programming model utilizes the DPC++ programming language. In at least one embodiment, the DPC++ programming language is a programming language that includes, but is not limited to, a functionally similar version of the CUDA mechanism for defining device code and distinguishing device code from host code. In at least one embodiment, the DPC++ programming language may include a subset of the functionality of the CUDA programming language. In at least one embodiment, one or more CUDA programming model operations are performed using the oneAPI programming model that utilizes the DPC++ programming language. 【0320】 While the exemplary embodiments described herein may relate to CUDA programming models, it should be noted that the techniques described herein may be used with any preferred programming model, such as HIP, oneAPI (for example, using oneAPI-based programming to carry out or implement the methods disclosed herein), and / or variations thereof. 【0321】 In at least one embodiment, one or more components of the systems and / or processors disclosed above may communicate with one or more CPUs, ASICs, GPUs, FPGAs, or other hardware, circuit elements, or integrated circuit components, including, for example, an upscaler or upsampler for upscaling an image, an image blender or image blender component for blending, mixing, or adding images together, a sampler for sampling an image (for example, as part of a DSP), a neural network circuit configured to perform an upscaler for upscaling an image (for example, from a low-resolution image to a high-resolution image), or other hardware for modifying or generating an image, frame, or video to adjust its resolution, size, or pixels, and one or more components of the systems and / or processors disclosed above may use the components described herein to perform methods, operations, or instructions for generating or modifying an image. 【0322】 At least one embodiment of this disclosure may be described in consideration of the following clauses. 1. A processor comprising one or more circuits for implementing an Application Programming Interface ("API") to direct storage for storing information to be compressed. 2. The API indicates that the storage is intended to contain information that is compressible for transmission to circuit elements in the processing device, as described in Clause 1. 3. A processor as described in Clause 1 or 2, in which the implementation of the application programming interface specifies the storage area to be allocated. 4. A processor as described in any one of clauses 1 to 3, wherein information is compressed by a processing device, at least in part, based on instructions, for transmission to the L2 cache. 5. One or more circuits for causing the data to be stored in the page table to indicate that the storage has compressible data, as described in any one of the clauses 1 to 4 of the processor. 6. A processor according to any one of clauses 1 to 5, wherein compressed information is decompressed by a post-cache compression circuit element. 7. A processor described in any one of clauses 1 through 6, wherein the API functionality includes parameters for specifying the type of data compression to be used to compress information. 8. An application programming interface is a processor as described in any one of Clauses 1 to 7, which causes the processing unit to store compressed information in a cache and to decompress the information in order to send the information to client circuit elements of the cache. 9. One or more processors to implement APIs to direct storage for storing information to be compressed. A system that includes these features. 10. The API can be used to indicate that information is compressible for transmission between components of a processing device, as described in Clause 9 of the System. 11. The system described in Clause 9 or 10, in which information is compressed by a processing device, at least in part, based on instructions, for transmission to the processor cache. 12. A system as described in any one of clauses 9 to 11, in which the instruction indicates that an allocated block of memory contains data to be compressed for transmission between components. 13. A system according to any one of clauses 9 to 12, wherein compressed information is decompressed by a circuit element of a processing device. 14. A system as described in any one of clauses 9 to 13, wherein the API has at least one function or parameter for indicating the type of compression to be used to transmit information stored in storage. 15. If implemented by one or more processors, one or more processors shall have at least: Implementing an API to instruct storage to store information that should be compressed. A machine-readable medium that stores commands to perform an action. 16. The API can be used to indicate that information is compressible for transmission between components of a processing device, as described in Clause 15. 17. A machine-readable medium as described in Clause 15 or 16, on which a processing device compresses information stored in storage and transmits the compressed information to an L2 cache. 18. A machine-readable medium as described in any one of clauses 15 to 17, having an API that allocates blocks of storage for storing compressible information. 19. The API function includes parameters for indicating that data stored in storage may be compressed for transmission between components of a processing device, as described in any one of clauses 15 to 18. 20. If implemented by one or more processors, one or more processors shall have at least: The processing device causes information to be compressed, and the compressed information is sent to the cache. This causes the processing device to decompress the information for transmission to the client. A machine-readable medium, as described in any one of paragraphs 15 to 19, further storing the instructions to perform the actions. 21. At least one function or parameter for indicating the type of compression to be used to transmit information stored in storage, as described in any one of clauses 15 to 20 of the machine-readable media. 22. A step of providing an API to instruct storage to store information that should be compressed by the processing device. Methods that include... 23. A step to provide functionality in the API to indicate that information may be compressed before it is transmitted between components of the processing device. The method described in Clause 22, further including the method described in Clause 22. 24. A step to compress information in response to instructions, The steps include sending the compressed information to the L2 cache and The method described in Clause 22 or 23, further including the method described in Clause 22 or 23. 25. The method of any one of the clauses 22 to 24, wherein the instruction includes data indicating that an allocated block of memory is for containing data to be compressed for transmission between components of a processing device. 26. The method described in any one of the clauses 22 to 25, wherein the API function includes parameters for specifying the type of compression. 27. The step of storing the compressed information in the cache, A step of decompressing compressed information, wherein the decompressed information is decompressed before transmitting the decompressed information to the components of the processing device. The method described in any one of the clauses 22 to 26, further including the method described in any one of the clauses 22 to 26. 28. A step of providing a memory allocation function for allocating memory by an API, wherein the contents of the memory should be compressed in response to the initiation of transmissions between components of a processing device. The method described in any one of the clauses 22 to 27, further including the method described in any one of the clauses 22 to 27. 【0323】 Other variations are within the scope of this disclosure. Thus, the disclosed techniques can be modified and constructed in various ways, several exemplary embodiments of which are shown in the drawings and described in detail above. However, it should be understood that this disclosure is not intended to limit itself to any particular one or more disclosed forms, but rather to encompass all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the disclosure, as defined in the appended claims. 【0324】 In the context describing the disclosed embodiments (particularly in the context of the following claims), the terms “a,” “an,” and “the,” and similar demonstrative pronouns, should be interpreted as encompassing both singular and plural, and not as definitions of terms, unless otherwise stated herein or clearly refuted by the context. The terms “comprising,” “having,” “including,” and “containing” should be interpreted as open-ended terms (meaning “including, but not limited to,”) unless otherwise stated. The term “connected,” when unmodified and referring to a physical connection, should be interpreted as being partially or completely contained, attached, or joined to one another, even if there is something intervening. The detailing of ranges of values ​​herein is merely intended to serve as a concise way of individually referring to each distinct value that falls within a range, unless otherwise stated herein and unless each distinct value is incorporated into the specification as if it were individually detailed herein. The use of the terms “set” (for example, “set of items”) or “subset” should be interpreted as a non-empty set comprising one or more members, unless otherwise stated or denied by the context. Furthermore, unless otherwise stated or denied by the context, the term “subset” of a corresponding set does not necessarily refer to a strict subset of the corresponding set, and a subset and a corresponding set can be equivalent. 【0325】 Combinations such as “at least one of A, B, and C” or “at least one of A, B, and C” are understood in contexts generally used to indicate that an item, term, etc., can be either A, B, or C, or any non-empty subset of the set of A, B, and C, unless otherwise specifically stated or explicitly denied by the context. For example, in a descriptive example of a set having three members, the combinations “at least one of A, B, and C” and “at least one of A, B, and C” refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such combinations do not imply as a whole that some embodiments require the presence of each of A, B, and C. Furthermore, unless otherwise stated or negated by the context, the term "plurality" refers to the state of being multiple (for example, "a plurality of items" refers to multiple items). The number of items that are plural is at least two, but can be more when explicitly or by contextual indication. Furthermore, unless otherwise stated or clarified by the context, the phrase "based on" means "at least partially based on," and does not mean "based solely on." 【0326】 The operation of the processes described herein may be carried out in any preferred order unless otherwise stated herein or explicitly refuted by the context. In at least one embodiment, a process such as the process described herein (or its variations and / or combinations thereof) is carried out under the control of one or more computer systems consisting of executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs, or one or more applications) that is executed collectively on one or more processors, by hardware, or by a combination thereof. In at least one embodiment, the code is stored in a computer-readable storage medium, for example, in the form of a computer program comprising multiple instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-temporary computer-readable storage medium that excludes temporary signals (e.g., transient electrical or electromagnetic transmissions that propagate) but includes non-temporary data storage circuit elements (e.g., buffers, caches, and queues) in transceivers for temporary signals. In at least one embodiment, code (e.g., executable code or source code) is stored in a set of one or more non-temporary computer-readable storage media that, when executed by one or more processors of a computer system (e.g., as a result of execution), causes the computer system to perform the operations described herein (or has other memory for storing executable instructions). In at least one embodiment, the set of non-temporary computer-readable storage media comprises a plurality of non-temporary computer-readable storage media, where one or more of the individual non-temporary storage media of the plurality of non-temporary computer-readable storage media do not contain all of the code, but the plurality of non-temporary computer-readable storage media collectively contain all of the code.In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors, for example, a non-temporary computer-readable storage medium stores the instructions, the main central processing unit ("CPU") executes some of the instructions, and the graphics processing unit ("GPU") executes others. In at least one embodiment, different components of a computer system have separate processors, and different processors execute different subsets of instructions. 【0327】 Accordingly, in at least one embodiment, the computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system consists of applicable hardware and / or software that enables the performance of the operations. Furthermore, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment, a distributed computer system comprising multiple devices operating in different ways so that the distributed computer system performs the operations described herein and the single device does not perform all of the operations. 【0328】 Any use of any examples or illustrative language provided herein (e.g., "such as") is intended solely to further illustrate the embodiments of this disclosure and, unless otherwise asserted, does not limit the scope of this disclosure. Nothing in this specification should be construed as indicating any unclaimed element as essential to the practice of this disclosure. 【0329】 All references cited herein, including publications, patent applications, and patents, are incorporated herein by reference to the same extent as if they were included herein in their entirety, provided that each reference is clearly indicated by individual reference. 【0330】 In the specification and claims, the terms “joined” and “connected” may be used together with their derivatives. It should be understood that these terms may not be intended to be synonymous with one another. Rather, in certain instances, “connected” or “joined” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with one another. “Joined” may also mean that two or more elements are not in direct contact with one another, but still interact or communicate with one another. 【0331】 Unless otherwise specifically stated, throughout this specification, terms such as “processing,” “computing,” “calculating,” or “determining” should be understood to refer to actions and / or processes of a computer or computing system, or similar electronic computing device, that manipulate and / or transform data, represented as electronic or other physical quantities, in the registers and / or memory of the computing system, into other data, similarly represented as physical quantities in the memory, registers, or other such information storage, transmission, or display device of the computing system. 【0332】 Similarly, the term “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data that can be stored in registers and / or memory. In non-limiting examples, “processor” may be a CPU or a GPU. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Each process may also refer to multiple processes for executing instructions serially or in parallel, continuously or intermittently. The terms “system” and “method” are used interchangeably herein only if one or more methods can be embodied by a system, and a method can be considered a system. 【0333】 In at least one embodiment, an arithmetic logic unit is a set of combinational logic circuit elements that take one or more inputs to produce a result. In at least one embodiment, an arithmetic logic unit is used by a processor to implement mathematical operations such as addition, subtraction, or multiplication. In at least one embodiment, an arithmetic logic unit is used to implement logical operations such as logical AND / OR or XOR. In at least one embodiment, an arithmetic logic unit is made from physically switching components, such as semiconductor transistors that are stateless and configured to form logic gates. In at least one embodiment, an arithmetic logic unit may operate internally as a stateful logic circuit with an associated clock. In at least one embodiment, an arithmetic logic unit may be constructed as an asynchronous logic circuit with internal state that is not maintained in an associated set of registers. In at least one embodiment, an arithmetic logic unit is used by a processor to combine operands stored in one or more registers of the processor to produce an output that can be stored by the processor in another register or memory location. 【0334】 In at least one embodiment, as a result of processing an instruction retrieved by the processor, the processor presents one or more inputs or operands to an arithmetic logic unit, causing the arithmetic logic unit to produce a result based at least in part on the instruction code provided to the input of the arithmetic logic unit. In at least one embodiment, the instruction code provided to the ALU by the processor is based at least in part on an instruction executed by the processor. In at least one embodiment, the combinational logic in the ALU processes the inputs and produces an output that is placed on a bus within the processor. In at least one embodiment, the processor selects a destination register, memory location, output device, or output storage location on the output bus so that the result produced by the ALU is sent to a desired location by clocking the processor. 【0335】 This specification may refer to acquiring, obtaining, receiving, or inputting analog or digital data into subsystems, computer systems, or computer-implemented machines. The process of acquiring, obtaining, receiving, or inputting analog and digital data can be implemented in various ways, such as by receiving data as parameters to function calls or calls to application programming interfaces. In some implementations, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be implemented by transferring data via serial or parallel interfaces. In other implementations, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be implemented by transferring data via a computer network from a providing entity to a receiving entity. It may also refer to providing, outputting, transmitting, sending out, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending out, or presenting analog or digital data can be implemented by transferring data as input or output parameters to function calls, application programming interfaces, or parameters to inter-process communication mechanisms. 【0336】 While the above description outlines exemplary implementations of the techniques described, other architectures may be used to implement the described functionality and are intended to be within the scope of this disclosure. Furthermore, although specific distributions of responsibility are defined above for illustrative purposes, various functions and responsibilities may be distributed and divided in different ways depending on the context. 【0337】 Furthermore, while the subject matter is described in language specific to structural features and / or methodological actions, it should be understood that the subject matter claimed in the attached claims is not necessarily limited to the described specific features or actions. Rather, the specific features and actions are disclosed as exemplary forms that implement the claims.

Claims

[Claim 1] It comprises one or more circuits for implementing an application programming interface ("API") to direct storage for storing information to be compressed, Both the L2 cache and other caches are capable of storing compressed information. When transmitting the aforementioned information to the L2 cache, the information is compressed by the processing device based at least partially on the instructions. A processor in which a processing unit is used by the application programming interface when storing the compressed information in the L2 cache. [Claim 2] The processor according to claim 1, wherein the API indicates that the storage is intended to contain information that can be compressed for transmission to circuit elements in a processing device. [Claim 3] The processor according to claim 1, wherein the implementation of the application programming interface specifies the area of ​​the storage to be allocated. [Claim 4] The processor according to claim 1, wherein the one or more circuits cause the data to be stored in the page table to include data that the storage can compress. [Claim 5] The processor according to claim 1, wherein the compressed information is decompressed by a post-cache compression circuit element. [Claim 6] The processor according to claim 1, wherein the API function includes parameters for indicating the type of data compression to be used to compress the information. [Claim 7] The processor according to claim 1, wherein the application programming interface causes a processing unit to decompress the information in order to transmit the information to a client circuit element of the cache. [Claim 8] One or more processors to implement APIs to direct storage for storing information to be compressed. Equipped with, Both the cache and the processor cache are capable of storing compressed information. When transmitting the aforementioned information to the processor cache, the information is compressed by the processing device based at least partially on the instructions. A system in which a processing unit is used by the API when storing the compressed information in the cache. [Claim 9] The system according to claim 8, wherein the API can be used to indicate that the information is compressible for transmission between components of a processing device. [Claim 10] The system according to claim 8, wherein the instruction indicates that an allocated block of memory contains data to be compressed for transmission between components. [Claim 11] The system according to claim 8, wherein the compressed information is decompressed by a circuit element of a processing device. [Claim 12] The system according to claim 8, wherein the API comprises at least one of a function or parameter for indicating the type of compression to be used to transmit the information stored in the storage. [Claim 13] A system comprising one or more processors and a machine-readable medium, When the machine-readable medium is implemented by the one or more processors, the one or more processors provide at least the following: Implement an API to instruct storage to store information that should be compressed. It stores the command to perform the action, Both the L2 cache and other caches are capable of storing compressed information. When transmitting the aforementioned information to the L2 cache, the information stored in the storage is compressed by the processing device. A system in which a processing unit is used by the API when storing the compressed information in the L2 cache. [Claim 14] The system according to claim 13, wherein the API can be used to indicate that the information is compressible for transmission between components of a processing device. [Claim 15] The system according to claim 13, wherein the API has a function for allocating storage blocks for storing compressible information. [Claim 16] The system according to claim 13, wherein the API function includes parameters for indicating that data stored in the storage can be compressed for transmission between components of a processing device. [Claim 17] When the machine-readable medium is implemented by the one or more processors, the one or more processors provide at least: The processing device causes the information to be decompressed for transmission to the client. The system according to claim 13, further storing commands to perform the following actions. [Claim 18] The system according to claim 13, wherein the API comprises at least one of a function or parameter for indicating the type of compression to be used to transmit the information stored in the storage. [Claim 19] Steps to instruct the processing device via API to specify storage for storing information to be compressed. Includes, Both the L2 cache and other caches are capable of storing compressed information. The processing device performs the steps of compressing the information in response to the instruction, The processing device transmits the compressed information to the L2 cache. This further includes, A method further comprising the step of storing compressed information in the L2 cache by a processing unit. [Claim 20] The API instructs that the information may be compressed before it is transmitted between the components of the processing device. The method according to claim 19, further comprising: [Claim 21] The method according to claim 19, wherein the instruction includes data indicating that an allocated block of memory is for containing data to be compressed for transmission between components of the processing device. [Claim 22] The method according to claim 19, wherein the API function includes parameters for indicating the type of compression. [Claim 23] A step of decompressing the compressed information, wherein the decompressed information is decompressed before transmitting the decompressed information to the components of the processing device. The method according to claim 19, further comprising: [Claim 24] The steps include providing a memory allocation function for allocating memory using the API, wherein the contents of the memory are to be compressed in response to the initiation of transmission between components of the processing device, and The method according to claim 19, further comprising:

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