Interposer manufacturing method

Abstract

To provide a manufacturing method for interposers that reduces manufacturing costs. [Solution] A method for manufacturing an interposer 1, comprising: a through-hole forming step of forming through-holes 14 in a substrate 10; an insulating film forming step of forming an insulating film 12; a barrier seed layer forming step of forming a barrier seed layer 13 on the formed insulating film 12; a photoresist pattern forming step of forming a photoresist pattern 18 on the upper surface 15 and lower surface 16 of the substrate 10 on which the barrier seed layer 13 is formed; and an electroplating step of performing electroplating on the substrate 10 on which the photoresist pattern 18 is formed, thereby forming plated copper 19 on the barrier seed layer 13 on the upper surface 15 and lower surface 16 of the substrate 10, and simultaneously forming or filling plated copper 20 on the barrier seed layer 13 on the inner wall surface 17 of the through-holes 14.

Description

Technical Field

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[0001] The present invention relates to a method for manufacturing an interposer.

Background Art

[0002] An interposer is interposed between a semiconductor element and a mounting substrate and is used for the purpose of electrically connecting these electronic components.

[0003] Currently, there are silicon interposers, glass interposers, and organic interposers for interposers; silicon interposers enable fine processing, glass interposers enable adjustment of the thermal expansion coefficient, and organic interposers have the advantage of being able to be manufactured at low cost.

[0004] In a silicon interposer, through electrodes for electrically connecting wiring between both sides of the interposer are provided. At that time, through holes are provided in the silicon substrate of the interposer, and after filling the through holes with a conductive metal by plating or the like, lead-out wiring is formed on the front and back surfaces of the silicon interposer in a separate process (see Patent Document 1 and Patent Document 2).

[0005] For example, Patent Document 1 describes a method for manufacturing a silicon interposer including a step of forming through electrodes and a step of forming electrodes serving as lead-out wiring on both sides of a silicon wafer, but these steps are performed in separate processes.

[0006] Also, regarding Patent Document 2, a method for manufacturing an interposer including a step of forming through electrodes and a step of forming a conductive layer by performing electroless plating and electrolytic copper plating in sequence on the upper and lower ends of the through electrodes is described, but regarding Patent Document 2 as well, the step of forming through electrodes and the step of forming a conductive layer serving as lead-out wiring are described as separate steps.

Prior Art Documents

Patent Documents

[0007] [Patent Document 1] Japanese Patent Publication No. 2009-277895 [Patent Document 2] Japanese Patent Publication No. 2019-54290 [Overview of the project] [Problems that the invention aims to solve]

[0008] However, in conventional technology, the through-electrode formation process and the lead-out wiring formation process are carried out separately, and this increase in the number of processes leads to an increase in the manufacturing cost of the interposer.

[0009] Therefore, the present invention provides a method for manufacturing an interposer that reduces manufacturing costs. [Means for solving the problem]

[0010] A method for manufacturing an interposer according to one aspect of the present invention is a method for manufacturing an interposer which is a relay member for electrically connecting different semiconductor chips, Made of silicon On the circuit board The diameter is 10 μm to 20 μm, and the depth is 50 μm to 100 μm. A method for manufacturing an interposer, comprising: a through-hole forming step of forming through-holes; an insulating film forming step of forming insulating films on the upper surface, lower surface, and inner wall surface of the through-holes of the substrate; a barrier seed layer forming step of forming a barrier seed layer on the insulating films formed on the upper surface, lower surface, and inner wall surface of the through-holes of the substrate; a photoresist pattern forming step of forming a photoresist pattern on the upper and lower surfaces of the substrate on which the barrier seed layer is formed; an electroplating step of performing electroplating on the substrate on which the photoresist pattern is formed to form plated copper on the barrier seed layers on the upper and lower surfaces of the substrate and simultaneously to form plated copper on the barrier seed layers on the inner wall surface of the through-holes of the substrate; and a photoresist pattern removal step of removing at least the photoresist pattern from the substrate after the electroplating step. [Effects of the Invention]

[0011] This invention makes it possible to manufacture interposers at a reduced manufacturing cost. [Brief explanation of the drawing]

[0012] [Figure 1] Figure 1 is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment. [Figure 2] Figure 2 is a cross-sectional view showing the configuration of an interposer according to an embodiment. [Figure 3] Figure 3 is a diagram showing a method for manufacturing an interposer according to an embodiment. [Modes for carrying out the invention]

[0013] The embodiments will be described in detail below with reference to the drawings. Note that the embodiments described below are all general or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit the present invention. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components.

[0014] Please note that each figure is a schematic diagram and not necessarily a strictly accurate representation. Furthermore, in each figure, substantially identical components are denoted by the same reference numerals, and redundant explanations may be omitted or simplified.

[0015] (Configuration of semiconductor device 100) Figure 1 is a cross-sectional view showing the configuration of a semiconductor device 100 according to an embodiment. As shown in Figure 1, the semiconductor device 100 comprises a circuit board 25, a package substrate 30, an interposer 1, and semiconductor chips 40, 50, and 60.

[0016] The circuit board 25 is a substrate on which the package board 30 is mounted, and is, for example, a resin substrate or a ceramic substrate.

[0017] The package substrate 30 is mounted on the circuit board 25 and is a substrate that improves the mountability of the semiconductor chips 40, 50, and 60 to the circuit board 25. The package substrate 30 has wirings 31 inside and external connection terminals 32 such as solder balls on the lower surface, and is used for electrical connection with the circuit board 25. Further, the package substrate 30 constitutes a resin package (not shown) that seals the mounted interposer 1 and the upper surfaces and side surfaces of the semiconductor chips 40, 50, and 60 with a resin material. The package is, for example, a hybrid IC package.

[0018] The interposer 1 is an intermediate member that is mounted on the package substrate 30 and electrically connects the package substrate 30 and the semiconductor chips 40, 50, and 60. The interposer 1 includes through electrodes 11 and electrically connects the semiconductor chips 40, 50, and 60 provided on the upper part of the interposer 1 and the package substrate 30 provided on the lower part of the interposer 1. Further, the interposer 1 includes external connection terminals and relays the electrical connection between the semiconductor chips 40, 50, and 60 and the package substrate 30.

[0019] The semiconductor chips 40, 50, and 60 are active elements that are mounted on the interposer 1. The semiconductor chips 40, 50, and 60 are, for example, a CPU, a GPU, a memory (DRAM, SRAM, flash memory, etc.), an ASIC, and an FPGA. The semiconductor chips 40, 50, and 60 each have micro bumps 41, 51, and 61 on the lower surface and are electrically connected to the interposer 1 through the micro bumps.

[0020] (Configuration of Interposer 1) FIG. 2 is a cross-sectional view showing the configuration of the interposer 1 according to the embodiment.

[0021] As shown in FIG. 2, the interposer 1 according to the present embodiment includes a substrate 10, through electrodes 11, an insulating film 12, a barrier seed layer 13, upper surface wirings 21, and lower surface wirings 22. In this figure, the external connection terminals provided at the lower part of the interposer 1 shown in FIG. 1 are omitted.

[0022] The substrate 10 is a substrate mainly composed of silicon, glass, or resin, but it is not necessarily mainly composed of the above materials.

[0023] The through electrodes 11 are formed of a conductive material and electrically connect the upper surface wirings 21 and the lower surface wirings 22. As the conductive material for forming the through electrodes 11, the upper surface wirings 21, and the lower surface wirings 22, for example, any single metal such as copper, silver, gold, nickel, platinum, palladium, ruthenium, tin, silver tin, silver tin copper, tin copper, tin bismuth, or tin lead, or any laminate or compound of any single metal can be used, and a material with high adhesion to the inorganic adhesion layer and high electrical connection stability can be selected.

[0024] Further, as the conductive material for forming the through electrodes 11, for example, a conductive paste that is a mixture of at least one metal powder and a resin material among the above-described materials can also be used.

[0025] The insulating film 12 is a film formed along the surface of the substrate 10 to cut off the electrical connection between the substrate 10 and the through electrodes 11 and make the through electrodes 11 independent electrical paths. When the substrate 10 is formed of silicon, the insulating film 12 made of SiO2 can be formed by oxidizing the surface of the substrate 10. The oxidation method of the substrate 10 is, for example, thermal oxidation. When the substrate 10 is formed of resin, the insulating film 12 can be formed by a chemical vapor deposition (CVD) method or a sputtering method.

[0026] The barrier seed layer 13 is a layer formed along the surface of the insulating film 12 in order to form the through-electrode 11, upper wiring 21, and lower wiring 22 of the interposer 1 by electroplating, using the barrier seed layer 13 as an electrode. The barrier seed layer 13 can be formed by depositing Ti and Cu films, or by electroless Cu plating.

[0027] The upper wiring 21 is made of a conductive material, is formed on the upper surface 15 of the interposer 1, and is connected to the upper end of the through electrode 11.

[0028] The lower wiring 22 is made of a conductive material, is formed on the lower surface 16 of the interposer 1, and is connected to the lower end of the through electrode 11.

[0029] Furthermore, in this figure, the through electrodes 11 are electrically connected to each other by the upper wiring 21 or the lower wiring 22, but it is not necessary for multiple through electrodes 11 to be electrically connected to each other.

[0030] (Manufacturing method for interposer 1) Figure 3 is a diagram showing a method for manufacturing the interposer 1 according to an embodiment. The method for manufacturing the interposer 1 according to this embodiment includes the following steps.

[0031] Figure 3(a) shows the substrate 10 before processing.

[0032] First, as shown in Figure 3(b), through holes 14 are formed in the substrate 10 (through hole formation step).

[0033] When the substrate 10 is made of silicon, it is preferable to use deep reactive ion etching (DRIE) to form the through holes 14. DRIE can form through holes with a high aspect ratio. When the substrate 10 is made of glass or resin, CO2 lasers, UV lasers, photosensitive gases, blasting, etc., can be used, and the method should be selected based on the thickness of the substrate 10 and the diameter of the through holes 14.

[0034] The diameter of the through-hole 14 can be, for example, 10 μm to 20 μm, and its depth can be, for example, 50 μm to 100 μm.

[0035] Next, as shown in Figure 3(c), an insulating film 12 is formed on the upper surface 15, the lower surface 16 of the substrate 10 in which the through-hole 14 is formed, and on the inner wall surface 17 of the through-hole 14 (insulating film formation step).

[0036] When the substrate 10 is made of silicon, thermal oxidation is preferably used to form the insulating film 12. Thermal oxidation allows for the uniform formation of an SiO2 film on the surface of the substrate 10. Thermal oxidation is carried out, for example, at 900 to 1200°C.

[0037] The thickness of the insulating film 12 can be, for example, 0.2 μm to 0.3 μm.

[0038] Next, as shown in Figure 3(d), a barrier seed layer 13 is formed on the insulating film 12 formed on the upper surface 15, the lower surface 16, and the inner wall surface 17 of the through hole 14 of the substrate 10 (barrier seed layer formation step).

[0039] The barrier seed layer 13 functions as a power supply layer in the subsequent electroplating step and also plays a role in improving the adhesion between the insulating film 12 and the electroplating layer.

[0040] As a method for forming the barrier seed layer 13, film deposition of Ti and Cu, or electroless Cu plating can be used.

[0041] When depositing Ti and Cu films, first a Ti layer is formed by sputtering, and then a Cu layer is formed. The thickness of the Ti layer is, for example, 50 nm, and the thickness of the Cu film is, for example, 300 nm.

[0042] When electroless plating is used, a Cu layer is formed on the front surface of the substrate 10 by a chemical reaction. The thickness of the electroless plating can be, for example, 50 nm to 100 nm.

[0043] Next, as shown in Figure 3(e), a photoresist is applied to the upper surface 15 and lower surface 16 of the substrate 10 on which the barrier seed layer 13 is formed, and a photoresist pattern 18 is formed by patterning through a mask (photoresist pattern formation step).

[0044] Specifically, a liquid or dry film photoresist pattern is not formed on the inner wall surface 17 of the through-hole 14 of the substrate 10. This allows the plated copper 20 to be filled into the through-hole 14 in the next electroplating step.

[0045] Next, as shown in Figure 3(f), electroplating is performed on the substrate 10 on which the photoresist pattern 18 is formed, thereby forming plated copper 19 on the barrier seed layer 13 (openings of the photoresist pattern 18) on the upper surface 15 and lower surface 16 of the substrate 10, and at the same time filling the inner wall surface 17 of the through hole 14 with plated copper 20 (electroplating step). Electroplating is carried out, for example, using a copper sulfate plating bath, with the barrier seed layer 13 acting as the power supply layer.

[0046] In detail, during the electroplating step, the copper plate is first connected to a DC power supply or pulsed power supply as the anode and the intermediate product after the photoresist pattern formation step as the cathode, and the copper plate and the intermediate product after the photoresist pattern formation step are immersed in a bath containing the plating solution. The plating solution contains, for example, additives (suppressor, accelerator, leveler). The intermediate product after the photoresist pattern formation step is fixed with a jig so as not to be in close contact with the bottom of the bath and immersed in the plating solution. Here, the intermediate product after the photoresist pattern formation step may be immersed in the plating solution so that its upper surface 15 and lower surface 16 are perpendicular to the ground, or it may be immersed so that it is parallel to the ground.

[0047] Through electroplating, plated copper 19 is formed in the openings of the photoresist pattern 18 on the upper surface 15 to form upper surface wiring 21, and in the openings of the photoresist pattern 18 on the lower surface 16 to form lower surface wiring 22, while simultaneously filling the through holes 14 with plated copper 20. The plated copper 19 also becomes the through-electrode 11 of the interposer 1.

[0048] The thickness of the plated copper 19 and 20 can be, for example, 2 μm to 3 μm. Depending on the size of the through hole 14, the plated copper can be formed to completely fill the through hole 14 or along the inner wall surface 17.

[0049] Next, as shown in Figure 3(g), the photoresist pattern 18 is removed from the substrate 10 after the electroplating step (photoresist pattern removal step). The photoresist pattern 18 can be removed by chemical stripping using a stripping solution.

[0050] Finally, as shown in Figure 3(h), the barrier seed layer 13 attached to the location where the photoresist pattern 18 was formed is also removed (barrier seed layer removal step). That is, the barrier seed layer 13 in the area where the wiring pattern is not formed is etched off.

[0051] The barrier seed layer 13 can be etched, for example, by wet etching using a ferric chloride solution, or by dry etching such as ion milling or sputter etching. This step electrically isolates the wiring pattern and forms the upper wiring 21 and lower wiring 22.

[0052] The barrier seed layer formation step, photoresist pattern formation step, photoresist pattern removal step, and barrier seed layer removal step may be performed simultaneously on the upper surface 15 and the lower surface 16, or they may be performed sequentially.

[0053] [Effects, etc.] The following describes examples of embodiments that can be obtained from the disclosures of this specification, and explains the effects and other benefits that can be obtained from these examples.

[0054] Embodiment 1 is a method for manufacturing an interposer 1, which is a relay member for electrically connecting different semiconductor chips 40, comprising: a through-hole forming step of forming through holes 14 in a substrate 10; an insulating film forming step of forming an insulating film 12 on the upper surface 15, lower surface 16 of the substrate 10 where the through holes 14 are formed, and on the inner wall surface 17 of the through holes 14; a barrier seed layer forming step of forming a barrier seed layer 13 on the insulating film 12 formed on the upper surface 15, lower surface 16 of the substrate 10 and on the inner wall surface 17 of the through holes 14; and a photoresist on the upper surface 15 and lower surface 16 of the substrate 10 where the barrier seed layer 13 is formed. The method for manufacturing an interposer 1 includes a photoresist pattern formation step of forming a photoresist pattern 18; an electroplating step of performing electroplating on the substrate 10 on which the photoresist pattern 18 is formed, thereby forming plated copper 19 on the barrier seed layer 13 on the upper surface 15 and lower surface 16 of the substrate 10, and simultaneously forming or filling plated copper 20 on the barrier seed layer 13 on the inner wall surface 17 of the through hole 14; and a photoresist pattern removal step of removing at least the photoresist pattern 18 from the substrate 10 after the electroplating step.

[0055] In the electroplating step, depressions occur on the surface of the plated copper 19, specifically in the areas directly above and below the through-holes 14 of the upper and lower wiring 21 and 22. Therefore, the depressions on the upper and lower surfaces 15 and 16 of the interposer 1 may be removed. One method for removing the depressions is chemical mechanical polishing (CMP).

[0056] This method for manufacturing the interposer 1 includes an electroplating step in which plated copper 19 is formed on the barrier seed layer 13 on the upper surface 15 and lower surface 16 of the substrate 10, while simultaneously forming plated copper 20 on the barrier seed layer 13 on the inner wall surface 17 of the through hole 14. Therefore, a method for manufacturing the interposer 1 that reduces the number of steps and thus the manufacturing cost can be reduced.

[0057] Embodiment 2 is a method for manufacturing the interposer 1 of Embodiment 1, wherein the substrate 10 is made of silicon, and in the through-hole formation step, through-holes 14 are formed by deep reactive ion etching.

[0058] This method of manufacturing the interposer 1 employs deep reactive ion etching, which allows for the formation of high aspect ratio through-holes 14 in a silicon substrate 10.

[0059] Embodiment 3 is a method for manufacturing the interposer 1 according to Embodiment 1 or 2, wherein the substrate 10 is made of silicon, and in the insulating film formation step, an insulating film 12 is formed by thermal oxidation.

[0060] This method of manufacturing the interposer 1 allows for the formation of the insulating film 12 through a simple process.

[0061] Embodiment 4 is a method for manufacturing the interposer 1 according to Embodiment 1 or 2, wherein in the barrier seed layer formation step, a barrier seed layer 13 is formed by depositing Ti and Cu films by sputtering or by electroless Cu plating.

[0062] In this method of manufacturing the interposer 1, the plated copper 19 and 20 can be easily filled into the barrier seed layer 13 and the inner wall surface 17 of the through hole 14 during the electroplating step.

[0063] Embodiment 5 is a method for manufacturing the interposer 1 according to Embodiment 1 or 2, wherein in the photoresist pattern removal step, in addition to the photoresist pattern 18, the barrier seed layer 13 located below the photoresist pattern 18 is also removed.

[0064] This method of manufacturing the interposer 1 can form the desired wiring pattern. [Industrial applicability]

[0065] The method for manufacturing the interposer 1 according to the present invention can be used in the field of semiconductor device manufacturing. [Explanation of Symbols]

[0066] 1 Interposer 10 circuit boards 11 Through electrode 12 Insulating film 13. Barrier Seed Layer 14 Through holes 15 Top side 16 Bottom side 17 Interior wall surface 18 Photoresist Patterns 19, 20 Plated copper 21 Top wiring 22 Bottom wiring 25 Circuit boards 30 Package substrates 31 Wiring 32 External connection terminals 40, 50, 60 semiconductor chips 100 Semiconductor Equipment

Claims

1. A method for manufacturing an interposer, which is a relay member for electrically connecting different semiconductor chips, A through-hole formation step in which through-holes having a diameter of 10 μm to 20 μm and a depth of 50 μm to 100 μm are formed in a silicon substrate, An insulating film forming step of forming an insulating film on the upper surface, lower surface, and inner wall surface of the through hole formed on the substrate, A barrier seed layer formation step, in which a barrier seed layer is formed on the insulating film formed on the upper surface, lower surface, and inner wall surface of the through hole of the substrate, A photoresist pattern forming step in which a photoresist pattern is formed on the upper and lower surfaces of the substrate on which the barrier seed layer is formed, The electroplating step involves applying electroplating to the substrate on which the photoresist pattern is formed, thereby forming plated copper on the barrier seed layer on the upper and lower surfaces of the substrate, and simultaneously forming plated copper on the barrier seed layer on the inner wall surface of the through hole. The process includes, after the electroplating step, a photoresist pattern removal step of removing at least the photoresist pattern from the substrate, A method for manufacturing an interposer.

2. In the through-hole formation step, the through-hole is formed by deep reactive ion etching. A method for manufacturing an interposer according to claim 1.

3. In the insulating film formation step, the insulating film is formed by thermal oxidation. A method for manufacturing an interposer according to claim 1 or 2.

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