Photoelectric conversion devices and equipment

Abstract

To provide a technique advantageous to improve characteristics of a photoelectric conversion device.SOLUTION: A photoelectric conversion device includes: a pixel circuit in which a plurality of pixels are arranged; a plurality of ramp signal lines to which ramp signals having different gradients are supplied; and an AD conversion part in which a plurality of AD conversion circuits including a first AD conversion circuit and a second AD conversion circuit adjacent to each other are arranged. Each of the plurality of AD conversion circuits includes: a selection circuit which selects a ramp signal line so as to select a ramp signal to be used for AD conversion among the plurality of ramp signals; a comparison circuit which compares the ramp signal selected by the selection circuit and a pixel signal from the pixel; and a supply line which supplies the ramp signal from the selection circuit to the comparison circuit. The supply line includes a first portion extending from the comparison circuit and a second portion for connecting the first portion and the selection circuit. A wiring region in which the supply line is arranged includes a region in which the second portion provided in the first AD conversion circuit or the first portion provided in the second AD conversion circuit is arranged between the first portion provided in the first AD conversion circuit and the second portion provided in the second AD conversion circuit.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a photoelectric conversion device and equipment.

Background Art

[0002] With the increase in pixel count and frame rate of television standards, even in a photoelectric conversion device that captures television images, high pixel count and high frame rate of recordable images are required. To achieve this requirement, high speed of the analog-to-digital converter (ADC) of the photoelectric conversion device is demanded. Furthermore, not only high pixel count and high frame rate but also expansion of the dynamic range are important elements in image representation. Patent Document 1 discloses an imaging device capable of improving the dynamic range without increasing the time taken for AD conversion by supplying ramp signals with different slopes to the ADC according to the magnitude of the signal obtained by the pixel.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] For high frame rate, it is conceivable to provide a plurality of ADCs for each pixel column and simultaneously perform signal processing on signals output from pixels in a plurality of rows. When a plurality of ADCs are provided for each pixel column, unintended coupling capacitance may occur between the wiring patterns for inputting signals to the ADCs among the ADCs arranged at high density. When ramp signals with different slopes are supplied to adjacent ADCs, if the ramp signals with different slopes affect each other through the coupling capacitance, the slope of the ramp signal changes and the AD conversion gain changes. As a result, the image quality of the obtained image may deteriorate.

[0005] The present invention aims to provide a technology that is advantageous for improving the characteristics of photoelectric conversion devices. [Means for solving the problem]

[0006] In view of the above problems, a photoelectric conversion device according to an embodiment of the present invention comprises: a pixel circuit in which a plurality of pixels are arranged to constitute a plurality of rows and a plurality of columns; a plurality of lamp signal lines to which lamp signals with different inclinations are supplied; and an AD conversion unit in which a plurality of AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, wherein each of the plurality of AD conversion circuits includes a selection circuit that selects a lamp signal line to be used for AD conversion from among the plurality of lamp signal lines, and the selection circuit The device includes a comparison circuit that compares a selected lamp signal with a pixel signal from a pixel, and a supply line that supplies the lamp signal from the selection circuit to the comparison circuit, wherein the supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit, and the wiring region in which the supply line is arranged includes a region between the first portion of the first AD conversion circuit and the second portion of the second AD conversion circuit in which the second portion of the first AD conversion circuit or the first portion of the second AD conversion circuit is arranged. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a technology that is advantageous for improving the characteristics of photoelectric conversion devices. [Brief explanation of the drawing]

[0008] [Figure 1] A block diagram showing an example configuration of the photoelectric conversion device of this embodiment. [Figure 2] Figure 1 shows an example of the configuration of the AD conversion circuit of the photoelectric converter. [Figure 3] Figure 1 shows an example of the configuration of the AD conversion circuit of the photoelectric converter. [Figure 4]Figure 1 shows an example of the operation of the AD conversion circuit of the photoelectric converter. [Figure 5] Figure 1 shows an example layout of the AD conversion circuit of the photoelectric converter. [Figure 6] This figure shows an example of a wiring pattern layout for supplying the lamp signal to the AD conversion circuit of the photoelectric converter shown in Figure 1. [Figure 7] Figure 1 shows an example of the configuration of the AD conversion circuit of the photoelectric converter. [Figure 8] Figure 1 shows an example of the operation of the AD conversion circuit of the photoelectric converter. [Figure 9] Figure 1 shows an example of the configuration of the AD conversion circuit of the photoelectric converter. [Figure 10] This figure shows an example of the configuration of a device incorporating the photoelectric converter shown in Figure 1. [Modes for carrying out the invention]

[0009] The embodiments will be described in detail below with reference to the attached drawings. Note that the following embodiments do not limit the invention as defined in the claims. While the embodiments describe multiple features, not all of these features are essential to the invention, and the features may be combined in any way. Furthermore, in the attached drawings, identical or similar configurations are given the same reference numerals, and redundant descriptions are omitted.

[0010] A photoelectric converter according to an embodiment of the present disclosure will be described with reference to Figures 1 to 9. Figure 1 is a block diagram showing an example configuration of an imaging device 1000 including the photoelectric converter 1 according to this embodiment. The imaging device 1000 includes a photoelectric converter 1 with a parallel AD converter mounted on it, and an image processing LSI 2. The photoelectric converter 1 may also be called a CMOS image sensor or the like.

[0011] The image processing LSI 2 performs various processes on the image data output from the photoelectric converter 1. These processes include white balance processing, gamma processing, high dynamic range synthesis processing, and processing to correct the ratio of two pixel signals with different gains. The image data output from the photoelectric converter 1 and the image data processed by the image processing LSI 2 are recorded on a recording medium such as memory. The recording medium may be built into the image processing LSI 2 or it may be provided separately from the imaging device 1000. Furthermore, the image processing LSI 2 may have a built-in CPU, which may communicate with the photoelectric converter 1 and other devices (e.g., serial communication) based on a computer program stored in memory, and control the entire imaging device 1000.

[0012] The photoelectric converter 1 includes a pixel circuit 110, a vertical scanning circuit 120, a lamp circuit 140, an AD conversion unit 150, a horizontal transfer circuit 160, a signal processing circuit 170, an external output circuit 180, a controller circuit 300, and the like. Furthermore, for example, the photoelectric converter 1 may include an amplification amplifier between the pixel circuit 110 and the AD conversion unit 150 to amplify the analog signal (pixel signal) from the pixel circuit 110.

[0013] The controller circuit 300 acts as an interface with the image processing LSI 2 and receives control signals from the CPU of the image processing LSI 2 to the photoelectric converter 1 using serial communication or the like. The controller circuit 300 controls each component within the photoelectric converter 1.

[0014] In the pixel circuit 110, a plurality of pixels 111 are arranged to form a plurality of rows and a plurality of columns. Each of the pixels 111 includes a photoelectric conversion element (e.g., a photodiode) that photoelectrically converts according to the amount of incident light and outputs a voltage signal. The pixel 111 may have a color filter, a microlens, etc. arranged on an incident surface for allowing light to enter the photoelectric conversion element. For example, any one of three-color color filters that respectively transmit red, green, and blue may be periodically arranged so as to respectively correspond to the photoelectric conversion elements arranged in the pixel 111. The color filter may be, for example, in a Bayer array as the entire pixel circuit 110, but this is not necessarily the case.

[0015] The timing control circuit 100 supplies an operation clock CLK or a timing signal to each component of the photoelectric conversion device 1. The timing control circuit 100 controls the operation of each component by the operation clock CLK or the timing signal.

[0016] The vertical scanning circuit 120 performs timing control for sequentially reading out the output signals of the pixels 111 two-dimensionally arranged in the pixel circuit 110 row by row within one frame. For example, within one frame, signals are sequentially read out from the pixels 111 row by row from the upper row to the lower row shown in FIG. 1 in the pixel circuit 110.

[0017] The constant voltage circuit 400 can supply a predetermined voltage to each of the signal output lines. Instead of the constant voltage circuit 400, a clip circuit that clips a signal with a predetermined constant voltage may be used.

[0018] The ramp circuit 140 is a signal generator that generates a ramp-shaped voltage signal (ramp signal) whose voltage changes with a constant slope over time. As will be described later, the ramp circuit 140 can generate a plurality of ramp signals having different slopes from each other.

[0019] The AD conversion unit 150 includes a comparison circuit that compares the pixel signal read from the pixel circuit 110 with the ramp signal supplied from the ramp circuit 140. It also includes a counter-latch circuit that counts the time until the voltage level of the pixel signal and the voltage level of the ramp signal match, and holds the count value. The detailed configuration of the AD conversion circuit for each pixel row in the AD conversion unit 150 will be described later.

[0020] In this embodiment, the AD conversion unit 150 includes an AD conversion unit 150u and an AD conversion unit 150d. As shown in Figure 1, the AD conversion unit 150u and the AD conversion unit 150d are provided above and below the pixel circuit 110, respectively. It can also be said that the pixel circuit 110 is positioned between the AD conversion unit 150u and the AD conversion unit 150d. For example, the pixel signals output from pixels 111 arranged in odd-numbered rows of the pixel circuit 110 may be converted to time count values ​​and read out by the AD conversion unit 150u located above the pixel circuit 110. Alternatively, the pixel signals output from pixels 111 arranged in even-numbered rows of the pixel circuit 110 may be converted to time count values ​​and read out by the AD conversion unit 150d located below the pixel circuit 110.

[0021] The count values ​​for each column of a row held in the counter-latch circuit of the AD conversion unit 150 are sequentially read out as AD-converted image data by the horizontal transfer circuit 160, for example, starting from the column corresponding to the rightmost end of the pixel circuit 110. The image data output from the horizontal transfer circuit 160 is input to the signal processing circuit 170. The signal processing circuit 170 is a circuit that performs signal processing digitally. The signal processing circuit 170 may, for example, add a certain amount of offset value in digital processing, or perform shift operations or multiplication. In other words, the signal processing circuit 170 is capable of performing digital gain calculations.

[0022] Image data output from the signal processing circuit 170 is supplied to the external output circuit 180. The external output circuit 180 has a serializer function and converts the multi-bit parallel signal input from the signal processing circuit 170 into a serial signal. The external output circuit 180 then converts this serial signal into a signal such as the Low Voltage Differential Signaling (LVDS) standard and outputs it as image data to an external device (e.g., image processing LSI2).

[0023] First Embodiment Next, the configuration and operation of the AD conversion unit 150 of the first embodiment of this disclosure will be described. Figure 2 is a circuit block diagram showing the detailed configuration of the AD conversion circuit 220 corresponding to one column of pixels in the pixel circuit 110 in the AD conversion unit 150. As shown in Figure 2, two AD conversion units 150u and 150d are provided flanking the pixel circuit 110. Multiple AD conversion circuits 220 are arranged in the AD conversion units 150u and 150d, corresponding to one column. In the configuration shown in Figure 2, for the sake of simplicity of explanation, eight pixels 111 for eight rows arranged in one column are shown, but this is not limited to the number of rows in which pixels 111 are arranged.

[0024] Each of the multiple AD conversion circuits 220 includes a selection circuit 201, a buffer circuit 202, a comparator circuit 209, and a counter-latch circuit 210. The photoelectric converter 1 is provided with multiple lamp signal lines (two lamp signal lines 141 and 142 in the configuration shown in Figure 2) supplied from a lamp circuit 140, each having a lamp signal with a different slope. The selection circuit 201 selects the lamp signal lines 141 and 142 from among the multiple lamp signal lines 141 and 142 to be used for AD conversion. In this embodiment, a configuration is shown in which two types of lamp signals are supplied from the lamp circuit 140 via two lamp signal lines 141 and 142. However, it is not limited to this, and three or more lamp signal lines may be provided, and the selection circuit 201 may select the lamp signal lines to be used for AD conversion from three or more types of lamp signals. The buffer circuit 202 corrects the signal voltage of the lamp signal supplied from the selection circuit 201 and outputs it to the subsequent comparator circuit 209. The buffer circuit 202 may be, for example, a source follower circuit. The comparator circuit 209 compares the ramp signal selected by the selection circuit 201 with the pixel signal from the pixel 111. The counter-latch circuit 210 stores the time count value as an AD conversion result and outputs it to the subsequent horizontal transfer circuit 160. The AD conversion circuit 220 also includes a supply line SL that supplies the ramp signal from the selection circuit 201 to the comparator circuit 209. The supply line SL connects the output terminal of the selection circuit 201 and one input terminal of the comparator circuit 209 via the buffer circuit 202 and the input capacitor 205. In the configuration shown in Figure 2, an example is shown in which there are a total of eight AD conversion circuits 220, four on each side of the pixel circuit 110 corresponding to one row, but the number of AD conversion circuits 220 per row is not limited to this and may be between two and seven, or eight or more.

[0025] To transmit pixel signals from the pixel circuit 110 to the AD conversion units 150u and 150d, multiple signal output lines VL are provided, each corresponding to one of the multiple AD conversion circuits 220, which are provided for each row in the pixel circuit 110 where the pixels 111 are located. The signal output lines VL are connected to the comparator circuit 209 via the input capacitor 208. In the configuration shown in Figure 2, the pixel signals output from the pixels 111 located in the odd-numbered rows of the pixel circuit 110 are read out to the AD conversion circuit 220 of the AD conversion unit 150d via the signal output lines VL. Similarly, the pixel signals output from the pixels 111 located in the even-numbered rows of the pixel circuit 110 are read out to the AD conversion circuit 220 of the AD conversion unit 150d via the signal output lines VL. An amplification circuit may also be provided between the signal output lines VL and the AD conversion units 150u and 150d, so that the signal voltage output from the pixels 111 is amplified before being input to the comparator circuit 209 of the AD conversion circuit 220. Other configurations of the AD conversion unit 150 may be common to both the AD conversion unit 150u and the AD conversion unit 150d.

[0026] Figure 3 shows a more detailed circuit block diagram of the AD conversion unit 150. Although Figure 3 shows the AD conversion unit 150d, the AD conversion unit 150u may have a similar configuration.

[0027] The signal output lines VL1 to VL4 are each signal output lines corresponding to one row of pixels arranged in the pixel circuit 110. A pixel signal is input to each signal output line from a pixel 111 located in the same row of pixels in the pixel circuit 110. Each signal output line VL consists of a portion 206 to which the pixel 111 is connected, a portion 207 connected to the comparator circuit 209, and an input capacitor 208. In Figure 3, portions 206a to 206d, portions 207a to 207d, and input capacitors 208a to 208d are shown according to the signal output lines VL1 to VL4. Hereafter, when referring to a specific signal output line within the signal output line VL, a subscript is added to the reference code, such as signal output line VL "1". Similarly, when referring to a specific portion within portion 206, a subscript is added to the reference code, such as portion 206 "a". The same applies to other components.

[0028] As described above, the selection circuit 201 selects either the lamp signal line 141 or 142 to select the lamp signal Ramp1 supplied from the lamp circuit 140 to the lamp signal line 141 and the lamp signal Ramp2 supplied to the lamp signal line 142. Then, the selection circuit 201 outputs the lamp signals Ramp1 and Ramp2 to the comparison circuit 209 for each selection circuit 201.

[0029] The supply line SL for supplying ramp signals Ramp1 and Ramp2 from the selection circuit 201 to the comparison circuit 209 includes a portion 204 extending from the comparison circuit 209 and a portion 203 connecting portion 204 and the selection circuit 201, with the input capacitance 205 as the boundary. Portion 203 can also be described as the portion extending from the selection circuit 201 to the input capacitance 205 via the buffer circuit 202. The buffer circuit 202 can also be described as being located in portion 203 of the supply line SL.

[0030] One of the two input terminals of the comparator circuit 209 receives the ramp signals Ramp1 and Ramp2, selected by the selection circuit 201 via the buffer circuit 202, through a supply line SL that includes the input capacitor 205. The other of the two input terminals of the comparator circuit 209 receives the signal voltage (pixel signal) from the pixel 111 via the input capacitor, through the signal output line VL. The comparator circuit 209 compares the input pixel signal with the ramp signals and outputs a signal level corresponding to the comparison result. As an example, here, if the voltage levels of the ramp signals Ramp1 and Ramp2 are higher than the voltage level of the pixel signal, an H level is output, and if the voltage levels of the ramp signals Ramp1 and Ramp2 are lower than the voltage level of the pixel signal, an L level is output. In this configuration, the signal voltages of the ramp signals Ramp1 and Ramp2 are monotonically increased over time, and the time until the output of the comparator circuit 209 inverts from an H level to an L level is counted. This time count value can then be used as the AD conversion result of the pixel signal.

[0031] Furthermore, a predetermined voltage is input to the comparison circuit 209 instead of the ramp signals Ramp1 and Ramp2 and compared with the pixel signal. This allows the comparison circuit 209 to be used as a level determination circuit to determine whether the signal level of the pixel signal is higher or lower than a predetermined voltage. Details of the operation of using the comparison circuit 209 as a level determination circuit will be described later. As shown in Figure 3, the AD conversion circuit 220 may also include a determination holding circuit 211 to hold the determination result of the comparison circuit 209 when the comparison circuit 209 is used as a level determination circuit. The comparison circuit 209 may also be configured to generate a determination signal according to the held determination result and to be fed back to the selection circuit 201. This allows the selection circuit 201 to select the ramp signals Ramp1 and Ramp2 according to the fed-back determination signal.

[0032] Next, the operating timing of the AD conversion circuit 220 involved in the AD conversion of this embodiment will be explained using Figures 4(a) and 4(b). As shown in Figure 4(a), the comparator circuit 209 compares the input voltage Sout with the input voltage VRAMP and outputs a comparison signal PCOMP as the comparison result. In this embodiment, the input voltage Sout is a voltage corresponding to the pixel signal input from the pixel 111 to the comparator circuit 209 via the signal output line VL. The input voltage VRAMP is a voltage corresponding to the ramp signals Ramp1 and Ramp2, which are selected by the selection circuit 201 and input to the comparator circuit 209 via the buffer circuit 202.

[0033] Figure 4(b) shows the operating timing of the AD conversion circuit 220. In this embodiment, when performing AD conversion of the signal from pixel 111, first, a noise signal (hereinafter sometimes referred to as the N signal) is read from pixel 111 and AD conversion is performed. Next, the S signal, which includes the signal and noise that have been photoelectrically converted by the photoelectric conversion element, is read from pixel 111 and AD conversion is performed. For these two digital signals, the signal processing circuit 170 performs a subtraction process by subtracting the N signal from the S signal to cancel out the noise component and improve the S / N ratio.

[0034] During the AD conversion of the N signal, the reset level is read from pixel 111 of the pixel circuit 110 as the N signal and sent to the signal output line VL. All selection circuits 201 arranged in the AD conversion unit 150 select the ramp signal line 142 from among the multiple ramp signals Ramp1 and Ramp2 supplied from the ramp circuit 140, which supplies ramp signal Ramp1, having a gentler slope than ramp signal Ramp2. The voltage corresponding to ramp signal Ramp1 is supplied to the comparator circuit 209 via the buffer circuit 202 as the input voltage VRAMP. Time counting by the counter of the counter-latch circuit 210 begins when the supply of input voltage VRAMP (ramp signal Ramp1) begins. The comparator circuit 209 compares the input voltage Sout corresponding to the N signal with the input voltage VRAMP corresponding to ramp signal Ramp1, and outputs an H level as the comparator signal PCOMP while the input voltage Sout is higher than the ramp signal Ramp1. When the voltage level of ramp signal Ramp1 rises over time and exceeds the input voltage Sout, the comparator signal PCOMP inverts to an L level. Upon receiving the inversion of the comparison signal PCOMP from a high level to a low level, the counter-latch circuit 210 stores the time count value from the counter as the digital value of the N signal.

[0035] Once the AD conversion of the N signal is complete, the level determination period begins, in which the comparator circuit 209 is used as a level determination circuit. During the level determination period, the signal level of the S signal stored in the pixel 111 of the pixel circuit 110 is determined. First, the S signal stored in the pixel 111 of the pixel circuit 110 is read out to the signal output line VL. Meanwhile, the ramp circuit 140 supplies a fixed voltage Vth, which is the signal level determination threshold, to at least one of the ramp signal lines 141 and 142. The selection circuit 201 selects the ramp signal lines 141 and 142 to which the fixed voltage Vth is supplied, and supplies the fixed voltage Vth to the comparator circuit 209 as the input voltage VRAMP. The comparator circuit 209 compares the input voltage Sout corresponding to the S signal with the fixed voltage Vth, and outputs an H level if the input voltage Sout is higher than the fixed voltage Vth, and an L level if it is lower. For example, from pixel 111 where the amount of incident light from the subject was low, an input voltage Sout1 below the fixed voltage Vth is input as an S signal, and the comparator circuit 209 outputs a L level as the comparison signal PCOMP. From pixel 111 where the amount of incident light was high, an input voltage Sout2 above the fixed voltage Vth is input, and the comparator circuit 209 outputs an H level as the comparison signal PCOMP. When the input voltages Sout and VRAMP are stable, the judgment hold circuit 211 holds the level of the comparison signal PCOMP as the judgment signal jdg.

[0036] Next, during the AD conversion of the S signal, the selection circuit 201 selects one of the multiple ramp signals Ramp1 and Ramp2 supplied from the ramp circuit 140 based on the determination signal jdg from the corresponding determination holding circuit 211. If the determination signal jdg is at a low level, the selection circuit 201 selects the ramp signal Ramp1, which has a gentle slope, as the input voltage VRAMP, and if the determination signal jdg is at a high level, it selects the ramp signal Ramp2, which has a steep slope, as the input signal VRAMP. Time counting by the counter of the counter-latch circuit 210 begins as soon as the supply of the input voltage VRAMP (ramp signal Ramp1 or ramp signal Ramp2) begins. The comparison circuit 209 compares the input voltage Sout corresponding to the S signal with the input voltage VRAMP corresponding to the ramp signal Ramp1 or ramp signal Ramp2 selected by the selection circuit 201. The comparison circuit 209 outputs a high level as the comparison signal PCOMP while the input voltage Sout is higher than the input signal VRAMP. As the voltage level of the input signal VRAMP rises over time and exceeds the input voltage Sout, the comparison signal PCOMP inverts to a low level. Upon receiving the inversion of the comparison signal PCOMP from a high level to a low level, the counter-latch circuit 210 stores the time count value from the counter as the digital value of the S signal.

[0037] If the slope of ramp signal Ramp2 is N times that of ramp signal Ramp1, the time it takes for ramp signal Ramp2 to equalize with input voltage Sout is 1 / N times the time it takes for ramp signal Ramp1 to equalize with input voltage Sout. Depending on the level determination result, if the input voltage Sout has a low voltage level, AD conversion is performed using ramp signal Ramp1, which has a small slope, as the input voltage VRAMP. On the other hand, if the input voltage Sout has a high voltage level, AD conversion is performed using ramp signal Ramp2, which has a large slope, as the input voltage VRAMP. This reduces the time required for AD conversion. For pixel signals (input voltage Sout) with the same signal level, the time count value when selecting ramp signal Ramp2, which has a large slope, is 1 / N times that when selecting ramp signal Ramp1, which has a small slope. Therefore, by applying a correction gain of N times to the pixel value converted using ramp signal Ramp2 as the input voltage VRAMP through bit shifting or correction by a subsequent signal processing circuit, it becomes possible to treat it as a pixel signal with the same gradation as the pixel value converted using ramp signal Ramp1.

[0038] As described above, in this embodiment, the ramp signal to be used is selected according to the level of the pixel signal input to the AD conversion circuit 220. In other words, the photoelectric converter 1 performs an operation in which a different ramp signal may be selected for each comparison circuit 209 arranged in each AD conversion circuit 220.

[0039] Next, using the conceptual diagram in Figure 5, the physical arrangement image of each circuit block constituting the AD conversion unit 150 will be explained. Among the circuit blocks constituting the AD conversion unit 150, circuit blocks of the same type are laid out to be placed together in adjacent areas. This is because, in order to reduce manufacturing characteristic variations that occur between circuit blocks of the same type, it is appropriate to form each circuit element of the same type of circuit block in adjacent areas. Here, among the circuit blocks corresponding to the signal output lines VL1, VL2, VL3, and VL4, the selection circuits 201a, 201b, 201c, and 201d and the buffer circuits 202a, 202b, 202c, and 202d are to be placed in adjacent areas. Also, the respective comparison circuits 209a, 209b, 209c, and 209d are to be placed in adjacent areas. The wiring area 200 represents the region between the buffer circuits 202a, 202b, 202c, and 202d and the comparator circuits 209a, 209b, 209c, and 209d. The wiring area 200 contains parts 203a, 203b, 203c, and 203d, parts 204a, 204b, 204c, and 204d, which are part of the supply line SL, and input capacitors 205a, 205b, 205c, and 205d. The wiring area 200 also contains parts 206a, 206b, 206c, and 206d, parts 207a, 207b, 207c, and 207d, which are part of the signal output lines VL1, VL2, VL3, and VL4, and input capacitors 208a, 208b, 208c, and 208d.

[0040] Figures 6(a) and 6(b) show wiring layouts corresponding to the wiring region 200 illustrated in Figure 5. Figures 6(a) and 6(b) can also be described as wiring layouts focusing on the supply line SL portions 203 and 204 and the input capacitance 205 in Figure 3. Figure 6(a) shows a planar layout of the wiring layer on which the supply line SL is located. Figure 6(b) is a cross-sectional view between A and A' in Figure 6(a). The wiring region 200 includes a region 212 in which portions 203 and 204 of each AD conversion circuit 220 are arranged parallel to each other on the same wiring layer M4, as shown in Figure 6(a). In this case, by arranging, for example, portions 203a and 204a corresponding to one AD conversion circuit 220 facing each other, an input capacitance 205a is formed between portions 203a and 204a. Each AD conversion circuit 220 has a supply line SL that can supply ramp signals Ramp1 and Ramp2 from the selection circuit 201 to the comparator circuit 209 by capacitive coupling between sections 203 and 204 in region 212. In the configuration shown in Figure 6(a), sections 203 and 204 of the supply line SL are arranged on wiring layer M4, and the input capacitance 205 is formed between them. However, it is not limited to this, and capacitive elements may be formed on wiring layers M1 to M3 and M5, which are different from wiring layer M4 on which sections 203 and 204 are arranged as input capacitances. In that case, the connections between section 203 and the capacitive element, and between section 204 and the capacitive element, may be made by conductive patterns via conductive vias or the like.

[0041] Here, we focus on adjacent AD conversion circuits 220. Between the portions 203a and 204a of the supply line SL1 of the AD conversion circuit 220 including the comparator circuit 209a, and the portions 203b and 204b of the supply line SL2 of the AD conversion circuit 220 including the comparator circuit 209b, there is a shielded wire 230 installed to reduce crosstalk caused by capacitive coupling. There is also a shielded wire 230 between the portions 203b and 204b of the supply line SL2 of the AD conversion circuit 220 including the comparator circuit 209b, and the portions 203c and 204c of the supply line SL3 of the AD conversion circuit 220 including the comparator circuit 209c. Similarly, a shield wire 230 is provided between portions 203c and 204c of the supply line SL3 provided by the AD conversion circuit 220 including the comparator circuit 209c, and portions 203d and 204d of the supply line SL4 provided by the AD conversion circuit 220 including the comparator circuit 209d. The shield wire 230 may be fixed to ground level, for example, as shown in Figure 6(a). However, parasitic capacitances 214, 215, and 216 may occur between adjacent supply lines SL separated by the shield wire 230 due to gaps in the shield wire 230. As shown in Figure 6(b), the supply lines SL are provided in wiring layer M4. The shield wire 230 is also provided in the same wiring layer M4, but parasitic capacitances 214, 215, and 216 may occur through the dielectric between wiring layer M4 and wiring layer M5, for example.

[0042] Let's assume that this parasitic capacitance 214~216 occurs, for example, between portion 204a of supply line SL1 connected to comparator circuit 209a and portion 203b of supply line SL2 connected to selector circuit 201b, which supplies a ramp signal to the adjacent comparator circuit 209b. In this case, the voltage level of portion 204a of supply line SL1 connected to comparator circuit 209a will not only follow the ramp signal supplied from selector circuit 201a via portion 203a, but will also be affected by the ramp signal supplied from selector circuit 201b via portion 203b of supply line SL2. Let's consider the case where the ramp signal input to comparator circuit 209a and the ramp signal input to comparator circuit 209b are different ramp signals. For example, consider the case where ramp signal Ramp1 is supplied from selector circuit 201a to comparator circuit 209b, and ramp signal Ramp2 is supplied from selector circuit 201b to comparator circuit 209b. In that case, the ramp signal input to the comparator circuit 209a via section 204a of the supply line SL1 changes from the slope of the ramp signal Ramp1 that is originally intended to be input to a slope that is intermediate between the slope of ramp signal Ramp2. When performing AD conversion of pixel signals, if such an unintended change in the slope of the ramp signal occurs in the AD conversion of some pixel signals, the uniformity of the AD conversion gain in the image is disrupted, which can lead to a deterioration in the image quality of the resulting image.

[0043] To suppress this unintended change in the slope of the ramp signal, in this embodiment, portions 203 and 204 of the supply line SL, to which the corresponding ramp signals are input between adjacent AD conversion circuits 220, are arranged symmetrically in region 212 with the shield line 230 in between. Here, we focus on adjacent AD conversion circuits 220 in region 212 where portions 203 and 204 of the supply line SL are arranged parallel to the same wiring layer M4. For example, portion 203a of the supply line SL1 of the AD conversion circuit 220 including the comparator circuit 209a is arranged between portion 204a of the supply line SL1 of the AD conversion circuit 220 including the comparator circuit 209a and portion 203b of the supply line SL2 of the AD conversion circuit 220 including the comparator circuit 209b. For example, between portion 204b of the supply line SL2 of the AD conversion circuit 220 including the comparator circuit 209b and portion 203c of the supply line SL3 of the AD conversion circuit 220 including the comparator circuit 209c, portion 204c of the supply line SL3 of the AD conversion circuit 220 including the comparator circuit 209c is positioned. In other words, in adjacent AD conversion circuits 220, between portion 204 of the supply line SL of one AD conversion circuit 220 and portion 203 of the supply line SL of the other AD conversion circuit 220, portion 203 of the supply line SL of one AD conversion circuit 220 or portion 204 of the supply line SL of the other AD conversion circuit 220 is positioned.

[0044] Typically, in each circuit configuration of the photoelectric converter 1, wiring patterns with the same function are formed in a similar shape and can have similar impedances. That is, the impedances of each section 203 of the supply line SL will be the same, and the impedances of each section 204 will also be the same. On the other hand, the impedances between section 203 and section 204 can be different. When wiring patterns with different impedances are in close proximity, the wiring pattern on the lower impedance side is more likely to influence the wiring pattern on the higher impedance side through potential fluctuations.

[0045] Therefore, the arrangement of the supply line SL as described above reduces parasitic capacitance between adjacent AD conversion circuits 220, specifically between the portion 204 of the supply line SL extending from the comparator circuit 209 and the portion 203 connecting portion 204 to the selection circuit 201. This suppresses crosstalk between adjacent AD conversion circuits 220 when different ramp signals are supplied to the comparator circuit 209, thereby preventing changes in the slope of the ramp signals. As a result, it becomes possible to obtain a photoelectric converter 1 in which the uniformity of the AD conversion gain in the image is maintained and the degradation of the image quality is suppressed.

[0046] Second Embodiment Next, a second embodiment of the present disclosure will be described with reference to Figures 7 and 8. Figure 7 shows a modified example of the pixel circuit 110 and AD conversion unit 150 shown in Figure 2 of the photoelectric conversion device 1. Similar to the configuration shown in Figure 2, the AD conversion unit 150u and AD conversion unit 150d are provided on both sides of the pixel circuit 110. The configuration of the AD conversion units 150u and 150d may be the same as the configuration shown in Figure 2. On the other hand, in the configuration shown in Figure 7, the arrangement of the signal output line VL connecting the pixel 111 and the comparison circuit 209 arranged in each of the AD conversion circuits 220 of the AD conversion unit 150 is different from the configuration shown in Figure 2. More specifically, the pixel signals from each of the pixels 111 arranged in the pixel circuit 110 are configured to be output to both the AD conversion unit 150u and the AD conversion unit 150d via the signal output line VL. The other configurations may be the same as those of the embodiments described above. For example, the arrangement of portions 203 and 204 of the supply line SL connecting the selection circuit 201 and the comparison circuit 209 may have the symmetrical configuration described above in region 212.

[0047] In the photoelectric converter 1 having the configuration of this embodiment shown in Figure 7, in addition to the drive mode described above in which adjacent AD conversion circuits 220 are supplied with different ramp signals according to the level of the pixel signal, it may also operate in the following drive mode. In the AD conversion unit 150u, the selection circuit 201 selects, for example, the ramp signal line 142 that supplies the ramp signal Ramp1 from among the multiple ramp signal lines 141 and 142, and the ramp signal Ramp1 is supplied to the comparison circuit 209. In this case, in the AD conversion unit 150d, the selection circuit 201 selects the ramp signal line 141 that supplies the ramp signal Ramp2, which is different from the ramp signal line 142 that supplies the ramp signal Ramp1, from among the multiple ramp signal lines 141 and 142. This is a drive mode in which the ramp signal Ramp2 is supplied to the comparison circuit 209 of the AD conversion unit 150d. In other words, in the AD conversion units 150u and 150d, while a ramp signal Ramp1 (or Ramp2) is supplied to the comparator circuit 209 of a certain AD conversion circuit 220, the AD conversion circuit 220 adjacent to that AD conversion circuit 220 also supplies the ramp signal Ramp1 (or Ramp2) to its comparator circuit 209. Alternatively, it can be described as a drive mode in which, while a ramp signal Ramp1 (or Ramp2) is supplied to the comparator circuit 209 of a certain AD conversion circuit 220, the AD conversion circuit 220 adjacent to that AD conversion circuit 220 does not supply the ramp signal Ramp2 (or Ramp1) to its comparator circuit 209. This drive mode can be used, for example, to expand the dynamic range of a pixel signal by converting the pixel signal output from a single pixel 111 with different AD conversion gains and combining the converted signals with different AD conversion gains. The photoelectric converter 1 may be configured to have both the drive mode described in the first embodiment and the drive mode of this embodiment, and to be switchable between the drive modes.

[0048] Figure 8 shows the operating timing of the AD conversion unit 150u and AD conversion unit 150d of the photoelectric converter 1 having the configuration shown in Figure 7. In the timing diagram shown in Figure 8, in the AD conversion unit 150u, the selection circuit 201 selects the ramp signal line 142 to which the ramp signal Ramp1 is supplied. In the AD conversion unit 150d, the selection circuit 201 selects the ramp signal line 141 to which the ramp signal Ramp2 is supplied. As a result, the comparator circuit 209 in the AD conversion unit 150u is supplied with a voltage corresponding to the ramp signal Ramp1 as the input voltage VRAMP, and the comparator circuit 209 in the AD conversion unit 150d is supplied with a voltage corresponding to the ramp signal Ramp2 as the input voltage VRAMP. Through this operation, adjacent AD conversion circuits 220 are supplied with ramp signals with the same slope. In other words, unintended changes in the slope of the ramp signal caused by the parasitic capacitance mentioned above are suppressed.

[0049] In the operation shown in Figure 8, an example is shown in which ramp signal Ramp1 is supplied to the AD conversion unit 150u and ramp signal Ramp2 is supplied to the AD conversion unit 150d. However, it is sufficient for ramp signals with the same slope to be supplied to each of the AD conversion units 150u and 150d. That is, for example, ramp signal Ramp2 may be supplied to the AD conversion unit 150u and ramp signal Ramp1 may be supplied to the AD conversion unit 150d.

[0050] In the drive mode of this embodiment, as explained using Figures 7 and 8, the ramp signal input to one comparison circuit 209 is fixed to a single ramp signal regardless of the level of the pixel signal. Therefore, the operation (level determination period) for determining the level of the pixel signal in the first embodiment, as explained using Figure 4(b), can be omitted. In addition, the AD conversion unit 150u and the AD conversion unit 150d simultaneously read the pixel signal from the same pixel 111, and perform AD conversion with different AD conversion gains. As described above, by combining the two signals obtained by converting one pixel signal with different AD conversion gains in a subsequent signal processing circuit 170 or image processing LSI 2, the dynamic range of the resulting image can be expanded. Furthermore, in the AD conversion units 150u and 150d, the same ramp signal is supplied to adjacent AD conversion circuits 220. Therefore, changes in the slope of the lamp signal are suppressed, the uniformity of the AD conversion gain in the image is maintained, and it becomes possible to obtain a photoelectric converter 1 in which the degradation of the image quality is suppressed.

[0051] Third Embodiment Next, a third embodiment of the present disclosure will be described with reference to Figure 9. Figure 9 is a diagram showing a modified example of the pixel circuit 110 and AD conversion unit 150 shown in Figures 2 and 7 of the photoelectric conversion device 1. Similar to the configuration shown in Figures 2 and 7, in this embodiment as well, the AD conversion unit 150u and AD conversion unit 150d are provided on both sides (top and bottom) of the pixel circuit 110.

[0052] In the configuration shown in Figure 9, the photoelectric converter 1 includes a drive mode in which, while a predetermined ramp signal is supplied to a comparator circuit 209 in a certain AD conversion circuit 220 located in the AD conversion unit 150, a constant voltage is supplied to the comparator circuit 209 in an adjacent AD conversion circuit 220. The photoelectric converter 1 may be configured to have the drive modes of the first and second embodiments described above and the drive mode of this embodiment, and to be switchable between each drive mode. The configuration for realizing the drive mode of this embodiment will be described below.

[0053] As shown in Figure 9, the buffer circuits 202 of the AD conversion units 150u and 150d receive a stop signal PSAVE from the controller circuit 300 via the stop signal line 811. When a stop signal PSAVE (e.g., high level) is input to a buffer circuit 202, it stops operating and its output voltage is fixed to a constant voltage, such as ground level. In other words, some buffer circuits 202 also function as circuits for stopping the supply of ramp signals from the selection circuit 201 to the comparator circuit 209. By fixing the output voltage of the buffer circuit 202 of the AD conversion circuit 220 to a constant voltage using the stop signal PSAVE, the supply of ramp signals from the AD conversion circuit 220 to the comparator circuit 209 is stopped.

[0054] In each of the AD conversion units 150u and 150d, the stop signal PSAVE is configured to be supplied to the buffer circuit 202 of every other AD conversion circuit 220 among the multiple AD conversion circuits 220 arranged to correspond to one pixel row. In the photoelectric converter 1 having the configuration shown in Figure 9, when the level of the pixel signal is determined as described above and the device is operated in a drive mode in which a ramp signal corresponding to the level of the pixel signal can be supplied, a high level is input as the stop signal PSAVE. As a result, the output voltage of the buffer circuit 202 connected to the stop signal line 811 is fixed to, for example, the ground level. The pixel 111 includes a pixel that outputs a pixel signal only to the AD conversion circuit 220 to which the stop signal PSAVE is not supplied, and a pixel that outputs a pixel signal to the AD conversion circuit 220 to which the stop signal PSAVE is not supplied and to the AD conversion circuit 220 to which the stop signal PSAVE is supplied. Then, AD conversion is performed using only the AD conversion circuit 220 to which the stop signal PSAVE is not input. The drive mode of this embodiment can also be described as a drive mode in which AD conversion is performed by downsampling the AD conversion circuit 220.

[0055] As described above, the buffer circuit 202 is located in portion 203 of the supply line SL. Therefore, in the wiring layout shown in Figures 6(a) and 6(b), for example, portions 203b and 203d of supply lines SL2 and SL4 are fixed to ground level. Accordingly, portions 204b and 204d of supply lines SL2 and SL4 are also fixed to ground level. Therefore, even when different ramp signals are supplied to supply lines SL1 and SL3, multiple ground-level wiring patterns, including the shield line 230, are arranged between supply lines SL1 and SL3. As a result, capacitive coupling of supply lines SL connected to different AD conversion circuits 220 prevents unintended changes in the slope of the ramp signals, as described above. Consequently, it becomes possible to obtain a photoelectric converter 1 in which the uniformity of the AD conversion gain in the image is maintained and the degradation of the image quality is suppressed.

[0056] The circuit configurations shown in Figures 2, 7, and 9 may be used in combination as appropriate. In other words, the photoelectric converter 1 may have a circuit configuration that can operate in the three drive modes of each embodiment described above. For example, one photoelectric converter 1 may have at least two of the above drive modes and can be used by switching between them as appropriate by the user. For example, normally the photoelectric converter 1 operates in the drive mode described in the first embodiment. On the other hand, when the user selects a mode that expands the dynamic range, the photoelectric converter 1 operates in the drive mode described in the second embodiment. Furthermore, when a mode is selected that requires higher precision AD conversion for purposes such as improving image quality, the photoelectric converter 1 operates in the drive mode described in the third embodiment. This makes it possible to realize a photoelectric converter 1 with improved characteristics that are user-friendly, such as not only improved image quality by suppressing crosstalk in AD conversion, but also an expanded dynamic range.

[0057] Here, an application example of the photoelectric converter 1 of this embodiment will be described using Figure 10. Figure 10 is a schematic diagram of equipment 9191 equipped with the photoelectric converter 1. As shown in Figure 10, the photoelectric converter 1 is housed in a package 920. The package 920 may include a base on which the photoelectric converter 1 is fixed, and a lid made of glass or the like that faces the photoelectric converter 1. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to pads provided on the photoelectric converter 1.

[0058] The device 9191 may include at least one of the following: an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the photoelectric converter 1. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0059] The processing unit 960 processes the signals output from the photoelectric converter 1. The processing unit 960 is a semiconductor device such as a CPU or ASIC that constitutes an AFE (analog front end) or DFE (digital front end). The display device 970 is an EL display device or liquid crystal display device that displays the information (image) obtained from the photoelectric converter 1. The storage device 980 is a magnetic device or semiconductor device that stores the information (image) obtained from the photoelectric converter 1. The storage device 980 is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as flash memory or a hard disk drive.

[0060] The mechanical device 990 has movable parts or propulsion parts such as a motor or engine. The device 9191 displays the signals output from the photoelectric converter 1 on the display device 970 or transmits them to the outside using a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 may further include a storage device 980 and a processing device 960, separate from the memory circuits and arithmetic circuits of the photoelectric converter 1. The mechanical device 990 may be controlled based on the signals output from the photoelectric converter 1.

[0061] Furthermore, the device 9191 is suitable for electronic devices such as information terminals with shooting capabilities (e.g., smartphones and wearable devices) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). In a camera, the mechanical device 990 can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in a camera can move the photoelectric converter 1 for vibration damping.

[0062] Furthermore, the device 9191 can also be applied to on-board cameras mounted on transportation equipment such as vehicles, ships, airplanes, and industrial robots. The mechanical device 990 in transportation equipment can be used as a mobile device. As transportation equipment, the device 9191 is suitable for transporting the photoelectric converter 1 or for assisting and / or automating driving (operation) through its imaging function. The processing device 960 for assisting and / or automating driving (operation) can perform processing to operate the mechanical device 990 as a mobile device based on the information obtained from the photoelectric converter 1. The device 9191 incorporating the photoelectric converter 1 can be applied not only to transportation equipment but also to a wide range of equipment that utilizes object recognition, such as intelligent transportation systems (ITS). Alternatively, the device 9191 may be medical equipment such as endoscopes, measuring instruments such as distance sensors, analytical instruments such as electron microscopes, or office equipment such as photocopiers.

[0063] The disclosures herein include the following photoelectric conversion devices and equipment.

[0064] (Item 1) A photoelectric converter comprising: a pixel circuit in which multiple pixels are arranged to constitute multiple rows and multiple columns; multiple lamp signal lines to which lamp signals with different inclinations are supplied; and an AD conversion unit in which multiple AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, Each of the plurality of AD conversion circuits includes a selection circuit that selects a ramp signal line from among the plurality of ramp signal lines to be used for AD conversion, a comparison circuit that compares the ramp signal selected by the selection circuit with the pixel signal from the pixel, and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit. The supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit. The photoelectric conversion device is characterized in that the wiring area on which the supply line is arranged includes an area between the first part of the first AD conversion circuit and the second part of the second AD conversion circuit on which the second part of the first AD conversion circuit is arranged.

[0065] (Item 2) The photoelectric conversion device according to item 1, characterized in that, in the region, the first and second parts of the first AD conversion circuit and the first and second parts of the second AD conversion circuit are arranged in parallel on the same wiring layer.

[0066] (Item 3) The photoelectric converter according to item 1 or 2, characterized in that the supply line provided by each AD conversion circuit supplies a ramp signal from the selection circuit to the comparison circuit by capacitive coupling between the first and second portions in the region.

[0067] (Item 4) The photoelectric converter according to any one of items 1 to 3, characterized in that a shielded wire is arranged between the first part and the second part of the first AD conversion circuit and the first part and the second part of the second AD conversion circuit in the aforementioned region.

[0068] (Item 5) The photoelectric conversion device according to any one of items 1 to 4, characterized in that the selection circuit has a drive mode that selects a lamp signal line from among the plurality of lamp signal lines that supplies the lamp signal to be used for AD conversion according to the level of the pixel signal.

[0069] (Item 6) The photoelectric conversion device according to any one of items 1 to 5, characterized in that the first AD conversion circuit has a selection circuit that selects a lamp signal line from among the plurality of lamp signal lines that supplies a first lamp signal, and while the first lamp signal is supplied to the comparison circuit, the second AD conversion circuit has a drive mode in which the first lamp signal is supplied to the comparison circuit, or a drive mode in which a constant voltage is supplied.

[0070] (Item 7) A photoelectric converter comprising: a pixel circuit in which multiple pixels are arranged to constitute multiple rows and multiple columns; multiple lamp signal lines to which lamp signals with different inclinations are supplied; and an AD conversion unit in which multiple AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, Each of the plurality of AD conversion circuits includes a selection circuit that selects a ramp signal line from among the plurality of ramp signal lines to be used for AD conversion, a comparison circuit that compares the ramp signal selected by the selection circuit with the pixel signal from the pixel, and a supply line that supplies the ramp signal from the selection circuit to the comparison circuit. The supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit. The wiring region on which the supply line is arranged includes a region in which the first and second parts of the first AD conversion circuit and the first and second parts of the second AD conversion circuit are arranged parallel to each other on the same wiring layer. The photoelectric conversion device is characterized in that, in the first AD conversion circuit, the selection circuit selects a lamp signal line from among the plurality of lamp signal lines to supply a first lamp signal, and while the first lamp signal is supplied to the comparison circuit, the second AD conversion circuit includes at least one of a drive mode in which the first lamp signal is supplied to the comparison circuit and a drive mode in which a constant voltage is supplied to the comparison circuit.

[0071] (Item 8) The photoelectric converter according to item 7, characterized in that, in the first AD conversion circuit, while the first lamp signal is supplied to the comparison circuit, the second AD conversion circuit does not supply a lamp signal different from the first lamp signal to the selection circuit.

[0072] (Item 9) The aforementioned AD conversion unit includes a first AD conversion unit and a second AD conversion unit. The pixel circuit is arranged between the first AD conversion unit and the second AD conversion unit. The photoelectric converter according to item 7 or 8, characterized in that the photoelectric converter has a drive mode in which, in the first AD conversion unit, the selection circuit selects a lamp signal line from among the plurality of lamp signal lines that supplies a first lamp signal, and in the second AD conversion unit, the selection circuit selects a lamp signal line from among the plurality of lamp signal lines that supplies a second lamp signal different from the lamp signal line that supplies the first lamp signal.

[0073] (Item 10) The photoelectric converter according to item 9, characterized in that each of the plurality of pixels is configured to output a pixel signal to both the first AD conversion unit and the second AD conversion unit.

[0074] (Item 11) The photoelectric converter according to any one of items 7 to 10, characterized in that the supply line of the second AD conversion circuit has a circuit for stopping the supply of a ramp signal from the selection circuit to the comparison circuit.

[0075] (Item 12) A buffer circuit is provided in the aforementioned supply line. The photoelectric converter according to item 11, characterized in that the supply of the lamp signal is stopped by fixing the output voltage of the buffer circuit provided in the second AD conversion circuit to the constant voltage.

[0076] (Item 13) The photoelectric converter according to item 12, characterized in that the constant voltage includes the ground level.

[0077] (Item 14) The photoelectric converter according to item 12 or 13, characterized in that the buffer circuit is arranged in the second portion of the supply line.

[0078] (Item 15) The photoelectric converter according to any one of items 11 to 14, characterized in that the plurality of pixels include pixels that output a pixel signal to a first AD conversion circuit and pixels that output pixel signals to the first AD conversion circuit and the second AD conversion circuit.

[0079] (Item 16) A photoelectric converter described in any one of items 1 through 15, A processing device that processes the signal output from the aforementioned photoelectric converter, A device characterized by being equipped with the following features.

[0080] The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, claims are attached to disclose the scope of the invention. [Explanation of symbols]

[0081] 1: Photoelectric converter, 110: Pixel circuit, 111: Pixel, 141,142: Lamp signal line, 150: AD conversion unit, 200: Wiring area, 201: Selection circuit, 203,204: Part, 209: Comparison circuit, 212: Area, 220: AD conversion circuit, SL: Supply line

Claims

1. A photoelectric converter comprising: a pixel circuit in which multiple pixels are arranged to constitute multiple rows and multiple columns; multiple lamp signal lines to which lamp signals with different inclinations are supplied; and an AD conversion unit in which multiple AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, Each of the plurality of AD conversion circuits includes a selection circuit that selects a lamp signal line from among the plurality of lamp signal lines to be used for AD conversion, a comparison circuit that compares the lamp signal selected by the selection circuit with the pixel signal from the pixel, and a supply line that supplies the lamp signal from the selection circuit to the comparison circuit. The supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit. The photoelectric conversion device is characterized in that the wiring area on which the supply line is arranged includes an area between the first part of the first AD conversion circuit and the second part of the second AD conversion circuit on which the second part of the second AD conversion circuit is arranged.

2. The photoelectric conversion device according to claim 1, characterized in that, in the region, the first portion and the second portion of the first AD conversion circuit and the first portion and the second portion of the second AD conversion circuit are arranged in parallel on the same wiring layer.

3. The photoelectric converter according to claim 1, characterized in that the supply line provided by each AD conversion circuit supplies a ramp signal from the selection circuit to the comparison circuit by capacitive coupling between the first portion and the second portion in the region.

4. The photoelectric converter according to claim 1, characterized in that a shielded wire is arranged between the first part and the second part of the first AD conversion circuit and the first part and the second part of the second AD conversion circuit in the aforementioned region.

5. The photoelectric converter according to claim 1, further comprising a drive mode in which the selection circuit selects a lamp signal line from among the plurality of lamp signal lines that supplies the lamp signal to be used for AD conversion according to the level of the pixel signal.

6. The photoelectric conversion device according to claim 1, characterized in that the first AD conversion circuit has a selection circuit that selects a lamp signal line from among the plurality of lamp signal lines that supplies a first lamp signal, and while the first lamp signal is supplied to the comparison circuit, the second AD conversion circuit has a drive mode in which the first lamp signal is supplied to the comparison circuit, or a drive mode in which a constant voltage is supplied.

7. A photoelectric converter comprising: a pixel circuit in which multiple pixels are arranged to constitute multiple rows and multiple columns; multiple lamp signal lines to which lamp signals with different inclinations are supplied; and an AD conversion unit in which multiple AD conversion circuits, including a first AD conversion circuit and a second AD conversion circuit adjacent to each other, are arranged corresponding to one column, Each of the plurality of AD conversion circuits includes a selection circuit that selects a lamp signal line from among the plurality of lamp signal lines to be used for AD conversion, a comparison circuit that compares the lamp signal selected by the selection circuit with the pixel signal from the pixel, and a supply line that supplies the lamp signal from the selection circuit to the comparison circuit. The supply line includes a first portion extending from the comparison circuit and a second portion connecting the first portion and the selection circuit. The wiring region on which the supply lines are arranged includes a region in which the first and second parts of the first AD conversion circuit and the first and second parts of the second AD conversion circuit are arranged parallel to each other on the same wiring layer. The photoelectric conversion device is characterized in that, in the first AD conversion circuit, the selection circuit selects a lamp signal line from among the plurality of lamp signal lines that supplies a first lamp signal, and while the first lamp signal is supplied to the comparison circuit, the second AD conversion circuit includes at least one of a drive mode in which the first lamp signal is supplied to the comparison circuit and a drive mode in which a constant voltage is supplied to the comparison circuit.

8. The photoelectric converter according to claim 7, characterized in that, in the first AD conversion circuit, while the first lamp signal is supplied to the comparison circuit, in the second AD conversion circuit, a lamp signal different from the first lamp signal is not supplied to the selection circuit.

9. The AD conversion unit includes a first AD conversion unit and a second AD conversion unit. The pixel circuit is arranged between the first AD conversion unit and the second AD conversion unit. The photoelectric conversion device according to claim 7, characterized in that the first AD conversion unit has a drive mode in which the selection circuit selects a lamp signal line from among the plurality of lamp signal lines that supplies a first lamp signal, and the second AD conversion unit has a drive mode in which the selection circuit selects a lamp signal line from among the plurality of lamp signal lines that supplies a second lamp signal different from the lamp signal line that supplies the first lamp signal.

10. The photoelectric converter according to claim 9, characterized in that each of the plurality of pixels is configured to output a pixel signal to both the first AD conversion unit and the second AD conversion unit.

11. The photoelectric converter according to claim 7, characterized in that the supply line of the second AD conversion circuit is provided with a circuit for stopping the supply of a ramp signal from the selection circuit to the comparison circuit.

12. A buffer circuit is provided in the aforementioned supply line. The photoelectric converter according to claim 11, characterized in that the supply of the lamp signal is stopped by fixing the output voltage of the buffer circuit provided in the second AD conversion circuit to the constant voltage.

13. The photoelectric conversion device according to claim 12, characterized in that the constant voltage includes the ground level.

14. The photoelectric conversion device according to claim 12, characterized in that the buffer circuit is arranged in the second portion of the supply line.

15. The photoelectric converter according to claim 11, characterized in that the plurality of pixels include pixels that output a pixel signal to a first AD conversion circuit and pixels that output pixel signals to the first AD conversion circuit and the second AD conversion circuit.

16. A photoelectric conversion device according to any one of claims 1 to 15, A processing device that processes the signal output from the aforementioned photoelectric converter, A device characterized by being equipped with the following features.

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