A SAR ADC switched capacitor switching circuit

Abstract

A SAR ADC switched-capacitor switching circuit, belonging to the field of analog integrated circuit technology, is disclosed. It includes six capacitors C1-C6 and ten switches S1-S10. C1-C6 form a binary capacitor array of the switched-capacitor circuit, where the first switch C1, the second switch C2, the third switch C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are the P and N terminals of the differential capacitor array, respectively. This circuit employs a bottom-plate sampling technique, which avoids charge leakage during sampling and enables a higher-precision analog-to-digital converter. After sampling, the sampled voltage is maintained on the upper plate of the capacitor. During the conversion phase, the proposed switched-capacitor switching circuit is used for switching, achieving low-power conversion.

Description

Technical Field

[0001] This invention relates to a SAR ADC switched capacitor switching circuit, belonging to the field of analog integrated circuit technology, and is mainly applied to SAR ADC analog-to-digital converters. Background Technology

[0002] With the rapid development of technology, more and more intelligent devices are being applied to our lives. Consequently, various portable devices have also experienced rapid growth. Smart electronic products are used in all aspects of our lives, with widespread applications in aerospace, national defense, smart appliances, and 4G communications. During the rapid development of semiconductors, CMOS technology has become increasingly advanced, continuously improving the speed, area, and power consumption of circuits. In nature, familiar signals such as sound, light, and pressure are analog signals, which cannot be easily processed and applied. Therefore, analog-to-digital converters (ADCs) are necessary to convert these time- and amplitude-continuous analog signals into time-discrete, amplitude-quantized digital signals for subsequent processing. In circuit systems, the accuracy, speed, and power consumption of ADCs are gradually becoming bottlenecks in the development of systems towards high precision, high speed, and low power consumption.

[0003] With the continuous development and advancement of integrated circuit design processes and the increasing sophistication of SoC design technology, more and more circuit unit modules can be integrated into chips. Among these, portable systems, biomedical systems, and wireless sensor networks have stringent power consumption requirements. For A / D converters within chips, low-power design research has always been a key concern for designers. As semiconductor processes continue to improve, with CMOS process dimensions shrinking from 0.6μm to 14nm or even smaller, the power consumption of A / D converters is also constantly decreasing. Among various ADCs, the Successive Approximation Register (SAR) ADC, with its simple overall structure, has attracted widespread attention from researchers both domestically and internationally. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and propose a SAR ADC switched capacitor switching circuit. This circuit adopts the lower plate sampling technology, which can avoid charge leakage during the sampling process and realize a higher precision analog-to-digital converter. After sampling, the sampled voltage is maintained on the upper plate of the capacitor. During the conversion stage, the proposed switched capacitor switching circuit is used to switch the voltage, thereby achieving low-power conversion.

[0005] The technical solution to achieve the objective of this invention is:

[0006] A SAR ADC switched-capacitor switching circuit comprises two parts: a non-overlapping clock source and a switched-capacitor circuit. The non-overlapping clock source generates a two-phase non-overlapping clock to enable sampling of the lower plate of the analog-to-digital converter. The switched-capacitor circuit enables switching of the capacitors, allowing for conversion with lower power consumption.

[0007] The 4-bit switched capacitor circuit includes six capacitors C1-C6 and ten switches S1-S10. C1-C6 form a binary capacitor array, where the first switch C1, the second switch C2, the third switch C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are the P and N terminals of the differential capacitor array, respectively. The P-terminal capacitor array is arranged from left to right as the first, second, and third capacitors, while the N-terminal capacitor array is arranged sequentially from right to left as the sixth, fifth, and fourth capacitors. The positions of the first, second, and third capacitors C1, C2, and C3 are horizontally symmetrical to those of the sixth, fifth, and fourth capacitors C4, respectively. The first capacitor C1 and the sixth capacitor C6 are the highest-order capacitors of the P and N-terminal capacitor arrays, respectively. The values ​​of the third capacitor C3 and the fourth capacitor C4 are both unit capacitance C, which can be any value. The second capacitor C2 and the fifth capacitor C5 are the least significant capacitors in the capacitor array, with a value of unit capacitance C. The first capacitor C1 and the sixth capacitor C6 are the most significant capacitors in the capacitor array, with a value twice that of the second capacitor C2 or the fifth capacitor C5, which is twice the unit capacitance 2C. To form a binary capacitor array, the values ​​of the third capacitor C3, the fourth capacitor C4, the second capacitor C2, and the fifth capacitor C5 must be equal. The first capacitor C1 is equal to the sum of the second capacitor C2 and the third capacitor C3, forming a binary capacitor array. The sixth capacitor C6 is equal to the sum of the fifth capacitor C5 and the fourth capacitor C4, forming a binary capacitor array.

[0008] Switches S1-S6 are CMOS switches. One end of each of switches S1, S2, and S3 is connected to the lower plates of the first capacitor C1, second capacitor C2, and third capacitor C3 in the P-side capacitor array, respectively. The other end is connected to the voltage reference Vref, Vcm, and GND, respectively, where Vcm is half of Vref. One end of each of switches S4, S5, and S6 is connected to the lower plates of the fourth capacitor C4, fifth capacitor C5, and sixth capacitor C6 in the N-side capacitor array, respectively. The other end is connected to the voltage reference Vref, Vcm, and GND, respectively. Switches S7-S8 are CMOS switches. One end of each of switches S7 and S8 is connected to the upper plates of the P-side and N-side differential capacitor arrays, respectively. The other end of each switch is connected to the reference voltage source Vcm. The ninth switch S9 and the tenth switch S10 are bootstrap switches. One end of the ninth switch S9 and the tenth switch S10 is connected to the lower plate of the P and N terminal capacitor arrays, respectively, and the other end is connected to Vin and Vip, respectively. The upper plates of the P and N terminal capacitor arrays are connected to the positive and negative terminals of the comparator, respectively.

[0009] Each of the switches S1-S6 consists of three CMOS switches. Taking the first switch S1 as an example, the first switch S1 consists of S13, S14, and S15. S13 consists of the first MOSTET M1 and the second MOSTET M2. S14 consists of the third MOSTET M3 and the fourth MOSTET M4. S15 consists of the fifth MOSTET M5 and the sixth MOSTET M6. The drains of the first MOSTET M1 and the second MOSTET M2 are connected together, and the sources of the first MOSTET M1 and the second MOSTET M2 are connected together as one end of the switch input connected to Vref. The gate of the first MOSTET M1 is connected to ~S_Ref, and the gate of the second MOSTET M2 is connected to S_Ref. ~S_Ref and S_Ref are high or low potentials that control the switch to turn on or off, and the two signals are complementary signals. The drains of the third MOST transistor M3 and the fourth MOST transistor M4 are connected. The sources of the third MOST transistor M3 and the fourth MOST transistor M4 are connected together, serving as one input of a switch connected to Vcm. The gate of the third MOST transistor M3 is connected to ~S_Vcm, and the gate of the fourth MOST transistor M4 is connected to S_Vcm. ~S_Vcm and S_Vcm are high or low potentials that control the switch to turn on or off, and the two signals are complementary. The drains of the fifth MOST transistor M5 and the sixth MOST transistor M6 are connected. The sources of the fifth MOST transistor M5 and the sixth MOST transistor M6 are connected together, serving as one input of a switch connected to GND. The gate of the fifth MOST transistor M5 is connected to ~S_GND, and the gate of the sixth MOST transistor M6 is connected to S_GND. ~S_GND and S_GND are high or low potentials that control the switch to turn on or off, and the two signals are complementary. The drains of M1-M6 are connected together as one end of the switch, and the input is connected to the lower plate of the capacitor. Attached Figure Description

[0010] Figure 1 This is a structural diagram of the switch switching circuit proposed in this invention.

[0011] Figure 2 This is a schematic diagram of the switching process for the switching strategy proposed in this invention.

[0012] Figure 3 The switch in the switching circuit used in this invention

[0013] Figure 4 This is a schematic diagram of the waveform of the non-overlapping clock circuit used in this invention. Detailed Implementation

[0014] A SAR ADC switched capacitor switching circuit is provided. To more clearly illustrate the purpose and technical advantages of this invention, the following will provide a more detailed description of the invention in conjunction with the accompanying drawings and examples, but this is not intended to limit the scope of application of the invention.

[0015] like Figure 1 The above is a circuit structure diagram of the present invention. Figure 2 This paper presents a switched-capacitor circuit structure for a SAR ADC. The switched-capacitor circuit is used to sample the input signal and maintain the voltage in the SAR ADC. During the conversion stage, the proposed switching capacitor strategy is used for switching to achieve low-power conversion. Figure 3 This refers to the CMOS switch used in switched-capacitor circuits. Figure 4 This is a timing diagram generated by a non-overlapping clock source.

[0016] This circuit operates using a two-phase non-overlapping clock:

[0017] During the sampling phase, when the first clock cycles Clk1 and Clk2 are at their high potentials, switches S7, S8, S9, and S10 are closed, while switches S1, S2, S3, S4, S5, and S6 are open, charging the capacitor array. At the end of sampling, Clk1 first enters a low potential, and switches S7 and S8 open. Subsequently, Clk2 enters a low potential, and switches S9 and S10 are turned off. This is to prevent charge leakage from the MOSFETs in switches S9 and S10, which would affect sampling accuracy and prevent the implementation of a high-precision analog-to-digital converter. After sampling, switches S1, S2, S3, S4, S5, and S6 are connected to level Vcm. At this time, the voltage Vxp on the upper plate of the P-terminal capacitor array is Vref-Vin, and the voltage Vxn on the upper plate of the N-terminal capacitor array is Vref-Vip. The input of the comparator compares Vip-Vin to obtain the highest bit of the SAR ADC, b3. If the comparison result is greater than zero, the highest bit b3 = 1, and switches S1, S2, and S3 on the P-terminal capacitor array are switched to GND. At this time, the voltage Vxp on the upper plate of the P-terminal capacitor array decreases by half the Vref value, preparing for the next comparison. If the comparison result is equal to zero, the highest bit b3 = 0, and switches S4, S5, and S6 on the N-terminal capacitor array are switched to GND, which decreases Vxn by half the Vref value, preparing for the next comparison.

[0018] After the first stage, the second stage of comparison begins. If b3 = 1, and the comparison result of Vip - Vin - 1 / 2Vref is also non-zero, then b2 = 1. Switches S1, S2, S3, S4, and S5 remain unchanged, and switch S6 switches to Vref. The result is that Vxn increases by one-quarter of the Vref value. In the next stage, the comparator will compare whether Vip - Vin - 3 / 4Vref is greater than zero. If b3 = 1, and the comparison result of Vip - Vin - 1 / 2Vref is zero, then b2 = 0. Switches S2, S3, S4, S5, and S6 remain unchanged, and switch S1 switches to Vcm. The result is that the voltage at terminal P, Vxp, increases by one-quarter of the Vref value. In the next stage, the comparator will compare whether Vip - Vin - 1 / 4Vref is greater than zero. If b3 = 0, and the comparison result of Vip - Vin + 1 / 2Vref is non-zero, then b2 = 1. Switches S1, S2, S3, S4, and S5 remain unchanged, and switch S6 switches to Vcm. The result is that Vxn increases by one-quarter of the Vref value. The next stage comparator will compare whether Vip - Vin + 1 / 4Vref is greater than zero. If b3 = 0, and the comparison result of Vip - Vin + 1 / 2Vref is zero, then b2 = 0. Switches S2, S3, S4, S5, and S6 remain unchanged, and switch S1 switches to Vref. The result is that Vxp increases by one-quarter of the Vref value. The next stage comparator will compare whether Vip - Vin + 3 / 4Vref is greater than zero.

[0019] After the second stage ends, the third stage of comparison begins. If b3 = 1, b2 = 1, and the comparison result of Vip-Vin-3 / 4Vref is also non-zero, then b1 = 1. Switches S1, S2, S3, S4, and S6 remain unchanged, and switch S5 switches to Vref. The result is that Vxn increases by one-eighth of the Vref value. In the next stage, the comparator will compare whether Vip-Vin-7 / 8Vref is greater than zero. If the comparison result of Vip-Vin-7 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. If b3 = 1, b2 = 1, and the comparison result of Vip - Vin - 3 / 4Vref is also zero, then b1 = 0. Switches S1, S3, S4, S5, and S6 remain unchanged, and switch S2 switches to Vcm. The result is that Vxp increases by one-eighth of the Vref value. The next stage comparator will compare whether Vip - Vin - 5 / 8Vref is greater than zero. If Vip - Vin - 5 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. If b3 = 1, b2 = 0, and the comparison result of Vip - Vin - 1 / 4Vref is also non-zero, then b1 = 1. Switches S1, S2, S3, S4, and S6 remain unchanged, and switch S5 switches to Vref. The result is that Vxn increases by one-eighth of the Vref value. The next stage comparator will compare whether Vip - Vin - 3 / 8Vref is greater than zero. If Vip - Vin - 3 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. If b3 = 1, b2 = 0, and the comparison result of Vip - Vin - 1 / 4Vref is also zero, then b1 = 0. Switches S1, S3, S4, S5, and S6 remain unchanged, and switch S2 switches to Vcm. The result is that Vxp increases by one-eighth of the Vref value. The next stage comparator will compare whether Vip - Vin - 1 / 8Vref is greater than zero. If Vip - Vin - 1 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. If b3 = 0, b2 = 1, and the comparison result of Vip - Vin + 1 / 4Vref is also non-zero, then b1 = 1. Switches S1, S2, S3, S4, and S6 remain unchanged, and switch S5 switches to Vcm. The result is that Vxn increases by one-eighth of the Vref value. The next stage comparator will compare whether Vip - Vin + 1 / 8Vref is greater than zero. If Vip - Vin + 1 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. If b3 = 0, b2 = 1, and the comparison result of Vip - Vin + 1 / 4 Vref is also zero, then b1 = 0. Switches S1, S3, S4, S5, and S6 remain unchanged, and switch S2 switches to Vref. The result is that Vxp increases by one-eighth of the Vref value. In the next stage, the comparator will compare whether Vip - Vin + 3 / 8 Vref is greater than zero. If the comparison result of Vip - Vin + 3 / 8 Vref is greater than zero, then b0 = 1; otherwise, b0 = 0.If b3 = 0, b2 = 0, and the comparison result of Vip - Vin + 3 / 4Vref is also non-zero, then b1 = 1. Switches S1, S2, S3, S4, and S6 remain unchanged, and switch S5 switches to Vcm. The result is that Vxn increases by one-eighth of the Vref value. The next stage comparator will compare whether Vip - Vin + 5 / 8Vref is greater than zero. If Vip - Vin + 5 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. If b3 = 0, b2 = 0, and the comparison result of Vip - Vin + 3 / 4Vref is also zero, then b1 = 0. Switches S1, S3, S4, S5, and S6 remain unchanged, and switch S2 switches to Vref. The result is that Vxp increases by one-eighth of the Vref value. The next stage comparator will compare whether Vip - Vin + 7 / 8Vref is greater than zero. If Vip - Vin + 7 / 8Vref is greater than zero, then b0 = 1; otherwise, b0 = 0. After four comparisons, a 4-bit digital code was obtained.

[0020] Of course, the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.

Claims

1. A SAR ADC switched capacitor switching circuit, characterized in that, include: The circuit consists of six capacitors C1-C6 and ten switches S1-S10. C1-C6 form a binary capacitor array for the switched capacitor circuit. Switches C1, C2, C3, C4, C5, and C6 are located at the P and N ends of the differential capacitor array, respectively. The P-end capacitor array, arranged from left to right, consists of the first, second, and third capacitors, while the N-end capacitor array, arranged from right to left, consists of the sixth, fifth, and fourth capacitors. The positions of C1, C2, and C3 are horizontally symmetrical to C6, C5, and C4, respectively. C1 and C6 are located at the P-end. The highest-order capacitor in the N-terminal capacitor array; the values ​​of the third capacitor C3 and the fourth capacitor C4 are both unit capacitance C; the second capacitor C2 and the fifth capacitor C5 are the lowest-order capacitors in the capacitor array, with a value of unit capacitance C; the first capacitor C1 and the sixth capacitor C6 are the highest-order capacitors in the capacitor array, with a value twice that of the second capacitor C2 or the fifth capacitor C5, which is twice the unit capacitance 2C; in order to form a binary capacitor array, the values ​​of the third capacitor C3, the fourth capacitor C4, the second capacitor C2, and the fifth capacitor C5 must be equal; the first capacitor C1 is equal to the sum of the second capacitor C2 and the third capacitor C3, forming a binary capacitor array; the sixth capacitor C6 is equal to the sum of the fifth capacitor C5 and the fourth capacitor C4, forming a binary capacitor array; Switches S1-S6 are CMOS switches. One end of each of the following switches (S1, S2, and S3) is connected to the lower plates of the first capacitor C1, second capacitor C2, and third capacitor C3 in the P-terminal capacitor array, respectively. The other end is connected to the voltage reference Vref, Vcm, and GND, respectively, where Vcm is half of Vref. One end of each of the following switches (S4, S5, and S6) is connected to the lower plates of the fourth capacitor C4, fifth capacitor C5, and sixth capacitor C6 in the N-terminal capacitor array, respectively. The other end is connected to the voltage reference Vref, Vcm, and GND respectively; switches S7-S8 are CMOS switches, one end of the seventh switch S7 and the eighth switch S8 is connected to the upper plate of the differential capacitor array at the P and N ends respectively, and the other end is connected to the reference voltage source Vcm; switches S9 and S10 are bootstrap switches, one end of the ninth switch S9 and the tenth switch S10 is connected to the lower plate of the capacitor array at the P and N ends respectively, and the other end is connected to Vin and Vip respectively; the upper plates of the capacitor array at the P and N ends are connected to the positive and negative terminals of the comparator respectively; Each of the switches S1-S6 consists of three CMOS switches. Taking the first switch S1 as an example, the first switch S1 consists of S13, S14, and S15. S13 consists of the first MOSTET M1 and the second MOSTET M2; S14 consists of the third MOSTET M3 and the fourth MOSTET M4; and S15 consists of the fifth MOSTET M5 and the sixth MOSTET M6. The drains of the first MOSTET M1 and the second MOSTET M2 are connected together, and their sources are connected together as one input terminal of the switch, connected to Vref. The gate of the first MOSTET M1 is connected to ~S_Ref, and the gate of the second MOSTET M2 is connected to S_Ref. ~S_Ref and S_Ref are high or low potentials controlling the switch's on / off state, and the two signals are complementary. The third MOSTET M3 and the fourth MOSTET M6... The drain of transistor M4 is connected. The sources of the third MOTET transistor M3 and the fourth MOTET transistor M4 are connected together as one input to Vcm. The gate of the third MOTET transistor M3 is connected to ~S_Vcm, and the gate of the fourth MOTET transistor M4 is connected to S_Vcm. ~S_Vcm and S_Vcm are high or low potentials that control the switch to turn on or off, and the two signals are complementary. The drains of transistors M5 and M6 are connected. The sources of the fifth MOTET transistor M5 and the sixth MOTET transistor M6 are connected together as one input to GND. The gate of the fifth MOTET transistor M5 is connected to ~S_GND, and the gate of the sixth MOTET transistor M6 is connected to S_GND. ~S_GND and S_GND are high or low potentials that control the switch to turn on or off, and the two signals are complementary. The drains of M1-M6 are connected together as one input to the lower plate of the capacitor.

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