Successive Analog-to-Digital Converter

Abstract

The successive approximation analog-to-digital converter comprises a sampling circuit for sampling an analog input signal to obtain a sampled voltage, and a regenerative comparator for comparing the sampled voltage with a series of reference voltages to generate, for each reference voltage, a decision bit indicative of the comparison result. The converter also includes a digital-to-analog converter adapted to generate a series of reference voltages in response to successive comparison results in the comparator so as to progressively approach the sampled voltage. The regenerative comparator comprises an integrator circuit for generating output signals defining the decision bits, and a plurality of regenerative circuits for receiving these output signals. The regenerative circuits are operable to store respective decision bits defined by successive output signals from the integrator circuits in response to respective control signals.

Description

Technical Field

[0001] The present invention relates to a successive approximation analog-to-digital converter (SAR ADC). The SAR ADC is provided together with a device incorporating these converters.

Background Art

[0002] An analog-to-digital converter (ADC) is a well-known device that repeatedly samples an analog input signal in order to generate a digital signal representing the analog waveform. The SAR ADC uses a binary search algorithm to map the voltage sampled from the analog input signal to a digital representation of the sampled voltage level. After the binary search by the possible quantization levels, the sampled voltage is compared with a series of reference voltages so as to gradually approach the sampled voltage level.

[0003] Most of the SAR ADCs use a regenerative comparator to compare the sampled voltage with a reference voltage. These comparators use two respective stages, namely two circuits for integration and regeneration. The integration stage generates an output signal according to the input voltage to be compared. When this output signal reaches a sufficient level, the second stage starts regeneration. The regeneration circuit provides the output of the comparator to a subsequent circuit configuration in the SAR ADC, and that circuit configuration stores the comparator decision and controls the binary search process.

Summary of the Invention

[0004] A first aspect of the present invention provides a successive approximation analog-to-digital converter. The converter includes a sampling circuit configured to sample an analog input signal to obtain a sampled voltage, and a regenerative comparator configured to compare the sampled voltage with a set of reference voltages and, for each reference voltage, generate a decision bit based on the comparison. The converter further comprises a digital-to-analog converter configured to generate a set of reference voltages that progressively approach the sampled voltage, wherein the generation of the set of reference voltages is based on a set of comparison results from the comparator. The regenerative comparator includes an integrating circuit configured to generate output signals that define each decision bit, and a plurality of regenerative circuits configured to receive these output signals. The regenerative circuits are further configured to receive control signals and, in response to the reception of control signals, store decision bits defined by the output signals from the integrating circuits.

[0005] A second aspect of the present invention provides an in-memory computing device. The device comprises an array of memory devices connected between each pair of word lines and bit lines of an array for storing values ​​for calculations, where input signals are supplied to bit lines to obtain analog output signals on word lines. Each word line is connected to a successive approximation analog-to-digital converter (SAR ADC) according to the first aspect of the present invention for analog-to-digital conversion of the output signal on that word line to a digital signal for further processing.

[0006] Embodiments of the present invention are described below in more detail with reference to the accompanying drawings, using exemplary and non-limiting examples. The above summary is not intended to describe each illustrated embodiment or implementation of the present disclosure. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic block diagram of an unrolled SAR ADC according to some embodiments of the present disclosure. [Figure 2]The following are schematic diagrams of unrolled regenerative comparators according to some embodiments of the present disclosure. [Figure 3] This is a schematic block diagram of an asynchronous SAR ADC according to some embodiments of the present disclosure. [Figure 4] This is a schematic block diagram of a further embodiment of a regenerative comparator for a SAR ADC with a dynamic offset compensation mechanism, according to some embodiments of the present disclosure. [Figure 5] This is a schematic diagram of an in-memory computing device according to some embodiments of the present disclosure. [Figure 6] This invention provides a high-level analog-to-digital conversion method according to several embodiments of this disclosure. [Modes for carrying out the invention]

[0008] A part of this disclosure relates to analog-to-digital converters (ADCs). A more specific part of this disclosure relates to unrolled-regeneration successive approximation ADCs (SAR ADCs).

[0009] An exemplary conventional SAR ADC may comprise SAR logic including a sampling circuit, a comparator, a digital-to-analog converter (DAC), and memory cells for storing the decisions from the comparator. Additional logic blocks may be included for timing control, as described below. For example, a sampling switch T s And, capacitor C s A sampling circuit that may include the sampled voltage V supplied to the comparator s To obtain this, the input analog waveform can be sampled. The DAC also uses a reference voltage V supplied to the comparator. ref It generates V s V ref It compares this with the output signal showing the comparison result and provides it to the SAR logic. s ≥V refIn this case, the decision bit d1 = 1 can be stored in the memory cell of the SAR logic. V s <V ref In this case, the stored decision bit is d1 = 0. Then, the SAR logic supplies a control code to the DAC to update the reference voltage V ref and the comparison is repeated to store the next decision bit d2. This process is repeated until n decision bits for the n-bit SAR ADC are stored in the SAR logic. Then, the stored decision bits d1~dn are the digital representation of the sampled voltage V s and provide the SAR ADC output D out .

[0010] The SAR logic controls the DAC to update the reference voltage V ref for successive decision steps according to the comparison result in the comparator. This DAC can be implemented in various ways using switches whose states are controlled by input code bits from the SAR logic. For the first decision step, V ref can be set to the mid-voltage V DAC / 2 (where V DAC is the internal DAC reference voltage). Subsequent reference voltages V ref may follow a binary search through quantization levels so that the successive values V ref approach the sampled voltage V s gradually. In one example, for a sampled voltage V s = 3.1 volts and V DAC = 4 volts, a 4-bit SAR ADC can show how V ref changes over time t for the four decision steps, i = 1~4, of the SAR ADC. For the first decision i = 1, the SAR logic may supply the control code 1000 to the DAC switches to set V ref = V DAC / 2 = 2V. For each subsequent decision i = 2~4, the DAC control code can be updated according to the decision for the previous step, whereby V ref is V ref ±VDAC / 2 i It can be updated to V in the previous step. s ≥V ref In the case of V ref =V ref +V DAC / 2 i Therefore, in the previous step, V s <V ref In the case of V ref =V ref -V DAC / 2 i In this example, the binary search could proceed as follows:

[0011] DAC control code 1000,V ref =2V,d1=1;

[0012] DAC control code 1100,V ref =3V,d2=1;

[0013] DAC control code 1110,V ref =3.5V,d3=0;and

[0014] DAC control code 1101,V ref =3.25V, d4=0

[0015] At each determination step, the above control code sets the i-th bit to 1, and then d i It can be seen that if =1 or 0, the bit is either kept or reset, respectively. The resulting output code is D out = 1100.

[0016] Comparators can typically be implemented as regenerative comparators. These comparators offer zero static power loss, rail-to-rail output, and a compact design. For example, a two-stage clock-operated comparator design with a double-tail topology may comprise two stages: an integrating stage and a regenerative stage. The integrating stage may comprise an integrating preamplifier with a differential configuration. In the operation of the exemplary SAR ADC described above, the differential input signals DP,DN are sampled voltage V s and the reference signal V from the DAC ref Defined by: The inputs RP and RN can be used for offset calibration, as described later. Sampled voltage V s This can be applied across DP and DN (i.e., DP-DN=V s ). In each decision step, the DAC uses the reference signal V ref The differential input can be updated using this method, thereby making the residual voltage available at inputs DP and DN (i.e., DP-DN=V s -V ref The comparator can then determine at each decision step whether the resulting differential input is positive or negative. dd When the clock signal CKP is applied to connect to the node, the differential input voltages DN and DP can be converted into differential currents, which can then be integrated over nodes GP and GN. When the voltage difference between GP and GN reaches the desired level, the second stage (in response to the clock signal CKN) is activated. dd The (connected to) starts playback. Then, output V op or V on One of them is voltage V dd It can be regenerated to supply one component, but the other decreases to ground. Output V op and V on Which of these is reproduced depends on whether the preamplifier's differential output signal GP-GN is positive or negative. Consequently, this depends on whether DP-DN is positive or negative, and therefore V s and V refIt depends on which of the two is larger. This determines the differential output V op -V on This may show the comparison results. During the SAR cycle, input RP and RN are statically set to calibration values ​​that were set only once at startup to cancel out offsets caused by non-idealities in the comparator circuit configuration.

[0017] SAR ADCs generally feature a digitally integrated architecture with very few critical analog blocks. However, the sampling rate of a SAR ADC is limited by a feedback loop containing comparators, DACs, and SAR logic. (Feedback delay T) fb is a comparator (T ckq ) Clock-output delay, memory cell and SAR logic (T comb ) combined delay, and DAC settling time (T dac ) consists of.

[0018] T fb =T ckq +T comb +T dac

[0019] The sampling rate can be improved by asynchronous internal timing implemented by the logic blocks described above. In a synchronous architecture, the entire conversion process is synchronized to an external clock. In an asynchronous architecture, a timing logic block provides an internally generated clock to orchestrate the conversion process, thereby allocating exactly sufficient time for each comparison completed in the binary search process. This offers a significant speed advantage, eliminating the need for a high-speed clock distribution to control the conversion process and thereby reducing power consumption. However, the feedback loop remains a major speed limiter, as the DAC output must settle to an exact value before the next comparison takes place.

[0020] Various other techniques have been proposed to improve the sampling rate. Set-and-down conversion provides more efficient switching in the DAC. A multi-bit per conversion step approach is applicable using multiple comparators to perform two or more decisions in each step. DAC redundancy is possible for partial setting of the CDA, but increases the number of conversion steps for a given resolution. The architecture may also use a separate comparator for each bit decision. Successive control schemes are also applicable to SAR ADCs, allowing all parts of the circuit to operate in parallel. However, all of the above techniques have various drawbacks in terms of power consumption and / or area consumption, particularly due to the use of additional DACs or additional comparators or other important analog blocks, or both. Set-and-down switching techniques reduce the combined delay between the comparator output and the DAC switch, but the sampling rate is still limited by the DAC feedback loop. Furthermore, in a single-comparator architecture, when decisions must propagate across multiple memory cells, the decision requires more buffering, resulting in increased power loss and further delay.

[0021] Figure 1 is a schematic block diagram of an unrolled SAR ADC 10 according to several embodiments of the present disclosure. This SAR ADC 10 comprises a sampling circuit 11, a DAC 12, and a regeneration comparator 13. The regeneration comparator 13 has an integrating circuit and a plurality of regeneration circuits, which are described in detail below and are referred to herein as a regeneration-unrolled comparator (RUC). The sampling circuit 11 processes the sampled voltage V s To obtain the sampled voltage V, the analog input signal is sampled. RUC13 then takes the sampled voltage V as detailed below. s a series of reference voltages Vref In comparison, it operates to generate a decision bit indicating the comparison result for each reference voltage. DAC12 gradually approaches the voltage sampled by the binary search process described above, using a series of reference voltages V in response to the continuous comparison results in RUC13. ref This generates the following. During this operation, the RUC13's integrator generates output signals that define the aforementioned decision bits for the successive steps of the comparison process. The RUC13's regenerator receives the output signals from the integrator. These regenerators are operable to store the respective decision bits defined by the successive output signals from the integrator in response to their respective control signals. The resulting set of stored decision bits is the SAR ADC output D out To provide.

[0022] Figure 2 shows a schematic of a regenerative unrolled comparator 13 according to several embodiments of the present disclosure. This design is based on a double-tail regenerative comparator. However, while RUC13 has a single integrating circuit, RUC13 also includes multiple n regenerative circuits, where n depends on the accuracy of the SAR ADC. In this example, there are eight regenerative circuits R0 to R7 for an 8-bit SAR ADC 10. In addition, the integrating circuit 18 includes additional transistors NP and NN that convert the differential output voltage GP / GN of the preamplifier into a differential current. This differential current output signal is directed to one of the regenerative circuits R0 to R7, as described below.

[0023] The operation of RUC13 is controlled by clock signals (CKP and CKN0~CKN7) and control signals (ENB0~ENB7) that can be generated by the control signal generator 15. When CKP is applied for the sequential steps i=0~7 of the comparison operation, the integrating circuit 18 generates a differential output current indicating the comparison result. This output signal is directed to one of the regeneration circuits R0~R7 by the control signals ENB0~ENB7. In the first decision step i=0, ENB0 is asserted at the cascaded transistor of regeneration circuit R0, connecting R0 to the integrating circuit. CKN0 is also asserted to enable regeneration. Then, one of the outputs (e.g., QP) is used. <0> or QN <0> Either of the following is V dd The first component is regenerated, while the other component decreases to ground according to the comparison result. Once this regeneration is complete, ENB0 goes down while CKN0 remains asserted in order to disconnect R0 from the integrating circuit 18. As a result, the regeneration circuit R0 stores the first comparator decision, and the decision bit d0 is set to the differential output QP of this circuit. <0> ,QN <0> This is defined by the state. For the subsequent decision steps i=1~7, the output of the integrating circuit 18 is directed to the continuous regeneration circuits R1~R7 in response to the assertion of the continuous control signals EBN1~EBN7. These circuits are enabled by the continuous clock signals CKN1~CKN7, thereby storing the subsequent decision bits d1~d7 in their respective circuits R1~R7. When the final decision step is completed, the decision bits d0~d7 stored in R0~R7 are sent to the output D of the SAR ADC 10. out To provide.

[0024] As described above, by storing the comparator decision, the RUC13 eliminates the need for memory cells and logic between the comparator and the DAC of the SAR ADC10. The DAC12 is controllable directly based on the comparison result in the RUC13. Beneficially, the DAC is configured to receive decision bits d1~d7 stored by the playback circuits R0~R7. Thereafter, the DAC switch is directly controllable by the decision bits, reducing buffering requirements. Eliminating the SAR logic between the comparator and the DAC reduces the feedback loop delay T. fb This significantly reduces the feedback delay T, providing an improved sampling rate. In the SAR ADC10, the feedback delay T fb is, T fb =T ckq +T dac It can be approximated as such, providing a significant increase in sampling rate. The SAR ADC10 also achieves a very compact design with only one key analog block, namely the RUC13.

[0025] In the design shown in Figure 2, the additional gain circuits introduced by the NN and NP reduce the potential offset caused by the mismatch in the regeneration circuits R0-R7. This can be further reduced by simply adjusting the comparator gains as needed. The higher the sampling rate provided by the SAR ADC10, the more it can be further improved by the known speed-enhancing techniques mentioned above. For example, asynchronous implementation allows for fine-tuning of the clock generation loop to accommodate different settling times for different decisions.

[0026] Figure 3 is a schematic block diagram of an asynchronous SAR ADC 20 using RUC 13. The SAR ADC 20 includes a clock oscillation logic, collectively shown as 21, for generating a clock signal CKP that initiates the alternating comparison and reset operations of the comparator. The clock oscillation logic 21 initiates the continuous reset operation of the comparator in response to the storage of continuous decision bits by the regeneration circuits R0 to R7. In the shown design, the clock oscillation logic 21 comprises a first pulse generator 22, a second pulse generator 23, and a clock signal generator 24. The first pulse generator 22 comprises component pulse generators P0 to P7, each of which is connected to its respective regeneration circuits R0 to R7 to generate a pulse in response to the storage of decision bits by its regeneration circuit. The pulse generator logic 23 is connected to the integrator circuit 18 of RUC 13 and receives differential output signals GP and GN from this circuit. The pulse generator logic 23 can generate pulses in response to the reset of the output signals GP and GN after each comparison step. The clock signal generator 24 is connected to the pulse generators 22 and 23 and controls the transition of the clock signal CKP in response to pulses from the pulse generators. When the regeneration circuits R0 to R7 store the decision bits, pulse P from the pulse generator 22 is generated. <0> ~P <7> However, the clock generator 24 pulls down CKP to initiate the reset operation. Then, when GP / GN goes high to indicate that the reset is complete, a pulse from the pulse generator 23 pulls up CKP to the clock generator 24, initiating another comparison. Thus, this variable clock timing allows just enough time for each decision step to complete.

[0027] In the SAR ADC described herein, offset compensation is required only in the integrating circuit. This is in contrast to previous designs that use multiple comparators where each comparator needs to be calibrated.

[0028] Figure 4 is a schematic block diagram of a further embodiment of a regenerative comparator for a SAR ADC with a dynamic offset compensation mechanism. Using this RUC25, the SAR ADC10 can operate in conversion mode and calibration mode. In conversion mode, the SAR ADC performs analog-to-digital conversion of the sampled input voltage as described above. In calibration mode, the input to RUC25 is short-circuited as shown in Figure 4. RUC25 generally corresponds to RUC13 in Figure 3 but includes an additional regenerative circuit RC. This regenerative circuit RC is enabled (generally by control and clock signals, as described for other regenerative circuits) to receive an output signal from the integrating circuit in calibration mode and store an additional decision bit defined by this output signal. The resulting decision bits, defined by the outputs QPC,QNC of RC, are supplied to calibration logic 26. This calibration logic can be implemented in known ways and calculates the comparator offset from the decision bits stored by RC over multiple calibration cycles. In particular, the decision bit stored by RC should be either 1 or 0, with equal probability for a zero comparator offset. Any distortion in this probability distribution can be corrected by applying a differential voltage to the inputs RP and RN of the integrating circuit. For example, if the DP input transistor is more powerful due to non-idealism in the circuit, RP will be greater than RN to balance both sides. The comparator offset can be periodically calculated by calibration logic 26, for example, after a continuous conversion operation or multiple conversion operations. The appropriate offset signal is then applied to the inputs RP and RN to cancel out the comparator offset.

[0029] The RUC-based SAR ADCs described offer a highly efficient design with reduced feedback delay and significantly improved sampling rates. These SAR ADCs do not increase the number of significant analog blocks or design overhead, and do not involve a substantial increase in area, power consumption, or hardware complexity. Initial results indicate that higher conversion speeds are achievable with similar power values ​​and area. A comparison of RUC SAR ADCs and SAR ADCs using conventional regenerative comparators shows similar DAC settling times in the two architectures. However, the simulated delay from comparator decision to DAC input was 16.5–19 ps (depending on the bit) in the conventional architecture. With the RUC architecture, the above delay was reduced to 6.6–9 ps (depending on the bit).

[0030] Sampling speed and current consumption are significantly improved when using RUC SAR ADCs compared to conventional comparator asynchronous SAR ADCs. The DAC loop is considerably faster with RUC than with standard SAR ADC topologies, making higher sampling speeds achievable in other designs. Assuming the same power losses, RUC SAR ADCs are also expected to have lower noise due to higher integrator gains.

[0031] RUC-based SAR ADCs offer improved performance in numerous applications, including data acquisition systems such as I / O relay receivers, and in various systems where multiple sensor outputs require digitization, for example, for biomedical applications. The SAR ADCs described herein also have significant potential in so-called "in-memory" computing architectures. In-memory computing refers to techniques for performing specific computational tasks in place in a computing memory unit using an array of memory devices. The basic architecture of an in-memory computing device is schematically shown in Figure 5. Device 30 comprises an array of memory devices connected between each pair of word lines and bit lines of the array. These memory devices store values ​​for computations that provide computational results on the word lines, to which input signals are applied to the bit lines of the array to acquire analog output signals. Each word line is connected to an ADC for converting the analog output signal on that word line into a digital signal for further processing. These high-density crossbar arrays of memory devices provide a large-scale parallel and highly area-efficient and energy-efficient computing architecture, offering a solution to the so-called "von Neumann bottleneck" that limits conventional computing systems. In-memory computing is generally particularly beneficial for high-numerical computation applications such as neural networks and AI (artificial intelligence) applications. In-memory computing architectures for these applications require a large number of ADCs. These ADCs should not compromise the speed advantages of in-memory computing and should not be driven by power consumption. RUC-based SAR ADCs in the above systems offer a promising solution, providing zero latency, power efficiency, and the potential for large-scale integration for both parallel and time-interleaved applications.

[0032] Figure 6 shows a high-level analog-to-digital conversion method 600 according to some embodiments of the present disclosure. Method 600 includes, in operation 602, acquiring an analog input voltage. Operation 602 may include, for example, sampling the analog input by a sampling circuit, such as sampling circuit 11. Method 600 further includes, in operation 604, generating a reference voltage. Operation 604 may be performed by a digital-to-analog converter (DAC), such as DAC12. In some examples, the initial reference voltage is some internal DAC voltage V DAC It can be based on this.

[0033] Method 600 further includes comparing a sampled voltage with a reference voltage in operation 606. Operation 606 may be performed by a regenerative comparator, such as regenerative comparator 13.

[0034] Method 600 further includes generating a decision bit based on a comparison in operation 608. Operation 608 may be performed by an integrator of a regenerative comparator, such as integrator 18. The decision bit may be represented by a differential current output from the integrator.

[0035] Method 600 further includes storing a decision bit in the regeneration circuit in operation 610. Operation 610 may include, for example, directing a current output from the integrator circuit to the regeneration circuit. Operation 610 may be performed by a control signal, for example, one of ENB0 to ENB7. Depending on the value of the decision bit, one of the two outputs of the regeneration circuit may be zero (the other may be regenerated), and as a result, the decision bit is stored in the regeneration circuit.

[0036] Method 600 further includes iteration by n regeneration circuits for n decision bits. Thereafter, method 600 further includes determining in decision 612 whether n decision bits have been stored. For example, a regeneration comparator having 8 regeneration circuits may store n=8 decision bits (one decision bit in each regeneration circuit). If the desired number of decision bits have been stored (612, "Yes"), method 600 may terminate in 616.

[0037] If more decision bits still need to be generated / stored (612, "No"), method 600 proceeds in operation 614 to generate the next reference voltage based on the previous comparison. Operation 614 may include, for example, generating a higher reference voltage if the previous reference voltage was less than the sample voltage (as determined in operation 606). On the other hand, if it is determined that the previous reference voltage was higher than the sample voltage (in operation 606), operation 614 may include generating a lower reference voltage.

[0038] Using the next reference voltage, method 600 loops back in operation 606 to compare the next reference voltage with the (same) sampled voltage, and then proceeds again with operations 608-612. In this way, method 600 can, as a result, approach the analog voltage and store the result (i.e., the decision bit) in the regeneration circuit.

[0039] It will be understood that many alternatives and modifications can be made to the specific embodiments described above. For example, the integration and regeneration circuits for the SAR ADC according to this disclosure can be implemented using various other circuit designs that will be obvious to those skilled in the art. Other clock generation circuits and timing control circuits can also be envisioned.

[0040] While descriptions of various embodiments of the present invention are provided for illustrative purposes, they are not intended to be exhaustive or limitful to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art, without departing from the scope and spirit of the described embodiments. The terms used herein have been chosen to best describe the principles of the embodiments, the practical application or improvement of existing technologies, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A successive approximation analog-to-digital converter, A sampling circuit configured to sample an analog input signal in order to obtain a sampled voltage, A regenerative comparator, The sampled voltage is compared with a series of reference voltages, For each of the series of reference voltages, a determination bit is generated based on the comparison, wherein the determination bit is included in the set of determination bits. The regeneration comparator is configured to perform the following: A digital-to-analog converter configured to generate a series of reference voltages that gradually approach the sampled voltage, wherein the series of reference voltages includes at least the following reference voltage, the generation of the following reference voltage is based on a previous comparison result from the regenerative comparator, and the digital-to-analog converter The regenerative comparator is equipped with, An integral circuit configured to generate an output signal that defines each of the set of determination bits, Multiple playback circuits, wherein the playback circuit is Receiving the aforementioned output signal, Receiving control signals, The regeneration circuit is configured to store the determination bit defined by the output signal from the integration circuit in response to the control signal, and Includes, Generating a clock signal, Controlling the transition of the clock signal between an up state and a down state, wherein the control is based on the storage of the set of determination bits by the regeneration circuit. The comparison operation and reset operation of the regenerative comparator are performed alternately via the clock signal, and the alternation is based on whether the clock signal is in the up state or the down state. The clock oscillation logic is further configured to perform the following: The aforementioned clock oscillation logic A first pulse generator connected to the regeneration circuit, wherein the first pulse generator is configured to generate a first pulse in response to the storage of any determination bit of the set of determination bits by each regeneration circuit, A second pulse generator connected to the integration circuit, wherein the second pulse generator is configured to generate a second pulse in response to the reset of each output signal from the integration circuit, A clock signal generator connected to the first and second pulse generators for controlling the transition of the clock signal in response to pulses from the pulse generators, Equipped with, Analog-to-digital converter.

2. The aforementioned digital-to-analog converter Receiving the set of determination bits stored by the regeneration circuit, Based on the set of determination bits, the generation of the reference voltage is controlled, The analog-to-digital converter according to claim 1, configured to perform the following:

3. The analog-to-digital converter according to claim 1, wherein the regeneration comparator includes n regeneration circuits, and each of the n regeneration circuits is configured to store a correspondence determination bit.

4. The analog-to-digital converter is capable of operating in a conversion mode for analog-to-digital conversion of the sampled input voltage. The analog-to-digital converter is capable of operating in a calibration mode where the input to the regeneration comparator is short-circuited. The aforementioned regenerative comparator, A further regeneration circuit configured to receive an output signal from the integrating circuit in the calibration mode, wherein the further regeneration circuit is operable to store a further decision bit defined by the output signal in response to a further control signal, Calibration logic, The comparator offset is calculated from the determination bits stored by the aforementioned further regeneration circuit, To reduce the comparator offset, an offset signal is applied to the comparator, The calibration logic configured to perform the following: The analog-to-digital converter according to claim 3, further comprising:

5. The analog-to-digital converter according to claim 1, wherein the integrating circuit comprises an integrating preamplifier.

6. The analog-to-digital converter according to claim 5, wherein the integrating preamplifier is configured to convert a differential voltage output signal into a differential current output signal, and the differential current output signal is directed to a continuous regeneration circuit by the control signal.

7. The analog-to-digital converter according to claim 5, wherein the integrating preamplifier has a double-tail topology.

8. The analog-to-digital converter according to claim 1, further comprising a control signal generator for generating the aforementioned control signal.

9. An in-memory computing device comprising an array of memory devices, wherein input signals are supplied to bit lines to obtain analog output signals on word lines, the memory devices are connected between each pair of word lines and bit lines of the array to store values ​​for calculations, each word line is connected to an analog-to-digital converter for analog-to-digital conversion of the output signals on the word lines, and the analog-to-digital converter A sampling circuit configured to sample an analog input signal in order to obtain a sampled voltage, A regenerative comparator, The sampled voltage is compared with a series of reference voltages, For each of the series of reference voltages, a determination bit is generated based on the comparison, wherein the determination bit is included in the set of determination bits. The regeneration comparator is configured to perform the following: A digital-to-analog converter configured to generate a series of reference voltages, including at least the following reference voltages, wherein the generation of the following reference voltages is based on a previous comparison result from the regenerative comparator to gradually approach the sampled voltage, and The regenerative comparator is equipped with, An integral circuit configured to generate an output signal that defines each of the set of determination bits, Multiple playback circuits, wherein the playback circuit is Receiving the aforementioned output signal, Receiving control signals, The regeneration circuit is configured to store the determination bit defined by the output signal from the integration circuit in response to the control signal, and Includes, Generating a clock signal, Controlling the transition of the clock signal between an up state and a down state, wherein the control is based on the storage of the set of determination bits by the regeneration circuit. The comparison operation and reset operation of the regenerative comparator are performed alternately via the clock signal, and the alternation is based on whether the clock signal is in the up state or the down state. The clock oscillation logic is further configured to perform the following: The aforementioned clock oscillation logic A first pulse generator connected to the regeneration circuit, wherein the first pulse generator is configured to generate a first pulse in response to the storage of any determination bit of the set of determination bits by each regeneration circuit, A second pulse generator connected to the integration circuit, wherein the second pulse generator is configured to generate a second pulse in response to the reset of each output signal from the integration circuit, A clock signal generator connected to the first and second pulse generators for controlling the transition of the clock signal in response to pulses from the pulse generators, Equipped with, In-memory computing device.

10. The sampling circuit samples the analog input signal, and Based on the aforementioned sampling, the sampled voltage is obtained, The comparison is performed by a regenerative comparator, wherein the regenerative comparator includes an integrating circuit and a plurality of regenerative circuits, The regenerative comparator generates a determination bit for each of the series of reference voltages based on the comparison, wherein the determination bit is included in the set of determination bits. The process involves generating a series of reference voltages by a digital-to-analog converter such that the sampled voltage is gradually approached, wherein generating the series of reference voltages includes generating the next reference voltage, and generating the next reference voltage is based on the previous comparison result from the regenerative comparator. The integration circuit included in the regenerative comparator generates an output signal that defines each of the set of determination bits, The plurality of regeneration circuits receive the output signal, The aforementioned multiple regeneration circuits receive control signals, In response to the control signal, and using the plurality of regeneration circuits, the determination bit defined by the output signal from the integration circuit is stored. Includes, The clock oscillation logic generates a clock signal, The clock oscillation logic controls the transition of the clock signal between an up state and a down state, and this control is based on the storage of the set of determination bits by the plurality of regeneration circuits. Based on whether the clock signal is in the up state or the down state, the comparison operation and reset operation of the regeneration comparator are performed alternately. It further includes, A first pulse generator connected to the plurality of regeneration circuits generates a first pulse in response to the storage of any determination bit of the set of determination bits by each regeneration circuit. A second pulse generator connected to the integrating circuit generates a second pulse in response to the reset of each output signal from the integrating circuit. The transition of the clock signal is controlled by a clock signal generator connected to the first and second pulse generators in response to pulses from the pulse generators, This also includes, method.

11. The digital-to-analog converter receives the set of determination bits stored by the playback circuit, The generation of the reference voltage is controlled by the digital-to-analog converter and based on the set of determination bits, The method according to claim 10, further comprising:

12. A further regeneration circuit included in the aforementioned regeneration comparator receives the calibration output signal from the integration circuit in calibration mode, The aforementioned further regeneration circuit stores further decision bits defined by the calibration output signal in response to further control signals, The calibration logic included in the regeneration comparator calculates the comparator offset from the determination bits stored by the further regeneration circuit, The calibration logic involves applying an offset signal to the comparator in order to reduce the comparator offset, The method according to claim 10, further comprising:

13. The method according to claim 10, wherein the integrating circuit comprises an integrating preamplifier.

14. The integral preamplifier included in the integral circuit converts the differential voltage output signal into a differential current output signal, The control signal directs the differential current output signal to a continuous regeneration circuit, The method according to claim 13, further comprising:

15. The method according to claim 13, wherein the integrating preamplifier has a double-tail topology.

16. The method according to claim 10, further comprising generating the control signal using a control signal generator.

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