A reference output buffer circuit for use in an analog-to-digital converter system

Abstract

The application relates to the field of integrated circuits, in particular to a reference output buffer circuit applied to an analog-to-digital converter system, which comprises four-stage operational amplifiers, the positive-phase output end of the first-stage operational amplifier is connected with the positive-phase input end of the next-stage operational amplifier, a switch and a capacitor cascade structure are arranged between the negative-phase output end of the first-stage operational amplifier and the positive-phase output end of the second-stage operational amplifier and between the negative-phase output end of the third-stage operational amplifier, a capacitor is arranged between the positive-phase output end of the first-stage operational amplifier and the negative-phase output end of the second-stage operational amplifier and between the positive-phase output end of the third-stage operational amplifier, the capacitor is controlled to be turned on or turned off through a switch controlled by a trimming signal, and the output of the fourth-stage operational amplifier is the optimized reference voltage and serves as the negative-phase input of the first-stage operational amplifier. The circuit meets the loop stability requirement of the reference buffer circuit under the condition of using different types of external capacitors.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically to a reference output buffer circuit applied in an analog-to-digital converter system. Background Technology

[0002] In high-precision SAR ADC systems, a stable, low-noise, and precise reference voltage capable of driving subsequent circuitry is required. The reference output buffer, as a crucial component, primarily provides sufficient drive for the reference voltage while meeting requirements for low noise, low offset, low temperature drift, and stability. The reference voltage source is critical to the performance of a high-precision ADC. The reference output buffer first ensures the stability of the reference voltage, making it unaffected by load variations, maintaining a constant reference voltage even between different conversion cycles or when external circuits have significant demands on the reference voltage. Secondly, it possesses sufficient drive capability to provide a strongly driven reference voltage to the ADC's internal capacitor array (DAC) module, ensuring accurate reference voltage transmission throughout the ADC conversion and meeting the DAC's settling time and accuracy requirements. Finally, a well-designed reference output buffer can also reduce the impact of power supply noise and crosstalk on the reference voltage.

[0003] Current technology still lacks a reference output buffer circuit that can meet the requirements of low noise, low offset, low temperature drift, and stability. Summary of the Invention

[0004] To provide sufficient drive capability for the reference voltage and meet the requirements of low noise, low offset, low temperature drift, and stability in the reference output buffer circuit of a high-speed, high-precision analog-to-digital converter, this invention proposes a reference output buffer circuit for use in an analog-to-digital converter system. This buffer circuit includes four operational amplifier stages. The non-inverting output of the preceding stage operational amplifier is connected to the non-inverting input of the following stage operational amplifier. A cascaded switch and capacitor structure is provided between the negative output of the first stage operational amplifier and the non-inverting output of the second stage operational amplifier, and between the negative output of the third stage operational amplifier. A capacitor is also provided between the non-inverting output of the first stage operational amplifier and the negative output of the second stage operational amplifier, and between the non-inverting output of the third stage operational amplifier. The switching on and off of this capacitor is controlled by a switch controlled by a trimming signal. The optimized reference voltage output of the fourth stage operational amplifier is used as the negative input of the first stage operational amplifier.

[0005] Furthermore, the input transistor of the first-stage operational amplifier uses a bipolar device as the input transistor.

[0006] Compared with the prior art, the reference output buffer circuit of the present invention adopts a high-gain operational amplifier connected in a unity-gain buffer structure. The operational amplifier circuit adopts a multi-stage amplification structure to meet the gain requirements. The input stage circuit of the first stage operational amplifier uses bipolar devices to improve the gain and reduce noise and offset. The output stage circuit can provide sufficient driving capability. The intermediate stage operational amplifier uses an adjustable Miller compensation structure to meet the loop stability requirements of the reference buffer circuit under different types of external capacitors. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a common reference output buffer.

[0008] Figure 2 This is a schematic diagram of the first-stage operational amplifier structure of the present invention;

[0009] Figure 3 This is a schematic diagram of the second-stage operational amplifier structure of the present invention;

[0010] Figure 4 This is a schematic diagram of the fourth-stage operational amplifier structure of the present invention;

[0011] Figure 5 This is a schematic diagram of the overall structure of a reference output buffer circuit applied in an analog-to-digital converter system according to the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] This invention proposes a reference output buffer circuit for use in an analog-to-digital converter system. The buffer circuit includes a four-stage operational amplifier. The non-inverting output of the previous stage operational amplifier is connected to the non-inverting input of the next stage operational amplifier. A cascaded switch and capacitor are arranged between the negative output of the first stage operational amplifier and the positive output of the second stage operational amplifier, and between the negative output of the third stage operational amplifier. A capacitor is arranged between the positive output of the first stage operational amplifier and the negative output of the second stage operational amplifier, and between the positive output of the third stage operational amplifier. The capacitor is switched on and off by a switch controlled by a trimming signal. The optimized reference voltage output of the fourth stage operational amplifier is used as the negative input of the first stage operational amplifier.

[0014] Figure 1 This is a common reference output buffer principle, with a reference voltage V. REFINV is provided by the precision reference circuit within the ADC system chip or by an external reference chip. REFIN The reference buffer circuit outputs a reference voltage to the DAC module. An external voltage regulator capacitor is required at the output port of the reference buffer to ensure that the provided reference voltage is stable and is not affected by kickback noise generated by the switching capacitors in the DAC module.

[0015] In this invention, the high-gain operational amplifier adopts a four-stage cascaded operational amplifier structure, specifically, as follows: Figure 5 Reference voltage V REFIN Connect the non-inverting input terminal of the first-stage operational amplifier A1. Connect the non-inverting output terminal of the previous stage operational amplifier (A1, A2, A3) to the non-inverting input terminal of the next stage operational amplifier (A2, A3, A4), and connect the negative-inverting output terminal of the previous stage operational amplifier (A1, A2, A3) to the negative-inverting input terminal of the next stage operational amplifier (A2, A3, A4). That is, connect the negative-inverting output terminal of the first-stage operational amplifier A1 to the negative-inverting input terminal of the second-stage operational amplifier A2, and connect the non-inverting output terminal of the first-stage operational amplifier A1 to the non-inverting input terminal of the second-stage operational amplifier A2, and so on.

[0016] A switch and capacitor are cascaded between the negative output of the first-stage operational amplifier A1 and the positive output of the second-stage operational amplifier A2, and between the negative output of the third-stage operational amplifier A3, forming an adjustable Miller compensation structure. Specifically, as shown... Figure 5 A cascaded switch and a first capacitor C1 are provided between the negative output terminal of the first-stage operational amplifier A1 and the positive output terminal of the second-stage operational amplifier A2; a cascaded switch and a third capacitor C3 are provided between the negative output terminal of the first-stage operational amplifier A1 and the negative output terminal of the third-stage operational amplifier A3.

[0017] A cascaded switch and a second capacitor C2 are provided between the non-inverting output terminal of the first-stage operational amplifier A1 and the negative-inverting output terminal of the second-stage operational amplifier A2. A cascaded switch and a fourth capacitor C4 are provided between the non-inverting output terminal of the first-stage operational amplifier A1 and the non-inverting output terminal of the third-stage operational amplifier A3.

[0018] The negative input terminal of the fourth-stage operational amplifier A4 is connected to the negative output terminal of the third-stage operational amplifier A3, and the positive input terminal is connected to the positive output terminal of the third-stage operational amplifier A3. The output terminal of the fourth-stage operational amplifier A4 outputs the optimized reference voltage V. REFOUT ;

[0019] The first to fourth capacitors are switched on and off by a switch controlled by a tuning signal.

[0020] The input stage of the operational amplifier in this invention consists of differential pairs, whose performance affects parameters such as noise, offset, and bandwidth. Optimizing the input stage circuit is key to improving the operational amplifier's performance. Therefore, the input transistors of the first-stage operational amplifier are bipolar devices. In this embodiment, a high-β NPN transistor is used. Compared to using MOS devices, bipolar devices offer advantages such as low noise, low mismatch, and high transconductance. However, since bipolar devices, as input transistors, require a base current of approximately 10nA to 100nA, a base current compensation structure is designed.

[0021] Specifically, such as Figure 2 In this embodiment, the first-stage operational amplifier includes thirty-three MOSFETs (M1 to M33), three transistors (Q1 to Q3), and six resistors (R1 to R6).

[0022] The gates of the first MOSFET M1 to the fifth MOSFET M5, the gate of the eighth MOSFET M8, the gate of the tenth MOSFET M10, the gate of the nineteenth MOSFET M19, the gate of the twenty-second MOSFET M22, the source of the twenty-third MOSFET M23, and the drain of the first MOSFET M1 are connected to the first bias current terminal PIB0, and the source of the first MOSFET M1 is connected to the drain of the second MOSFET M2.

[0023] The source of the second MOSFET M2 is connected to the drain of the third MOSFET M3;

[0024] The source of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4;

[0025] The sources of the fourth MOSFET M4, the sixth MOSFET M6, the seventh MOSFET M7, the ninth MOSFET M9, the twentieth MOSFET M20, and the twenty-first MOSFET M21 are connected to the ground terminal GND.

[0026] The source of the fifth MOSFET M5 is connected to the drain of the sixth MOSFET M6. The drain of the fifth MOSFET M5, the gate of the sixth MOSFET M6, the gate of the seventh MOSFET M7, the gate of the ninth MOSFET M9, the gate of the twentieth MOSFET M20, and the gate of the twenty-first MOSFET M21 are connected to the second bias current terminal PIB1.

[0027] The drain of the seventh MOSFET M7 is connected to the source of the eighth MOSFET M8;

[0028] The drain of the eighth MOSFET M8 is connected to one end of the fourth resistor R4, the gate of the twenty-ninth MOSFET M29, and the gates of the thirty-first MOSFETs M31 to M33 MOSFETs M33.

[0029] The drain of the ninth MOSFET M9 is connected to the source of the tenth MOSFET M10;

[0030] The drain of the tenth MOSFET M10 is connected to the source of the eleventh MOSFET M11 through the twelfth MOSFET M12.

[0031] The gate of the eleventh MOSFET M11 is connected to the drain of the thirteenth MOSFET M13, the drain of the sixteenth MOSFET M16, the gate and drain of the thirty-first MOSFET M31, and the base of the third transistor Q3.

[0032] The gate of the twelfth MOSFET M12, the drain of the thirteenth MOSFET M13, the drain of the seventeenth MOSFET M17, the source and drain of the thirty-second MOSFET M32, and the base of the first transistor Q1 are connected together as the non-inverting input terminal of the first-stage operational amplifier A1. The drain of the twelfth MOSFET M12 is connected to one end of the sixth resistor R6, the drain of the fifteenth MOSFET M15, and the gates of the sixteenth MOSFET M16 to the eighteenth MOSFET M18.

[0033] The gate of the thirteenth MOSFET M13 is connected to the enable terminal ENP. Preferably, when the entire reference buffer is off, the enable terminal input control is low, the thirteenth MOSFET M13 is turned on, so that the base voltages of the first transistor Q1 and the third transistor Q3 are the same. When the reference buffer starts working, the enable terminal input control is high, the thirteenth MOSFET M13 is turned off, and the auxiliary operational amplifier is activated.

[0034] The gate of the fourteenth MOSFET M14 is connected to the other end of the fifth resistor R5, the other end of the sixth resistor R6, and the gate of the fifteenth MOSFET M15. The drains of the fourteenth MOSFET M14 to the eighteenth MOSFET M18, the drain of the thirtieth MOSFET M30, one end of the first resistor R1, and one end of the second resistor R2 are connected to the power supply terminal VCC.

[0035] The drain of the eighteenth MOSFET M18 is connected to the gate and drain of the thirty-third MOSFET M33 and the base of the second transistor Q2, serving as the negative input terminal of the first-stage operational amplifier A1.

[0036] The source of the nineteenth MOSFET M19 is connected to the drain of the twentieth MOSFET M20, and the drain of the nineteenth MOSFET M19 is connected to the emitter of the third transistor Q3.

[0037] The drain of the 21st MOSFET M21 is connected to the source of the 22nd MOSFET M22;

[0038] The drain of the 22nd MOSFET M22 is connected to the emitter of the 1st MOSFET Q1, the emitter of the 2nd MOSFET Q2, the source of the 25th MOSFET M25, and the source of the 27th MOSFET M27.

[0039] The gate of the 23rd MOSFET M23 is connected to the drain of the 23rd MOSFET M23 and the source of the 24th MOSFET M24.

[0040] The gate and drain of the 24th MOSFET M24, one end of the third resistor R3, and the collector of the third transistor Q3 are connected together.

[0041] The gate and drain of the 25th MOSFET M35 and the drain of the 26th MOSFET M26 are connected together;

[0042] The gate and drain of the 26th MOS transistor M26, the collector of the first transistor Q1, and the other end of the second resistor R2 are connected together and serve as the negative output terminal of the first-stage operational amplifier A1.

[0043] The gate and drain of the 27th MOSFET M27 and the drain of the 28th MOSFET M28 are connected together;

[0044] The gate and drain of the 28th MOSFET M28, the collector of the 2nd transistor Q2, and the other end of the first resistor R1 are connected together and serve as the non-inverting output terminal of the first-stage operational amplifier A1.

[0045] The source of the 29th MOSFET M29 is connected to the drain of the 30th MOSFET M30. The drain of the 29th MOSFET M29 is connected to the other end of the fourth resistor R4 and the gate of the 30th MOSFET M30.

[0046] Specifically, such as Figure 2As shown, transistors Q1 and Q2 are the input pair of the operational amplifier. Since NPN transistors require input bias current, even with their high β value, a small input bias current is still needed to serve as the base current for the input pair. A simple differential operational amplifier is used as the auxiliary operational amplifier, consisting of MOSFETs M9 and M10 as tail current sources, MOSFETs M11 and M12 as input transistors, MOSFET M13 as a switch, and MOSFETs M14 and M15 as load transistors. This auxiliary operational amplifier clamps the base voltages of transistors Q3 and Q1. The output of the operational amplifier is connected to MOSFETs M15, M16, and M17. The gate of MOSFET M47 is adjusted by regulating the branch currents flowing through MOSFETs M15, M16, and M47 to obtain the required base compensation current. MOSFETs M25 and M26 are connected in series as diodes, which accelerates the setup speed when the op-amp starts working. MOSFETs M27, M28, M23, and M24 serve the same purpose. MOSFETs M31, M32, and M33 form a capacitor structure, which also accelerates the setup speed when the op-amp starts working.

[0047] Specifically, the second-stage operational amplifier A2 and the third-stage operational amplifier A3 adopt the same structure, such as... Figure 3 This embodiment uses the second-stage operational amplifier structure as an example for illustration. The second-stage operational amplifier A2 includes six MOSFETs (the thirty-fourth MOSFET M34 to the thirty-ninth MOSFET M39) and two resistors (the seventh resistor R7 to the eighth resistor R8), wherein:

[0048] The gate of the 34th MOSFET M34 is connected to the second bias voltage VB2, the source is connected to the ground terminal GND, and the drain is connected to the source of the 35th MOSFET M35.

[0049] The gate of the 35th MOSFET M35 is connected to the first bias voltage VB1, and the drain is connected to the source of the 36th MOSFET M36 and the source of the 37th MOSFET M37. In this embodiment, the first bias voltage VB1 and the second bias voltage VB2 are two bias voltages of different magnitudes, used to provide bias voltage for the tail current source transistor of the second stage operational amplifier.

[0050] The gate of the 36th MOSFET M36 serves as the positive input terminal of the second-stage operational amplifier A2. The drains of the 36th MOSFET M36, the drain of the 38th MOSFET M38, and one end of the 7th resistor R7 are connected together to serve as the negative output terminal of the second-stage operational amplifier A2.

[0051] The gate of the 37th MOSFET M37 serves as the negative input terminal of the second-stage operational amplifier A2. The drains of the 37th MOSFET M37, the drain of the 39th MOSFET M39, and one end of the 8th resistor R9 are connected together to serve as the positive output terminal of the second-stage operational amplifier A2.

[0052] The gate of the 38th MOSFET M38 is connected to the other end of the 7th resistor R7, the other end of the 8th resistor R8, and the gate of the 39th MOSFET M39. The source of the 38th MOSFET M38 and the source of the 39th MOSFET M39 are connected to the power supply terminal.

[0053] In this embodiment, the 34th MOS transistor M34 and the 35th MOS transistor M35 in the second-stage operational amplifier A2 are current sources with a cascode structure. The first bias voltage VB1 and the second bias voltage VB2 can be provided by the first MOS transistor M1 to the sixth MOS transistor M6 in the first-stage operational amplifier.

[0054] Specifically, such as Figure 4 In this embodiment, the fourth-stage operational amplifier includes twenty-one MOSFETs (the 40th MOSFET M34 to the 60th MOSFET M60) and two resistors, wherein:

[0055] The gate and drain of the 40th MOSFET M40, the gate of the 41st MOSFET M41, the gate of the 42nd MOSFET M42, the gate of the 43rd MOSFET M43, the gate of the 44th MOSFET M44, the gate of the 47th MOSFET M47, and the gate of the 54th MOSFET M54 are connected to the third bias current terminal PIB2. The source of the 40th MOSFET M40 is connected to the drain of the 41st MOSFET M41.

[0056] The source of the forty-first MOSFET M41 is connected to the drain of the forty-second MOSFET M42;

[0057] The source of the forty-second MOSFET M42 is connected to the drain of the forty-third MOSFET M43;

[0058] The sources of the 43rd MOSFET M43, the 45th MOSFET M45, the 46th MOSFET M46, the 55th MOSFET M55, the 58th MOSFET M58, and the 59th MOSFET M59 are all grounded.

[0059] The source of the forty-fourth MOSFET M44 is connected to the drain of the forty-fifth MOSFET M45. The drain of the forty-fourth MOSFET M44 is connected to the gate of the forty-fifth MOSFET M45, the gate of the forty-sixth MOSFET M46, and the gate of the fifty-fifth MOSFET M55 are connected to the fourth bias current terminal PIB3.

[0060] The drain of the forty-sixth MOSFET M46 is connected to the source of the forty-seventh MOSFET M47;

[0061] The drain of the 47th MOSFET M47 is connected to the source of the 48th MOSFET M48, and the source of the 48th MOSFET M48 is connected together.

[0062] The gate of the forty-eighth MOSFET M48 serves as the non-inverting input of the fourth-stage operational amplifier A4. The drain of the forty-eighth MOSFET M48 is connected to the gate and drain of the fiftieth MOSFET M50 and the gate of the fifty-sixth MOSFET M56.

[0063] The gate of the forty-ninth MOSFET M49 serves as the negative input terminal of the fourth-stage operational amplifier A4. The drain of the forty-ninth MOSFET M49 is connected to the gate and drain of the fifty-first MOSFET M51 and the gate of the sixtieth MOSFET M60.

[0064] The drains of the 50th MOSFET M50, the 51st MOSFET M51, the 52nd MOSFET M52, the 56th MOSFET M56, and the 60th MOSFET M60 are connected to the power supply terminal VCC.

[0065] The gate and drain of the 52nd MOSFET M52 are connected together with the drain of the 53rd MOSFET M53;

[0066] The gate and drain of the 53rd MOSFET M53, the gate of the 57th MOSFET M57, and the drain of the 54th MOSFET M54 are connected together;

[0067] The source of the 54th MOSFET M54 is connected to the drain of the 55th MOSFET M55;

[0068] The drain of the 56th MOSFET M56 is connected to the source of the 57th MOSFET M57;

[0069] The drain of the 57th MOSFET M57, the gate and source of the 58th MOSFET M58, and the gate of the 59th MOSFET M59 are connected together;

[0070] The drain of the 59th MOSFET M59 is connected to one end of the 10th resistor R10;

[0071] The drain of the sixtieth MOSFET M60 is connected to one end of the ninth resistor R9;

[0072] The other end of the ninth resistor R9 and the other end of the tenth resistor R10 are connected together and serve as the output of the fourth operational amplifier A4.

[0073] In this invention, the output stage circuit of the fourth operational amplifier needs to provide sufficient driving capability; therefore, a push-pull output structure with large-size MOSFETs is adopted, such as... Figure 4 As shown, the third bias current terminal PIB2 and the fourth bias current terminal PIB3 provide bias current for the fourth stage operational amplifier, which is provided by an external bias current source circuit. The forty-sixth MOSFET M46 to the fifty-first MOSFET M51 form a single-stage operational amplifier structure, and the fifty-second MOSFET M52 to the sixtieth MOSFET M60 form a push-pull output structure. Among them, the sixtieth MOSFET M60 and the fifty-ninth MOSFET M59 are large-size transistors (in this embodiment, large-size means MOSFETs with W / L greater than 200u / 1u; preferably, large-size MOSFETs with W / L of 200u / 1u are selected) to provide sufficient current driving capability.

[0074] like Figure 5 The four operational amplifiers mentioned above are cascaded together and then connected into a unity-gain negative feedback structure, that is, the output terminal of the operational amplifier is connected to the negative input terminal of the operational amplifier, and the positive input terminal of the operational amplifier is connected to the reference voltage V. REFIN In high-precision ADC systems, a voltage regulator capacitor needs to be connected externally to the reference buffer output port to ensure that the provided reference voltage is stable and unaffected by kickback noise generated by the switching capacitors in the internal DAC module. However, due to the different parasitic resistances on different types of external capacitors and the complexity of the zeros and poles of the closed-loop circuit connected by multi-stage op-amps, the loop stability of the reference buffer circuit may be affected. Therefore, in this design, an adjustable Miller compensation structure is used in the intermediate stage op-amp. Specifically, capacitors C1 and C2 connected between the input and output of the second-stage op-amp, and capacitors C3 and C4 connected between the input of the second-stage op-amp and the output of the third-stage op-amp, are connected by a switch controlled by an adjustment signal to form a Miller compensation structure, thereby meeting the requirements for loop stability of the reference buffer circuit when using different types of external capacitors.

[0075] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A reference output buffer circuit applied in an analog-to-digital converter system, characterized in that, The buffer circuit includes a four-stage operational amplifier. The non-inverting output of the previous stage operational amplifier is connected to the non-inverting input of the next stage operational amplifier, and the negative-inverting output of the previous stage operational amplifier is connected to the negative-inverting input of the next stage operational amplifier. A switch and capacitor are cascaded between the negative-inverting output of the first stage operational amplifier and the positive-inverting output of the second stage operational amplifier, and between the negative-inverting output of the third stage operational amplifier. A capacitor is placed between the positive-inverting output of the first stage operational amplifier and the negative-inverting output of the second stage operational amplifier, and between the positive-inverting output of the third stage operational amplifier. The capacitor is switched on and off by a switch controlled by a trimming signal. The optimized reference voltage output of the fourth stage operational amplifier is used as the negative-inverting input of the first stage operational amplifier.

2. The reference output buffer circuit applied in an analog-to-digital converter system according to claim 1, characterized in that, The first-stage operational amplifier uses bipolar devices as its input transistors.

3. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 1 or 2, characterized in that, The first-stage operational amplifier consists of thirty-three MOSFETs, three transistors, and six resistors, among which: The gates of the first to fifth MOSFETs, the gate of the eighth MOSFET, the gate of the tenth MOSFET, the gate of the nineteenth MOSFET, the gate of the twenty-second MOSFET, the source of the twenty-third MOSFET, and the drain of the first MOSFET are connected to the first bias current terminal, and the source of the first MOSFET is connected to the drain of the second MOSFET. The source of the second MOSFET is connected to the drain of the third MOSFET; The source of the third MOSFET is connected to the drain of the fourth MOSFET; The sources of the fourth, sixth, seventh, ninth, twentieth, and twenty-first MOSFETs are connected to the ground terminal. The source of the fifth MOSFET is connected to the drain of the sixth MOSFET, and the drain of the fifth MOSFET, the gate of the sixth MOSFET, the gate of the seventh MOSFET, the gate of the ninth MOSFET, the gate of the twentieth MOSFET, and the gate of the twenty-first MOSFET are connected to the second bias current terminal. The drain of the seventh MOSFET is connected to the source of the eighth MOSFET; The drain of the eighth MOSFET is connected to one end of the fourth resistor, the gate of the twenty-ninth MOSFET, and the gates of the thirty-first and thirty-third MOSFETs. The drain of the ninth MOSFET is connected to the source of the tenth MOSFET; The drain of the tenth MOSFET is connected to the source of the eleventh to twelfth MOSFETs. The gate of the eleventh MOSFET is connected to the drain of the thirteenth MOSFET, the drain of the sixteenth MOSFET, the gate and drain of the thirty-first MOSFET, and the base of the third MOSFET. The gate of the twelfth MOSFET, the drain of the thirteenth MOSFET, the drain of the seventeenth MOSFET, the source and drain of the thirty-second MOSFET, and the base of the first transistor are connected together as the non-inverting input of the first-stage operational amplifier. The drain of the twelfth MOSFET is connected to one end of the sixth resistor, the drain of the fifteenth MOSFET, and the gates of the sixteenth to eighteenth MOSFETs. The gate of the thirteenth MOSFET is connected to the enable terminal; The gate of the fourteenth MOSFET is connected to the other end of the fifth resistor, the other end of the sixth resistor, and the gate of the fifteenth MOSFET. The drains of the fourteenth to eighteenth MOSFETs, the drain of the thirtieth MOSFET, one end of the first resistor, and one end of the second resistor are connected to the power supply. The drain of the eighteenth MOSFET is connected together with the gate and drain of the thirty-third MOSFET and the base of the second transistor to serve as the negative inverting input of the first-stage operational amplifier; The source of the nineteenth MOSFET is connected to the drain of the twentieth MOSFET, and the drain of the nineteenth MOSFET is connected to the emitter of the third transistor. The drain of the 21st MOSFET is connected to the source of the 22nd MOSFET. The drain of the 22nd MOSFET is connected to the emitter of the first transistor, the emitter of the second transistor, the source of the 25th MOSFET, and the source of the 27th MOSFET. The gate of the 23rd MOSFET is connected to the drain of the 23rd MOSFET and the source of the 24th MOSFET. The gate and drain of the 24th MOSFET, one end of the third resistor, and the collector of the third transistor are connected together. The gate and drain of the 25th MOSFET and the drain of the 26th MOSFET are connected together; The gate and drain of the 26th MOS transistor, the collector of the first transistor, and the other end of the second resistor are connected together and serve as the negative output terminal of the first-stage operational amplifier. The gate and drain of the 27th MOSFET and the drain of the 28th MOSFET are connected together; The gate and drain of the 28th MOS transistor, the collector of the 2nd transistor, and the other end of the first resistor are connected together and serve as the non-inverting output terminal of the first-stage operational amplifier. The source of the 29th MOSFET is connected to the drain of the 30th MOSFET, and the drain of the 29th MOSFET is connected to the other end of the fourth resistor and the gate of the 30th MOSFET.

4. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 3, characterized in that, The 13th to 18th MOSFETs and the 29th to 33rd MOSFETs are P-type MOSFETs, while the other MOSFETs are N-type MOSFETs.

5. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 3, characterized in that, The first to third transistors are NPN type transistors.

6. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 1, characterized in that, The second-stage operational amplifier and the third-stage operational amplifier use the same structure. The second-stage operational amplifier includes six MOSFETs and two resistors, wherein: The gate of the 34th MOSFET is connected to the second bias voltage VB2, the source is connected to the ground terminal, and the drain is connected to the source of the 35th MOSFET. The gate of the 35th MOSFET is connected to the first bias voltage VB1, and the drain is connected to the source of the 36th MOSFET and the source of the 37th MOSFET. The gate of the 36th MOS transistor serves as the positive input terminal of the second-stage operational amplifier, while the drains of the 36th MOS transistor, the 38th MOS transistor, and one end of the 7th resistor are connected together to serve as the negative output terminal of the second-stage operational amplifier. The gate of the 37th MOSFET serves as the negative input terminal of the second-stage operational amplifier, while the drains of the 37th MOSFET, the 39th MOSFET, and one end of the 8th resistor are connected together to serve as the positive output terminal of the second-stage operational amplifier. The gate of the 38th MOSFET is connected to the other end of the 7th resistor, the other end of the 8th resistor, and the gate of the 39th MOSFET. The source of the 38th MOSFET and the source of the 39th MOSFET are connected to the power supply terminal.

7. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 6, characterized in that, The 38th and 39th MOSFETs are P-type MOSFETs, while the 34th to 37th MOSFETs are N-type MOSFETs.

8. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 1, characterized in that, The fourth-stage operational amplifier consists of twenty-one MOSFETs and two resistors, wherein: The gates and drains of the 40th MOS transistor, the gates of the 41st MOS transistor, the 42nd MOS transistor, the 43rd MOS transistor, the 44th MOS transistor, the 47th MOS transistor, and the 54th MOS transistor are connected to the third bias current terminal, and the source of the 40th MOS transistor is connected to the drain of the 41st MOS transistor. The source of the forty-first MOSFET is connected to the drain of the forty-second MOSFET; The source of the 42nd MOSFET is connected to the drain of the 43rd MOSFET; The sources of the 43rd, 45th, 46th, 55th, 58th, and 59th MOSFETs are all grounded; The source of the forty-fourth MOSFET is connected to the drain of the forty-fifth MOSFET, and the drain of the forty-fourth MOSFET is connected to the gate of the forty-fifth MOSFET, the gate of the forty-sixth MOSFET, and the gate of the fifty-fifth MOSFET are connected to the fourth bias current terminal. The drain of the forty-sixth MOSFET is connected to the source of the forty-seventh MOSFET; The drain of the 47th MOSFET is connected to the source of the 48th MOSFET. The gate of the forty-eighth MOS transistor serves as the non-inverting input of the fourth-stage operational amplifier, and the drain of the forty-eighth MOS transistor is connected to the gate and drain of the fiftieth MOS transistor and the gate of the fifty-sixth MOS transistor. The gate of the 49th MOS transistor serves as the negative inverting input of the fourth-stage operational amplifier, and the drain of the 49th MOS transistor is connected to the gate and drain of the 51st MOS transistor and the gate of the 60th MOS transistor. The drains of the 50th, 51st, 52nd, 56th, and 60th MOSFETs are connected to the power supply. The gate and drain of the 52nd MOSFET are connected together with the drain of the 53rd MOSFET; The gate and drain of the 53rd MOSFET, the gate of the 57th MOSFET, and the drain of the 54th MOSFET are connected together; The source of the 54th MOSFET is connected to the drain of the 55th MOSFET; The drain of the 56th MOSFET is connected to the source of the 57th MOSFET; The drain of the 57th MOSFET, the gate and source of the 58th MOSFET, and the gate of the 59th MOSFET are connected together; The drain of the 59th MOSFET is connected to one end of the 10th resistor; The drain of the sixtieth MOSFET is connected to one end of the ninth resistor; The other ends of the ninth resistor and the tenth resistor are connected together and serve as the output of the fourth operational amplifier.

9. A reference output buffer circuit applied in an analog-to-digital converter system according to claim 8, characterized in that, MOSFETs 50 through 53, 56, 57, and 60 are P-type MOSFETs, while MOSFETs 40 through 49, 54 through 56, 58, and 59 are N-type MOSFETs.

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