Signal processing circuit, motor control device, motor, and blower

Abstract

To provide a signal processing circuit and a motor control device that can suppress occurrence of troubles in control of a control target while reducing noise in PWM signals.SOLUTION: A signal processing circuit includes comprises: a first output circuit unit that includes a low-pass filter and outputs a first PWM signal; a clamping circuit unit that clamps with a predetermined voltage value; and a second output circuit unit that outputs a second PWM signal on the basis of the first PWM signal being clamped. The first output circuit unit includes: an input terminal part; and a first resistance part with one end connected to the input terminal part via the low-pass filter. In a waveform of the first PWM signal, a rise time when a signal level switches from low to high is longer than a fall time when the signal level switches from high to low. A rate of change at a start point of a rise edge when the signal level switches from low to high is larger than a rate of change at an end point of the rise edge, and a fall edge when the signal level switches from high to low is a linear shape.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a signal processing circuit, a motor control device, a motor, and a blower device.

Background Art

[0002] As a method for controlling a control target such as a motor, PWM (Pulse Width Modulation) control is known. For example, Patent Document 1 describes a method for controlling a dimming device by PWM control.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a circuit for performing PWM control as described above, a low-pass filter may be provided in order to reduce the noise of the PWM signal. However, when a low-pass filter is provided, a distortion may occur in the waveform of the PWM signal, and a problem may occur in the control of the control target.

[0005] One aspect of the present invention is, in view of the above circumstances, to provide a signal processing circuit capable of suppressing the occurrence of problems in the control of a control target while reducing the noise of a PWM signal, a motor control device including such a signal processing circuit, a motor including such a motor control device, and a blower device including such a motor.

Means for Solving the Problems

[0006] One aspect of the signal processing circuit of the present invention includes a first output circuit section having a low-pass filter and outputting a first PWM signal based on an input signal; a clamp circuit section clamping the first PWM signal at a predetermined voltage value; and a second output circuit section outputting a second PWM signal based on the first PWM signal clamped by the clamp circuit section. The first output circuit section has an input terminal section connected to the output terminal of a transistor operating based on the input signal, and a first resistor section, one end of which is connected to the input terminal section via the low-pass filter. The other end of the first resistor section is connected to a first power supply. In the waveform of the first PWM signal, the rise time when the signal level switches from low to high is longer than the fall time when the signal level switches from high to low, the rate of change at the starting point of the rising edge when the signal level switches from low to high is greater than the rate of change at the ending point of the rising edge, and the fall edge when the signal level switches from high to low is linear.

[0007] One embodiment of the motor control device of the present invention comprises the above-described signal processing circuit and a motor driver circuit to which the second PWM signal output from the signal processing circuit is input.

[0008] One embodiment of the motor of the present invention comprises the above-described motor control device and a motor body controlled by the motor control device.

[0009] One embodiment of the blower device of the present invention comprises the above-mentioned motor and an impeller rotated by the motor. [Effects of the Invention]

[0010] According to one aspect of the present invention, it is possible to reduce noise in the PWM signal while suppressing malfunctions in the control of the controlled object. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a schematic diagram illustrating a blower device in one embodiment. [Figure 2] Figure 2 is a circuit diagram showing a signal processing circuit in one embodiment. [Figure 3] Figure 3 is a graph showing the waveform of the first PWM signal in one embodiment. [Figure 4] Figure 4 is a graph showing the waveform of the clamped first PWM signal in one embodiment. [Figure 5] Figure 5 shows graphs illustrating the waveforms of the PWM signal output from the first transistor and the waveforms of the second PWM signal in one embodiment. [Modes for carrying out the invention]

[0012] The blower 100 of this embodiment shown in Figure 1 is, for example, a blower mounted on a vehicle. The blower 100 is controlled by a vehicle control unit 50 mounted on the vehicle. As shown in Figure 2, the vehicle control unit 50 has a control circuit 50a that controls the blower 100. In this embodiment, the control circuit 50a is an open collector output circuit. The control circuit 50a has a transistor 51 and an output terminal section 52. The output terminal section 52 is connected to an input terminal section 40a of the blower 100, which will be described later.

[0013] In this embodiment, transistor 51 is a bipolar transistor. Transistor 51 is an NPN type transistor. Transistor 51 has an input terminal 51a, an output terminal 51b, and a ground terminal 51c. The input terminal 51a is the base, the output terminal 51b is the collector, and the ground terminal 51c is the emitter. An input signal IS is input to the input terminal 51a. The input signal IS is a command signal generated in the vehicle control unit 50 and is a signal for controlling the blower 100. An output terminal unit 52 is connected to the output terminal 51b. The ground terminal 51c is connected to ground GND and is grounded.

[0014] Transistor 51 operates based on the input signal IS. The input signal IS is a rectangular wave pulse signal whose signal level alternates between high and low at predetermined intervals. When the signal level of the input signal IS is high, current flows from the input terminal 51a to the ground terminal 51c, and current flows from the output terminal 51b to the ground terminal 51c. When the signal level of the input signal IS is low, no current flows between the input terminal 51a and the ground terminal 51c, and no current flows between the output terminal 51b and the ground terminal 51c.

[0015] Note that transistor 51 may be a transistor other than a bipolar transistor. Transistor 51 may be, for example, a field-effect transistor (FET). In this case, for example, the input terminal 51a is the gate, the output terminal 51b is the drain, and the ground terminal 51c is the source. Also in this case, the control circuit 50a is an open-drain circuit.

[0016] As shown in Figure 1, the blower 100 comprises a motor 10 and an impeller 20 rotated by the motor 10. The motor 10 comprises a motor body 10a and a motor control device 10b. The motor body 10a is controlled by the motor control device 10b. The motor body 10a rotates the impeller 20. The motor control device 10b comprises a motor driver circuit 30 and a signal processing circuit 40. The motor driver circuit 30 is connected to the motor body 10a. The motor driver circuit 30 supplies power to the motor body 10a based on signals input from the signal processing circuit 40. The signal processing circuit 40 is connected to a control circuit 50a. As shown in Figure 2, the signal processing circuit 40 comprises a first output circuit section 41, a second output circuit section 42, and a clamp circuit section 43.

[0017] The first output circuit section 41 includes an input terminal section 40a, a low-pass filter 44, and a first resistor section 61. The input terminal section 40a is connected to the output terminal section 52. As a result, the input terminal section 40a is connected to the output terminal 51b of the transistor 51. The input terminal section 40a is connected to the input-side terminal 44a of the low-pass filter 44.

[0018] The low-pass filter 44 includes a capacitor 44c and an inductor 44d. In this embodiment, the low-pass filter 44 is a Π-type low-pass filter having two capacitors 44c and one inductor 44d. Both ends of the inductor 44d are respectively connected to the input-side terminal 44a and the output-side terminal 44b of the low-pass filter 44. The two capacitors 44c are respectively connected to both ends of the inductor 44d. Each of one electrode of the two capacitors 44c is respectively connected to both ends of the inductor 44d. Each of the other electrode of the two capacitors 44c is connected to the ground GND and grounded.

[0019] One end of the first resistor section 61 is connected to the output-side terminal 44b of the low-pass filter 44. One end of the first resistor section 61 is connected to the input terminal section 40a via the low-pass filter 44. The other end of the first resistor section 61 is connected to the first power supply 71. The power supply voltage V1 of the first power supply 71 is, for example, 12V. The resistance value of the first resistor section 61 is larger than the resistance value of the low-pass filter 44 and the resistance value of the transistor 51. The resistance value of the transistor 51 is the resistance value between the output terminal 51b and the ground terminal 51c when a current flows between the output terminal 51b and the ground terminal 51c. The resistance value of the first resistor section 61 is, for example, 10 kΩ. In this embodiment, the voltage at a certain part means the magnitude of the potential of a certain part with respect to the potential of the ground GND.

[0020] When the signal level of the input signal IS is high, a current flows between the output terminal 51b and the ground terminal 51c of the transistor 51, so a current flows from the first power supply 71 to the ground GND to which the ground terminal 51c is connected. As a result, a voltage drop occurs in the first resistor portion 61, and the voltage V at the output-side terminal 44b of the low-pass filter 44 becomes lower than the power supply voltage V1 of the first power supply 71. Here, since the resistance value of the first resistor portion 61 is sufficiently larger than the resistance value of the low-pass filter 44 and the resistance value of the transistor 51, when the signal level of the input signal IS is high, the voltage V at the output-side terminal 44b of the low-pass filter 44 becomes sufficiently small, and the signal level of the signal output from the output-side terminal 44b of the low-pass filter 44 becomes low.

[0021] On the other hand, when the signal level of the input signal IS is low, no current flows between the output terminal 51b and the ground terminal 51c of the transistor 51, so no current flows between the first power supply 71 and the ground GND to which the ground terminal 51c is connected. As a result, no voltage drop occurs in the first resistor portion 61, and the voltage V at the output-side terminal 44b of the low-pass filter 44 becomes the power supply voltage V1 of the first power supply 71. Therefore, when the signal level of the input signal IS is low, the voltage V at the output-side terminal 44b of the low-pass filter 44 becomes sufficiently larger than when the signal level of the input signal IS is high, and the signal level of the signal output from the output-side terminal 44b of the low-pass filter 44 becomes high.

[0022] In this way, by alternately switching the signal level of the input signal IS between low and high, the signal output from the output-side terminal 44b of the low-pass filter 44 is alternately switched between high and low. As a result, the first PWM signal SA shown in FIG. 3 is output from the output-side terminal 44b of the low-pass filter 44. That is, the first output circuit section 41 outputs the first PWM signal SA based on the input signal IS. In the graph shown in FIG. 3, the horizontal axis represents time t, and the vertical axis represents voltage V.

[0023] As shown in Figure 3, the voltage V of the first PWM signal SA when it is high is the power supply voltage V1. The voltage V of the first PWM signal SA when it is low is the low voltage VL. The low voltage VL is sufficiently smaller than the power supply voltage V1. The low voltage VL is also smaller than the threshold voltage Vt1, which will be described later. The first PWM signal SA has a waveform that resembles a flattened rectangular pulse wave. The phase of the first PWM signal SA is inverted with respect to the phase of the input signal IS. That is, when the signal level of the input signal IS is high, the signal level of the first PWM signal SA is low. When the signal level of the input signal IS is low, the signal level of the first PWM signal SA is high.

[0024] In this embodiment, the rising edge E1 of the first PWM signal SA, where the signal level switches from low to high, changes in a curved manner. The rate of change at the starting point E1a of the rising edge E1 is greater than the rate of change at the ending point E1b of the rising edge E1. The starting point E1a is the point at which the voltage V of the first PWM signal SA begins to rise from the low voltage VL. The ending point E1b is the point at which the voltage V of the first PWM signal SA begins to fall from the power supply voltage V1. In this embodiment, the voltage V at the rising edge E1 of the first PWM signal SA continues to rise from the starting point E1a to the ending point E1b, reaching the power supply voltage V1 at the ending point E1b. The rate of change at the rising edge E1 is the rate of change of voltage V with respect to time t at the rising edge E1, and is the slope of the rising edge E1. The rate of change at the rising edge E1 gradually decreases as it moves from the starting point E1a to the ending point E1b. The rate of change at the starting point E1a is the value obtained by dividing the voltage V that increased per unit time from the starting point E1a by that unit time. The rate of change at the ending point E1b is the value obtained by dividing the voltage V that increased from the time before the ending point E1b to the ending point E1b by that unit time.

[0025] The falling edge E2 of the first PWM signal SA, where the signal level switches from high to low, changes linearly. In other words, the falling edge E2 in the first PWM signal SA is linear. As a result, the rate of change at the falling edge E2 is constant. The rate of change at the falling edge E2 is the rate of change of voltage V with respect to time t at the falling edge E2, and is the slope of the falling edge E2. At the falling edge E2, the voltage V of the first PWM signal SA changes instantaneously from the power supply voltage V1 to the low voltage VL. In other words, in the first PWM signal SA, the falling time t2 when the signal level switches from high to low is almost zero. As a result, in the first PWM signal SA of this embodiment, the falling time t2 when the signal level switches from high to low is shorter than the rising time t1 when the signal level switches from low to high. In other words, in the first PWM signal SA of this embodiment, the rise time t1 when the signal level switches from low to high is longer than the fall time t2 when the signal level switches from high to low.

[0026] Since the fall time t2 is almost zero, the rate of change at the falling edge E2 approaches infinity. As a result, the falling edge E2 is almost parallel to the vertical axis in the graph shown in Figure 3. The absolute value of the rate of change at the falling edge E2 is greater than the absolute value of the rate of change at the starting point E1a of the rising edge E1.

[0027] When the signal level of the first PWM signal SA switches from low to high, charge gradually accumulates in the capacitor 44c provided in the low-pass filter 44, causing the voltage V of the first PWM signal SA to gradually rise. Therefore, the rising edge E1 of the first PWM signal SA takes on the shape described above. On the other hand, when the signal level of the first PWM signal SA switches from high to low, current flows from the output terminal 51b of the transistor 51 to the ground terminal 51c. As a result, the charge accumulated in the capacitor 44c provided in the low-pass filter 44 instantly flows to the ground GND to which the ground terminal 51c is connected, and the voltage V of the first PWM signal SA instantly drops to the low voltage VL. Therefore, the falling edge E2 of the first PWM signal SA takes on the shape described above.

[0028] The clamp circuit section 43 is a circuit that clamps the first PWM signal SA at a predetermined voltage value. The clamp circuit section 43 is connected to the output terminal 44b of the low-pass filter 44. The clamp circuit section 43 has a first transistor 81. In other words, in this embodiment, the signal processing circuit 40 includes a first transistor 81 which constitutes at least a part of the clamp circuit section 43. The first transistor 81 is connected to the output terminal 44b of the low-pass filter 44 via a second resistor section 62, which will be described later.

[0029] In this embodiment, the first transistor 81 is a bipolar transistor. The first transistor 81 is an NPN type transistor. The first transistor 81 has an input terminal 81a, an output terminal 81b, and a ground terminal 81c. The input terminal 81a is the base, the output terminal 81b is the collector, and the ground terminal 81c is the emitter. The input terminal 81a is connected to one end of the first resistor 61 and to the output terminal 44b of the low-pass filter 44 via a second resistor 62, which will be described later. The ground terminal 81c is connected to ground GND and is grounded. In this embodiment, the predetermined voltage value for clamping the first PWM signal SA by the clamp circuit 43 is the threshold voltage Vt1 of the first transistor 81. The threshold voltage Vt1 is, for example, 0.7V.

[0030] When the voltage V at input terminal 81a is lower than the threshold voltage Vt1, no current flows between input terminal 81a and ground terminal 81c, and no current flows between output terminal 81b and ground terminal 81c. On the other hand, when the voltage V at input terminal 81a reaches the threshold voltage Vt1, current flows from input terminal 81a to ground terminal 81c, and current flows from output terminal 81b to ground terminal 81c.

[0031] When no current flows from input terminal 81a to ground terminal 81c, the voltage V at input terminal 81a is the same as the voltage V at output terminal 44b of the low-pass filter 44, i.e., the voltage V of the first PWM signal SA. Therefore, when the voltage of the first PWM signal SA becomes greater than or equal to the threshold voltage Vt1, the voltage V at input terminal 81a becomes the threshold voltage Vt1, and current begins to flow from input terminal 81a to ground terminal 81c. When the voltage V of the first PWM signal SA is greater than or equal to the threshold voltage Vt1, the voltage V at input terminal 81a is maintained at the threshold voltage Vt1. As a result, the waveform of the voltage V at input terminal 81a becomes a waveform in which the voltage V of the first PWM signal SA that is greater than the threshold voltage Vt1 is fixed at the threshold voltage Vt1. Specifically, the waveform of the voltage V at input terminal 81a becomes the waveform of the first PWM signal SB shown in Figure 4. The first PWM signal SB is the first PWM signal clamped by the clamp circuit 43. In this way, the clamp circuit 43 clamps the first PWM signal SA with a threshold voltage Vt1 to obtain the first PWM signal SB. In the graph shown in Figure 4, the horizontal axis represents time t, and the vertical axis represents voltage V.

[0032] Note that the first transistor 81 may be a transistor other than a bipolar transistor. For example, the first transistor 81 may be a field-effect transistor (FET). In this case, for example, the input terminal 81a is the gate, the output terminal 81b is the drain, and the ground terminal 81c is the source.

[0033] As shown in Figure 2, in this embodiment, a second resistor 62 is positioned between the output terminal 44b of the low-pass filter 44 and the input terminal 81a of the first transistor 81. In other words, the signal processing circuit 40 includes a second resistor 62. The second resistor 62 is positioned between one end of the first resistor 61 and the input terminal 81a of the first transistor 81. The second resistor 62 is connected in series with the first resistor 61. The resistance value of the second resistor 62 is, for example, the same as the resistance value of the first resistor 61. The resistance value of the second resistor 62 is, for example, 10kΩ. When current flows from the input terminal 81a of the first transistor 81 to the ground terminal 81c, the current flows from the first power supply 71 through the first resistor 61, the second resistor 62, and the first transistor 81 to the ground GND to which the ground terminal 81c is connected.

[0034] The provision of the second resistor 62 makes it easier to electrically isolate the input terminal 81a of the first transistor 81 from the output terminal 44b of the low-pass filter 44. Therefore, it is possible to suppress the application of an unintended voltage V to the input terminal 81a of the first transistor 81. This prevents the first transistor 81 from malfunctioning. As a result, the signal processing in the signal processing circuit 40 can be stabilized.

[0035] In this embodiment, a fourth resistor 64 is provided, connected to the input terminal 81a and the ground terminal 81c of the first transistor 81. That is, the signal processing circuit 40 includes a fourth resistor 64. One end of the fourth resistor 64 is connected to the input terminal 81a of the first transistor 81. The other end of the fourth resistor 64 is connected to the ground terminal 81c of the first transistor 81. The resistance value of the fourth resistor 64 is greater than the resistance value between the input terminal 81a and the ground terminal 81c of the first transistor 81 when current flows between them. The resistance value of the fourth resistor 64 is, for example, greater than the resistance value of the first resistor 61 and the resistance value of the second resistor 62. The resistance value of the fourth resistor 64 is, for example, 20 kΩ.

[0036] The fourth resistor 64 connects the input terminal 81a and the ground terminal 81c of the first transistor 81, so that when no current flows between the input terminal 81a and the ground terminal 81c, the potential of the input terminal 81a and the potential of the ground terminal 81c can be stably kept at the same potential. This allows, for example, if an unintended disturbance voltage occurs at the input terminal 81a, the energy of that disturbance voltage can be dissipated to the ground GND. Therefore, it is possible to suppress the voltage V at the input terminal 81a from unintentionally becoming the threshold voltage Vt1, and to further suppress malfunction of the first transistor 81. As a result, signal processing in the signal processing circuit 40 can be made more stable. In particular, when the input terminal 81a of the first transistor 81 is electrically separated from the output terminal 44b of the low-pass filter 44 by the second resistor 62, the voltage V at the input terminal 81a is prone to becoming unstable due to disturbance voltages. In contrast, by providing the fourth resistor 64, the voltage V at the input terminal 81a can be stabilized as described above, even when the second resistor 62 is provided. Furthermore, when current flows from the input terminal 81a to the ground terminal 81c, no current flows through the fourth resistor 64, so the fourth resistor 64 does not interfere with the operation of the first transistor 81.

[0037] The second output circuit section 42 is a circuit that outputs a second PWM signal SD based on the first PWM signal SB clamped by the clamp circuit section 43. The second output circuit section 42 includes the first transistor 81, the third resistor section 63, and the second transistor 82 as described above. In other words, the signal processing circuit 40 includes the first transistor 81, the third resistor section 63, and the second transistor 82, which each constitute a part of the second output circuit section 42. In this embodiment, the second output circuit section 42 is composed of the first transistor 81, the third resistor section 63, and the second transistor 82.

[0038] One end of the third resistor 63 is connected to the output terminal 81b of the first transistor 81. The other end of the third resistor 63 is connected to the second power supply 72. In this embodiment, the power supply voltage V2 of the second power supply 72 is the same as the power supply voltage V1 of the first power supply 71. The power supply voltage V2 of the second power supply 72 is, for example, 12V. The resistance value of the third resistor 63 is, for example, the same as the resistance value of the first resistor 61. The resistance value of the third resistor 63 is, for example, 10kΩ.

[0039] In this embodiment, the second transistor 82 is a bipolar transistor. The second transistor 82 is an NPN type transistor. The second transistor 82 has an input terminal 82a, an output terminal 82b, and a ground terminal 82c. The input terminal 82a is the base, the output terminal 82b is the collector, and the ground terminal 82c is the emitter. The input terminal 82a is connected to the output terminal 81b of the first transistor 81. The input terminal 82a is connected to one end of the third resistor 63 that is connected to the output terminal 81b. The output terminal 82b is connected to the motor driver circuit 30. The ground terminal 82c is connected to ground GND and is grounded. The threshold voltage Vt2 of the second transistor 82 is smaller than the power supply voltage V2 of the second power supply 72. The threshold voltage Vt2 of the second transistor 82 is, for example, the same as the threshold voltage Vt1 of the first transistor 81. The threshold voltage Vt2 of the second transistor 82 is, for example, 0.7V.

[0040] When the voltage V at input terminal 82a is less than the threshold voltage Vt2 of the second transistor 82, no current flows between input terminal 82a and ground terminal 82c, and between output terminal 82b and ground terminal 82c. On the other hand, when the voltage V at input terminal 82a becomes the threshold voltage Vt2 of the second transistor 82, current flows from input terminal 82a to ground terminal 82c, and current flows from output terminal 82b to ground terminal 82c. The voltage V at input terminal 82a of the second transistor 82 is the same as the voltage V at output terminal 81b of the first transistor 81.

[0041] When the voltage V at the input terminal 81a of the first transistor 81 becomes the threshold voltage Vt1 and current flows from the output terminal 81b of the first transistor 81 to the ground terminal 81c, current flows from the second power supply 72 through the third resistor 63 and the first transistor 81 to the ground GND to which the ground terminal 81c of the first transistor 81 is connected. As a result, a voltage drop occurs in the third resistor 63, and the voltage V at the output terminal 81b of the first transistor 81 and the voltage V at the input terminal 82a of the second transistor 82 become the power supply voltage V2 minus the voltage drop in the third resistor 63. In this embodiment, the resistance value of the third resistor 63 is sufficiently large compared to the resistance value of the first transistor 81, so the voltage drop that occurs in the third resistor 63 is sufficiently large and is approximately the same as the magnitude of the power supply voltage V2. As a result, when current flows from the second power supply 72 to the ground GND connected to the ground terminal 81c, the voltage V at the output terminal 81b of the first transistor 81 and the voltage V at the input terminal 82a of the second transistor 82 become approximately 0V. Note that the resistance value of the first transistor 81 is the resistance value between the output terminal 81b and the ground terminal 81c when current flows between the output terminal 81b and the ground terminal 81c.

[0042] On the other hand, when the voltage V at the input terminal 81a of the first transistor 81, i.e., the voltage V of the first PWM signal SB, is smaller than the threshold voltage Vt1, and no current flows from the output terminal 81b of the first transistor 81 to the ground terminal 81c, the voltage V at the input terminal 82a of the second transistor 82 becomes the threshold voltage Vt2, and current flows from the second power supply 72 through the third resistor 63 and the second transistor 82 to the ground GND to which the ground terminal 82c of the second transistor 82 is connected.

[0043] As described above, the waveform of the voltage V at input terminal 82a is the waveform of the PWM signal SC shown in Figure 5, in which the value of voltage V alternates between the threshold voltage Vt2 of the second power supply 72 and approximately 0V. The PWM signal SC is the signal output from the first transistor 81. The waveform of the PWM signal SC is rectangular. The phase of the PWM signal SC is inverted with respect to the phase of the first PWM signal SB. That is, when the signal level of the first PWM signal SB is high, the signal level of the PWM signal SC is low. When the signal level of the first PWM signal SB is low, the signal level of the PWM signal SC is high. In each graph shown in Figure 5, the horizontal axis represents time t, and the vertical axis represents voltage V.

[0044] When the signal level of the PWM signal SC is high, the voltage V at the input terminal 82a of the second transistor 82 becomes the threshold voltage Vt2, causing current to flow from the input terminal 82a to the ground terminal 82c, and also from the output terminal 82b to the ground terminal 82c. In this case, current flows from the third power supply 31 of the motor driver circuit 30 connected to the output terminal 82b, through the second transistor 82, to the ground GND to which the ground terminal 82c of the second transistor 82 is connected. This current causes a voltage drop across the resistors in the motor driver circuit 30, and the signal level of the second PWM signal SD output to the motor driver circuit 30 becomes low. Here, if the resistance value of the resistors in the motor driver circuit 30 is sufficiently larger than the resistance value of the second transistor 82, the voltage V of the second PWM signal SD when the signal level is low will be approximately 0V. The resistance value of the second transistor 82 is the resistance value between the output terminal 82b and the ground terminal 82c when current flows between the output terminal 82b and the ground terminal 82c.

[0045] On the other hand, when the signal level of the PWM signal SC is low, the voltage V at the input terminal 82a of the second transistor 82 is less than the threshold voltage Vt2, and no current flows between the input terminal 82a and the ground terminal 82c, and between the output terminal 82b and the ground terminal 82c. In this case, no voltage drop occurs in the resistors within the motor driver circuit 30, and the voltage V of the second PWM signal SD output to the motor driver circuit 30 becomes the power supply voltage V3 of the third power supply 31, and the signal level of the second PWM signal SD becomes high. As an example, the power supply voltage V3 is 3.3V.

[0046] As a result, the second output circuit 42 outputs a second PWM signal SD, as shown in Figure 5, in which the voltage V alternates between the power supply voltage V3 of the third power supply 31 and approximately 0V. As shown in Figure 5, the waveform of the second PWM signal SD is rectangular. The phase of the second PWM signal SD is inverted with respect to the phase of the PWM signal SC. That is, when the signal level of the PWM signal SC is high, the signal level of the second PWM signal SD is low. When the signal level of the PWM signal SC is low, the signal level of the second PWM signal SD is high. The phase of the second PWM signal SD is the same as the phase of the first PWM signal SB. That is, when the signal level of the first PWM signal SB is high, the signal level of the second PWM signal SD is high. When the signal level of the first PWM signal SB is low, the signal level of the second PWM signal SD is low.

[0047] As described above, the voltage V at the high position of the second PWM signal SD is the power supply voltage V3, which is greater than the voltage V at the high position of the first PWM signal SB, i.e., the threshold voltage Vt1. Thus, in this embodiment, the second output circuit 42 is an amplification circuit that amplifies the first PWM signal SB, which has been clamped by the clamp circuit 43, and outputs it as the second PWM signal SD. As shown in Figure 2, the second PWM signal SD output from the second output circuit 42 is input to the motor driver circuit 30.

[0048] Note that the second transistor 82 may be a transistor other than a bipolar transistor. The second transistor 82 may be, for example, a field-effect transistor (FET). In this case, for example, the input terminal 82a is the gate, the output terminal 82b is the drain, and the ground terminal 82c is the source.

[0049] In this embodiment, a fifth resistor 65 is provided, connected to the input terminal 82a and the ground terminal 82c of the second transistor 82. That is, the signal processing circuit 40 includes a fifth resistor 65. One end of the fifth resistor 65 is connected to the input terminal 82a of the second transistor 82. The other end of the fifth resistor 65 is connected to the ground terminal 82c of the second transistor 82. The resistance value of the fifth resistor 65 is greater than the resistance value between the input terminal 82a and the ground terminal 82c of the second transistor 82 when current flows between them. The resistance value of the fifth resistor 65 is greater than, for example, the resistance value of the first resistor 61, the resistance value of the second resistor 62, and the resistance value of the third resistor 63, and is the same as the resistance value of the fourth resistor 64. The resistance value of the fifth resistor 65 is, for example, 20kΩ.

[0050] The fifth resistor 65 connects the input terminal 82a and the ground terminal 82c of the second transistor 82, ensuring that the potential of the input terminal 82a and the ground terminal 82c are stably equal when no current flows between them. This allows the energy of an unintended disturbance voltage to be released to ground (GND) even if an unintended disturbance voltage occurs at the input terminal 82a. Consequently, the voltage V at the input terminal 82a is prevented from unintentionally reaching the threshold voltage Vt2, thus preventing the second transistor 82 from malfunctioning. This further stabilizes the signal processing in the signal processing circuit 40. When current flows from the input terminal 82a to the ground terminal 82c, no current flows through the fifth resistor 65, and therefore the fifth resistor 65 does not interfere with the operation of the second transistor 82.

[0051] According to this embodiment, the signal processing circuit 40 includes a first output circuit section 41 having a low-pass filter 44 and outputting a first PWM signal SA based on an input signal IS, a clamp circuit section 43 clamping the first PWM signal SA with a predetermined voltage value, and a second output circuit section 42 outputting a second PWM signal SD based on the first PWM signal SB clamped by the clamp circuit section 43. In the waveform of the first PWM signal SA, the rise time t1 when the signal level switches from low to high is longer than the fall time t2 when the signal level switches from high to low, the rate of change at the starting point E1a of the rising edge E1 when the signal level switches from low to high is greater than the rate of change at the ending point E1b of the rising edge E1, and the fall edge E2 when the signal level switches from high to low is linear. Therefore, in the vicinity of the starting point E1a, the rate of change at the rising edge E1 is relatively large, and the distortion of the first PWM signal SA is relatively small. Furthermore, at the falling edge E2, the first PWM signal SA is either unsaturated or its saturation is significantly smaller than that at the rising edge E1. By clamping the first PWM signal SA with a sufficiently small predetermined voltage value, the first PWM signal SA can be transformed into a waveform with corrected saturation, such as the first PWM signal SB shown in Figure 4. Therefore, by outputting the second PWM signal SD from the second output circuit 42 based on the high and low switching of the clamped first PWM signal SB, the signal output from the signal processing circuit 40 can be made noise-reduced by the low-pass filter 44 and have no saturation, or with suitably small saturation. As a result, it is possible to suppress problems such as the motor driver circuit 30 being unable to correctly detect the signal output from the signal processing circuit 40. Thus, according to this embodiment, it is possible to reduce noise in the PWM signal while suppressing malfunctions in the control of the motor 10 as the controlled object.

[0052] As described above, the waveform signal of the first PWM signal SA in this embodiment is realized by the first output circuit section 41 having an input terminal section 40a connected to the output terminal 51b of a transistor 51 that operates based on the input signal IS, and a first resistor section 61 with one end connected to the input terminal section 40a via a low-pass filter 44, with the other end of the first resistor section 61 connected to the first power supply 71. Conventionally, when a low-pass filter is simply applied to a PWM signal, the PWM signal becomes distorted at both the rising and falling edges, and a suitable PWM signal cannot be obtained by simply clamping the PWM signal with a predetermined voltage value. Specifically, because the falling edge becomes distorted, the endpoint of the falling edge is significantly delayed, resulting in problems such as a large difference in duty cycle compared to the PWM signal before the distortion.

[0053] In contrast, in this embodiment, by configuring the first output circuit section 41, which includes a low-pass filter 44, as described above, the smearing in the PWM signal by the low-pass filter 44 is intentionally controlled to create a waveform in which smearing occurs at the rising edge E1, such as the first PWM signal SA, but no smearing occurs at the falling edge E2, or almost no smearing occurs. As a result, by clamping the first PWM signal SA with a predetermined voltage value, the smearing is suitably corrected, and a first PWM signal SB is produced in which the duty cycle differs from that of the first PWM signal SA, thereby suppressing this difference.

[0054] Furthermore, since there is a slight delay near the starting point E1a of the rising edge E1 of the first PWM signal SA, the timing at which the signal level of the first PWM signal SA changes from low to high is slightly delayed compared to the timing at which the signal level of the input signal IS changes from high to low. Consequently, the timing at which the signal level of the clamped first PWM signal SB changes from low to high is also slightly delayed compared to the timing at which the signal level of the input signal IS changes from high to low. For this reason, the magnitude of this delay may be known in advance, and this delay may be compensated for in the motor driver circuit 30, etc. This allows for accurate control of the rotation speed of the motor 10 using the second PWM signal SD output based on the first PWM signal SA. For example, when relatively increasing or decreasing the current rotation speed of the motor 10, the duty cycle of the input signal IS can be changed relatively, so the slight delay in the first PWM signal SA mentioned above is not a problem. Therefore, when relatively increasing or decreasing the rotational speed of the current motor 10, the rotational speed of the motor 10 can be suitably controlled without compensating for the delay.

[0055] Furthermore, according to this embodiment, the signal processing circuit 40 includes a first transistor that constitutes at least a part of the clamp circuit section 43. The input terminal 81a of the first transistor 81 is connected to one end of the first resistor section 61 and the output terminal 44b of the low-pass filter 44. The predetermined voltage value for clamping the first PWM signal SA is the threshold voltage Vt1 of the first transistor 81. Therefore, as described above, the first PWM signal SA can be suitably clamped using the first transistor 81.

[0056] Furthermore, according to this embodiment, the second output circuit section 42 is an amplification circuit that amplifies the first PWM signal SB clamped by the clamp circuit section 43. At least a part of the second output circuit section 42 is composed of a first transistor 81 and a third resistor section 63. Therefore, when the threshold voltage Vt1 of the first transistor 81 is set as a predetermined voltage value for clamping the first PWM signal SA, even if the magnitude of the clamped first PWM signal SB becomes relatively small, the second output circuit section 42 can amplify the first PWM signal SB to output a second PWM signal SD of a suitable magnitude.

[0057] Furthermore, according to this embodiment, the signal processing circuit 40 includes a second transistor 82 that constitutes part of the second output circuit section 42. The output terminal 81b of the first transistor 81 is connected to the input terminal 82a of the second transistor 82. Here, as described above, when the first PWM signal SA is clamped using the first transistor 81, the phase of the PWM signal SC output from the output terminal 81b of the first transistor 81 is inverted with respect to the phase of the clamped first PWM signal SB. In contrast, by providing the second transistor 82 as in this embodiment, the phase of the PWM signal SC, which was inverted as described above, can be further inverted and output as a second PWM signal SD. As a result, a second PWM signal SD with the same phase as the first PWM signal SA can be output to the motor driver circuit 30. Note that if it is acceptable to output a PWM signal with a phase inverted with respect to the phase of the first PWM signal SA to the motor driver circuit 30, the output terminal 81b of the first transistor 81 may be connected to the motor driver circuit 30 without providing the second transistor 82.

[0058] The present invention is not limited to the embodiments described above, and other configurations and methods may be adopted within the scope of the technical idea of ​​the present invention. The low-pass filter of the first output circuit may be any type of low-pass filter. The clamp circuit may have any configuration as long as it can clamp the first PWM signal output from the first output circuit to a predetermined voltage value. The clamp circuit may not have a first transistor. The clamp circuit may be a circuit in which at least a part is composed of an operational amplifier, or a circuit in which at least a part is composed of a Zener diode. At least one of the second resistor, third resistor, fourth resistor, and fifth resistor may not be provided. The second output circuit may not be an amplification circuit. The second output circuit may be a circuit that outputs the first PWM signal clamped by the clamp circuit as a second PWM signal. The second output circuit may not have a second transistor.

[0059] The signal processing circuit to which the present invention is applied may be mounted in any device. The applications of the motor and blower to which the present invention is applied are not particularly limited. The motor and blower may be mounted in any device. The motor and blower do not have to be mounted in a vehicle. Furthermore, the configurations described herein can be combined as appropriate, within the limits of what is not mutually contradictory. [Explanation of symbols]

[0060] 10…Motor, 10a…Motor body, 10b…Motor control device, 20…Impeller, 30…Motor driver circuit, 40…Signal processing circuit, 40a…Input terminal section, 41…First output circuit section, 42…Second output circuit section (amplification circuit), 43…Clamp circuit section, 44…Low-pass filter, 44a,44b…Terminals, 51…Transistor, 51a,81a,82a…Input terminals, 51b,81b,82b…Output terminals, 51c,81c,82c ...Grounding terminal, 52...Output terminal section, 61...First resistor section, 62...Second resistor section, 63...Third resistor section, 64...Fourth resistor section, 65...Fifth resistor section, 71...First power supply, 72...Second power supply, 81...First transistor, 82...Second transistor, 100...Blower, E1...Rising edge, E2...Falling edge, E1a...Start point, E1b...End point, IS...Input signal, SA, SB...First PWM signal, SD...Second PWM signal, Vt1...Threshold voltage

Claims

1. A first output circuit section having a low-pass filter and outputting a first PWM signal based on the input signal, A clamping circuit unit that clamps the first PWM signal with a predetermined voltage value, A second output circuit unit outputs a second PWM signal based on the first PWM signal clamped by the clamp circuit unit, Equipped with, The first output circuit section is, An input terminal section connected to the output terminal of a transistor that operates based on the aforementioned input signal, A first resistor, one end of which is connected to the input terminal via the low-pass filter, It has, The other end of the first resistor is connected to the first power supply. In the waveform of the first PWM signal, The rise time for the signal level to switch from low to high is longer than the fall time for the signal level to switch from high to low. The rate of change at the beginning of the rising edge where the signal level switches from low to high is greater than the rate of change at the end of the rising edge. The falling edge where the signal level switches from high to low is linear. A signal processing circuit in which the absolute value of the rate of change at the falling edge is greater than the absolute value of the rate of change at the starting point of the rising edge.

2. The clamp circuit section comprises a first transistor which constitutes at least a part of the clamp circuit section, The input terminal of the first transistor is connected to one end of the first resistor and the output terminal of the low-pass filter. The signal processing circuit according to claim 1, wherein the predetermined voltage value is the threshold voltage of the first transistor.

3. The signal processing circuit according to claim 2, further comprising a second resistor positioned between the output terminal of the low-pass filter and the input terminal of the first transistor, and between one end of the first resistor and the input terminal of the first transistor.

4. It includes a third resistor, one end of which is connected to the output terminal of the first transistor, The other end of the third resistor is connected to the second power supply. The second output circuit is an amplification circuit that amplifies the first PWM signal clamped by the clamp circuit, The signal processing circuit according to claim 2 or 3, wherein at least a portion of the second output circuit section is composed of the first transistor and the third resistor section.

5. A first output circuit section having a low-pass filter and outputting a first PWM signal based on an input signal, A clamping circuit unit that clamps the first PWM signal with a predetermined voltage value, A second output circuit unit outputs a second PWM signal based on the first PWM signal clamped by the clamp circuit unit, A first transistor which constitutes at least a part of the clamp circuit section, Equipped with, The first output circuit section is, An input terminal section connected to the output terminal of a transistor that operates based on the aforementioned input signal, A first resistor, one end of which is connected to the input terminal via the low-pass filter, It has, The other end of the first resistor is connected to the first power supply. In the waveform of the first PWM signal, The rise time for the signal level to switch from low to high is longer than the fall time for the signal level to switch from high to low. The rate of change at the beginning of the rising edge where the signal level switches from low to high is greater than the rate of change at the end of the rising edge. The falling edge where the signal level switches from high to low is linear. The input terminal of the first transistor is connected to one end of the first resistor and the output terminal of the low-pass filter. The predetermined voltage value is the threshold voltage of the first transistor, The system further comprises a third resistor, one end of which is connected to the output terminal of the first transistor. The other end of the third resistor is connected to the second power supply. The second output circuit is an amplification circuit that amplifies the first PWM signal clamped by the clamp circuit, A signal processing circuit in which at least a portion of the second output circuit section is composed of the first transistor and the third resistor section.

6. The signal processing circuit according to any one of claims 2 to 5, comprising a fourth resistor whose one end is connected to the input terminal of the first transistor and whose other end is connected to the ground terminal of the first transistor.

7. A first output circuit section having a low-pass filter and outputting a first PWM signal based on an input signal, A clamping circuit unit that clamps the first PWM signal with a predetermined voltage value, A second output circuit unit outputs a second PWM signal based on the first PWM signal clamped by the clamp circuit unit, A first transistor which constitutes at least a part of the clamp circuit section, Equipped with, The first output circuit section is, An input terminal section connected to the output terminal of a transistor that operates based on the aforementioned input signal, A first resistor, one end of which is connected to the input terminal via the low-pass filter, It has, The other end of the first resistor is connected to the first power supply. In the waveform of the first PWM signal, The rise time for the signal level to switch from low to high is longer than the fall time for the signal level to switch from high to low. The rate of change at the beginning of the rising edge where the signal level switches from low to high is greater than the rate of change at the end of the rising edge. The falling edge where the signal level switches from high to low is linear. The input terminal of the first transistor is connected to one end of the first resistor and the output terminal of the low-pass filter. The predetermined voltage value is the threshold voltage of the first transistor, A signal processing circuit further comprising a fourth resistor, one end of which is connected to the input terminal of the first transistor and the other end of which is connected to the ground terminal of the first transistor.

8. The second output circuit section includes a second transistor, The signal processing circuit according to any one of claims 2 to 7, wherein the output terminal of the first transistor is connected to the input terminal of the second transistor.

9. A first output circuit section having a low-pass filter and outputting a first PWM signal based on an input signal, A clamping circuit unit that clamps the first PWM signal with a predetermined voltage value, A second output circuit unit outputs a second PWM signal based on the first PWM signal clamped by the clamp circuit unit, A first transistor which constitutes at least a part of the clamp circuit section, Equipped with, The first output circuit section is, An input terminal section connected to the output terminal of a transistor that operates based on the aforementioned input signal, A first resistor, one end of which is connected to the input terminal via the low-pass filter, It has, The other end of the first resistor is connected to the first power supply. In the waveform of the first PWM signal, The rise time for the signal level to switch from low to high is longer than the fall time for the signal level to switch from high to low. The rate of change at the beginning of the rising edge where the signal level switches from low to high is greater than the rate of change at the end of the rising edge. The falling edge where the signal level switches from high to low is linear. The input terminal of the first transistor is connected to one end of the first resistor and the output terminal of the low-pass filter. The predetermined voltage value is the threshold voltage of the first transistor, The circuit further comprises a second transistor which constitutes part of the second output circuit section, The output terminal of the first transistor is connected to the input terminal of the second transistor in a signal processing circuit.

10. The signal processing circuit according to claim 8 or 9, further comprising a fifth resistor whose one end is connected to the input terminal of the second transistor and whose other end is connected to the ground terminal of the second transistor.

11. A signal processing circuit according to any one of claims 1 to 10, A motor driver circuit to which the second PWM signal output from the signal processing circuit is input, A motor control device equipped with the following features.

12. A motor control device according to claim 11, The motor body is controlled by the motor control device, A motor equipped with a motor.

13. The motor according to claim 12, An impeller rotated by the aforementioned motor, A blower equipped with a ventilation device.

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