Semiconductor device and its manufacturing method
By concentrating p-type impurities through ion implantation and heat treatment in semiconductor devices, the method addresses lateral diffusion issues, achieving balanced impurity distribution and enhanced performance in semiconductor devices with repeating structures.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2022-12-27
- Publication Date
- 2026-06-22
AI Technical Summary
The lateral diffusion of p-type impurities in semiconductor devices with repeating structures leads to decreased concentration and formation of tapered regions, preventing the formation of desired p-type regions, which affects the device's performance.
A manufacturing method involving ion implantation with a mask and subsequent heat treatment to create a high defect density region, concentrating p-type impurities within the semiconductor layer, suppressing lateral diffusion and forming a desired shape for the p-type regions.
The method effectively suppresses tapering of p-type regions, enabling high concentration and balanced impurity distribution, resulting in improved charge balance and performance characteristics such as low on-resistance and high breakdown voltage.
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Abstract
Description
[Technical Field]
[0001] The technologies disclosed herein relate to semiconductor devices and methods for manufacturing the same. [Background technology]
[0002] Certain semiconductor devices include a semiconductor layer comprising a repeating structure in which p-type regions and n-type regions are alternately and repeatedly arranged along at least one direction. Patent Document 1 discloses an example of a semiconductor device having such a repeating structure. [Prior art documents] [Patent Documents]
[0003] [Patent Document 1] Japanese Patent Publication No. 2022-118464 [Overview of the project] [Problems that the invention aims to solve]
[0004] Such repeating structures are formed, for example, by ion implanting p-type impurities into a predetermined region of an n-type semiconductor layer. When p-type impurities are ion implanted, the p-type impurities implanted into the n-type semiconductor layer from the upper surface diffuse laterally due to scattering phenomena as the depth of the n-type semiconductor layer increases. When p-type impurities diffuse laterally, their concentration decreases. Therefore, in regions where p-type impurities have diffused laterally, the p-type impurities cancel each other out with the n-type impurities in the n-type semiconductor layer, and it is not possible to form a p-type region. As a result, tapered p-type regions are formed in predetermined regions within the n-type semiconductor layer. This specification provides a technique for forming repeating structures of a desired shape in semiconductor devices equipped with repeating structures. [Means for solving the problem]
[0005] This specification can disclose a method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) having a repeating structure in which a first conductivity type region (14a) and a second conductivity type region (14b) are alternately and repeatedly arranged along at least one direction. This manufacturing method may comprise: a film deposition step of forming a mask (42) on the upper surface of the semiconductor layer, wherein the semiconductor layer has a second conductivity type semiconductor layer containing a second conductivity type impurity located at a position exposed on the upper surface, and the mask has an opening corresponding to the formation range of the first conductivity type region; an ion implantation step of ion implanting a first conductivity type impurity into the second conductivity type semiconductor layer of the semiconductor layer through the opening in the mask, wherein the concentration of the implanted first conductivity type impurity increases toward the depth of the semiconductor layer along the depth direction of the semiconductor layer; and a heat treatment step of heat treating the semiconductor layer after the ion implantation step. In this manufacturing method, defects are formed in the region where the first conductivity type impurity is implanted due to implantation damage in the ion implantation step. The region where defects are formed is located within the aperture range of the mask when observed along the irradiation direction of the first conductivity type impurity. Furthermore, the density of the formed defects increases towards the depth of the semiconductor layer along the depth direction. When the heat treatment process is carried out, the formed defects can act to trap the first conductivity type impurity. As a result, the first conductivity type impurity that has diffused laterally due to scattering can be concentrated within the region where defects are formed. In particular, since the defect density is high in the deeper part of the semiconductor layer, the lateral diffusion of the first conductivity type impurity in the deeper part of the semiconductor layer is effectively suppressed. As a result, the region into which the first conductivity type impurity is injected is prevented from becoming tapered. According to the above manufacturing method, a semiconductor device having a repeating structure of a desired shape can be manufactured.
[0006] A semiconductor device (1) disclosed herein may include a semiconductor layer (10) having a repeating structure in which a first conductivity type region (14a) and a second conductivity type region (14b) are alternately and repeatedly arranged along at least one direction. The concentration of the first conductivity type impurity contained in the first conductivity type region may increase toward the depth of the semiconductor layer along the depth direction of the semiconductor layer. [Brief explanation of the drawing]
[0007] [Figure 1] A schematic cross-sectional view of the main parts of the semiconductor device of the embodiment disclosed herein is shown. [Figure 2] This shows the concentration distribution of p-type impurities in p-type columns in the depth direction of the semiconductor layer. [Figure 3] This shows the concentration distribution of n-type impurities in n-type columns in the depth direction of the semiconductor layer. [Figure 4] Figure 1 schematically shows a cross-sectional view of a key part during the manufacturing process of the semiconductor device shown. [Figure 5] Figure 1 schematically shows a cross-sectional view of a key part during the manufacturing process of the semiconductor device shown. [Figure 6] Figure 1 shows a cross-sectional view of a key part during the manufacturing process of a semiconductor device, schematically illustrating the range of injected p-type impurities and the range of high-concentration defects formed by injection damage. [Figure 7] Figure 1 shows a cross-sectional view of a key part during the manufacturing process for the semiconductor device shown, schematically illustrating the range of p-type impurities after the heat treatment process. [Modes for carrying out the invention]
[0008] The semiconductor devices disclosed herein will be described below with reference to the drawings. For the purpose of clarity in the illustrations, only one of the repeatedly arranged components will be given a reference numeral.
[0009] Fig. 1 schematically shows a cross-sectional view of the main part of the semiconductor device 1. The semiconductor device 1 is a type of power semiconductor device called a MOSFET, and includes a semiconductor layer 10, a drain electrode 22 covering the lower surface of the semiconductor layer 10, a source electrode 24 covering the upper surface of the semiconductor layer 10, and a plurality of trench gates 30 provided in the upper layer portion of the semiconductor layer 10.
[0010] The semiconductor layer 10 is not particularly limited, but may be, for example, a 4H silicon carbide layer. The upper crystal plane of the semiconductor layer 10 may be inclined by an off-angle with respect to the (0001) Si plane. The off-angle is not particularly limited, but may be, for example, 4°. Instead of the silicon carbide layer, the semiconductor layer 10 may be, for example, a silicon layer, a nitride semiconductor layer, or a gallium oxide layer. The semiconductor layer 10 is an n + -type drain region 12, a drift region 14, a p-type body region 16, and an n + -type source region 18, and a p + -type body contact region 19.
[0011] The drain region 12 is disposed in the lower layer portion of the semiconductor layer 10 and is provided at a position exposed on the lower surface of the semiconductor layer 10. The drain region 12 makes an ohmic contact with the drain electrode 22 covering the lower surface of the semiconductor layer 10.
[0012] The drift region 14 is provided between the drain region 12 and the body region 16 and has a plurality of p-type columns 14a and a plurality of n-type columns 14b. The p-type column 14a is an example of a first conductivity type region, and the n-type column 14b is an example of a second conductivity type region. The p-type column 14a and the n-type column 14b are arranged to alternately repeat along at least one direction in the cross-section of the semiconductor layer 10, constituting a superjunction structure. The plurality of p-type columns 14a and the plurality of n-type columns 14b are not particularly limited, but may be arranged, for example, in a stripe shape when viewed from a direction perpendicular to the upper surface of the semiconductor layer 10 (hereinafter referred to as "when viewed in plan view").
[0013] As shown in FIG. 2, the concentration of the p-type impurity in each of the plurality of p-type columns 14a increases monotonically from the portion contacting the body region 16 toward the deeper part of the semiconductor layer 10 along the depth direction of the semiconductor layer 10, that is, toward the portion contacting the drain region 12. Similarly, as shown in FIG. 3, the concentration of the n-type impurity in each of the plurality of n-type columns 14b also increases monotonically from the portion contacting the body region 16 toward the deeper part of the semiconductor layer 10 along the depth direction of the semiconductor layer 10, that is, toward the portion contacting the drain region 12.
[0014] When the drift region 14 is depleted, the p-type column 14a is negatively charged and the n-type column 14b is positively charged. When the charge amount of the negative charge of the p-type column 14a balances the charge amount of the positive charge of the n-type column 14b, the drift region 14 is well depleted and the breakdown voltage of the semiconductor device 1 is improved. As described above, the concentration distributions of the p-type impurity in the p-type column 14a and the n-type impurity in the n-type column 14b both increase monotonically from the portion contacting the body region 16 toward the deeper part of the semiconductor layer 10 along the depth direction of the semiconductor layer 10. Thereby, the charge amounts of the p-type column 14a and the n-type column 14b are adjusted to balance along the depth direction of the semiconductor layer 10. Further, when the charge amounts of the p-type column 14a and the n-type column 14b balance in a high-concentration state, the trade-off relationship between the on-resistance and the breakdown voltage is improved. Thus, in the semiconductor device 1, it is designed so that charge balance is achieved between the p-type column 14a and the n-type column 14b.
[0015] As shown in FIG. 1, the body region 16 is provided on the drift region 14 and is disposed in the upper part of the semiconductor layer 10. The body region 16 is provided between the n-type column 14b of the drift region 14 and the source region 18, contacts both the n-type column 14b and the source region 18, and separates the n-type column 14b and the source region 18. The concentration of the p-type impurity in the body region 16 is adjusted according to a desired gate threshold voltage.
[0016] The source region 18 is located on the body region 16, positioned in the upper part of the semiconductor layer 10, and exposed on the surface of the semiconductor layer 10. The source region 18 is in contact with the side surface of the trench gate 30. The source region 18 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor layer 10.
[0017] The body contact region 19 is provided on the body region 16, positioned in the upper part of the semiconductor layer 10, and is located in a position that is exposed on the surface of the semiconductor layer 10. The body contact region 19 is in ohmic contact with the source electrode 24 that coats the surface of the semiconductor layer 10.
[0018] The trench gate 30 is filled in a trench formed in the upper part of the semiconductor layer 10, and penetrates the source region 18 and the body region 16 to reach the n-type column 14b of the drift region 14. In this example, the trench gate 30 extends along the longitudinal direction of the p-type column 14a and the n-type column 14b when the semiconductor layer 10 is viewed from above. Alternatively, the trench gate 30 may extend along the repeating direction of the p-type column 14a and the n-type column 14b, i.e., in a direction perpendicular to the longitudinal direction of the p-type column 14a and the n-type column 14b, when the semiconductor layer 10 is viewed from above. The trench gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 is formed of polysilicon containing impurities and faces the semiconductor layer 10 via the gate insulating film 34. In particular, the gate electrode 32 faces the body region 16 of the drift region 14, which separates the n-type column 14b and the source region 18, via the gate insulating film 34. The gate insulating film 34 is made of silicon oxide and covers the inner wall of the trench.
[0019] Next, the operation of the semiconductor device 1 will be explained with reference to Figure 1. When the potential of the drain electrode 22 is positive compared to the potential of the source electrode 24, and the potential of the gate electrode 32 of the trench gate 30 is positive compared to the source electrode 24 and controlled to be higher than a threshold, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 16 that separates the source region 18 and the n-type column 14b of the drift region 14. Electrons supplied from the source region 18 reach the n-type column 14b of the drift region 14 via the channel of the inversion layer. Electrons that reach the n-type column 14b flow through the n-type column 14b to the drain region 12. Since the n-type column 14b has a high concentration of n-type impurities, the semiconductor device 1 can have the characteristic of low on-resistance.
[0020] When the potential of the gate electrode 32 of the trench gate 30 is controlled to be the same as the potential of the source electrode 24, the channel in the inversion layer disappears, and the semiconductor device 1 turns off. The multiple p-type columns 14a and multiple n-type columns 14b constituting the superjunction structure are substantially completely depleted, and a wide area of the drift region 14 is depleted. Furthermore, because the drift region 14 has a superjunction structure, the electric field distribution of the drift region 14 is leveled in the depth direction. As a result, the drift region 14 can bear a large potential difference, and the semiconductor device 1 can have the characteristic of high breakdown voltage.
[0021] (First method for manufacturing a semiconductor device) Next, with reference to Figures 4 to 7, the step of forming the superjunction structure, which is part of the first manufacturing method of the semiconductor device 1, will be described. For the other steps for manufacturing the semiconductor device 1, known manufacturing techniques can be used.
[0022] First, as shown in Figure 4, n +A drain region 12, which is a silicon carbide substrate of type n, is prepared. Next, an n-type epitaxial layer 140 of silicon carbide is grown from the surface of the drain region 12 using epitaxial growth technology, although this is not particularly limited. The epitaxial layer 140 constitutes at least a part of the semiconductor layer 10 and may also be referred to as the semiconductor layer or n-type semiconductor layer.
[0023] The concentration of n-type impurities in the epitaxial layer 140 increases monotonically from the top to the bottom of the epitaxial layer 140 (see Figure 3). Alternatively, the concentration of n-type impurities in the epitaxial layer 140 may increase in multiple stages from the top to the bottom of the epitaxial layer 140. Such a distribution of n-type impurity concentrations may be adjusted during the epitaxial growth of the epitaxial layer 140, adjusted after epitaxial growth using ion implantation techniques, or adjusted by a combination of these methods.
[0024] Next, as shown in Figure 5, a mask 42 is deposited on the epitaxial layer 140 using photolithography. The mask 42 is patterned to have openings corresponding to the formation area of the p-type column 14a.
[0025] Next, as shown in Figure 6, p-type impurities are ion-implanted into the epitaxial layer 140 through the opening of the mask 42 using ion implantation technology. The area enclosed by the dashed line labeled 44 indicates the range where the implanted p-type impurities are present. The p-type impurities implanted into the epitaxial layer 140 diffuse laterally as the depth of the epitaxial layer 140 increases due to the scattering phenomenon that occurs when the p-type impurities are ion-implanted.
[0026] Reference numeral 46 denotes a defect formed by injection damage, with a defect density of 5 [defects / 0.01 μm]. 2It shows the range where the above defects are formed at high density. In this ion implantation process, the irradiation conditions are adjusted so that the concentration of the implanted p-type impurities increases monotonically toward the deep part of the epitaxial layer 140 along the depth direction of the epitaxial layer 140 (see Fig. 2). Instead of this example, the concentration of the p-type impurities implanted into the epitaxial layer 140 may increase in multiple steps toward the deep part of the epitaxial layer 140 along the depth direction of the epitaxial layer 140. Here, when the concentration of the implanted p-type impurities exceeds a predetermined concentration, the formed defect density becomes 5 [pieces / 0.01μm 2 or more. In Fig. 2, the predetermined concentration is indicated as "14N". The high-density range where the defect density becomes 5 [pieces / 0.01μm 2 or more is indicated as "14D". The predetermined concentration varies depending on the ion species. For example, when aluminum (Al) is used as the p-type impurity, the defect density becomes 5 [pieces / 0.01μm 17 cm -3 or more in the depth range of 2×10 2 or more, and when boron (B) is used as the p-type impurity, the defect density becomes 5 [pieces / 0.01μm 17 cm -3 or more in the depth range of 8×10 2 or more. The region where the defects are formed is within the range of the opening of the mask 42 when observed along the irradiation direction of the p-type impurities. In this example, since the p-type impurities are irradiated from the direction perpendicular to the upper surface of the epitaxial layer 140, the region where the defects are formed is within the range directly below the opening of the mask 42.
[0027] Next, as shown in Figure 7, the semiconductor layer 10 is heat-treated to activate the implanted p-type impurities. Here, the defects formed within the epitaxial layer 140 can act to trap the p-type impurities once the heat treatment process is carried out. As a result, when the heat treatment process is carried out, the p-type impurities that have diffused laterally due to scattering phenomena can be concentrated within the region where the defects were formed. In particular, since a high-density defect region is formed in the deeper part of the epitaxial layer 140, the lateral diffusion of p-type impurities in the deeper part of the epitaxial layer 140 is effectively suppressed. As a result of this heat treatment process, the region of the epitaxial layer 140 enclosed by the dashed line 44 becomes a p-type column 14a, and the remaining part of the epitaxial layer 140 becomes an n-type column 14b.
[0028] For example, if there are no high-density defect regions, in regions where p-type impurities diffuse laterally, the p-type impurities cancel out with the n-type impurities in the epitaxial layer 140, preventing the formation of p-type regions. As a result, the regions of activated p-type impurities tend to have a tapered shape. In particular, when forming a superjunction structure, the thickness of the mask 42 is often large, and its aperture width is narrow (for example, the thickness is about 5 μm and the aperture width is about 1 μm). Furthermore, p-type impurities are irradiated with high energy of several MeV. In such cases, the p-type impurities are ion-implanted while being collected by reflection at the side walls that define the aperture of the mask 42. As a result, the p-type regions formed within the epitaxial layer 140 tend to have a tapered shape.
[0029] In the above manufacturing method, by causing the laterally diffused p-type impurities to be unevenly distributed within the high-density defect region, the tapering shape of the p-type region is suppressed, and a p-type column 14a of the desired width can be formed. Furthermore, since the cancellation of p-type and n-type impurities due to the diffusion of p-type impurities can be suppressed, the impurities in the p-type column 14a and n-type column 14b can be activated to a high concentration. For this reason, the superjunction structure formed by the above manufacturing method can achieve both low on-resistance and high breakdown voltage.
[0030] In the above, a superjunction structure was given as an example of a repeating structure. The technology disclosed herein can also be applied to other repeating structures. For example, a p-type region provided to protrude from the bottom surface of the body region 16 into the drift region 14 in order to mitigate the electric field at the bottom surface of the trench gate 30 constitutes a repeating structure with respect to the drift region. For example, a pressure-resistant structure called an FLR also constitutes a repeating structure with respect to the drift region. The technology disclosed herein may be applied to these repeating structures.
[0031] The above example illustrates a manufacturing method in which p-type impurities are ion-implanted into an n-type semiconductor layer to form a repeating structure in which p-type and n-type regions alternate. Alternatively, a repeating structure in which p-type and n-type regions alternate may be formed by ion-implanting n-type impurities into a p-type semiconductor layer. In this case as well, by ion-implanting the n-type impurities so that they increase toward the depth of the semiconductor layer along the depth direction, it is possible to suppress the tapering shape of the activated n-type regions. In this case as well, in order to concentrate the n-type impurities in the defect regions, the defect density should be 5 [impurities / 0.01 μm]. 2 It is desirable to form a high-density range of 2 × 10⁻¹⁰ or higher. For example, when phosphorus (P) is used as the n-type impurity, the impurity concentration should be 2 × 10⁻¹⁰. 17 cm -3 In the depth range above, the defect density is 5 [defects / 0.01 μm] 2 ] Therefore, when nitrogen (N) is used as the n-type impurity, the impurity concentration is 1 × 10 19 cm -3 In the depth range above, the defect density is 5 [defects / 0.01 μm] 2 This concludes the explanation.
[0032] The features of the technology disclosed herein are summarized below. Note that the technical elements described below are independent elements that exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing.
[0033] (Feature 1) A method for manufacturing a semiconductor device (1) comprising a semiconductor layer (10) including a repeating structure in which a first conductivity type region (14a) and a second conductivity type region (14b) are alternately and repeatedly arranged along at least one direction, A film deposition step comprising forming a mask (42) on the upper surface of the semiconductor layer, wherein the semiconductor layer has a second conductivity type semiconductor layer (140) containing a second conductivity type impurity located at a position exposed on the upper surface, and the mask has an opening corresponding to the formation range of the first conductivity type region, An ion implantation step of implanting a first conductivity type impurity into the second conductivity type semiconductor layer of the semiconductor layer through an opening in the mask, wherein the concentration of the implanted first conductivity type impurity increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer; A method for manufacturing a semiconductor device, comprising a heat treatment step of heat-treating the semiconductor layer after the ion implantation step.
[0034] (Feature 2) In the ion implantation step, the defect density is 5 [defects / 0.01 μm] in at least a portion of the depth range of the region where the first conductive impurity is implanted. 2 The method for manufacturing a semiconductor device according to Feature 1, wherein the first conductive impurity is ion-implanted in such a manner as described above.
[0035] (Feature 3) The concentration of the second conductivity type impurity contained in the second conductivity type semiconductor layer increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer. A method for manufacturing a semiconductor device according to feature 1 or 2, wherein the repeating structure is a superjunction structure.
[0036] (Feature 4) Semiconductor device (1) The semiconductor layer (10) includes a repeating structure in which a first conductivity type region (14a) and a second conductivity type region (14b) are alternately and repeatedly arranged along at least one direction. A semiconductor device wherein the concentration of the first conductivity type impurity contained in the first conductivity type region increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer.
[0037] (Feature 5) The first conductive type region has a defect density of 5 [defects / 0.01 μm] in at least a portion of its depth range. 2 The semiconductor device described in Feature 4 is as described above.
[0038] (Feature 6) The concentration of the second conductivity type impurity contained in the second conductivity type region increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer. The semiconductor device according to feature 4 or 5, wherein the repeating structure is a superjunction structure.
[0039] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. Furthermore, the technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technologies illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving even one of these objectives itself constitutes technical usefulness. [Explanation of symbols]
[0040] 1: Semiconductor device, 10: Semiconductor layer, 12: Drain region, 14: Drift region, 14a: p-type column, 14b: n-type column, 16: Body region, 18: Source region, 19: Body contact region, 22: Drain electrode, 24: Source electrode, 30: Trench gate, 32: Gate electrode, 34: Gate insulating film, 140: Epitaxial layer
Claims
1. A method for manufacturing a semiconductor device (1), comprising a semiconductor layer (10) having a repeating structure in which a first conductivity type region (14a) and a second conductivity type region (14b) are alternately and repeatedly arranged along at least one direction, A film deposition step comprising forming a mask (42) on the upper surface of the semiconductor layer, wherein the semiconductor layer has a second conductivity type semiconductor layer (140) containing a second conductivity type impurity located at a position exposed on the upper surface, and the mask has an opening corresponding to the formation range of the first conductivity type region, An ion implantation step of implanting a first conductivity type impurity into the second conductivity type semiconductor layer of the semiconductor layer through an opening in the mask, wherein the concentration of the implanted first conductivity type impurity increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer; The process includes a heat treatment step for heat-treating the semiconductor layer after the ion implantation step, A method for manufacturing a semiconductor device, wherein in the ion implantation step, the first conductivity type impurity is ion-implanted such that the defect density is 5 [defects / 0.01 μm²] or more in at least a portion of the depth range of the region in which the first conductivity type impurity is implanted.
2. The concentration of the second conductivity type impurity contained in the second conductivity type semiconductor layer increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer. The method for manufacturing a semiconductor device according to claim 1, wherein the repeating structure is a superjunction structure.
3. Semiconductor device (1) The semiconductor layer (10) includes a repeating structure in which a first conductivity type region (14a) and a second conductivity type region (14b) are alternately and repeatedly arranged along at least one direction. The concentration of the first conductivity type impurity contained in the first conductivity type region increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer. The first conductivity type region is a semiconductor device in which the defect density is 5 [defects / 0.01 μm²] or more in at least a portion of the depth range.
4. The concentration of the second conductivity type impurity contained in the second conductivity type region increases towards the depth of the semiconductor layer along the depth direction of the semiconductor layer. The semiconductor device according to claim 3, wherein the repeating structure is a superjunction structure.