Method for manufacturing a semiconductor device and semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device, in which method a deep p-type region can be easily formed.SOLUTION: A manufacturing method of a semiconductor device comprises: forming a mask material that has an opening on a surface of a silicon carbide layer; performing first processing to implant at least one material selected from a group composed of hydrogen (H), helium (He) and an electron into a first region of the silicon carbide layer using the mask material as a mask; performing first ion implantation to implant a p-type impurity into a second region being shallower than the first region using the mask material as a mask before the first processing or after the first processing; peeling the mask material after the first processing and the first ion implantation; and performing first heat treatment at 1600°C or higher after peeling the mask material.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is one of the materials for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has superior properties, including a band gap approximately three times larger, a breakdown field strength approximately ten times greater, and a thermal conductivity approximately three times greater. By utilizing these properties, it is possible to realize semiconductor devices that are low-loss and capable of high-temperature operation.

[0003] In vertical metal oxide semiconductor field effect transistors (MOSFETs), the superjunction structure (hereinafter also referred to as "SJ structure") is a structure that achieves both high breakdown voltage and low on-resistance. The SJ structure arranges p-type and n-type regions alternately in the lateral direction. The depletion layer extending laterally within the p-type and n-type regions relaxes the electric field strength in the semiconductor, enabling the high breakdown voltage of the MOSFET. At the same time, by increasing the concentration of impurities in the region, the on-resistance of the MOSFET can be achieved.

[0004] In SJ-structured MOSFETs, it is required to form a deep p-type region within the silicon carbide layer. Therefore, a method is needed that can easily form a deep p-type region. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2015-216182 [Overview of the project] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a method for manufacturing a semiconductor device that can easily form a deep p-type region. [Means for solving the problem]

[0007] The method for manufacturing a semiconductor device according to the embodiment involves forming a mask material having an opening on the surface of a silicon carbide layer, performing a first treatment on the mask material by implanting at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons into a first region of the silicon carbide layer, performing a first ion implantation on the mask material by implanting p-type impurities into a second region shallower than the first region, either before or after the first treatment, peeling off the mask material after the first treatment and the first ion implantation, and performing a first heat treatment at 1600°C or higher after peeling off the mask material. The first ion implantation is performed after the first treatment, and the first ion implantation is performed at a temperature of 300°C or higher. . [Brief explanation of the drawing]

[0008] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic plan view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10]A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 13] A schematic plan view of the semiconductor device according to the second embodiment. [Figure 14] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 15] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 16] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 17] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 18] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 19] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 20] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 21] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 22] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 23] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 24] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 25] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 26] A schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of the third embodiment. [Figure 27] A schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 28]Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 29] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 30] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 31] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 32] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 33] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 34] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment. [Figure 35] Schematic cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the third embodiment.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] Also, in the following description, n - , - , + , n, n - and, p + , p, p - When there is such notation, it represents the relative level of the impurity concentration in each conductivity type. That is, n + has a relatively higher n-type impurity concentration than n, and n - has a relatively lower n-type impurity concentration than n. Also, p + has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that the n + type, n - type are simply referred to as the n-type, p + type, p -The type is sometimes simply referred to as p-type. Unless otherwise specified, the impurity concentration in each region is represented by, for example, the value of the impurity concentration in the central part of each region.

[0011] Impurity concentrations can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Furthermore, the relative levels of impurity concentrations can be determined, for example, from the carrier concentrations obtained by Scanning Capacitance Microscopy (SCM). Additionally, the width and depth of impurity regions can be determined, for example, by SIMS. Furthermore, the width and depth of impurity regions can be determined, for example, from SCM images.

[0012] (First Embodiment) The semiconductor device of the first embodiment comprises a silicon carbide layer having a first electrode, a second electrode, a first surface located between the first electrode and the second electrode and parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first direction and facing the first surface, the silicon carbide layer including a first p-type silicon carbide region and a second n-type silicon carbide region alternately arranged in a first direction, a third p-type silicon carbide region located between the second silicon carbide region and the first surface, and a fourth n-type silicon carbide region located between the third silicon carbide region and the first surface, a gate electrode provided on the side of the first surface of the silicon carbide layer, facing the third silicon carbide region and extending in a second direction, and a gate insulating layer located between the gate electrode and the silicon carbide layer, wherein the first silicon carbide region has a Deep Level Transient Z measured by Spectroscopy (DLTS) 1 / 2 The level density is measured by DLTS in the second silicon carbide region. 1 / 2 It is smaller than the level density.

[0013] The first embodiment of the semiconductor device manufacturing method involves forming a mask material having an opening on the surface of a silicon carbide layer, performing a first treatment on the mask material by implanting at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons into a first region of the silicon carbide layer, performing a first ion implantation on the mask material by implanting p-type impurities into a second region shallower than the first region, either before or after the first treatment, peeling off the mask material after the first treatment and the first ion implantation, and performing a first heat treatment at 1600°C or higher after peeling off the mask material.

[0014] Figure 1 is a schematic cross-sectional view of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 is an n-channel type MOSFET that uses electrons as carriers. The MOSFET 100 has a superjunction structure (SJ structure).

[0015] Figure 2 is a schematic plan view of the semiconductor device according to the first embodiment. Figure 2 is a plan view of the first plane (P1 in Figure 1) of Figure 1. Figure 1 is a cross-sectional view AA' of Figure 2.

[0016] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0017] The silicon carbide layer 10 is n + Drain region 24 of type n - Type A drift region 26, p-type p-pillar region 28 (first silicon carbide region), n-type n-pillar region 30 (second silicon carbide region), p-type body region 32 (third silicon carbide region), n + Source region 34 of type (fourth silicon carbide region), p + It has a type contact area 38.

[0018] The silicon carbide layer 10 is located between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 has a first surface ("P1" in Figure 1) and a second surface ("P2" in Figure 1). Hereinafter, the first surface P1 will also be referred to as the front surface, and the second surface P2 as the back surface. The second surface P2 faces the first surface P1.

[0019] The first and second directions are parallel to the first plane P1. The second direction intersects the first direction. The second direction is, for example, perpendicular to the first direction. The third direction is perpendicular to the first plane. The third direction is perpendicular to both the first and second directions.

[0020] Hereafter, "depth" refers to the depth relative to the first surface P1. "Thickness" refers to the length in the third direction.

[0021] The silicon carbide layer 10 is single-crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC. The thickness of the silicon carbide layer 10 is, for example, 5 μm or more and 500 μm or less.

[0022] The first surface P1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. That is, it is a surface whose normal is inclined at an angle of 0 to 8 degrees relative to the c-axis in the

[0001] direction. In other words, its off-angle with respect to the (0001) surface is 0 to 8 degrees. The second surface P2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface.

[0023] The (0001) plane is referred to as the silicon plane. The (000-1) plane is referred to as the carbon plane. The inclination direction of the first plane P1 and the second plane P2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In Figure 1, for example, the first direction shown in the figure is the a-axis direction.

[0024] The gate electrode 16 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14. The gate electrode 16 extends in a second direction.

[0025] The gate electrode 16 is a conductive layer. The gate electrode 16 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0026] The gate insulating layer 18 is located between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is provided between the source region 34, the body region 32, and the n-pillar region 30 and the gate electrode 16.

[0027] The gate insulating layer 18 is, for example, a silicon oxide film. For the gate insulating layer 18, a high dielectric constant insulating film with a higher dielectric constant than a silicon oxide film can be applied, for example. Furthermore, a laminated film of a silicon oxide film and a high dielectric constant insulating film can also be applied to the gate insulating layer 18.

[0028] The interlayer insulating layer 20 is provided on the gate electrode 16. The interlayer insulating layer 20 is, for example, a silicon oxide film. The interlayer insulating layer 20 electrically isolates the gate electrode 16 and the source electrode 12.

[0029] The source electrode 12 is provided on the first surface P1 side of the silicon carbide layer 10. The source electrode 12 is provided on the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the source region 34 and the contact region 38.

[0030] The source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a layered structure of titanium (Ti) and aluminum (Al). The source electrode 12 may also contain metal silicide or metal carbide in contact with the silicon carbide layer 10.

[0031] The drain electrode 14 is provided on the second surface P2 side of the silicon carbide layer 10. The drain electrode 14 is provided on the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the drain region 24.

[0032] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0033] n + The drain region 24 is provided on the second surface P2 side of the silicon carbide layer 10. The drain region 24 is located between the second surface P2 and the p-pillar region 28 and the n-pillar region 30.

[0034] The drain region 24 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 24 is higher than the concentration of n-type impurities in the n-pillar region 30. The concentration of n-type impurities in the drain region 24 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0035] n - The drift region 26 is provided on the drain region 24. The drift region 26 is located between the second surface P2 and the p-pillar region 28 and the n-pillar region 30. The n-type impurity concentration in the drift region 26 is, for example, less than or equal to the n-type impurity concentration in the n-pillar region 30. For example, the n-type impurity concentration in the drift region 26 is lower than the n-type impurity concentration in the n-pillar region 30.

[0036] The drift region 26 contains, for example, nitrogen (N) as an n-type impurity. The impurity concentration of the n-type impurity in the drift region 26 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 18 cm -3 The following applies:

[0037] The p-type p-pillar region 28 and the n-type n-pillar region 30 are provided between the drain region 24 and the first surface P1. The p-pillar region 28 and the n-pillar region 30 are provided between the drift region 26 and the first surface P1.

[0038] The p-pillar regions 28 and n-pillar regions 30 are arranged alternately in the first direction. The p-pillar regions 28 and n-pillar regions 30 form a so-called superjunction structure (SJ structure).

[0039] In the MOSFET 100 having an SJ structure, the depletion layer extends laterally (in the first direction) within the p-pillar region 28 and the n-pillar region 30 during off-operation. This lateral extension of the depletion layer reduces the electric field strength in the silicon carbide layer 10, enabling high breakdown voltage.

[0040] The p-pillar region 28 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the p-pillar region 28 is, for example, 5 × 10⁻⁶. 15 cm -3 The above 5 x 10 17 cm -3 The following applies:

[0041] The n-pillar region 30 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the n-pillar region 30 is, for example, 5 × 10⁻⁶. 15 cm -3 The above 5 x 10 17 cm -3 The following applies:

[0042] For example, if the width of the p-pillar region 28 in the second direction is W1, the p-type impurity concentration of the p-pillar region 28 is N1, the width of the n-pillar region 30 in the second direction is W2, and the n-type impurity concentration of the n-pillar region 30 is N2, then the following relationship is satisfied. 0.8 ≤ (W1 × N1) / (W2 × N2) ≤ 1.2

[0043] The aspect ratio (d1 / W1) between the depth d1 of the p-pillar region 28 in the third direction and the width of the p-pillar region 28 in the second direction (W1 in Figure 1) is, for example, 3 or more. The depth d1 of the p-pillar region 28 in the third direction perpendicular to the first surface is, for example, 5 μm or more and 10 μm or less.

[0044] Z measured by Deep Level Transient Spectroscopy (DLTS) in the p-pillar region 281 / 2 The energy level density is measured by DLTS in the n-pillar region 30. 1 / 2 Smaller than the energy level density. Z in p-pillar region 28 1 / 2 The level density is, for example, Z in the n-pillar region 30. 1 / 2 It is less than 50% of the energy level density.

[0045] Z measured by DLTS 1 / 2 The level density corresponds to the density of carbon vacancies. Therefore, the density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30.

[0046] The p-shaped body region 32 is located between the n-pillar region 30 and the first surface P1. The p-shaped body region 32 is located between the p-pillar region 28 and the first surface P1.

[0047] The body region 32 functions as the channel region of the MOSFET 100. For example, when the MOSFET 100 is turned on, a channel is formed in the region of the body region 32 that is in contact with the gate insulating layer 18, allowing electrons to flow. The region of the body region 32 that is in contact with the gate insulating layer 18 becomes the channel formation region.

[0048] Body region 32 contains, for example, aluminum (Al) as a p-type impurity. The impurity concentration of the p-type impurity in body region 32 is, for example, 5 × 10⁻⁶ 16 cm -3 The above 5 x 10 17 cm -3 The following applies:

[0049] The depth of the body region 32 is, for example, between 0.2 μm and 1.0 μm.

[0050] n + The source region 34 of the mold is located between the body region 32 and the first surface P1. The source region 34 is in contact with the source electrode 12. The source region 34 is in contact with the gate insulating layer 18.

[0051] Source region 34 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration in source region 34 is higher than the n-type impurity concentrations in drift region 26 and n-pillar region 30. The n-type impurity concentration in source region 34 is, for example, 1 × 10⁻⁶ 19 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0052] The depth of the source region 34 is shallower than the depth of the body region 32. For example, the depth of the source region 34 is between 0.1 μm and 0.3 μm.

[0053] p + The contact region 38 of the type is located between the body region 32 and the first surface P1. The contact region 38 is in contact with the source electrode 12.

[0054] As shown in Figure 2, the contact region 38 is, for example, a stripe extending in a second direction.

[0055] The contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the contact region 38 is, for example, higher than the concentration of p-type impurities in the body region 32. The concentration of p-type impurities in the contact region 38 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0056] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0057] Figures 3, 4, 5, 6, 7, 8, 9, 10, and 11 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 3 to 11 show the cross-section corresponding to Figure 1. The following explanation will use the case where the p-type impurity is aluminum (Al) as an example.

[0058] First, n + A drain region 24 of type n -A silicon carbide layer 10 having type and n-type epitaxial layers 11 is prepared (Figure 3). The epitaxial layer 11 is a layer formed by epitaxial growth on the drain region 24. Parts of the epitaxial layer 11 eventually become the drift region 26 and the n-pillar region 30.

[0059] Next, a mask material 50 having openings is formed on the silicon carbide layer 10 (Figure 4). The mask material 50 is, for example, a laminated film of a silicon oxide film 50a and a metal film 50b. The metal film 50b is, for example, tungsten.

[0060] Next, hydrogen (H) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (Figure 5). Hydrogen (H) is an example of a substance. Ion implantation of hydrogen (H) is an example of the first treatment.

[0061] Hydrogen (H) is implanted into a first region 51 of the silicon carbide layer 10 by ion implantation. The ion implantation of hydrogen (H) involves multiple ion implantations. For example, the ion implantation of hydrogen (H) involves five ion implantations.

[0062] The five ion implantations are performed with different acceleration energies. Each of the five ion implantations implants hydrogen (H) into the first section 51a, second section 51b, third section 51c, fourth section 51d, and fifth section 51e at different depths. For example, the five ion implantations are performed so that the distribution of hydrogen (H) is continuous between the first section 51a, second section 51b, third section 51c, fourth section 51d, and fifth section 51e.

[0063] The concentration of hydrogen (H) in the first region 51 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 21 cm -3 Hydrogen (H) ions are implanted as follows.

[0064] Ion implantation of hydrogen (H) creates carbon vacancies in the first region 51. Each of the five ion implantations creates carbon vacancies in the first section 51a, second section 51b, third section 51c, fourth section 51d, and fifth section 51e at different depths.

[0065] Hydrogen (H) ion implantation is performed, for example, at a temperature of 300°C or higher. Hydrogen (H) ion implantation is performed, for example, while the holder on which the silicon carbide layer 10 is placed is maintained at a temperature of 300°C or higher. By performing hydrogen (H) ion implantation at a temperature of 300°C or higher, for example, the decrease in the crystallinity of the silicon carbide layer 10 is suppressed.

[0066] Next, aluminum (Al) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (Figure 6). Ion implantation of aluminum (Al) is an example of the first ion implantation.

[0067] By ion implantation of aluminum (Al), aluminum (Al) is implanted into a second region 52 of the silicon carbide layer 10. The second region 52 is shallower than the first region 51.

[0068] The second region 52 overlaps, for example, with a part of the first region 51. The second region 52 also overlaps, for example, with a part of the fifth portion 51e. The depth of the first region 51 is, for example, three times or more the depth of the second region 52.

[0069] Ion implantation of aluminum (Al) is carried out at temperatures above 300°C, for example.

[0070] Ion implantation of aluminum (Al) can also be performed, for example, before ion implantation of hydrogen (H).

[0071] Next, a second heat treatment is performed at a temperature of 300°C or higher (Figure 7). The second heat treatment is performed in a non-oxidizing atmosphere. The second heat treatment is performed, for example, in an inert gas atmosphere. The second heat treatment is performed, for example, in an argon gas atmosphere.

[0072] The second heat treatment causes aluminum (Al) to diffuse into the first region 51, forming the p-pillar region 28. The region between the p-pillar regions 28 becomes the n-pillar region 30.

[0073] Furthermore, if the ion implantation of aluminum (Al) is performed at a temperature of 300°C or higher, the aluminum (Al) will diffuse into the first region 51 even during the ion implantation process. For example, if sufficient aluminum (Al) can diffuse into the first region 51 during the ion implantation process, the second heat treatment can be omitted.

[0074] Next, a second ion implantation is performed on the silicon carbide layer 10 using the mask material 50 as a mask, implanting carbon (C) into it (Figure 8). Through ion implantation of carbon (C), carbon (C) is implanted into a third region 53. The third region 53 is shallower than the first region 51.

[0075] Ion implantation of carbon (C) is carried out at temperatures above 300°C, for example.

[0076] Next, a third heat treatment is performed at a temperature of 300°C or higher (Figure 9). The third heat treatment is performed in a non-oxidizing atmosphere. The third heat treatment is performed, for example, in an inert gas atmosphere. The third heat treatment is performed, for example, in an argon gas atmosphere.

[0077] The third heat treatment causes carbon (C) to diffuse into the p-pillar region 28.

[0078] Furthermore, if carbon (C) ion implantation is performed at a temperature of 300°C or higher, carbon (C) will diffuse into the p-pillar region 28 during the ion implantation process. For example, if sufficient carbon (C) can diffuse into the p-pillar region 28 during the ion implantation process, the third heat treatment can be omitted.

[0079] Next, the mask material 50 is removed. The mask material 50 is removed, for example, using a wet etching method.

[0080] Next, the epitaxial layer 11 is subjected to p-type body regions 32 and n using known photolithography and ion implantation methods. + Source area 34 of type, and p + A contact region 38 of the type is formed (Figure 10).

[0081] Next, a carbon film 55 is formed on the surface of the silicon carbide layer 10 (Figure 11).

[0082] Next, a first heat treatment is performed. The first heat treatment is performed, for example, at a temperature between 1600°C and 2000°C. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

[0083] The first heat treatment activates the ion-implanted aluminum (Al). Additionally, the first heat treatment allows the ion-implanted carbon (C) to fill the carbon vacancies formed by the hydrogen (H) ion implantation.

[0084] Next, the gate insulating layer 18, gate electrode 16, interlayer insulating layer 20, source electrode 12, and drain electrode 14 are formed using known process techniques. The MOSFET 100 shown in Figure 1 is manufactured by the above manufacturing method.

[0085] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0086] MOSFET100 features an SJ structure formed by a p-pillar region 28 and an n-pillar region 30. The SJ structure, with its laterally extending depletion layer within the p-pillar region 28 and n-pillar region 30, mitigates the electric field strength in the semiconductor, enabling the MOSFET100 to achieve high breakdown voltage. Furthermore, the presence of the SJ structure allows for a higher concentration of n-type impurities in the n-pillar region 30. Consequently, the on-resistance of MOSFET100 is reduced.

[0087] MOSFE100 is measured by Deep Level Transient Spectroscopy (DLTS) in the p-pillar region 28. 1 / 2 The energy level density is measured by DLTS in the n-pillar region 30. 1 / 2 It is smaller than the energy level density. Z measured by DLTS 1 / 2 The level density corresponds to the density of carbon vacancies. The density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30.

[0088] As described above, the SJ structure, through a depletion layer extending laterally within the p-pillar region 28 and the n-pillar region 30, mitigates the electric field strength in the semiconductor, thereby achieving the high breakdown voltage of the MOSFET 100. The presence of carbon vacancies shortens the lifetime of carriers in silicon carbide. For example, the presence of carbon vacancies shortens the lifetime of holes in the p-pillar region 28 and the lifetime of electrons in the n-pillar region 30. In particular, the presence of carbon vacancies shortens the lifetime of holes more than that of electrons.

[0089] Because the lifetime of holes is shorter than that of electrons, if the density of carbon vacancies in the p-pillar region 28 and the n-pillar region 30 are the same, the balance between the time evolution of the depletion layer width in the p-pillar region 28 and the depletion layer width in the n-pillar region 30 will be disrupted. Consequently, the breakdown voltage of the MOSFET may decrease.

[0090] In MOSFET100, the density of carbon vacancies in the p-pillar region 28 is lower than the density of carbon vacancies in the n-pillar region 30, which maintains a balance between the time evolution of the depletion layer width in the p-pillar region 28 and the depletion layer width in the n-pillar region 30. Therefore, a high breakdown voltage can be achieved in MOSFET100.

[0091] In SJ structure MOSFETs, it is required to form deep p-type regions within the silicon carbide layer. For example, it is required to form p-type regions deeper than 5 μm. With conventional ion implantation methods, it is difficult to implant p-type impurities such as aluminum (Al) and boron (B) into regions deeper than 5 μm.

[0092] Therefore, for example, when forming an SJ structure, there is a method of repeatedly performing epitaxial growth of a silicon carbide film, ion implantation of p-type impurities, and activation annealing of p-type impurities to form a deep p-type region in the silicon carbide layer. However, this method has the problem of increasing manufacturing costs due to the increased number of steps. Furthermore, this method has the problem of being unsuitable for miniaturization of MOSFETs because it requires precise positioning of the ion implantation of p-type impurities.

[0093] Furthermore, for example, when forming an SJ structure, there is a method of channeling ion implantation, which involves implanting p-type impurities along a specific crystal axis, thereby forming a deep p-type region within the silicon carbide layer. In this method, it is necessary to precisely match the crystal orientation on the surface of the silicon carbide layer with the ion implantation direction. Therefore, there is a problem in that variations in the crystal orientation on the surface of the silicon carbide layer lead to large variations in the depth of the p-type region.

[0094] In the semiconductor device manufacturing method of the first embodiment, hydrogen (H) ion implantation is performed before ion implantation of p-type impurities to form a first region 51 with a high and deep carbon vacancy density. Hydrogen (H) has a smaller ionic radius compared to aluminum (Al) and boron (B). For this reason, it is easy to implant it to depths of, for example, 5 μm or more. In the first region 51, the carbon vacancy density in silicon carbide increases due to damage caused by hydrogen (H) ion implantation.

[0095] For example, after forming a first region 51 with a high carbon vacancy density and depth, p-type impurities are ion-implanted. Then, for example, the p-type impurities are diffused by a second heat treatment. The presence of carbon vacancies in the silicon carbide promotes the diffusion of p-type impurities. Therefore, the p-type impurities can diffuse throughout the entire first region 51, for example, and form deep p-type regions in the silicon carbide layer. Thus, it becomes possible to form deep p-pillar regions 28 in the silicon carbide layer 10.

[0096] The p-type impurities diffuse along the first region 51, which has a high density of carbon vacancies. Therefore, the lateral diffusion of p-type impurities is suppressed. Thus, it becomes possible to form p-type regions that are deep and narrow in width, in other words, p-type regions with a large aspect ratio.

[0097] According to the semiconductor device manufacturing method of the first embodiment, it is possible to form a deep p-type region in the silicon carbide layer using a simple manufacturing method with a small number of steps.

[0098] Furthermore, in the semiconductor device manufacturing method of the first embodiment, hydrogen (H) ion implantation and multiple ion implantations of p-type impurities are performed using the same mask material. Therefore, coordination of ion implantation is unnecessary, enabling miniaturization of the MOSFET.

[0099] Furthermore, since the semiconductor device manufacturing method of the first embodiment does not depend on channeling ion implantation, it is possible to form p-type regions of the same depth regardless of the crystal orientation of the surface of the silicon carbide layer 10. Therefore, according to the semiconductor device manufacturing method of the first embodiment, variations in the depth of the p-type region can be suppressed. Since the substrate has an off-angle, when ion implantation is performed on the substrate from directly above, ion implantation is performed under conditions where channeling does not occur. Therefore, there is almost no variation in the depth of ion implantation.

[0100] From the viewpoint of increasing the uniformity of carbon vacancy density from the deep to the shallow parts of the first region 51, it is preferable that hydrogen (H) ion implantation be performed by multiple ion implantations with varying acceleration energies.

[0101] From the perspective of increasing the carbon vacancy density to promote the diffusion of p-type impurities, the hydrogen (H) concentration in the first region 51 is 1 × 10⁻⁶. 15 cm -3 It is preferable to perform hydrogen (H) ion implantation in such a manner as described above, 1 × 10 16 cm -3 It is more preferable to perform hydrogen (H) ion implantation in such a manner as described above, 1 × 10 17 cm -3It is even more preferable to perform hydrogen (H) ion implantation in such a manner as described above.

[0102] From the viewpoint of suppressing the decrease in crystallinity of the silicon carbide layer 10, the hydrogen (H) concentration in the first region 51 is 1 × 10⁻⁶. 21 cm -3 It is preferable to perform hydrogen (H) ion implantation so that the following occurs: 1 × 10 20 cm -3 It is more preferable to perform hydrogen (H) ion implantation so that the following occurs: 1 × 10 19 cm -3 It is even more preferable to perform hydrogen (H) ion implantation in the following manner.

[0103] From the viewpoint of suppressing a decrease in the crystallinity of the silicon carbide layer 10, hydrogen (H) ion implantation is preferably carried out at a temperature of 300°C or higher, more preferably at a temperature of 500°C or higher, and even more preferably at a temperature of 900°C or higher.

[0104] From the viewpoint of diffusing aluminum (Al) into the first region 51 during the first ion implantation in which aluminum (Al) is ion-implanted, the first ion implantation is preferably carried out at a temperature of 300°C or higher, more preferably at a temperature of 500°C or higher, and even more preferably at a temperature of 900°C or higher.

[0105] From the viewpoint of promoting the diffusion of aluminum (Al) into the first region 51, the temperature of the second heat treatment performed after the first ion implantation is preferably 300°C or higher, more preferably 500°C or higher, and even more preferably 900°C or higher.

[0106] From the viewpoint of eliminating the carbon vacancies generated in the first region 51 by hydrogen (H) ion implantation, it is preferable to perform a second ion implantation in which carbon (C) is ion-implanted into the silicon carbide layer 10 after the diffusion of aluminum (Al).

[0107] By performing a second ion implantation, it is possible to make the density of carbon vacancies in the p-pillar region 28 lower than the density of carbon vacancies in the n-pillar region 30.

[0108] From the viewpoint of promoting the diffusion of carbon (C) into the p-pillar region 28, the second ion implantation is preferably performed at a temperature of 300°C or higher, more preferably at a temperature of 500°C or higher, and even more preferably at a temperature of 900°C or higher. In the series of ion implantations, since the mask material 50 is composed of a laminated film of silicon oxide film 50a and metal film 50b, ion implantation at high temperatures that are difficult with resists can be achieved. Since a hard mask such as silicon oxide film 50a is used, the upper limit is about 1200°C.

[0109] From the viewpoint of promoting the diffusion of carbon (C) into the p-pillar region 28, the temperature of the third heat treatment performed after carbon (C) ion implantation is preferably 300°C or higher, more preferably 500°C or higher, and even more preferably 900°C or higher.

[0110] (First variation) The first modification of the first embodiment of the semiconductor device manufacturing method differs from the first embodiment of the semiconductor device manufacturing method in that the substance is helium (He) and the first process is ion implantation into a first region of helium (He).

[0111] Helium (He), like hydrogen (H), has a smaller ionic radius compared to aluminum (Al) and boron (B). Therefore, it is easy to implant it into deep regions, such as 5 μm or more.

[0112] According to the first modification of the first embodiment of the semiconductor device manufacturing method, the same functions and effects as those of the semiconductor device manufacturing method of the first embodiment can be obtained.

[0113] (Second variation) The second modification of the first embodiment of the semiconductor device manufacturing method differs from the first embodiment of the semiconductor device manufacturing method in that the substance is electrons and the first process is the injection of electrons into a first region by electron beam irradiation.

[0114] Because electrons have a smaller diameter compared to aluminum (Al) or boron (B), it is easy to inject them into deep regions, such as 5 μm or more, by electron beam irradiation.

[0115] According to the second modified example of the first embodiment of the semiconductor device manufacturing method, the same functions and effects as those of the first embodiment of the semiconductor device manufacturing method can be obtained.

[0116] As described above, according to the first embodiment and its modifications, a semiconductor device with high voltage resistance can be realized. Furthermore, according to the first embodiment and its modifications, a method for manufacturing a semiconductor device that can easily form a deep p-type region can be realized.

[0117] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the silicon carbide layer is located on the side of the first surface and further includes a trench extending in a second direction on the first surface, and the gate electrode is provided in the trench. Furthermore, the method for manufacturing the semiconductor device of the second embodiment differs from the method for manufacturing the semiconductor device of the first embodiment in that a trench is formed in the silicon carbide layer using a mask material as a mask before the first treatment and the first ion implantation. In the following, some descriptions that overlap with the first embodiment may be omitted.

[0118] Figure 12 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a trench gate type vertical MOSFET 200 using silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers. The MOSFET 200 has a superjunction structure (SJ structure).

[0119] Figure 13 is a schematic plan view of a semiconductor device according to the second embodiment. Figure 13 is a plan view of the first surface (P1 in Figure 12) of Figure 12. Figure 12 is a cross-sectional view AA' of Figure 13.

[0120] The MOSFET200 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0121] The silicon carbide layer 10 is located in the gate trench 22 (trench), n + Drain region 24 of type n - Type A drift region 26, p-type p-pillar region 28 (first silicon carbide region), n-type n-pillar region 30 (second silicon carbide region), p-type body region 32 (third silicon carbide region), n + Source region 34 of type (fourth silicon carbide region), p + Type electric field relaxation region 36, p + It has a type contact area 38.

[0122] The gate trench 22 is located within the silicon carbide layer 10. The gate trench 22 is located on the side of the first surface P1 of the silicon carbide layer 10. The gate trench 22 is a groove formed in the silicon carbide layer 10.

[0123] The gate trench 22 extends in a second direction as shown in Figure 13. The gate trench 22 is repeatedly arranged in a first direction as shown in Figure 13. The repeating pitch of the gate trench 22 in the first direction is, for example, 1 μm or more and 5 μm or less. The depth of the gate trench 22 is, for example, 1 μm or more and 2 μm or less. The width of the gate trench 22 in the first direction is, for example, 0.5 μm or more and 1 μm or less.

[0124] The gate electrode 16 is located within the gate trench 22. The gate electrode 16 is provided between the source electrode 12 and the drain electrode 14. The gate electrode 16 extends in a second direction.

[0125] The gate insulating layer 18 is located between the gate electrode 16 and the silicon carbide layer 10. The gate insulating layer 18 is provided between the source region 34, the body region 32, the electric field relaxation region 36, and the n-pillar region 30 and the gate electrode 16.

[0126] The p-type p-pillar region 28 and the n-type n-pillar region 30 are provided between the drain region 24 and the first surface P1. The p-pillar region 28 and the n-pillar region 30 are provided between the drift region 26 and the first surface P1.

[0127] The p-pillar region 28 is provided between the gate trench 22 and the second surface P2. It is provided between the drift region 26.

[0128] The p-pillar region 28 and the n-pillar region 30 are alternately arranged in the first direction. The p-pillar region 28 and the n-pillar region 30 form a so-called super junction structure (SJ structure).

[0129] The p-pillar region 28 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-pillar region 28 is, for example, 5×10 15 cm -3 or more and 5×10 17 cm -3 or less.

[0130] The n-pillar region 30 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the n-pillar region 30 is, for example, 5×10 15 cm -3 or more and 5×10 17 cm -3 or less.

[0131] For example, when the width of the p-pillar region 28 in the second direction is W1, the p-type impurity concentration of the p-pillar region 28 is N1, the width of the n-pillar region 30 in the second direction is W2, and the n-type impurity concentration of the n-pillar region 30 is N2, the following relationship of the formula is satisfied. 0.8 ≦ (W1×N1) / (W2×N2) ≦ 1.2

[0132] The aspect ratio (d1 / W1) of the depth d1 in the third direction of the p-pillar region 28 and the width (W1 in FIG. 12) in the second direction of the p-pillar region 28 is, for example, 3 or more. The depth d1 in the third direction perpendicular to the first surface of the p-pillar region 28 is, for example, 5 μm or more and 10 μm or less.

[0133] The density of the Z 1 / 2 level measured by Deep Level Transient Spectroscopy (DLTS) in the p-pillar region 28 is smaller than the density of the Z 1 / 2 level measured by DLTS in the n-pillar region 30. The density of the Z 1 / 2 level in the p-pillar region 28 is, for example, 50% or less of the density of the Z 1 / 2 level in the n-pillar region 30.

[0134] The density of the Z 1 / 2 level measured by DLTS corresponds to the density of carbon vacancies. The density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30.

[0135] p + type electric field relaxation region 36 is located between the p-pillar region 28 and the gate trench 22. The electric field relaxation region 36 contacts the bottom surface of the gate trench 22. The electric field relaxation region 36 contacts the gate insulating layer 18. The electric field relaxation region 36 contacts the p-pillar region 28.

[0136] The electric field relaxation region 36 has a function of relaxing the electric field applied to the gate insulating layer 18 during the off operation of the MOSFET 200. The electric field relaxation region 36 is, for example, fixed to the same potential as the source electrode 12.

[0137] The electric field relaxation region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the electric field relaxation region 36 is higher than the p-type impurity concentration in the p-pillar region 28. The p-type impurity concentration in the electric field relaxation region 36 is, for example, 10 times or more the p-type impurity concentration in the p-pillar region 28. The p-type impurity concentration in the electric field relaxation region 36 is, for example, 5×10 17 cm -3The above 5 x 10 19 cm -3 The following applies:

[0138] Next, an example of a method for manufacturing a semiconductor device according to the second embodiment will be described.

[0139] Figures 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, and 25 are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the second embodiment. Figures 14 to 25 show the cross-section corresponding to Figure 12.

[0140] First, n + A drain region 24 of type n - A silicon carbide layer 10 having type and n-type epitaxial layers 11 is prepared (Figure 14). A portion of the epitaxial layer 11 eventually becomes a drift region 26 and an n-pillar region 30.

[0141] Next, the epitaxial layer 11 is subjected to p-type body regions 32 and n using known photolithography and ion implantation methods. + Source area 34 of type, and p + A contact region 38 of the type is formed (Figure 15).

[0142] Next, a mask material 50 having openings is formed on the silicon carbide layer 10 (Figure 16). The mask material 50 is, for example, a laminated film of a silicon oxide film 50a and a metal film 50b. The metal film 50b is, for example, tungsten.

[0143] Next, a gate trench 22 is formed on the mask material 50 using a known reactive ion etching method (Figure 17). The gate trench 22 is formed to penetrate the source region 34 and the body region 32.

[0144] Next, hydrogen (H) is ion-implanted into the silicon carbide layer 10 from the opening using the mask material 50 as a mask (Figure 18). Hydrogen (H) is injected into the silicon carbide layer 10 from the bottom of the gate trench 22. Hydrogen (H) is an example of a substance. Ion implantation of hydrogen (H) is an example of the first treatment.

[0145] Hydrogen (H) is implanted into the first region 51 by ion implantation. Ion implantation of hydrogen (H) involves multiple implantations. For example, ion implantation of hydrogen (H) involves four implantations.

[0146] The four ion implantations are carried out with different acceleration energies. Through each of the four ion implantations, hydrogen (H) is implanted into the first section 51a, the second section 51b, the third section 51c, and the fourth section 51d at different depths.

[0147] The concentration of hydrogen (H) in the first region 51 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 21 cm -3 Hydrogen (H) ion implantation is performed as follows.

[0148] By implanting hydrogen (H) ions, carbon vacancies are formed in the first region 51. Each of the four ion implantations forms carbon vacancies in the first section 51a, second section 51b, third section 51c, and fourth section 51d at different depths.

[0149] Hydrogen (H) ion implantation is performed, for example, at a temperature of 300°C or higher. Hydrogen (H) ion implantation is performed, for example, while the holder on which the silicon carbide layer 10 is placed is maintained at a temperature of 300°C or higher. By performing hydrogen (H) ion implantation at a temperature of 300°C or higher, for example, the decrease in the crystallinity of the silicon carbide layer 10 is suppressed.

[0150] Next, aluminum (Al) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (Figure 19). Ion implantation of aluminum (Al) is an example of the first ion implantation.

[0151] By ion implantation of aluminum (Al), aluminum (Al) is implanted into the second region 52. The second region 52 is shallower than the first region 51. The second region 52 overlaps with a portion of the first region 51. The second region 52 overlaps with, for example, a portion of the fourth portion 51d. The depth of the first region 51 is, for example, more than three times the depth of the second region 52.

[0152] Ion implantation of aluminum (Al) is carried out at temperatures above 300°C, for example.

[0153] Next, a second heat treatment is performed at a temperature of 300°C or higher (Figure 20). The second heat treatment is performed in a non-oxidizing atmosphere. The second heat treatment is performed, for example, in an inert gas atmosphere. The second heat treatment is performed, for example, in an argon gas atmosphere.

[0154] The second heat treatment causes aluminum (Al) to diffuse into the first region 51, forming the p-pillar region 28. The region between the p-pillar regions 28 becomes the n-pillar region 30.

[0155] Furthermore, if the ion implantation of aluminum (Al) is performed at a temperature of 300°C or higher, the aluminum (Al) will diffuse into the first region 51 even during the ion implantation process. For example, if sufficient aluminum (Al) can diffuse into the first region 51 during the ion implantation process, the second heat treatment can be omitted.

[0156] Next, a second ion implantation is performed on the silicon carbide layer 10 using the mask material 50 as a mask, implanting carbon (C) into it (Figure 21). Through ion implantation of carbon (C), carbon (C) is implanted into a third region 53. The third region 53 is shallower than the first region 51.

[0157] Ion implantation of carbon (C) is carried out at temperatures above 300°C, for example.

[0158] Next, a third heat treatment is performed at a temperature of 300°C or higher (Figure 22). The third heat treatment is performed in a non-oxidizing atmosphere. The third heat treatment is performed, for example, in an inert gas atmosphere. The third heat treatment is performed, for example, in an argon gas atmosphere.

[0159] The third heat treatment causes carbon (C) to diffuse into the p-pillar region 28.

[0160] Furthermore, if carbon (C) ion implantation is performed at a temperature of 300°C or higher, carbon (C) will diffuse into the p-pillar region 28 during the ion implantation process. For example, if sufficient carbon (C) can diffuse into the p-pillar region 28 during the ion implantation process, the third heat treatment can be omitted.

[0161] Next, aluminum (Al) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (Figure 23). Due to the ion implantation of aluminum (Al), p is deposited at the bottom of the gate trench 22. + A type of electric field relaxation region 36 is formed.

[0162] Next, the mask material 50 is removed. The mask material 50 is removed, for example, using a wet etching method.

[0163] Next, a carbon film 55 is formed on the surface of the silicon carbide layer 10 (Figure 24).

[0164] Next, a first heat treatment is performed. The first heat treatment is performed, for example, at a temperature between 1600°C and 2000°C. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

[0165] The first heat treatment activates the ion-implanted aluminum (Al). Additionally, the first heat treatment allows the ion-implanted carbon (C) to fill the carbon vacancies formed by the hydrogen (H) ion implantation.

[0166] Next, the gate insulating layer 18 and the gate electrode 16 are formed in the gate trench 22 using known process techniques (Figure 25).

[0167] Next, the interlayer insulating layer 20, the source electrode 12, and the drain electrode 14 are formed using known process techniques. The MOSFET 200 shown in Figure 12 is manufactured by the above manufacturing method.

[0168] By incorporating a trench gate structure, MOSFET200 can reduce the on-resistance per unit area compared to, for example, MOSFET100, which has a planar gate structure.

[0169] Furthermore, the MOSFET200 has an SJ structure formed by the p-pillar region 28 and the n-pillar region 30. Therefore, the MOSFET200 can achieve high breakdown voltage and low on-resistance.

[0170] MOSFE200 measures Z by Deep Level Transient Spectroscopy (DLTS) in the p-pillar region 28. 1 / 2 The energy level density is measured by DLTS in the n-pillar region 30. 1 / 2 It is smaller than the energy level density. Therefore, in MOSFET200, the density of carbon vacancies in the p-pillar region 28 is smaller than the density of carbon vacancies in the n-pillar region 30. Thus, the balance between the time evolution of the depletion layer width in the p-pillar region 28 and the depletion layer width in the n-pillar region 30 is maintained. As a result, a high breakdown voltage can be achieved in MOSFET200.

[0171] According to the second embodiment of the semiconductor device manufacturing method, similar to the first embodiment of the semiconductor device manufacturing method, it is possible to form a deep p-type region in the silicon carbide layer using a simple manufacturing method with fewer steps.

[0172] Furthermore, in the semiconductor device manufacturing method of the second embodiment, for example, hydrogen (H) ion implantation and multiple ion implantations of p-type impurities are performed using the same mask material. Therefore, coordination of ion implantation is unnecessary, and miniaturization of the MOSFET can be achieved.

[0173] Furthermore, since the semiconductor device manufacturing method of the second embodiment does not depend on channeling ion implantation, it is possible to form p-type regions of the same depth regardless of the crystal orientation of the surface of the silicon carbide layer 10. Therefore, according to the semiconductor device manufacturing method of the second embodiment, variations in the depth of the p-type regions can be suppressed.

[0174] As described above, according to the second embodiment, a semiconductor device with high voltage resistance can be realized. Furthermore, according to the second embodiment, a method for manufacturing a semiconductor device that can easily form a deep p-type region can be realized.

[0175] (Third embodiment) The third embodiment of the semiconductor device manufacturing method does not form an SJ structure, p + This method differs from the semiconductor device manufacturing methods of the first and second embodiments in that it forms a deep contact area of ​​the mold. Hereafter, some descriptions that overlap with the first or second embodiment may be omitted.

[0176] Figure 26 is a schematic cross-sectional view of a semiconductor device manufactured by the semiconductor device manufacturing method of the third embodiment. The semiconductor device of the third embodiment is a trench gate type vertical MOSFET 300 using silicon carbide. The MOSFET 300 is an n-channel type MOSFET that uses electrons as carriers.

[0177] The MOSFET300 comprises a silicon carbide layer 10, a source electrode 12, a drain electrode 14, a gate electrode 16, a gate insulating layer 18, and an interlayer insulating layer 20.

[0178] The silicon carbide layer 10 is located in the gate trench 22, n + Drain region 24 of type n - Type 26 drift region, p-type body region 32, n + Source area 34 of type p + It has a type contact area 38.

[0179] p +The contact region 38 is located between the drift region 26 and the first surface P1. The contact region 38 is in contact with the source electrode 12. The contact region 38 is provided between the two gate trenches 22. The depth of the contact region 38 is greater than the depth of the body region 32.

[0180] The contact region 38 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the contact region 38 is, for example, higher than the concentration of p-type impurities in the body region 32. The concentration of p-type impurities in the contact region 38 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0181] The MOSFET 300 has a deep contact region 38, which reduces the electric field strength applied to the gate insulating layer 18 when the MOSFET 300 is off. The deep contact region 38 suppresses dielectric breakdown of the gate insulating layer 18 of the MOSFET 300, improving the reliability of the MOSFET 300.

[0182] Next, an example of a method for manufacturing a semiconductor device according to the third embodiment will be described.

[0183] Figures 27, 28, 29, 30, 31, 32, 33, 34, and 35 are schematic cross-sectional views showing an example of a semiconductor device manufacturing method according to the third embodiment. Figures 27 to 35 show cross-sections corresponding to Figure 26.

[0184] First, n + A drain region 24 of type n - A silicon carbide layer 10 having a drift region 26 of a certain type is prepared (Figure 27). The drift region 26 is, for example, an epitaxial growth layer formed on top of the drain region 24.

[0185] Next, a mask material 50 having openings is formed on the silicon carbide layer 10 (Figure 28). The mask material 50 is, for example, a laminated film of a silicon oxide film 50a and a metal film 50b. The metal film 50b is, for example, tungsten.

[0186] Next, hydrogen (H) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (Figure 29). Hydrogen (H) is an example of a substance. Ion implantation of hydrogen (H) is an example of the first treatment.

[0187] Hydrogen (H) is implanted into the first region 51 by ion implantation. Ion implantation of hydrogen (H) involves multiple ion implantations. For example, ion implantation of hydrogen (H) involves two ion implantations.

[0188] The two ion implantations are carried out with different acceleration energies. Through each of the two ion implantations, hydrogen (H) is implanted into the first section 51a and the second section 51b at different depths.

[0189] The concentration of hydrogen (H) in the first region 51 is, for example, 1 × 10⁻⁶ 15 cm -3 The above 1 x 10 21 cm -3 Hydrogen (H) ion implantation is performed as follows.

[0190] By implanting hydrogen (H) ions, carbon vacancies are formed in the first region 51. Through two separate ion implantations, carbon vacancies are formed in the first portion 51a and the second portion 51b at different depths.

[0191] Hydrogen (H) ion implantation is performed, for example, at a temperature of 300°C or higher. Hydrogen (H) ion implantation is performed, for example, while the holder on which the silicon carbide layer 10 is placed is maintained at a temperature of 300°C or higher. By performing hydrogen (H) ion implantation at a temperature of 300°C or higher, for example, the decrease in the crystallinity of the silicon carbide layer 10 is suppressed.

[0192] Next, aluminum (Al) is ion-implanted into the silicon carbide layer 10 using the mask material 50 as a mask (Figure 30). Ion implantation of aluminum (Al) is an example of the first ion implantation.

[0193] By ion implantation of aluminum (Al), aluminum (Al) is implanted into the second region 52. The second region 52 is shallower than the first region 51. The second region 52 overlaps, for example, with a portion of the second part 51b. The depth of the first region 51 is, for example, more than three times the depth of the second region 52.

[0194] Ion implantation of aluminum (Al) is carried out at temperatures above 300°C, for example.

[0195] Next, a second heat treatment is performed at a temperature of 300°C or higher (Figure 31). The second heat treatment is performed in a non-oxidizing atmosphere. The second heat treatment is performed, for example, in an inert gas atmosphere. The second heat treatment is performed, for example, in an argon gas atmosphere.

[0196] The second heat treatment causes aluminum (Al) to diffuse into the first region 51, p + A typed contact region 38 is formed.

[0197] Furthermore, if the ion implantation of aluminum (Al) is performed at a temperature of 300°C or higher, the aluminum (Al) will diffuse into the first region 51 even during the ion implantation process. For example, if sufficient aluminum (Al) can diffuse into the first region 51 during the ion implantation process, the second heat treatment can be omitted.

[0198] Next, a second ion implantation is performed on the silicon carbide layer 10 using the mask material 50 as a mask, implanting carbon (C) into it (Figure 32). Through ion implantation of carbon (C), carbon (C) is implanted into a third region 53. The third region 53 is shallower than the first region 51.

[0199] Ion implantation of carbon (C) is carried out at temperatures above 300°C, for example.

[0200] Next, a third heat treatment is performed at a temperature of 300°C or higher (Figure 33). The third heat treatment is performed in a non-oxidizing atmosphere. The third heat treatment is performed, for example, in an inert gas atmosphere. The third heat treatment is performed, for example, in an argon gas atmosphere.

[0201] The third heat treatment causes carbon (C) to diffuse into the contact region 38.

[0202] Furthermore, if carbon (C) ion implantation is performed at a temperature of 300°C or higher, carbon (C) will diffuse into the contact region 38 during the ion implantation process. For example, if sufficient carbon (C) can diffuse into the contact region 38 during the ion implantation process, the third heat treatment can be omitted.

[0203] Next, the mask material 50 is removed. The mask material 50 is removed, for example, using a wet etching method.

[0204] Next, the epitaxial layer 11 is subjected to known photolithography and ion implantation methods to create p-type body regions 32 and n + A source region 34 of the type is formed (Figure 34).

[0205] Next, a carbon film 55 is formed on the surface of the silicon carbide layer 10 (Figure 35).

[0206] Next, a first heat treatment is performed. The first heat treatment is performed, for example, at a temperature between 1600°C and 2000°C. The first heat treatment is performed in a non-oxidizing atmosphere. The first heat treatment is performed, for example, in an inert gas atmosphere. The heat treatment is performed, for example, in an argon gas atmosphere.

[0207] The first heat treatment activates the ion-implanted aluminum (Al). Additionally, the first heat treatment allows the ion-implanted carbon (C) to fill the carbon vacancies formed by the hydrogen (H) ion implantation.

[0208] Next, the gate trench 22, gate insulating layer 18, gate electrode 16, interlayer insulating layer 20, source electrode 12, and drain electrode 14 are formed using known process techniques. The MOSFET 300 shown in Figure 26 is manufactured by the above manufacturing method.

[0209] According to the third embodiment of the semiconductor device manufacturing method, similar to the first embodiment, it is possible to form a deep p-type region in the silicon carbide layer using a simple manufacturing method with fewer steps. Furthermore, for example, hydrogen (H) ion implantation and multiple ion implantations of p-type impurities are performed using the same mask material. Therefore, coordination of ion implantation is unnecessary, enabling miniaturization of the MOSFET.

[0210] Furthermore, since it does not depend on channeling ion implantation, it is possible to form p-type regions of the same depth regardless of the crystal orientation of the surface of the silicon carbide layer 10. Therefore, according to the semiconductor device manufacturing method of the third embodiment, variations in the depth of the p-type region can be suppressed.

[0211] As described above, according to the third embodiment, a method for manufacturing a semiconductor device that can easily form a deep p-type region can be realized.

[0212] In the first to third embodiments, the n-type impurity is, for example, nitrogen or phosphorus. It is also possible to use arsenic (As) or antimony (Sb) as the n-type impurity.

[0213] Furthermore, in the first to third embodiments, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be used as the p-type impurity.

[0214] In the first to third embodiments, the case of silicon carbide with a 4H-SiC crystal structure was described as an example, but the present invention can also be applied to silicon carbide with other crystal structures such as 6H-SiC and 3C-SiC.

[0215] In the first to third embodiments, the p-pillar region 28 or the contact region 38 were described as examples of deep p-type regions, but the present invention can also be applied to other deep p-type regions formed in the silicon carbide layer.

[0216] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0217] 10. Silicon carbide layer 12 Source electrode (first electrode) 14. Drain electrode (second electrode) 16 Guard Station 18 Gate insulating layer 22 Gate Trench (Trench) 28 p-pillar region (first silicon carbide region) 30 n-pillar region (second silicon carbide region) 32 Body region (third silicon carbide region) 34. Source region (fourth silicon carbide region) 50 Masking materials 50b metal film 51 The first area 52 Second Domain 55 Carbon film 100 MOSFETs (Semiconductor Devices) 200 MOSFETs (Semiconductor Devices) 300 MOSFETs (semiconductor equipment) P1 First surface (front) P2 Second side

Claims

1. A mask material having openings on the surface of the silicon carbide layer is formed. The mask material is subjected to a first treatment in which at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons is injected into a first region of the silicon carbide layer. Before or after the first treatment, a first ion implantation is performed on the mask material to implant p-type impurities into a second region shallower than the first region. After the first treatment and the first ion implantation, the mask material is removed. After removing the mask material, a first heat treatment at 1600°C or higher is performed. A method for manufacturing a semiconductor device, wherein the first ion implantation is performed after the first process, and the first ion implantation is performed at a temperature of 300°C or higher.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first process includes a plurality of processes, and in each of the plurality of processes, the at least one substance is injected to different depths in the silicon carbide layer.

3. A mask material having openings on the surface of the silicon carbide layer is formed, The mask material is subjected to a first treatment in which at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons is injected into a first region of the silicon carbide layer. Before or after the first treatment, a first ion implantation is performed on the mask material to implant p-type impurities into a second region shallower than the first region. After the first treatment and the first ion implantation, the mask material is removed. After removing the mask material, a first heat treatment at 1600°C or higher is performed. A method for manufacturing a semiconductor device, comprising performing a second heat treatment at 300°C or higher after the first treatment and the first ion implantation, and before peeling off the mask material.

4. A mask material having openings on the surface of the silicon carbide layer is formed, The mask material is subjected to a first treatment in which at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons is injected into a first region of the silicon carbide layer. Before or after the first treatment, a first ion implantation is performed on the mask material to implant p-type impurities into a second region shallower than the first region. After the first treatment and the first ion implantation, the mask material is removed. After removing the mask material, a first heat treatment at 1600°C or higher is performed. A method for manufacturing a semiconductor device, comprising performing a second ion implantation, in which carbon (C) is ion-implanted into the mask material, after the first ion implantation and before the mask material is peeled off.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the second ion implantation is performed at a temperature of 300°C or higher.

6. A method for manufacturing a semiconductor device according to claim 4, wherein a third heat treatment of 300°C or higher is performed after the second ion implantation and before the peeling of the mask material.

7. A mask material having openings on the surface of the silicon carbide layer is formed. The mask material is subjected to a first treatment in which at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons is injected into a first region of the silicon carbide layer. Before or after the first treatment, a first ion implantation is performed on the mask material to implant p-type impurities into a second region shallower than the first region. After the first treatment and the first ion implantation, the mask material is removed. After removing the mask material, a first heat treatment at 1600°C or higher is performed. A method for manufacturing a semiconductor device, wherein the depth of the first region is three times or more the depth of the second region.

8. A mask material having openings on the surface of the silicon carbide layer is formed, The mask material is subjected to a first treatment in which at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons is injected into a first region of the silicon carbide layer. Before or after the first treatment, a first ion implantation is performed on the mask material to implant p-type impurities into a second region shallower than the first region. After the first treatment and the first ion implantation, the mask material is removed. After removing the mask material, a first heat treatment at 1600°C or higher is performed. A method for manufacturing a semiconductor device, wherein the depth of the first region is 5 μm or more.

9. The method for manufacturing a semiconductor device according to claim 1, wherein the first process is performed at 300°C or higher.

10. The concentration of at least one substance in the first region is 1 × 10 １５ cm －３ The above 1 x 10 ２１ cm －３ The method for manufacturing a semiconductor device according to claim 1, which is as follows:

11. A method for manufacturing a semiconductor device according to claim 1, wherein after peeling off the mask material and before the first heat treatment, a carbon film is formed on the surface of the silicon carbide layer.

12. The method for manufacturing a semiconductor device according to claim 1, wherein the mask material includes a metal film.

13. A mask material having openings on the surface of the silicon carbide layer is formed. The mask material is subjected to a first treatment in which at least one substance selected from the group consisting of hydrogen (H), helium (He), and electrons is injected into a first region of the silicon carbide layer. Before or after the first treatment, a first ion implantation is performed on the mask material to implant p-type impurities into a second region shallower than the first region. After the first treatment and the first ion implantation, the mask material is removed. After removing the mask material, a first heat treatment at 1600°C or higher is performed. A method for manufacturing a semiconductor device, comprising forming trenches in the silicon carbide layer using the mask material as a mask before the first treatment and the first ion implantation.

14. The method for manufacturing a semiconductor device according to claim 1, wherein the p-type impurity is aluminum (Al) or boron (B).

15. The first electrode and The second electrode and A silicon carbide layer having a first surface located between the first electrode and the second electrode, parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first direction and facing the first surface, A first p-type silicon carbide region and a second n-type silicon carbide region are arranged alternately in the first direction, A p-type third silicon carbide region located between the second silicon carbide region and the first surface, An n-type fourth silicon carbide region located between the third silicon carbide region and the first surface, A silicon carbide layer containing, A gate electrode is provided on the side of the first surface of the silicon carbide layer, facing the third silicon carbide region and extending in the second direction, The gate insulating layer is located between the gate electrode and the silicon carbide layer, Z measured by Deep Level Transient Spectroscopy (DLTS) in the first silicon carbide region. １／２ The level density is measured by DLTS in the second silicon carbide region Z １／２ A semiconductor device with a level density smaller than the energy level density.

16. The silicon carbide layer further includes trenches located on the side of the first surface and extending in the second direction on the first surface. The semiconductor device according to claim 15, wherein the gate electrode is provided in the trench.

17. The semiconductor device according to claim 16, wherein the first silicon carbide region is provided between the trench and the second surface.

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