Method for determining the epitaxy suitability of Czochralski growth conditions for manufacturing substrates.

Abstract

A method for determining the epitaxy suitability of Czochralski growth conditions for producing silicon substrates includes evaluating substrates sliced ​​from ingots grown under different growth conditions (e.g., impurity profiles) by imaging the wafers with infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters can be compared to determine suitable growth conditions for producing substrates for epitaxy and / or post-epi thermal processing.

Description

Cross - reference to related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 213,460, filed on June 22, 2021, which is hereby incorporated by reference in its entirety.

Technical Field

[0002] The field of the present disclosure relates to a method for determining the epitaxial compatibility of Chochralski growth conditions (e.g., melt impurity profile) for manufacturing a silicon substrate, and particularly to a method for determining the slip resistance of a substrate during epitaxy and during heat treatment after epitaxy.

Background Art

[0003] Slip often occurs during the manufacture of epitaxial wafers and during the thermal cycle after epitaxy. Slip resistance has become an increasingly important ability in advanced integrated circuit manufacturing technology. Conventional methods for detecting slip resistance are destructive processes that render the wafer unusable. For example, the wafer may be stressed in an annealing furnace and the warp of the wafer may be measured as an indicator of wafer strength. Furthermore, with conventional processes, different epitaxial substrates cannot be evaluated for slip resistance under different epitaxial processes and post - epi treatments.

[0004] The substrates used in epitaxial wafer manufacturing can be grown by a so - called Chochralski process in which a silicon seed crystal is brought into contact with a silicon melt. The silicon seed crystal and the single - crystal silicon ingot attached to it are pulled out of the melt. There is a need for a reliable non - destructive process that can quantitatively evaluate the Chochralski process (e.g., differences in melt impurity levels) with respect to the slip resistance of the resulting substrate under various epitaxial processes and heat treatments.

[0005] This section is intended to introduce to the reader various aspects of the technology that may be relevant to the various aspects of the disclosure described and / or claimed below. This discussion is intended to be useful in providing the reader with background information to better understand the various aspects of the disclosure. Accordingly, these statements should be read in this context and should be understood not as an endorsement of prior art. [Overview of the project]

[0006] One aspect of the present disclosure relates to a method for determining the epitaxy suitability of Czochralski growth conditions for manufacturing silicon substrates. A crucible containing a charge of silicon is heated to form a silicon melt in the crucible. A silicon seed crystal is brought into contact with the silicon melt. The silicon melt has a first impurity profile. The silicon seed crystal is pulled up to grow a first single-crystal silicon ingot. A first plurality of silicon substrates are sliced ​​from the first single-crystal silicon ingot. A silicon-containing gas is brought into contact with the front surface of the silicon substrates of the first plurality of silicon substrates. The silicon-containing gas decomposes to form an epitaxial silicon layer on the silicon substrates, forming a first epitaxial wafer. The first epitaxial wafer is imaged by infrared depolarization to determine a first infrared depolarization parameter. A crucible containing a charge of silicon is heated to form a second silicon melt in the crucible. A silicon seed crystal is brought into contact with the second silicon melt. The second silicon melt has a second impurity profile. The first impurity profile of the first melt is different from the second impurity profile of the second melt. A silicon seed crystal is pulled up to grow a second single-crystal silicon ingot. Multiple second silicon substrates are sliced ​​from the second single-crystal silicon ingot. A silicon-containing gas is brought into contact with the front surface of the silicon substrates of the multiple second silicon substrates. The silicon-containing gas decomposes to form an epitaxial silicon layer on the silicon substrates, forming a second epitaxial wafer. The second epitaxial wafer is imaged by infrared depolarization to determine a second infrared depolarization parameter. The epitaxy suitability of the first and second impurity profiles for manufacturing the substrate is determined based on the first and second infrared depolarization parameters.

[0007] Another aspect of this disclosure relates to a method for determining the epitaxy compatibility of a silicon substrate. The silicon substrate is placed on a susceptor located in a processing reactor. The front surface of the silicon substrate is brought into contact with a silicon-containing gas. The silicon-containing gas decomposes to form a first epitaxial silicon layer on the silicon substrate. The front surface of the first epitaxial silicon layer is brought into contact with the silicon-containing gas. The silicon-containing gas decomposes to form a second epitaxial silicon layer on the first epitaxial silicon layer, thereby forming an epitaxial wafer. The epitaxial wafer is imaged by infrared depolarization to determine the infrared depolarization.

[0008] Further aspects of this disclosure relate to a method for determining the epitaxy compatibility of a silicon substrate. The substrate is heat-treated in a first heat treatment step. The substrate is heat-treated in a second heat treatment step. After the first and second heat treatment steps, the substrate is imaged by infrared depolarization to determine infrared depolarization parameters.

[0009] Various improvements to the features described in relation to the above-described embodiments of this disclosure exist. Further features can also be incorporated into the above-described embodiments of this disclosure. These improvements and additional features may exist individually or in any combination. For example, the various features discussed below in relation to any of the illustrated embodiments of this disclosure may be incorporated individually or in any combination into any of the above-described embodiments of this disclosure. [Brief explanation of the drawing]

[0010] [Figure 1] This is a cross-sectional view of the ingot pulling device before silicon ingot growth. [Figure 2] Figure 1 is a cross-sectional view of the ingot pulling device during silicon ingot growth. [Figure 3] This is a cross-sectional view of a semiconductor substrate used to manufacture epitaxial wafers. [Figure 4] This is a cross-sectional view of an epitaxial wafer. [Figure 5]This is a flowchart of one embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 6] This is a flowchart of another embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 7] This is a flowchart of yet another embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 8] This is a flowchart of a further embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 9] This is a flowchart of a further embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 10] This is a flowchart of another exemplary embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 11] This is a flowchart of another embodiment of a method for determining the epitaxy compatibility of a silicon substrate. [Figure 12] This graph shows the nitrogen concentration in single-crystal silicon ingots against various starting nitrogen concentrations. [Figure 13] This is a graph of oxygen profiles at various oxygen concentrations in various ingots used to manufacture substrates for epitaxial layers. [Figure 14] This is a perspective view of a processing reactor used to deposit an epitaxial layer onto a substrate; the reactor cover has been removed. [Figure 15] This is a schematic diagram of a device that images epitaxial wafers by depolarizing infrared light. [Figure 16] This is a top view of an epitaxial wafer showing annular edge rings imaged by infrared depolarization. [Figure 17] This is a variation plot showing the depolarization of an epitaxial wafer having a substrate sliced ​​from a wafer grown in melts with different nitrogen and oxygen concentrations after the growth of two epitaxial layers. [Figure 18]Another variation plot showing the polarization extinction of an epitaxial wafer having a substrate sliced from a wafer grown from melts with different nitrogen and oxygen concentrations after the growth of two epitaxial layers. [Figure 19] A variation plot showing the polarization extinction of a substrate sliced from a wafer grown from melts with different impurity profiles after two heat treatments.

[0011] Throughout the drawings, corresponding reference characters indicate corresponding parts.

Best Mode for Carrying Out the Invention

[0012] The provisions of the present disclosure relate to a method of determining the epitaxial compatibility of a silicon substrate, such as by determining the slip resistance of the substrate during epitaxial layer deposition and / or during post-epi heat treatment. In some embodiments, the composition of the melt in which a silicon ingot is grown to produce the substrate of an epitaxial wafer is varied, and the resulting epitaxial wafer is imaged by infrared polarization extinction. As a result of the imaging, one or more infrared polarization extinction parameters are generated for each imaged wafer. These parameters are used to determine the compatibility (e.g., slip resistance) of the silicon substrate (and the impurity profile of the melt in which it is grown) with respect to the epitaxy.

[0013] The method of the present disclosure may generally be implemented in any ingot pulling apparatus configured to pull a single crystal silicon ingot. An exemplary ingot pulling apparatus (or more simply "ingot pulling apparatus") is shown generally as "101" in FIG. 1. The ingot pulling apparatus 101 includes a crucible 102 for holding a melt 104 of a semiconductor or solar cell grade material such as silicon, supported by a susceptor 106. The ingot pulling apparatus 101 includes a crystal pulling apparatus housing 108 that defines a growth chamber 152 for pulling a silicon ingot 113 (FIG. 2) from the melt 104 along a pulling axis A.

[0014] The crucible 102 includes a floor 129 and a side wall 131 extending upward from the floor 129. The side wall 131 is generally vertical. The floor 129 includes a curved portion of the crucible 102 that extends below the side wall 131. Inside the crucible 102 is a silicon melt 104 having a melt surface 111 (i.e., a melt-ingot interface).

[0015] In some embodiments, the crucible 102 is layered. For example, the crucible 102 may consist of a quartz base layer and a synthetic quartz liner placed on the quartz base layer.

[0016] The susceptor 106 is supported by the shaft 105. The susceptor 106, crucible 102, shaft 105, and ingot 113 (Figure 2) have a common longitudinal axis A or "tension axis" A.

[0017] The ingot pulling device 101 is equipped with a pulling mechanism 114 for growing the ingot 113 and pulling it out of the molten metal 104. The pulling mechanism 114 includes a pulling cable 118, a seed holder or chuck 120 coupled to one end of the pulling cable 118, and a silicon seed crystal 122 coupled to the seed holder or chuck 120 to initiate crystal growth. One end of the pulling cable 118 is connected to a pulley (not shown) or drum (not shown), or another suitable type of pulling mechanism, such as a shaft, and the other end is connected to the chuck 120 that holds the seed crystal 122. During operation, the seed crystal 122 is lowered to contact the molten metal 104. The pulling mechanism 114 is activated to raise the seed crystal 122. This pulls the single-crystal ingot 113 (Figure 2) out of the molten metal 104.

[0018] During heating and crystal pulling, a crucible drive unit 107 (e.g., a motor) rotates the crucible 102 and susceptor 106. A lift mechanism 112 raises and lowers the crucible 102 along the pulling axis A during the growth process. For example, the crucible 102 may be at its lowest position (near the bottom heater 126) where the initial charge of solid-phase polycrystalline silicon pre-added to the crucible 102 is melted. Crystal growth is initiated by bringing the molten silicon 104 into contact with the seed crystal 122 and lifting the seed crystal 122 by the pulling mechanism 114. As the ingot grows, the silicon molten silicon 104 is consumed and the height of the molten silicon in the crucible 102 decreases. The crucible 102 and susceptor 106 can be raised to maintain the molten surface 111 in the same position or near the ingot pulling device 101 (Figure 2).

[0019] A crystal drive unit (not shown) may also rotate the pull-up cable 118 and the ingot 113 (Figure 2) in the opposite direction to the direction in which the crucible drive unit 107 rotates the crucible 102 (e.g., reverse rotation). In embodiments using the same rotation, the crystal drive unit rotates the pull-up cable 118 in the same direction as the crucible drive unit 107 rotates the crucible 102. Furthermore, the crystal drive unit may, if desired, raise and lower the ingot 113 relative to the molten surface 111 during the growth process.

[0020] The ingot lifting device 101 may include an inert gas system for introducing and withdrawing an inert gas such as argon from the growth chamber 152. The ingot lifting device 101 may also include a dopant supply system (not shown) for introducing a dopant into the molten liquid 104.

[0021] According to the Czochralski single-crystal growth process, a predetermined amount of polycrystalline silicon, or polysilicon, is charged into a crucible 102. The initial semiconductor or solar-grade material introduced into the crucible is melted by heat supplied from one or more heating elements, forming a silicon melt within the crucible. The ingot pulling device 101 then... ingotThe ingot puller includes bottom insulation 115 and side insulation 124 for retaining heat within the puller. In the illustrated embodiment, the ingot puller 101 includes a bottom heater 126 located below the crucible bed 129. The crucible 102 can be moved to a relatively close position to the bottom heater 126 in order to melt the polycrystalline material charged in the crucible 102.

[0022] To form the ingot, a seed crystal 122 is brought into contact with the surface 111 of the molten metal 104. The pulling mechanism 114 is activated to pull the seed crystal 122 from the molten metal 104. Next, referring to Figure 2, the ingot 113 includes a crown portion 142, in which the ingot transitions outward from the seed crystal 122 and becomes tapered to reach the target diameter. The ingot 113 includes a constant diameter portion 145 or cylindrical "body" of the crystal that grows by increasing the pulling rate. The body 145 of the ingot 113 has a relatively constant diameter. The ingot 113 includes a tail cone or end cone (not shown) that tapers in diameter after the body 145. When the diameter becomes sufficiently small, the ingot 113 is separated from the molten metal 104.

[0023] The ingot pulling device 101 includes side heaters 135 and a susceptor 106 that surround the crucible 102 to maintain the temperature of the molten metal 104 during crystal growth. The side heaters 135 are positioned radially outward relative to the crucible sidewalls 131 as the crucible 102 moves up and down along the pulling axis A. The side heaters 135 and bottom heater 126 may be any type of heater that enables them to operate as described herein. In some embodiments, the heaters 135 and 126 are resistance heaters. The side heaters 135 and bottom heater 126 may be controlled by a control system (not shown) so that the temperature of the molten metal 104 is controlled throughout the pulling process.

[0024] The ingot lifting device 101 may include a heat shield 151. The heat shield 151 covers the ingot 113 and may be placed inside the crucible 102 during crystal growth (Figure 2).

[0025] In embodiments of the present disclosure, in a first step 100 (Figure 5), Czochralski growth conditions are selected to determine the suitability of the substrate subsequently sliced ​​for use in epitaxy. For example, the properties of the substrate obtained as a result of the formation of the epitaxial layer can be altered by changing the impurity concentration and / or dopant concentration of the crucible melt. For example, one or more of the nitrogen concentration, oxygen concentration, or boron concentration (or other dopant concentration) may be altered as further described below. In some embodiments, the concentration of the compound (e.g., oxygen, nitrogen, or boron) is changed during the growth of the segments of the body 145 of the ingot 113.

[0026] In some embodiments, the nitrogen concentration is varied. Various concentrations of nitrogen can be doped into the ingot. For example, as shown in Figure 12, the nitrogen concentration in the crystal is 1 × 10⁻⁶. 13 atoms / cm 3 ~1 × 10 15 atoms / cm 3 These may be any appropriate amounts. Nitrogen doping in the ingot follows a segregation curve, meaning that the nitrogen concentration at the start of ingot growth and the nitrogen concentration at the end of ingot growth can differ by 6 to 7 times, regardless of the initial concentration. To accommodate such nitrogen concentration differences, the ingot growth conditions may be controlled to vary the oxygen concentration towards the early, middle, and / or final stages of crystal growth, depending on the nitrogen concentration difference due to segregation. Furthermore, the oxygen and nitrogen combination may be controlled according to the quality of the epitaxial wafer and the measured scanning infrared depolarization (SIRD), for example, after a series of specially designed epitaxial and / or thermal processes that result in increased slip resistance (e.g., under a specific combination of high-temperature heat treatments while maintaining a structure free of epitaxial stacking faults).

[0027] As shown in Figure 13, the oxygen concentration may be varied (for example, increasing the oxygen concentration at the start of ingot growth compared to the conventional method, and / or decreasing the oxygen concentration at the end of ingot growth compared to the conventional method). In some embodiments, the ingot has an oxygen concentration of less than 12.5 nppma.

[0028] The boron concentration of the ingot (and the resulting substrate) may be varied (e.g., from low-doped to high-doped). For example, boron may be doped into the silicon melt to 1.0 × 10⁻⁶ 12 ~1.0×10 20 atoms / cm 3 It is possible to manufacture doped silicon ingots (and sliced ​​wafers) having boron concentrations in the range of [specified range].

[0029] Once the ingot 113 is grown, in a second step 200 (Figure 5), the ingot 113 is sliced ​​into multiple silicon substrates (i.e., wafers) for use in the fabrication of epitaxial wafers 20 (Figure 4). The substrate 1 is a single-crystal silicon wafer. Referring here to Figure 3, each substrate 1 has a front surface 3 and a back surface 9.

[0030] Once the substrate 1 is sliced ​​(for example, in the first step 100 (Figure 5)), the substrate 1 is processed (for example, sliced ​​from an ingot, followed by various processes of smoothing and / or reducing surface roughness). In the third step 300, the epitaxial layer 25 (Figure 4) is deposited on the front surface 3 (Figure 3) of the substrate 1 by bringing the front surface 3 into contact with a silicon-containing gas that decomposes to form an epitaxial silicon layer 25 on the substrate 1. Generally, unless otherwise specified, any method available to those skilled in the art can be used to deposit a silicon epitaxial layer on a silicon substrate. For example, the epitaxial layer 25 is as shown in Figure 5. 14The material can be deposited in an exemplary processing reactor 110 as shown. The reactor 110 includes a processing chamber 103 on which a single semiconductor is etched. A gas manifold 140 is used to guide the incoming gas into the processing chamber 103. The incoming processing gas flows through the gas manifold 140 into the processing chamber 103 and is discharged through a gas exhaust port. The reactor 110 includes a susceptor 121 positioned inside the processing chamber 103 to support the substrate 1. A preheating ring 127 surrounds the susceptor 121 and raises the process gas to a temperature before contacting the substrate 1. The substrate 1 is rotated to uniformly deposit an epitaxial layer on the substrate 1.

[0031] Silicon can be epitaxially grown to an appropriate thickness depending on the device application. For example, silicon can be deposited using metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atmospheric pressure chemical vapor deposition (APCVD), reduced-pressure chemical vapor deposition (RPCVD), or molecular beam epitaxy (MBE). Examples of silicon precursors (i.e., silicon-containing gases) for LPCVD or PECVD include methylsilane, silicon tetrahydrate (silane), trisilane, disilane, pentasilan, neopentasilane, tetrasilane, dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and silicon tetrachloride (SiCl4). For example, silicon can be deposited by thermal decomposition of silane (SiH4) in a temperature range between approximately 550°C and 690°C, for example, between approximately 580°C and 650°C. The chamber pressure is in the range of approximately 70 to 400 mTorr.

[0032] In some embodiments, a boron-containing gas is introduced into the reactor 110 to dop the epitaxial layer with boron. For example, B2H6 can be added to the deposition gas. The mole fraction of B2H6 in the atmosphere used to obtain the desired properties (e.g., resistivity) depends on several factors, including the amount of boron leaching and diffusion from a particular substrate during epitaxial growth, the amounts of p-type and n-type dopants present in the reactor and substrate as contaminants, and the pressure and temperature of the reactor.

[0033] Once the epitaxial layer 25 is deposited, the epitaxial wafer 20 (which may be referred to herein as the “first” epitaxial wafer) may be imaged by infrared depolarization to determine the infrared depolarization parameters of the wafer 20 (step 400 shown in Figure 5). The epitaxial wafer 20 may be imaged directly after layer deposition, or one or more post-epitographic steps may be performed (e.g., cleaning). Infrared depolarization images are available from SIRD (Scanning Infrared Depolarization) systems sold by PVA TePla America, Inc. (Corona, California) or from Semilab Semiconductor Physics Laboratory Co., Ltd. (Budapest, Hungary).

[0034] Figure 15 shows an example of a device 201 for imaging an epitaxial wafer 20. A laser 230 transmits light through a polarizing plate 240. Linearly polarized light (for example, with a wavelength of approximately 1.3 μm) is transmitted through the wafer 20 approximately perpendicular to its surface. In the illustrated device 201, the light is guided through the back surface of the wafer 20, but in other embodiments, the device 201 guides the light through the front surface. The wafer 20 is rotated while being scanned.

[0035] Analyzer 251 measures the linear state of light passing through wafer 20. Analyzer 251 measures the power of the parallel (P||) and perpendicular (P⊥) electromagnetic field components by diodes 255 and 257. Without being bound by any particular theory, it is thought that the stress field residing in wafer 20 changes the polarization state due to stress-induced birefringence. Depolarization is thought to have a linear correlation with the local stress in the volume penetrated by the laser light.

[0036] Depolarization is as follows: It can be measured as shown in TIFF0007877368000001.tif19129. Depolarization (D) is a dimensionless value ranging from 0 to 2. As depolarization (D) approaches zero, little birefringence is observed, indicating no stress at the imaged wafer site. As depolarization (D) approaches 1, circular polarization is observed. As depolarization (D) approaches 2, half-plate (complete shift of polarization) is observed. Depolarization (D) is 1DU = 10⁻¹⁰ -6 *May be expressed in depolarization units (DU) which are D. In some embodiments, depolarization contrast (DC): The global stress defined by TIFF0007877368000002.tif16130 may be used. In some embodiments, the equivalent shear stress (G) may be determined (see pages 33-39 of the PVA TePla SIRD User Manual (2007), which is incorporated herein by reference).

[0037] Depolarization may be measured on a "track" basis of the scanned surface, with each track having a number of "track points" within the track where depolarization is measured (see page 32 of the PVA TePla SIRD User Manual (2007), incorporated herein by reference). An average may be set for each track, and the percentage of track points that deviate from the average may be recorded (i.e., the "defect rate"). The track point defect rate may be based on the minimum deviation from the average depolarization of the track (±20%, ±30%, ±40%, or ±50% of the average). Resolution can be adjusted by changing the number of track points measured within a track and by track separation.

[0038] Referring now to Figure 16, in some embodiments of this disclosure, only the annular edge region 302 of the epitaxial wafer 20 is imaged by infrared depolarization in order to determine the infrared depolarization parameter. For example, the annular edge region 302 may extend from at least about 85% of the radius R of the epitaxial wafer 20 toward the circular edge 315. In other embodiments, the annular edge region 302 extends from at least about 90% or at least about 95% of the radius R of the epitaxial wafer toward the circumferential edge 315. The annular edge region 302 may terminate at the circumferential edge 315 or terminate before the edge 315. For example, the annular edge region may extend to 99.5% of the radius R or to 99.9% of the radius R. In other embodiments, the entire wafer is imaged (optionally, the edge exclusion region is not imaged) rather than only the annular edge region of the wafer 20.

[0039] The infrared depolarization parameter of wafer 20 may generally be any parameter based on the characterization of the wafer image (step 500 in Figure 5). For example, the infrared depolarization parameter may be a wafer map (e.g., an image of the wafer showing defects, stress points, failure rate track points, or other characteristics of the scan). Alternatively or additionally, the parameter may be related to the "failure rate" of the track points (e.g., failure rate fluctuation chart, average failure rate, or total failure rate). Alternatively or additionally, the parameter may be related to the depolarization value (e.g., average depolarization value or total depolarization value), depolarization contrast, or shear equivalent value.

[0040] Once the infrared depolarization parameters are determined, the suitability of the substrate to be used for epitaxy is determined. For example, the parameters may be compared to threshold parameters, and / or it may be determined whether the parameters are within the threshold range.

[0041] In some embodiments of this disclosure, two or more epitaxial wafers sliced ​​from ingots grown from melts having different impurity profiles are imaged by infrared depolarization, and the respective infrared depolarization parameters are compared to determine the suitability (e.g., strength and / or slip resistance, and optionally after downstream heat treatment) for one or more ingot growth parameters (e.g., one or more impurity profiles) for manufacturing substrates used for epitaxy. For example, to manufacture a first epitaxial wafer, after a silicon melt is formed, a seed crystal 122 is brought into contact with a melt having a first impurity profile (e.g., oxygen, nitrogen, or boron or other dopant concentrations). The seed crystal is pulled up to form a first single-crystal silicon ingot, and a first plurality of silicon substrates are sliced ​​from the single-crystal silicon ingot. An epitaxial layer is deposited on one of the silicon substrates to form a first epitaxial wafer. The first epitaxial wafer is imaged by infrared depolarization to determine a first infrared depolarization parameter.

[0042] According to embodiments of the present disclosure, a second melt having a second impurity profile (e.g., a different impurity profile, such as having different concentrations of one or more impurities) is formed (using the same or different crystal pulling apparatus, or different crystal pulling apparatus). A silicon seed crystal (the same or a different crystal as before) is brought into contact with the second silicon melt and pulled up to grow a second single-crystal silicon ingot. The second single-crystal silicon ingot is sliced ​​into a second plurality of silicon substrates. An epitaxial layer is deposited on one of the silicon substrates to form a second epitaxial wafer. The second epitaxial wafer is imaged by infrared depolarization to determine a second infrared depolarization parameter. The suitability of the first and second impurity profiles for manufacturing an epitaxial substrate may be determined based on the first and second infrared depolarization parameters.

[0043] In some embodiments, multiple wafers sliced ​​from each of the first and second ingots may be processed as described above to determine the first and second infrared depolarization parameters (for example, the depolarization parameters are averaged over each ingot). For example, the epitaxial layer may be deposited on a batch of first silicon wafers sliced ​​from a first silicon ingot, or the epitaxial layer may be deposited on a batch of second silicon wafers sliced ​​from a second silicon ingot. The epitaxial wafers of the first batch may be imaged by infrared depolarization to determine the first infrared depolarization parameter, and the epitaxial wafers of the second batch may be imaged by infrared depolarization to determine the second infrared depolarization parameter.

[0044] In some embodiments, a batch (i.e., multiple) of ingots may be grown from one or more melts having a first impurity profile, and / or a batch of ingots may be grown from one or more melts having a second impurity profile, and the resulting epitaxial wafers may be imaged by infrared depolarization to determine first and second infrared depolarization parameters. For example, a first batch of single-crystal silicon ingots is formed from a melt having a first impurity profile. A first plurality of silicon substrates is sliced ​​from two or more single-crystal silicon ingots of the first batch, and the front surfaces of the first plurality of silicon substrates are brought into contact with a silicon-containing gas to form an epitaxial wafer of the first batch. A second batch of single-crystal silicon ingots is formed from a melt having a second impurity profile. A second plurality of silicon substrates is sliced ​​from two or more single-crystal silicon ingots of the second batch. The front surfaces of the second plurality of silicon substrates are brought into contact with a silicon-containing gas. The silicon-containing gas decomposes to form an epitaxial silicon layer on the silicon substrate, creating a second batch of epitaxial wafers. Each of the first and second batches of epitaxial wafers is imaged by infrared depolarization to determine the first and second infrared depolarization parameters. For example, the depolarization parameters can be averaged over wafers sliced ​​from ingots grown from melts having the first and second impurity profiles, respectively.

[0045] In embodiments of this disclosure, the epitaxy suitability of the impurity profile (e.g., oxygen, nitrogen, boron, or other dopants or impurities) of a melt for manufacturing a substrate may be determined based on first and second infrared depolarization parameters. For example, a first infrared depolarization parameter can be compared with a second infrared depolarization parameter to determine an impurity profile suitable for epitaxial growth. Alternatively, or in addition, the first and second infrared depolarization parameters can be compared with a threshold parameter (e.g., a parameter known to indicate acceptable slip resistance of the substrate). Such a threshold parameter may be determined by determining the infrared depolarization parameter of a substrate known or found to have acceptable slip resistance in epitaxial growth. In embodiments of this disclosure, the first infrared depolarization parameter and the second infrared depolarization parameter are the same parameter.

[0046] In embodiments where two or more epitaxial wafers are imaged, the epitaxial silicon layers may be formed on each silicon substrate under the same process conditions (e.g., process time and temperature). Using identical or similar process conditions can reduce the influence of process conditions on slip performance when comparing wafers.

[0047] Next, referring to Figure 6, in some embodiments, the process 300 After the epitaxial layer is deposited, imaging is performed. 400 Prior to this, the wafer may undergo a heat treatment process 350 (for example, if multiple wafers are to be imaged, both wafers are heat-treated under the same conditions). The heat treatment process 350 may mimic a heat treatment used during downstream device manufacturing. For example, the heat treatment may include heating to a maximum of 1150°C for 6 hours or more. As shown in Figure 7, in some embodiments, a second heat treatment 375 is performed after the first heat treatment 350 (for example, heating to 1150°C for 6 hours or more). The second heat treatment 375 may be performed after the wafer has cooled after the first heat treatment.

[0048] In some embodiments, as also shown in Figure 8, a second epitaxial layer is deposited on the first epitaxial layer before the infrared depolarization image 400 (step 325). In such embodiments, two layers exist on the substrate surface (i.e., two different layers). The second epitaxial layer may be deposited under the same process conditions as the first layer, or different process conditions may be used. Optionally, a heat treatment 350 (Figure 9) may be performed after the deposition of the second epitaxial layer 325 (e.g., heating to 1150°C for 6 hours or more). Optionally, a second heat treatment 375 (Figure 10) may be performed after the first heat treatment 350. In some embodiments, the heat treatment is performed between the deposition of the first and second epitaxial layers.

[0049] Referring now to Figure 11, in some embodiments, the epitaxial layer is not deposited. Instead, two heat treatments 350, 375 are performed (for example, consecutively).

[0050] Compared to conventional methods for determining the epitaxy suitability of one or more Czochralski growth parameters for wafer manufacturing, the method of this disclosure offers several advantages. The method allows for the quantitative characterization and comparison of slip characteristics under different epitaxial processes and post-epitaxial heat treatments when evaluating various types of substrates. The characterization process is consistent for each wafer tested. Because the method is non-destructive, the tested wafers can be commercially used after imaging and characterization. In embodiments where only the edge regions of the semiconductor structure are imaged, the epitaxial wafer can be scanned in a relatively short time and / or a sharper resolution can be used without increasing imaging time. Imagery of the edge region is representative of the wafer strength because high-temperature epitaxial processes have been found to impart thermal shock due to the internal stress field primarily present at the wafer edge. Unlike other methods (e.g., surface scanning and XRT), infrared depolarization can detect internal stress and is more sensitive than other methods. Conventional methods (e.g., XRT) only produce wafer maps, which are not quantitative.

[0051] In embodiments where two epitaxial layers are grown on the substrate before imaging, slips can proliferate exponentially, thereby facilitating the visualization of slips. That's all. By using heat treatment and / or the growth of two or more epitaxial layers, it may be possible to better simulate the customer's downstream processes.

[0052] Examples The processes described herein are further illustrated by the following embodiments, which should not be taken as limiting.

[0053] Example 1: Effects of changes in molten nitrogen and oxygen on slip resistance and characterization using two epitaxial layers The Czochralski growth conditions were varied to alter the nitrogen and oxygen concentrations in the melt and the resulting single-crystal silicon ingot (300 mm). The substrate underwent two epitaxial growth processes: 8 μm and 5 μm deposition (both at a deposition temperature of 1130°C and a deposition rate of 1.8 μm / min). The epitaxial wafers were imaged using a SIRD system (PVA TePla America, Inc. (California, Colorado)) with infrared depolarization (~1.3 μm). The annular edge region from 144 mm to 149 mm (0.96% to 99.3% of the radius) of each wafer was scanned. The target defect rate was 5% (40 DU). The variation plots are shown in Figures 17 and 18.

[0054] Example 2: Characterization by two-step heat treatment without epitaxial layer deposition The Czochralski growth conditions were varied to alter the nitrogen and oxygen concentrations in the melt and the resulting single-crystal silicon ingot (300 mm). Each substrate was subjected to two heat treatments at 1100°C for 80 minutes each (without epitaxial layer deposition). These substrates were imaged using a SIRD system (PVA TePla America, Inc. (California, Colorado)) by infrared depolarization (~1.3 μm). The annular edge region from 144 mm to 149 mm (0.96% to 99.3% of the radius) of each wafer was scanned. A defect rate of 5% (40 DU) was targeted as the upper limit. [Figure] 19 As shown, two types of crystals (A and D) met the specifications, while two types of ingots (B and C) did not.

[0055] In this specification, the terms “about,” “substantially,” “essentially,” and “approximately,” when used with dimensions, concentrations, temperatures, or other physical or chemical properties or ranges of properties, mean to cover the variations that may exist in the upper and / or lower limits of the range of a property or feature, including variations resulting from, for example, rounding, measurement methods, or other statistical variations.

[0056] When describing elements or embodiments of the present disclosure, the articles “a,” “an,” “the,” and “said” are intended to mean that there is one or more elements. The terms “comprising,” “including,” “containing,” and “having” are intended to mean comprehensive and that there may be additional elements other than those listed. The use of terms indicating a particular orientation (e.g., “top,” “bottom,” “side”) is for explanatory convenience and does not require a specific orientation of the items described.

[0057] Various modifications can be made to the above-described configurations and methods without departing from the scope of this disclosure. Therefore, all matters included in the above description and shown in the accompanying drawings are intended to be illustrative and not to be construed in a restrictive sense.

Claims

1. A method for determining the suitability of Czochralski growth conditions for manufacturing a silicon substrate for epitaxy by determining the slip resistance of the substrate, A step of heating a crucible containing a first charge of silicon to form a first silicon melt within the crucible; A step of bringing a silicon seed crystal into contact with a first silicon melt, wherein the first silicon melt has a first impurity profile; The process of pulling up a silicon seed crystal to grow a first single-crystal silicon ingot; A process of slicing a first set of silicon substrates from a first single-crystal silicon ingot; A step of bringing a first silicon-containing gas into contact with the front surface of a silicon substrate among a plurality of first silicon substrates, wherein the first silicon-containing gas decomposes to form a first epitaxial silicon layer on the silicon substrate, thereby forming a first epitaxial wafer; A step of imaging a first epitaxial wafer by infrared depolarization and determining a first infrared depolarization parameter; A step of heating a crucible containing a second charge of silicon to form a second silicon melt within the crucible; A step of bringing a silicon seed crystal into contact with a second silicon melt, wherein the second silicon melt has a second impurity profile, and the first impurity profile of the first melt is different from the second impurity profile of the second melt; The process of pulling up a silicon seed crystal to grow a second single-crystal silicon ingot; A process of slicing a second set of silicon substrates from a second single-crystal silicon ingot; A step of bringing a second silicon-containing gas into contact with the front surface of a silicon substrate among a second plurality of silicon substrates, wherein the second silicon-containing gas decomposes to form a second epitaxial silicon layer on the silicon substrate, thereby forming a second epitaxial wafer; A step of imaging a second epitaxial wafer by infrared depolarization and determining a second infrared depolarization parameter, wherein the first infrared depolarization parameter and the second infrared depolarization parameter are selected from a wafer map, a defect rate fluctuation chart, an average defect rate, a total defect rate, an average depolarization value, a total depolarization value, a depolarization contrast, and a shear stress equivalent value, respectively; and, A method comprising the step of determining the suitability of a first impurity profile and a second impurity profile for manufacturing an epitaxy substrate based on first and second infrared depolarization parameters by determining the slip resistance of a substrate, wherein the crucible in which a first silicon melt is formed is part of a crystal pulling apparatus, the crystal pulling apparatus is the same as or different from a crystal pulling apparatus including a crucible in which a second silicon melt is formed, and the silicon seed crystal in contact with the first silicon melt and the silicon seed crystal in contact with the second silicon melt are the same or different silicon seed crystals.

2. The method according to claim 1, wherein the step of determining the suitability of a first impurity profile and a second impurity profile for manufacturing a substrate for epitaxy is the step of comparing a first infrared depolarization parameter and a second infrared depolarization parameter.

3. The method according to claim 2, wherein the first infrared depolarization parameter and the second infrared depolarization parameter are the same parameter.

4. The method according to claim 1, wherein the first infrared depolarization parameter and the second infrared depolarization parameter relate to the depolarization value.

5. The method according to claim 1, wherein the first impurity profile and the second impurity profile relate to the concentrations of oxygen, nitrogen, or boron in the melt.

6. A step of heat-treating the first epitaxial wafer before imaging the first epitaxial wafer; and, The method according to claim 1, further comprising the step of heat-treating the second epitaxial wafer before imaging the second epitaxial wafer.

7. The method according to claim 1, wherein a first epitaxial silicon layer is formed on silicon substrates of a first plurality of substrates for forming a first epitaxial wafer under the same process conditions as a second epitaxial silicon layer is formed on silicon substrates of a second plurality of substrates for forming a second epitaxial wafer.

8. The method according to claim 1, wherein only the annular edge regions of the first and second epitaxial wafers are imaged.

9. A process of forming an epitaxial wafer of a first batch from a first batch of multiple silicon substrates; A step of imaging each epitaxial wafer of a first batch of epitaxial wafers by infrared depolarization and determining a first infrared depolarization parameter; A step of forming a second batch of epitaxial wafers from a second batch of multiple silicon substrates; and, A step of imaging each epitaxial wafer of a second batch of epitaxial wafers by infrared depolarization and determining a second infrared depolarization parameter. The method according to claim 1, including the method described in claim 1.

10. A step of forming a first batch of single-crystal silicon ingots from a plurality of first silicon melts having a first impurity profile, wherein the first single-crystal silicon ingots are part of the first batch; A process of slicing a first batch of multiple silicon substrates from two or more single-crystal silicon ingots; A process of forming a first batch of epitaxial wafers from a first plurality of silicon substrates; A step of imaging each epitaxial wafer of a first batch of epitaxial wafers by infrared depolarization and determining a first infrared depolarization parameter; A step of forming a second batch of single-crystal silicon ingots from a plurality of second silicon melts having a second impurity profile, wherein the second single-crystal silicon ingots are part of the second batch; A process of slicing a second batch of silicon substrates from two or more single-crystal silicon ingots; A step of forming a second batch of epitaxial wafers from a second plurality of silicon substrates; and, A process of imaging each epitaxial wafer of the second batch of epitaxial wafers by infrared depolarization and determining a second infrared depolarization parameter. The method according to claim 1, including the method described in claim 1.

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