Arithmetic processing unit and arithmetic processing method

By optimizing the placement of floating-point registers and arithmetic units in the processor, the arithmetic processing unit addresses inefficiencies in transfer cycles, enhancing floating-point arithmetic efficiency and reducing pipeline risks, thus improving performance and scalability.

JP7877733B2Active Publication Date: 2026-06-23FUJITSU LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
FUJITSU LTD
Filing Date
2022-03-15
Publication Date
2026-06-23

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Abstract

To efficiently execute floating point arithmetic.SOLUTION: An arithmetic processing device 1 includes: an instruction storage section 161 that stores an arithmetic instruction; a data cache section 18 that caches an arithmetic result of the arithmetic instruction; a plurality of floating point registers 172 that is arranged on a side of the instruction storage section 161 and stores a register value for executing the arithmetic instruction transferred from the instruction storage section 161; and a plurality of floating point arithmetic units 171 that is arranged on a side of the data cache section 18 and performs floating point arithmetic on the basis of the arithmetic instruction. The number of cycles is one when the register value is transferred from the instruction storage section 161 to one or more floating point registers 172, among the plurality of floating point registers 172, arranged at positions closest in a distance to the instruction storage section 161.SELECTED DRAWING: Figure 8
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Citation Information

Patent Citations

  • Microprocessor and data processing method

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  • Arithmetic processor and processing method for arithmetic processor

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  • Arithmetic processing device, computing element, and method for controlling arithmetic processing device

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  • Pointer chasing prediction

    US20140337581A1