Semiconductor circuits, semiconductor devices, motor systems, electrical equipment, and printers

Abstract

To provide a semiconductor element capable of suppressing occurrence of latch-up at current off operation while suppressing increase in mounting area by layout improvement.SOLUTION: A semiconductor element includes: first to fourth transistor formation regions (1, 2, 3, 4) formed mutually apart on a semiconductor substrate (S1) of a first conductivity type; a first impurity region (R1) of the first conductivity type with higher impurity concentration than the semiconductor substrate and formed between the first transistor formation region (2) and the second transistor formation region (3); and a second impurity region of the first conductivity type with higher impurity concentration than the semiconductor substrate and formed between the third transistor formation region (4) and the fourth transistor formation region (1), wherein the first to fourth transistor formation regions are arranged in line along a first direction (X direction).SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The invention disclosed in this specification relates to half conductor circuits, semiconductor devices, motor systems, electrical equipment, and printers.

Background Art

[0002] Conventionally, motor drive circuits that generate drive currents for motors using bridge output stages have been used in various applications. Examples of bridge output stages provided in motor drive circuits include H-bridge output stages and three-phase bridge output stages.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a general motor drive circuit, there is a risk of unintentional latch-up during a current-off operation that switches the drive current flowing through the excitation coil of the motor from an on state to an off state.

[0005] In paragraph 0076 of Patent Document 1, as countermeasures for eliminating latch-up by layout design, (i) a layout that widens the element-to-element distance between the first-phase high-side transistor and the second-phase low-side transistor, (ii) a layout that embeds an element isolation section between the first-phase high-side transistor and the second-phase low-side transistor, and (iii) a layout that forms an n-type well to which a power supply voltage is applied and a p-type well to which a ground voltage is applied to make the second-phase low-side transistor have a floating structure are exemplified. However, the above countermeasures (i) to (iii) for eliminating latch-up have the demerit of increasing the mounting area.

[0006] A motor drive circuit disclosed herein comprises a first-phase half-bridge circuit and a second-phase half-bridge circuit. The first-phase half-bridge circuit comprises a first-phase high-side FET configured to have a first voltage applied to its first terminal, and a first-phase low-side FET configured to have the second terminal of the first-phase high-side FET connected to its first terminal, and a second voltage lower than the first voltage applied to its second terminal. The second-phase half-bridge circuit comprises a second-phase high-side FET configured to have the first voltage applied to its first terminal, and a second-phase low-side FET configured to have the second terminal of the second-phase high-side FET connected to its first terminal, and a second voltage applied to its second terminal. A first-phase low-side FET or a second-phase high-side FET is positioned between the first-phase high-side FET and the second-phase low-side FET. A second-phase low-side FET or a first-phase high-side FET is positioned between the first-phase low-side FET and the second-phase high-side FET.

[0007] A motor system disclosed herein comprises a motor and a motor drive circuit configured to drive the motor.

[0008] The electrical equipment disclosed herein comprises a motor system having the above configuration. [Effects of the Invention]

[0009] According to the motor drive circuits, motor systems, and electrical equipment disclosed herein, by optimizing the layout, it is possible to suppress the occurrence of latch-up during current-off operation while suppressing an increase in mounting area. [Brief explanation of the drawing]

[0010] [Figure 1] Figure 1 shows the configuration of a motor drive circuit according to the first embodiment. [Figure 2] Figure 2 shows the vertical structure of an N-channel FET and a P-channel FET. [Figure 3]Figure 3 shows a thyristor composed of a parasitic PNP transistor Q1 and a parasitic NPN transistor Q2. [Figure 4] Figure 4 shows a first layout example of a P-channel FET and an N-channel FET. [Figure 5] Figure 5 shows an example of a wiring pattern in the first layout example. [Figure 6] Figure 6 shows another example of the wiring pattern in the first layout example. [Figure 7] Figure 7 shows a second layout example of a P-channel FET and an N-channel FET. [Figure 8] Figure 8 shows a third layout example for P-channel and N-channel FETs. [Figure 9] Figure 9 shows a fourth layout example for P-channel and N-channel FETs. [Figure 10] Figure 10 shows the configuration of the motor drive circuit according to the second embodiment. [Figure 11] Figure 11 shows the vertical structure of an N-channel FET. [Figure 12] Figure 12 is a block diagram of the motor system. [Figure 13] Figure 13 is an external perspective view of the printer. [Figure 14] Figure 14 shows the configuration of a motor drive circuit according to a modified example. [Figure 15] Figure 15 shows example layouts for P-channel and N-channel FETs. [Modes for carrying out the invention]

[0011] <First Embodiment> Figure 1 shows the configuration of the motor drive circuit 10 (hereinafter referred to as "motor drive circuit 10") according to the first embodiment.

[0012] The motor drive circuit 10 includes a first-phase half-bridge circuit HB1 and a second-phase half-bridge circuit HB2.

[0013] The first-phase half-bridge circuit HB1 includes a P-channel type FET (Field Effect Transistor) 1 and an N-channel type FET2. The P-channel type FET1 is the first-phase high-side FET, and the N-channel type FET2 is the first-phase low-side FET.

[0014] The power supply voltage VCC is applied to the source and back gate of the P-channel type FET1.

[0015] The drain of the P-channel type FET1 is connected to the drain of the N-channel type FET2. The ground voltage is applied to the source and back gate of the N-channel type FET2. The ground voltage is a voltage lower than the power supply voltage VCC.

[0016] A parasitic diode D1 is formed in the P-channel type FET1. The anode of the parasitic diode D1 is connected to the drain of the P-channel type FET1, and the cathode of the parasitic diode D1 is connected to the source and back gate of the P-channel type FET1. A parasitic diode D2 is formed in the N-channel type FET2. The anode of the parasitic diode D2 is connected to the source and back gate of the N-channel type FET1, and the cathode of the parasitic diode D2 is connected to the drain of the N-channel type FET1.

[0017] The second-phase half-bridge circuit HB2 includes a P-channel type FET3 and an N-channel type FET4. The P-channel type FET3 is the second-phase high-side FET, and the N-channel type FET4 is the second-phase low-side FET.

[0018] The power supply voltage VCC is applied to the source and back gate of the P-channel type FET3.

[0019] The drain of the N-channel FET4 is connected to the drain of the P-channel FET3. A ground voltage is applied to the source and back gate of the N-channel FET4.

[0020] A parasitic diode D3 is formed on the P-channel FET 3. The anode of parasitic diode D3 is connected to the drain of the P-channel FET 3, and the cathode of parasitic diode D3 is connected to the source and back gate of the P-channel FET 3. A parasitic diode D4 is formed on the N-channel FET 4. The anode of parasitic diode D4 is connected to the source and back gate of the N-channel FET 4, and the cathode of parasitic diode D4 is connected to the drain of the N-channel FET 4.

[0021] Connection node N1 is the connection node between the drain of P-channel FET1 and the drain of N-channel FET2. Connection node N2 is the connection node between the drain of P-channel FET3 and the drain of N-channel FET4. A stepping motor 20 is provided between connection node N1 and connection node N2. More specifically, the stepping motor 20 comprises a first excitation coil and a second excitation coil, with the first end of the first excitation coil connected to connection node N1 and the second end of the first excitation coil connected to connection node N2.

[0022] When P-channel FET1 and N-channel FET4 are ON, and P-channel FET3 and N-channel FET2 are OFF, a drive current flows through the first excitation coil in the direction from connection node N1 to connection node N2. From this state, when P-channel FET1 and FET3 and N-channel FET2 and N-channel FET4 are turned OFF, the first excitation coil attempts to continue flowing the drive current in the direction it was previously flowing. Therefore, as shown by the dashed arrow in Figure 1, the drive current flows through a current path from the ground application terminal to the power supply voltage VCC application terminal, via parasitic diode D2, the first excitation coil, and parasitic diode D3.

[0023] Figure 2 shows the vertical structure of N-channel FET2 and P-channel FET3. Note that Figure 2 shows the parts related to parasitic diodes and parasitic transistors, while parts not related to parasitic diodes and transistors are omitted.

[0024] The N-channel FET2 and P-channel FET3 are formed on the P-type semiconductor substrate S1. The high-density P-type region R1 is also formed on the P-type semiconductor substrate S1. The high-density P-type region R1 is the terminal to which the ground voltage is applied.

[0025] The N-channel FET 2 includes an N-type region 21, a P-type region 22, a high-concentration P-type region 23, and a high-concentration N-type region 24. The high-concentration P-type region 23 is the back gate of the N-channel FET 2, and the high-concentration N-type region 24 is the drain of the N-channel FET 2.

[0026] The P-channel FET 3 includes an N-type region 31, a P-type region 32, a high-concentration P-type region 33, and a high-concentration N-type region 34. The high-concentration P-type region 33 is the drain of the P-channel FET 3, and the high-concentration N-type region 34 is the back gate of the P-channel FET 3.

[0027] A parasitic diode D2 is formed by the P-type semiconductor substrate S1, the P-type region 22, and the N-type region 21, and a parasitic diode D3 is formed by the P-type region 32 and the N-type region 31. Furthermore, a parasitic PNP transistor Q1 is formed by the P-type region 32, the N-type region 31, and the P-type semiconductor substrate S1, and a parasitic NPN transistor Q2 is formed by the N-type region 31, the P-type semiconductor substrate S1, and the N-type region 21.

[0028] When the drive current indicated by the dashed arrow in Figure 1 flows, the current indicated by the dashed arrow in Figure 2 also flows. In other words, when the drive current indicated by the dashed arrow in Figure 1 flows, current also flows through the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2. The parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 constitute a thyristor as shown in Figure 3. Therefore, if the gain of the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 is high, the thyristor formed by the parasitic PNP transistor Q1 and the parasitic NPN transistor Q2 turns on during current-off operation, causing latch-up.

[0029] On the other hand, when P-channel FET1 and N-channel FET4 are off and P-channel FET3 and N-channel FET2 are on, a drive current flows through the first excitation coil in the direction from connection node N2 to connection node N1. If P-channel FET1 and FET3 and N-channel FET2 and N-channel FET4 are turned off from this state, the first excitation coil will continue to flow the drive current in the direction it was previously flowing. Therefore, the drive current flows through a current path from the ground application terminal to the power supply voltage VCC application terminal, via parasitic diode D4, the first excitation coil, and parasitic diode D1.

[0030] Therefore, just like with the N-channel FET2 and P-channel FET3 mentioned above, latch-up will occur in P-channel FET1 and N-channel FET4 if the gain of the parasitic transistor is high.

[0031] Furthermore, the motor drive circuit 10 includes an H-bridge (first-phase half-bridge circuit HB1 and second-phase half-bridge circuit HB2) for supplying drive current to the first excitation coil of the stepping motor 20, as well as an H-bridge for supplying drive current to the second excitation coil of the stepping motor 20.

[0032] The H-bridge for supplying drive current to the second excitation coil of the stepping motor 20 has the same configuration as the H-bridge for supplying drive current to the first excitation coil of the stepping motor 20. Furthermore, each of the layout examples described later can also be applied to the H-bridge for supplying drive current to the second excitation coil of the stepping motor 20.

[0033] <Example 1 layout> Figure 4 shows a first layout example of P-channel FETs 1 and 3 and N-channel FETs 2 and 4. Figure 4 is a top view of the main part of the semiconductor chip on which the motor drive circuit 10 is mounted.

[0034] In the first layout example, the second-phase low-side FET 4 is positioned between the first-phase low-side FET, an N-channel type FET 2, and the second-phase high-side FET, a P-channel type FET 3. This allows the gains of the parasitic PNP transistor Q1 and parasitic NPN transistor Q2 shown in Figure 2 to be reduced without creating dead space as described in Patent Document 1.

[0035] In the first layout example, an N-channel FET 2, which is a first-phase low-side FET, is placed between a P-channel FET 1, which is a first-phase high-side FET, and an N-channel FET 4, which is a second-phase low-side FET. This makes it possible to reduce the gain of parasitic transistors without creating dead space as described in Patent Document 1.

[0036] Therefore, according to the first layout example, it is possible to suppress latch-up during current-off operation while suppressing an increase in mounting area.

[0037] Furthermore, in the first layout example and the fourth layout described later, unlike the second and third layout examples described later, the P-channel FET1, which is the first-phase high-side FET, and the N-channel FET2, which is the first-phase low-side FET, are adjacent to each other. Therefore, it is not necessary to run a wiring pattern connecting the drain of the P-channel FET1 and the drain of the N-channel FET2. Similarly, in the first layout example and the fourth layout described later, unlike the second and third layout examples described later, the P-channel FET3, which is the second-phase high-side FET, and the N-channel FET4, which is the second-phase low-side FET, are adjacent to each other. Therefore, it is not necessary to run a wiring pattern connecting the drain of the P-channel FET3 and the drain of the N-channel FET4.

[0038] Furthermore, for each of the P-channel FETs 1 and 3 and N-channel FETs 2 and 4, it is desirable that the length W1 in the direction in which the P-channel FETs 1 and 3 and N-channel FETs 2 and 4 are aligned (X direction) is shorter than the length L1 in the direction perpendicular to the X direction and the thickness direction of the substrate (P-type semiconductor substrate S1 in this embodiment) on which the P-channel FETs 1 and 3 and N-channel FETs 2 and 4 are formed (Y direction). This prevents the mounting area of ​​the P-channel FETs 1 and 3 and N-channel FETs 2 and 4 from becoming extremely elongated in the X direction. The lengths W1 of each of the P-channel FETs 1 and 3 and N-channel FETs 2 and 4 may all be the same, or at least one may be different from the others. Similarly, the lengths L1 of each of the P-channel FETs 1 and 3 and N-channel FETs 2 and 4 may all be the same, or at least one may be different from the others. The thickness direction of the substrate described above can be defined, for example, as the direction perpendicular to the surface on which the impurity regions (P-type regions, N-type regions) formed on the substrate are exposed to the outside of the substrate.

[0039] Figure 5 shows an example of a wiring pattern in the first layout example. Figure 6 shows another example of a wiring pattern in the first layout example.

[0040] The first conductor portion C1 is connected to the source 1A of the P-channel FET 1 and the source 3A of the P-channel FET 3. The first conductor portion C1 is separated into a first region connected to the source 1A of the P-channel FET 1 and a second region connected to the source 3A of the P-channel FET 3, but the first region and the second region are electrically connected to each other by a connecting wiring pattern (not shown). This connecting wiring pattern is located, for example, on one side in the Y direction from the first and second regions or on the other side in the Y direction from the first and second regions, and extends along the X direction. The second conductor portion C2 is connected to the drain 1B of the P-channel FET 1 and the drain 2A of the N-channel FET 2. The third conductor portion C3 is connected to the source 2B of the N-channel FET 2 and the source 4B of the N-channel FET 4. The fourth conductor portion C4 is connected to the drain 3B of the P-channel FET 3 and the drain 4A of the N-channel FET 4.

[0041] In the example shown in Figure 5, the first to fourth conductive portions C1 to C4 do not overlap when viewed from a direction (Y direction) perpendicular to the thickness direction of the substrate on which the P-channel FETs 1 and 3 and N-channel FETs 2 and 4 are formed (P-type semiconductor substrate S1 in this embodiment). This wiring pattern makes it easy to arrange the source and drain of each FET along the X direction.

[0042] In the example shown in Figure 6, when viewed from the Y direction, the second conductor portion C2 overlaps with the first conductor portion C1 and the third conductor portion C3, the fourth conductor portion C4 overlaps with the first conductor portion C1 and the third conductor portion C3, and the second conductor portion C2 and the fourth conductor portion C4 do not overlap each other. This wiring pattern makes it easy to arrange the source and drain of each FET along the Y direction.

[0043] <Examples of layouts 2-4> Figures 7 to 9 show examples of the second to fourth layouts of P-channel FETs 1 and 3 and N-channel FETs 2 and 4.

[0044] In the second layout example shown in Figure 7, a P-channel FET 3, which is a second-phase high-side FET, is positioned between a P-channel FET 1, which is a first-phase high-side FET, and an N-channel FET 4, which is a second-phase low-side FET.

[0045] Furthermore, an N-channel FET 4, which is the second-phase low-side FET, is positioned between the N-channel FET 2, which is the first-phase low-side FET, and the P-channel FET 3, which is the second-phase high-side FET.

[0046] According to the second layout example, similar to the first layout example, it is possible to suppress latch-up during current-off operation while suppressing an increase in mounting area.

[0047] In the third layout example shown in Figure 8, an N-channel FET 2, which is a first-phase low-side FET, is positioned between a P-channel FET 1, which is a first-phase high-side FET, and an N-channel FET 4, which is a second-phase low-side FET.

[0048] Furthermore, in the third layout example shown in Figure 8, the P-channel FET 1, which is the first-phase high-side FET, is positioned between the N-channel FET 2, which is the first-phase low-side FET, and the P-channel FET 3, which is the second-phase high-side FET.

[0049] According to the third layout example, similar to the first layout example, it is possible to suppress latch-up during current-off operation while suppressing an increase in mounting area.

[0050] In the fourth layout example shown in Figure 9, a P-channel FET 3, which is a second-phase high-side FET, is positioned between a P-channel FET 1, which is a first-phase high-side FET, and an N-channel FET 4, which is a second-phase low-side FET.

[0051] Furthermore, in the fourth layout example shown in Figure 9, the P-channel FET 1, which is the first-phase high-side FET, is positioned between the N-channel FET 2, which is the first-phase low-side FET, and the P-channel FET 3, which is the second-phase high-side FET.

[0052] According to the fourth layout example, similar to the first layout example, it is possible to suppress latch-up during current-off operation while suppressing an increase in mounting area.

[0053] <Second Embodiment> Figure 10 shows the configuration of the motor drive circuit 10' (hereinafter referred to as "motor drive circuit 10'") according to the second embodiment.

[0054] The motor drive circuit 10' differs from the motor drive circuit 10 in that it uses an N-channel FET 1' as the first-phase high-side FET and an N-channel FET 3' as the second-phase high-side FET, but is otherwise the same as the motor drive circuit 10.

[0055] Figure 11 shows the longitudinal structure of N-channel FETs 2 and 3'. Note that Figure 11 shows the parts related to parasitic diodes and parasitic transistors, while parts not related to parasitic diodes and transistors are omitted.

[0056] In the motor drive circuit 10', parasitic transistors similar to those in the motor drive circuit 10 are formed, so by using the same layout of each FET as in the motor drive circuit 10, it is possible to suppress the increase in mounting area while suppressing latch-up during current-off operation.

[0057] <Motor System> Figure 12 is a block diagram of the motor system. The motor system 100 shown in Figure 12 comprises a stepping motor 20, a motor drive circuit 10 configured to drive the stepping motor 20, and a control unit 30 configured to control the switching of each FET in the motor drive circuit 10. Of course, a motor drive circuit 10' may be used instead of the motor drive circuit 10.

[0058] <Electrical Equipment> The motor system 100 described above is incorporated into, for example, the printer 200 shown in Figure 13 and used as part of the paper feeding mechanism. Of course, the motor system 100 may also be installed in electrical equipment other than printers.

[0059] <Points to note> The configuration of the present invention can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the invention. The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention is indicated by the claims, not by the description of the embodiments described above, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0060] In the embodiment described above, the motor drive circuit drove a stepping motor equipped with a first excitation coil and a second excitation coil, but the motor drive circuit may drive a motor other than a stepping motor.

[0061] The modified motor drive circuit 10'' shown in Figure 14 drives a three-phase brushless motor 40. In addition to the first-phase half-bridge circuit HB1 and the second-phase half-bridge circuit HB2, the modified motor drive circuit 10'' includes a third-phase half-bridge circuit HB3. The third-phase half-bridge circuit HB3 includes a P-channel FET 5 and an N-channel FET 6. The P-channel FET 5 is a third-phase high-side FET, and the N-channel FET 6 is a third-phase low-side FET.

[0062] A parasitic diode D5 is formed in the P-channel FET 5. A parasitic diode D6 is formed in the N-channel FET 6.

[0063] In the modified motor drive circuit 10'', for example, as shown in Figure 15, the arrangement of the first phase high-side FET, first phase low-side FET, second phase high-side FET, and second phase low-side FET is the same as in the first layout example described above, and furthermore, a third phase high-side FET, a P-channel type FET 5, is placed between the second phase high-side FET, a P-channel type FET 3, and the third phase low-side FET, an N-channel type FET 6.

[0064] The motor drive circuit (10, 10', 10") described above comprises a first-phase half-bridge circuit (HB1) and a second-phase half-bridge circuit (HB2), wherein the first-phase half-bridge circuit comprises a first-phase high-side FET (1, 1') configured such that a first voltage is applied to its first terminal, and a first-phase low-side FET (2) whose first terminal is connected to the second terminal of the first-phase high-side FET and which is configured such that a second voltage lower than the first voltage is applied to its second terminal, and the second-phase half-bridge circuit comprises a first-phase high-side FET (1, 1') configured such that a first voltage is applied to its first terminal The device comprises a second-phase high-side FET (3, 3') and a second-phase low-side FET (4) configured such that the second terminal of the second-phase high-side FET is connected to the first terminal of the second-phase high-side FET and the second voltage is applied to the second terminal, wherein the first-phase low-side FET or the second-phase high-side FET is positioned between the first-phase high-side FET and the second-phase low-side FET, and the second-phase low-side FET or the first-phase high-side FET is positioned between the first-phase low-side FET and the second-phase high-side FET (first configuration).

[0065] The motor drive circuit, which is the first configuration described above, can suppress latch-up during current-off operation while suppressing an increase in mounting area.

[0066] In the motor drive circuit having the first configuration described above, the first phase low-side FET may be positioned between the first phase high-side FET and the second phase low-side FET (second configuration).

[0067] In the motor drive circuit, which is the second configuration described above, there is no need to run a wiring pattern connecting the drain of the first phase high-side FET and the drain of the first phase low-side FET, and there is no need to run a wiring pattern connecting the drain of the second phase high-side FET and the drain of the second phase low-side FET.

[0068] In the motor drive circuit having the second configuration described above, the first conductor portion is configured to be connected to the first end of the first phase high-side FET and the first end of the second phase high-side FET; the second conductor portion is configured to be connected to the second end of the first phase high-side FET and the first end of the first phase low-side FET; the third conductor portion is configured to be connected to the second end of the first phase low-side FET and the second end of the second phase low-side FET; and the fourth conductor portion is configured to be connected to the second end of the second phase high-side FET and the first end of the second phase low-side FET. The first conductor portion, the second conductor portion, the third conductor portion, and the fourth conductor portion may be configured not to overlap when viewed from a direction perpendicular to the direction in which the first phase high-side FET, the first phase low-side FET, the second phase low-side FET, and the second phase high-side FET are arranged and the thickness direction of the substrate on which the first phase high-side FET, the first phase low-side FET, the second phase low-side FET, and the second phase high-side FET are formed (third configuration).

[0069] In the third configuration of the motor drive circuit described above, it becomes easy to arrange the first and second ends of each FET along the direction in which the FETs are aligned.

[0070] In the motor drive circuit having the second configuration described above, the following components are included: a first conductive portion configured to be connected to the first end of the first phase high-side FET and the first end of the second phase high-side FET; a second conductive portion configured to be connected to the second end of the first phase high-side FET and the first end of the first phase low-side FET; a third conductive portion configured to be connected to the second end of the first phase low-side FET and the second end of the second phase low-side FET; and a fourth conductive portion configured to be connected to the second end of the second phase high-side FET and the first end of the second phase low-side FET. Alternatively, when viewed from a direction perpendicular to the direction in which the first phase high-side FET, the first phase low-side FET, the second phase low-side FET, and the second phase high-side FET are arranged, and from a direction perpendicular to the thickness direction of the substrate on which the first phase high-side FET, the first phase low-side FET, the second phase low-side FET, and the second phase high-side FET are formed, the second conductor portion may overlap with the first conductor portion and the third conductor portion, the fourth conductor portion may overlap with the first conductor portion and the third conductor portion, and the second conductor portion and the fourth conductor portion may not overlap with each other (fourth configuration).

[0071] In the motor drive circuit, which is the fourth configuration described above, it becomes easy to arrange the first and second ends of each FET in a direction perpendicular to the direction in which the FETs are aligned.

[0072] In a motor drive circuit having any of the first to fourth configurations described above, the length in the direction in which the first phase high-side FET, the first phase low-side FET, the second phase high-side FET, and the second phase low-side FET are aligned may be shorter than the length in the direction perpendicular to the thickness direction of the substrate on which the first phase high-side FET, the first phase low-side FET, the second phase high-side FET, and the second phase low-side FET are aligned (fifth configuration).

[0073] The motor drive circuit, which is the fifth configuration described above, can suppress the mounting regions of the first phase high-side FET, first phase low-side FET, second phase high-side FET, and second phase low-side FET from becoming extremely elongated in the direction in which the first phase high-side FET, first phase low-side FET, second phase high-side FET, and second phase low-side FET are aligned.

[0074] The motor system (100) described above comprises a motor (20) and a motor drive circuit which is one of the first to fifth configurations described above and is configured to drive the motor (sixth configuration).

[0075] The motor system, which is the sixth configuration described above, can suppress the increase in the mounting area of ​​the motor drive circuit while suppressing the occurrence of latch-up during current-off operation.

[0076] The electrical equipment (200) described above has a configuration that includes a motor system, which is the sixth configuration (seventh configuration).

[0077] The seventh configuration of the electrical equipment described above can suppress the increase in the mounting area of ​​the motor drive circuit while suppressing the occurrence of latch-up during current-off operation. [Explanation of symbols]

[0078] 1. P-channel FETs Source of 1A, 3A P-channel FET Drain of 1B and 3B P-channel FETs 2, 4, 1', 3' N-channel FETs Drain of 2A, 2A N-channel FET Source of 2B and 2B N-channel FETs 10 Motor drive circuit according to the first embodiment 10' Motor drive circuit according to the second embodiment 20 Stepping motors 21, 31 N-type region 22, 32 P-type region 23, 33 Highly concentrated P-type region 24, 34 Highly concentrated N-type region 30 Control Unit 40 Three-phase brushless motors 100 Motor System 200 printers C1~C4 1st~4th conductor part D1~D4 Parasitic Diodes HB1~HB3 Phase 1~Phase 3 Half-Bridge Circuit Q1 Parasitic PNP transistor Q2 Parasitic NPN transistor R1 High concentration P type region S1 P-type semiconductor substrate

Claims

1. comprising a first-phase half-bridge circuit and a second-phase half-bridge circuit, The first phase half-bridge circuit and the second phase half-bridge circuit are composed of semiconductor elements. The aforementioned semiconductor device is First to fourth transistor formation regions are formed spaced apart from each other on a semiconductor substrate of the first conductivity type, A first impurity region of a first conductivity type is formed between the first transistor formation region and the second transistor formation region and has a higher impurity concentration than the semiconductor substrate, It includes a second impurity region of a first conductivity type formed between the third transistor formation region and the fourth transistor formation region, and having a higher impurity concentration than the semiconductor substrate, The first to fourth transistor formation regions are arranged in a line in the first direction, Either the third transistor formation region or the fourth transistor formation region is located between the first transistor formation region and the second transistor formation region. The first impurity region and the second impurity region are the application terminals of the ground voltage. Each of the first to fourth transistor formation regions includes a second region of the second conductivity type and a first region of the first conductivity type formed within the second region. The first phase half-bridge circuit is composed of FETs formed in the first transistor formation region and the fourth transistor formation region, and the second phase half-bridge circuit is composed of FETs formed in the second transistor formation region and the third transistor formation region. The aforementioned semiconductor device is The first electrode is formed on the second region of each of the first to fourth transistor formation regions, and the second electrode is formed on the first region. The first electrode of the second transistor formation region is configured to be connectable to the first end of the load, and the second electrode of the first transistor formation region is configured to be connectable to the second end of the load. The first electrode of the third transistor formation region is configured to be connectable to the first end of the load, and the second electrode of the fourth transistor formation region is configured to be connectable to the second end of the load. The second electrode of the second transistor formation region is the terminal to which the power supply voltage is applied, and the first electrode of the first transistor formation region is the terminal to which the ground voltage is applied. A semiconductor circuit in which the second electrode of the third transistor formation region is the terminal to which the power supply voltage is applied, and the first electrode of the fourth transistor formation region is the terminal to which the ground voltage is applied.

2. Control unit and The semiconductor circuit according to claim 1, which is configured to be controlled by the control unit, A semiconductor device equipped with the following features.

3. Motor and, The semiconductor device according to claim 2, configured to drive the motor, A motor system equipped with the following features.

4. An electrical device comprising the motor system described in claim 3.

5. A printer comprising the motor system described in claim 3.

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