Electrode structure, display panel, and electronic equipment

Abstract

The embodiments of the present disclosure relate to an electrode structure, a display panel, and an electronic device. The electrode structure includes a first electrode portion (20) and a second electrode portion (21) arranged at an interval in a first direction (Y), and a conductive connection portion (22) located between the first electrode portion (20) and the second electrode portion (21). The first electrode portion (20) includes a first connection strip (201) extending in the first direction (Y) and a plurality of first electrode strips (202) arranged at an interval in the first direction (Y). The first connection strip (201) has a first side (20) facing a second direction (X). The second electrode portion (21) has a first side (201a) and a second side (201b), the plurality of first electrode strips (202) are located on a first side (201a) of the first connecting strip (201) and are connected to the first connecting strip (201), and ends of adjacent first electrode strips (202) that are away from the first connecting strip (201) are open, and the second electrode portion (21) has a second connecting strip (211) extending in the first direction (Y) and a plurality of second connecting strips (211) arranged at intervals in the first direction (Y). The second connecting strip (211) is located at a position away from the second side (201b) of the first side (201a), the second connecting strip (211) has a third side (211a) and a fourth side (211b) facing the second direction (X), the third side (211a) is located at a position closer to the first side (201a) of the fourth side (211b), and the plurality of second electrode strips (212) are disposed on the third side (211a) of the second connecting strip (211). and connected to the second connecting strip (211), an end portion between adjacent second electrode strips (212) away from the second connecting strip (211) is open, and both ends of the conductive connecting portion (22) are respectively connected to the first connecting strip (201) and the second connecting strip (211), the design of the electrode structure can improve the light efficiency around the electrode structure, and further improve the quality of the display panel when the electrode structure is used in a display panel.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202110041652.X filed on January 13, 2021, the priority of PCT International Application No. PCT / CN2021 / 083044 filed on March 25, 2021, and the priority of PCT International Application No. PCT / CN2021 / 085622 filed on April 6, 2021, and the entire contents disclosed in the above Chinese patent application and PCT international application are incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to the display technology field, specifically to electrode structures, display panels, and electronic devices.

Background Art

[0003] With the continuous development of liquid crystal display panels, high-resolution products have been continuously developed. However, with the increase in pixels, a series of problems are likely to occur. For example, when a pressure test or a drop test is performed on a liquid crystal display panel, problems such as luminance non-uniformity like bright spots and snow are likely to occur. In addition, the electrode structure of a liquid crystal display panel is easily affected by impurity particles (Partical) during the manufacturing process, and problems such as open circuits are likely to occur, thereby causing pixel defects, further reducing the yield of the liquid crystal display panel, and affecting the reliability of the liquid crystal display panel and the quality of the product.

Summary of the Invention

Means for Solving the Problems

[0004] Embodiments of the present disclosure provide an electrode structure, a display panel, and an electronic device. By respectively designing the first electrode portion and the second electrode portion of the electrode structure to have semi-open first slits and second slits, the deflection of liquid crystal molecules can also be generated at the opening positions of the first slits and the second slits. And by making the first slits and the second slits in a semi-open state, the light efficiency around the electrode structure can be further improved, and at least some of one or more problems caused by the limitations and defects of the related art can be solved.

[0005] At least one embodiment of the present disclosure provides a display panel comprising a cellular array substrate and a counter substrate, the array substrate comprising a first base and scan lines, data lines, a first obstruction wall and a second obstruction wall formed on one side of the first base closer to the counter substrate, the data lines extending in a first direction and the scan lines extending in a second direction, the first direction intersecting the second direction, the first obstruction wall and the second obstruction wall each located on opposite sides of the scan lines in the first direction, the first obstruction wall and the second obstruction wall each comprising a first obstruction layer located in the same layer as the scan lines and spaced apart from each other, and a second obstruction layer located in the same layer as the data lines and spaced apart from each other, the first base of the second obstruction wall The orthographic projection on the first base of the first inhibiting layer is superimposed on the orthographic projection on the first base of the first inhibiting layer, the distance between the first inhibiting layer and the scan line in the first direction is defined as the first interval, and the distance between the second inhibiting layer and the scan line in the first direction is defined as the second interval, the second interval being larger than the first interval, the opposing substrate includes a second base and a spacer located on one side of the second base closer to the array substrate, the surface of the spacer closer to the first base is defined as the top surface, the orthographic projection of the top surface of the spacer on the first base is located within the orthographic projection of the scan line on the first base and between the orthographic projections of the first inhibiting wall and the second inhibiting wall on the first base, and the size of the top surface of the spacer in the first direction is larger than the first interval.

[0006] For example, in a display panel according to at least one embodiment of the present disclosure, the ratio of the size of the top surface of the spacer in the first direction to the first spacing is 2 or more.

[0007] For example, in a display panel according to at least one embodiment of the present disclosure, the distance between the second inhibitory layer and the spacer in the first direction is defined as the third distance, and the ratio of the third distance to the size of the top surface of the spacer in the first direction is 0.5 or more.

[0008] For example, in a display panel according to at least one embodiment of the present disclosure, the ratio of the third interval to the size of the top surface of the spacer in the first direction is 1 or more.

[0009] For example, in a display panel according to at least one embodiment of the present disclosure, the ratio of the third interval to the size of the data line in the second direction is 2 to 4.

[0010] For example, in a display panel according to at least one embodiment of the present disclosure, the orthographic projection of the second inhibitory layer at the first base lies within the orthographic projection of the first inhibitory layer at the first base, and the first direction is perpendicular to the second direction.

[0011] For example, in a display panel according to at least one embodiment of the present disclosure, the array substrate further includes a first common line formed on the first base and extending in the second direction, the first common line being located in the same layer as the scan lines and spaced apart from each other, and the first inhibiting layer of the second inhibiting wall being a part of the structure of the first common line.

[0012] For example, in a display panel according to at least one embodiment of the present disclosure, the array substrate further includes a plurality of subpixel units arranged in an array on a first base in the second and first directions, each of which includes a pixel electrode, a common electrode, and a transistor, the transistor including a gate, a first pole, and a second pole, the gate being connected to the scan line, the first pole being connected to the pixel electrode, the second pole being connected to the data line, the orthographic projection of the common electrode on the first base being superimposed on the orthographic projection of the pixel electrode on the first base, and the common electrode being connected to a first common line.

[0013] For example, in a display panel according to at least one embodiment of the present disclosure, the pixel electrode is located on one side of the common electrode away from the first base, the pixel electrode includes a first electrode portion, a second electrode portion, and a conductive connection portion, the first electrode portion includes a first connection strip extending in the first direction, and a plurality of first electrode strips spaced apart in the first direction, the first connection strip has a first side and a second side facing the second direction, the plurality of first electrode strips are located on the first side of the first connection strip and connected to the first connection strip, and there is an opening between the ends of adjacent first electrode strips away from the first connection strip, the second electrode portion is spaced apart from the first electrode portion in the first direction, and the second electrode portion includes a second connection strip extending in the first direction The electrode portion includes a first electrode portion and a plurality of second electrode strips spaced apart in the first direction, wherein the second connection strip is located away from the second side on the first side, and the second connection strip has a third side and a fourth side facing the second direction, the third side being located closer to the first side on the fourth side, the plurality of second electrode strips are located on the third side of the second connection strip and connected to the second connection strip, and there is an opening between the ends of adjacent second electrode strips away from the second connection strip, the conductive connection portion is located between the first electrode portion and the second electrode portion, both ends of the conductive connection portion are connected to the first connection strip and the second connection strip, respectively, and the area of ​​the conductive connection portion is larger than the area of ​​the first electrode strip and the area of ​​the second electrode strip.

[0014] For example, in a display panel according to at least one embodiment of the present disclosure, the conductive connection portion includes a first conductive connection strip and a second conductive connection strip, which are spaced apart in the second direction and both extend in the first direction, and at least two third conductive connection strips, which are located between the first conductive connection strip and the second conductive connection strip and are spaced apart in the first direction, with both ends of each third conductive connection strip connected to the first conductive connection strip and the second conductive connection strip, respectively, the first conductive connection strip being connected to the first connection strip, and the second conductive connection strip being connected to the second connection strip.

[0015] For example, in a display panel according to at least one embodiment of the present disclosure, the first electrode strip, the second electrode strip, and the third conductive connection strip all extend in a third direction, the first widths of the first electrode strip, the second electrode strip, and the third conductive connection strip are equal, the first width is the size in a fourth direction, the third direction is perpendicular to the fourth direction, and the third direction intersects the first and second directions.

[0016] For example, in a display panel according to at least one embodiment of the present disclosure, the array substrate further includes a second common line, which is located on the same layer as the data line and is spaced apart from each other, the second common line extending in the first direction, and both ends of the second common line are connected via a first via-hole structure to the common electrode of two adjacent subpixel units in the first direction.

[0017] For example, in a display panel according to at least one embodiment of the present disclosure, the first via hole structure includes a first via hole section, a second via hole section, and a via hole connection section, wherein the via hole connection section is installed on the same layer as the pixel electrode and is spaced apart from each other, the via hole connection section is connected to the second common line via the first via hole section, and the via hole connection section is connected to the common electrode via the second via hole section.

[0018] At least one embodiment of the present disclosure further provides an electronic device, which includes a display panel of any of the above embodiments.

[0019] At least one embodiment of the present disclosure further provides an electrode structure comprising a first electrode portion and a second electrode portion spaced apart in a first direction, and a conductive connection portion located between the first electrode portion and the second electrode portion, wherein the first electrode portion comprises a first connection strip extending in the first direction, and a plurality of first electrode strips spaced apart in the first direction, the first connection strip having a first side and a second side facing each other in a second direction, the plurality of first electrode strips located on the first side of the first connection strip and connected to the first connection strip, with an opening between the ends of adjacent first electrode strips away from the first connection strip, and the second electrode The portion includes a second connecting strip extending in the first direction, and a plurality of second electrode strips spaced apart in the first direction, wherein the second connecting strip is located on the first side away from the second side, and the second connecting strip has a third side and a fourth side facing each other in the second direction, the third side being located on the fourth side closer to the first side, the plurality of second electrode strips are located on the third side of the second connecting strip and connected to the second connecting strip, the ends of adjacent second electrode strips away from the second connecting strip are open, and both ends of the conductive connection portion are connected to the first connecting strip and the second connecting strip, respectively.

[0020] For example, in an electrode structure according to at least one embodiment of the present disclosure, the area of ​​the conductive connection portion is larger than the area of ​​the first electrode strip and larger than the area of ​​the second electrode strip.

[0021] For example, in an electrode structure according to at least one embodiment of the present disclosure, the area of ​​the first electrode portion and the area of ​​the second electrode portion are both larger than the area of ​​the conductive connection portion.

[0022] For example, in an electrode structure according to at least one embodiment of the present disclosure, the conductive connection portion includes a first conductive connection strip and a second conductive connection strip, which are spaced apart in the second direction and both extend in the first direction, and at least two third conductive connection strips, which are located between the first conductive connection strip and the second conductive connection strip and are spaced apart in the first direction, with both ends of each third conductive connection strip connected to the first conductive connection strip and the second conductive connection strip, respectively, the first conductive connection strip being connected to the first connection strip, and the second conductive connection strip being connected to the second connection strip.

[0023] For example, in an electrode structure according to at least one embodiment of the present disclosure, the first electrode strip, the second electrode strip, and the third conductive connection strip all extend in a third direction, and the first widths of the first electrode strip, the second electrode strip, and the third conductive connection strip are equal in a fourth direction, the third direction is perpendicular to the fourth direction, and the third direction intersects the first and second directions.

[0024] For example, in an electrode structure according to at least one embodiment of the present disclosure, the ends of adjacent first electrode strips that are away from the first connecting strip are not connected, and the ends of adjacent second electrode strips that are away from the second connecting strip are not connected.

[0025] For example, in an electrode structure according to at least one embodiment of the present disclosure, there is a first slit between adjacent first electrode strips, the stretching direction of the first electrode strips and the first slit is the same, the first slit is semi-open, there is a second slit between adjacent second electrode strips, the stretching direction of the second electrode strips and the second slit is the same, the second slit is semi-open, and the opening directions of the first slit and the second slit are opposite.

[0026] For example, in the electrode structure according to at least one embodiment of the present disclosure, the first width of the first electrode strip and the second electrode strip in the fourth direction is equal, and the first width of the first slit in the fourth direction is equal to the first width of the second slit in the fourth direction.

[0027] For example, in the electrode structure according to at least one embodiment of the present disclosure, the first width of the first slit in the fourth direction is 1 to 4 times the first width of the first electrode strip in the fourth direction.

[0028] For example, in the electrode structure according to at least one embodiment of the present disclosure, the first width of the first electrode strip and the second electrode strip in the fourth direction are both 1.8 μm to 3 μm, and the first width of the first slit and the second slit in the fourth direction are both 3 μm to 7 μm.

[0029] For example, in the electrode structure according to at least one embodiment of the present disclosure, there is a third slit between adjacent third conductive connection strips, and the periphery of the third slit is closed.

[0030] For example, in the electrode structure according to at least one embodiment of the present disclosure, the conductive connection portion includes a plurality of the third slits.

[0031] For example, in the electrode structure according to at least one embodiment of the present disclosure, the first width of the third conductive connection strip in the fourth direction is equal to the first width of the first electrode strip in the fourth direction, and the first widths of the third slit, the first slit, and the second slit in the fourth direction are equal.

[0032] For example, in an electrode structure according to at least one embodiment of the present disclosure, there is a fourth slit between the third conductive connection strip and the adjacent first electrode strip, and there is a fifth slit between the third conductive connection strip and the adjacent second electrode strip, and the first widths of the first slit, second slit, third slit, fourth slit and fifth slit in the fourth direction are equal.

[0033] For example, in an electrode structure according to at least one embodiment of the present disclosure, the first width of the first electrode strip in the fourth direction and the first width of the second electrode strip in the fourth direction are smaller than the first width of the entire conductive connection portion in the fourth direction.

[0034] For example, in an electrode structure according to at least one embodiment of the present disclosure, the second width of the first connecting strip in the second direction is equal to the second width of the second connecting strip in the second direction, and the second widths of the first and second connecting strips in the second direction are equal to or greater than the first width of the first and second electrode strips in the fourth direction.

[0035] For example, in an electrode structure according to at least one embodiment of the present disclosure, the length of the first conductive connection strip in the first direction and the length of the second conductive connection strip in the first direction are both smaller than the length of the first connection strip in the first direction and smaller than the length of the second connection strip in the first direction.

[0036] For example, in an electrode structure according to at least one embodiment of the present disclosure, the length of the first connecting strip in the first direction is smaller than the length of the second connecting strip in the first direction.

[0037] For example, in an electrode structure according to at least one embodiment of the present disclosure, the ratio of the length of the first connecting strip in the first direction to the length of the second connecting strip in the first direction is 0.1 to 0.9.

[0038] For example, in an electrode structure according to at least one embodiment of the present disclosure, the entire structure connecting the first connecting strip, the conductive connection portion, and the second connecting strip is bent, one end of the first connecting strip is connected to one end of the conductive connection portion, the other end of the conductive connection portion is connected to one end of the second connecting strip, and the first connecting strip and the second connecting strip are located on opposite sides of the conductive connection portion in the second direction.

[0039] For example, in an electrode structure according to at least one embodiment of the present disclosure, the second width of the first conductive connection strip in the second direction is equal to the second width of the first connection strip in the second direction, and the second width of the second conductive connection strip in the second direction is equal to the second width of the second connection strip in the second direction.

[0040] For example, in an electrode structure according to at least one embodiment of the present disclosure, the conductive connection portion includes a conductive connection strip, the conductive connection strip extends in a third direction, and the third direction intersects the first and second directions.

[0041] For example, in an electrode structure according to at least one embodiment of the present disclosure, the third direction is perpendicular to the fourth direction, and the ratio of the first width of the conductive connection strip in the fourth direction to the first width of the first electrode strip in the fourth direction is 1.5 to 5.5.

[0042] For example, in an electrode structure according to at least one embodiment of the present disclosure, the first width of the conductive connection strip in the fourth direction is 5 μm to 10 μm, and the first width of the first electrode strip in the fourth direction is 1.8 μm to 3 μm.

[0043] For example, in an electrode structure according to at least one embodiment of the present disclosure, the second width of the first connecting strip in the second direction and the second width of the second connecting strip in the second direction are both 2.3 μm to 2.7 μm, the first width of the conductive connecting strip in the fourth direction is 2.5 μm to 3.0 μm, and the first width of the first electrode strip and the second electrode strip in the fourth direction are both 1.8 μm to 2.6 μm.

[0044] For example, in an electrode structure according to at least one embodiment of the present disclosure, the second electrode portion further includes a signal connection portion, the signal connection portion is located on one side of the plurality of second electrode strips away from the conductive connection portion and is connected to the second connection strip.

[0045] For example, in an electrode structure according to at least one embodiment of the present disclosure, the first connecting strip and the second electrode strip are arranged mirror images with respect to the second direction.

[0046] Other characteristics and advantages of this disclosure will be revealed by the following detailed description or will be acquired in part by the practice of this disclosure.

[0047] It should be understood that the above general statements and the detailed statements below are illustrative and interpretive and do not limit this disclosure.

[0048] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings of the embodiments are briefly introduced below, and as will be apparent, the drawings described below relate only to some embodiments of this disclosure and do not limit this disclosure. [Brief explanation of the drawing]

[0049] [Figure 1] Figure 1 is a schematic planar diagram of the electrode structure. [Figure 2] Figure 2 is a schematic plan view of an electrode structure according to one embodiment of the present disclosure. [Figure 3]Figure 3 is a schematic plan view of another electrode structure according to one embodiment of the present disclosure. [Figure 4] Figure 4 is a schematic diagram of the local cross-sectional structure of a display panel according to one embodiment of the present disclosure. [Figure 5] Figure 5 is a schematic plan view of a display panel according to one embodiment of the present disclosure. [Figure 6] Figure 6 is an enlarged schematic diagram of the structure of part A shown in Figure 5. [Figure 7] Figure 7 is a schematic diagram of the cross-sectional structure along the CC direction in Figure 6. [Figure 8] Figure 8 is an enlarged schematic diagram of the first via hole structure in Figure 5. [Modes for carrying out the invention]

[0050] To further clarify the objectives, technical solutions, and advantages of the embodiments of this disclosure, the technical solutions of the embodiments of this disclosure will be described clearly and completely below with reference to the drawings of the embodiments of this disclosure. As is obvious, the embodiments described are only a selection of embodiments of this disclosure, not all embodiments. All other embodiments that a person skilled in the art can obtain without requiring any creative work based on the embodiments of this disclosure described are all within the scope of this disclosure.

[0051] Unless otherwise defined, technical or scientific terms used in this disclosure have the ordinary meanings that are understood by those skilled in the art. The terms “First,” “Second,” and similar terms used in this disclosure do not indicate order, quantity, or importance, but are merely used to distinguish different components. Similar terms such as “includes” or “incorporates” mean that the element or component listed before the term includes, but does not exclude, other elements or components listed after the term.

[0052] Thin-film transistor-liquid crystal display (TFT-LCD) technology is a technology that skillfully combines microelectronics technology and liquid crystal display technology. Those skilled in the art utilize microelectronics microfabrication technology on a silicon substrate (Si), and further process thin-film transistor (TFT) arrays on a large area of ​​glass to form an array substrate. Then, using mature liquid crystal display (LCD) technology, they cellize the array substrate with another substrate with a color film layer (i.e., a counter substrate), thereby forming a single liquid crystal cell. Finally, through subsequent processes such as polarizing plate attachment, a liquid crystal display panel is formed.

[0053] As should be understood, the liquid crystal cell further includes a spacer (abbreviated as Photo Spacer, PS), the main function of which the spacer is to support the liquid crystal cell, maintain consistent cell thickness in each area of ​​the liquid crystal display panel, and ensure uniformity of brightness of the display panel. However, in horizontal electric field deflection products such as Advanced Super Dimension Switch (ADS) or In-Plane Switching (IPS), when the display panel is subjected to external stress, the spacer moves, and if the movement is large, the spacer can damage the alignment film (i.e., PI film) on the slot electrode (electrode structure with slits), resulting in liquid crystal alignment defects in that area, which may cause light leakage when the display panel is operating, thereby forming macroscopically irregular bright spots and further affecting product quality.

[0054] For example, Figure 1 is a schematic diagram of the planar structure of the electrode structure. As shown in Figure 1, the geometric design of the electrode structure 10 of the liquid crystal display panel has a slot 11 inside, and the four sides of the slot 11 are closed. However, the light efficiency around this slot electrode 10 is poor, which makes it prone to display defects.

[0055] Embodiments of this disclosure provide an electrode structure in which the first electrode portion and the second electrode portion are designed to have semi-open first and second slits, thereby enabling deflection of liquid crystal molecules at the openings of the first and second slits, and further improving the light efficiency around the electrode structure by making the first and second slits semi-open, and further resolving at least to some extent one or more problems due to limitations and defects of related technologies, and the electrode structure can be applied to liquid crystal display panels and used as pixel electrodes or common electrodes of liquid crystal display panels. In one example, the material of the electrode structure is indium tin oxide, i.e., the electrode structure may be an ITO (indium tin oxide) electrode, and the electrode structure has light transmission properties.

[0056] For example, Figure 2 is a schematic plan view of an electrode structure according to one embodiment of the present disclosure. As shown in Figure 2, the electrode structure includes a first electrode portion 20, a conductive connection portion 22, and a second electrode portion 21 arranged in order in a first direction Y. The first electrode portion 20 may include a first connection strip 201 extending in the first direction Y, and a plurality of first electrode strips 202 spaced apart in the first direction Y. The first connection strip 201 has a first side 201a and a second side 201b facing a second direction X. The plurality of first electrode strips 202 are located on the first side 201a of the first connection strip 201 and are connected to the first connection strip 201. The ends of adjacent first electrode strips 202 that are away from the first connection strip 201 are open, meaning that the ends of adjacent first electrode strips 202 that are away from the first connection strip 201 are not connected to each other.

[0057] Furthermore, the multiple first electrode strips 202 described above are arranged at intervals in the first direction Y, meaning that there is a first slit S1 between adjacent first electrode strips 202, and the first slit S1 is semi-open.

[0058] For example, as shown in Figure 2, the second electrode portion 21 includes a second connecting strip 211 extending in a first direction Y, and a plurality of second electrode strips 212 arranged at intervals in the first direction Y. The second connecting strip 211 is located away from the second side 201b on the first side 201a, and has a third side 211a and a fourth side 211b facing the second direction X, with the third side 211a located close to the first side 201a on the fourth side 211b. The second direction X and the first direction Y are perpendicular to each other. The plurality of second electrode strips 212 are located on the third side 211a of the second connecting strip 211 and are connected to the second connecting strip 211. The ends of adjacent second electrode strips 212 that are away from the second connecting strip 211 are open, meaning that the ends of adjacent second electrode strips 212 that are away from the second connecting strip 211 are not connected to each other.

[0059] Furthermore, the multiple second electrode strips 212 described above are arranged at intervals in the first direction Y, meaning that there is a second slit S2 between adjacent second electrode strips 212, and the second slit S2 is semi-open.

[0060] For example, as shown in Figure 2, the conductive connection portion 22 is located between the first electrode portion 20 and the second electrode portion 21, and both ends of the conductive connection portion 22 are connected to the first connection strip 201 and the second connection strip 211, respectively.

[0061] For example, in the embodiments of this disclosure, by designing the first electrode portion 20 and the second electrode portion 21 of the electrode structure to have semi-open first slits S1 and second slits S2, respectively, deflection of liquid crystal molecules can be generated even at the openings of the first slits S1 and second slits S2. Therefore, the optical efficiency around the electrode structure can be improved compared to the electrode structure in which the area around the slits is closed, as shown in Figure 1.

[0062] Furthermore, as shown in Figure 2, the opening direction of one of the first slits S1 of the first electrode section 20 and the second slit S2 of the second electrode section 21 is to the right, and the opening direction of the other is to the left. That is, the opening directions of the first slit S1 of the first electrode section 20 and the second slit S2 of the second electrode section 21 are opposite. In this way, the light efficiency on both sides of the second direction X of the electrode structure (i.e., both the left and right sides in Figure 2) can be made equal, thereby making the light efficiency around the electrode structure more uniform and improving the display effect.

[0063] For example, in one example, the orthographic projections of the first electrode portion 20, the second electrode portion 21, and the conductive connection portion 22 on the reference plane overlap each other, where overlapping means completely overlapping within the allowable error range. Such a design can reduce the difficulty of designing the electrode structure and is therefore beneficial for arranging multiple electrode structures on an array substrate. However, the embodiments of this disclosure are not limited to this, and the orthographic projections of the first electrode portion 20, the second electrode portion 21, and the conductive connection portion 22 on the reference plane do not have to overlap, and this depends on the specific circumstances.

[0064] The reference plane described in the embodiments of this disclosure is a plane perpendicular to the first direction Y.

[0065] For example, in one example, the first electrode strip 202 and the second electrode strip 212 described above may be parallel to each other, that is, the extension directions of the first electrode strip 202 and the second electrode strip 212 are parallel to each other, thereby equalizing the optical efficiency of the first electrode portion 20 and the second electrode portion 21. Specifically, both the first electrode strip 202 and the second electrode strip 212 extend in a third direction Q, and this third direction Q intersects with the first direction Y and the second direction X, that is, the third direction Q is not parallel to or in a straight line with the first direction Y and the second direction X. Such a design can reduce color shift, thereby improving the display effect of the display panel when the electrode structure is used in a display panel.

[0066] For example, in one example, the acute angle between the third direction Q and the second direction X may be 5° to 15°, such as 5°, 7°, 9°, 11°, 13°, 15°, etc., and the embodiments of this disclosure are not limited thereto.

[0067] For example, in one example, the first width of the first electrode strip 202 may be equal to the first width of the second electrode strip 212. Also, the first width of the first slit S1 may be equal to the first width of the second slit S2. In this way, the light efficiency of the first electrode portion 20 and the second electrode portion 21 can be made even more uniform, thereby improving the display effect of the display panel when the electrode structure is used in a display panel.

[0068] In the embodiments of this disclosure, the first width refers to the size in the fourth direction P, which is perpendicular to the third direction Q.

[0069] For example, in one example, in order to improve the optical efficiency of the first electrode portion 20 and the second electrode portion 21 by ensuring good deflection of liquid crystal molecules at the first electrode portion 20 and the second electrode portion 21, the first width of the first electrode strip 202 in the fourth direction P, the first width of the first slit S1 in the fourth direction P, the first width of the second electrode strip 212 in the fourth direction P, and the first width of the second slit S2 in the fourth direction P must satisfy certain requirements. That is, the ratio of the first width of the first slit S1 in the fourth direction P to the first width of the first electrode strip 202 in the fourth direction P may be 1 to 4, for example, 1, 1.5, 2, 2.5, 3, 3.5, 4, etc., and the embodiments of this disclosure are not limited thereto.

[0070] For example, in one example, the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P may be 1.8 μm to 3 μm, for example, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, etc., and the first width of the first slit S1 and the second slit S2 in the fourth direction P may be 3 μm to 7 μm, for example, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, etc.

[0071] Furthermore, in order to improve the display effect of the display panel when the electrode structure is used in a display panel, by further equalizing the optical efficiency of the first electrode portion 20 and the second electrode portion 21, the second width of the first connecting strip 201 in the second direction X and the second width of the second connecting strip 211 in the second direction X may be set to be equal. For example, the second width of the first connection strip 201 and the second connection strip 211 in the second direction X may be equal to the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P, but embodiments of the present disclosure are not limited thereto, and the second width of the first connection strip 201 and the second connection strip 211 in the second direction X may be slightly larger than the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P, thereby improving light efficiency and mitigating the problem that the first connection strip 201 and the second connection strip 211 are prone to breakage due to having too small a first width in the fourth direction P, thereby improving the yield of the final display panel.

[0072] The second width described in the embodiments of this disclosure is the size in the second direction X.

[0073] For example, the first electrode portion 20 and the second electrode portion 21 of the electrode structure described above are connected via a conductive connection portion 22. In order to avoid the problem of the conductive connection portion 22 being affected by impurity particles (partials) during the manufacturing process and resulting in disconnection, the embodiments of this disclosure design the conductive connection portion 22 to have a large area, thereby avoiding the situation of pixel defects caused by the likelihood of disconnection. For example, in one example, the area of ​​the conductive connection portion 22 is larger than the area of ​​the first electrode strip 202 and also larger than the area of ​​the second electrode strip 212.

[0074] As should be understood, the entire conductive connection portion 22 may extend in the third direction Q, thereby reducing the difficulty of the manufacturing design. For example, when the orthographic projection of the conductive connection portion 22 in the reference plane coincides with the orthographic projection of the first electrode portion 20 and the second electrode portion 21 in the reference plane, in order to make the area of ​​the conductive connection portion 22 larger than the area of ​​the first electrode strip 202 and the second electrode strip 212, in one example, the first width of the first electrode strip 202 in the fourth direction P and the first width of the second electrode strip 212 in the fourth direction P may be smaller than the first width of the entire conductive connection portion 22 in the fourth direction P.

[0075] For example, as shown in Figure 2, the conductive connection portion 22 may be a single conductive connection strip 22a, the conductive connection strip 22a extending in a third direction Q, and the ratio of the first width of the conductive connection strip 22a in a fourth direction P to the first width of the first electrode strip 202 in a fourth direction P may be 1.5 to 5.5, that is, the conductive connection portion 22 is processed to be wider than the first electrode strip 202, thereby improving the situation in which the conductive connection portion 22 is prone to disconnection, and thereby ensuring the quality of the display panel that is ultimately formed.

[0076] For example, in one case, when the conductive connection portion 22 is a single conductive connection strip 22a, the first width of the conductive connection strip 22a in the fourth direction P may be 5 μm to 10 μm, for example, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0077] For example, in one example, the second width of the first connection strip 201 in the second direction X and the second width of the second connection strip 211 in the second direction X are both 2.3 μm to 2.7 μm, the first width of the conductive connection strip 22a in the fourth direction P is 2.5 μm to 3.0 μm, and the first width of the first electrode strip 202 and the second electrode strip 212 in the fourth direction P are both 1.8 μm to 2.6 μm.

[0078] For example, in one example, the first connecting strip 201 and the second electrode strip 212 are positioned mirror images of each other with respect to the second direction X, thus simplifying the manufacturing process of the electrode structure.

[0079] For example, Figure 3 is a schematic plan view of another electrode structure according to one embodiment of the present disclosure, and as shown in Figure 3, the conductive connection portion 22 may include a first conductive connection strip 221, a second conductive connection strip 222 and at least two third conductive connection strips 223, both of which extend in a first direction Y, and which are spaced apart in a second direction X, and which are connected to a first connection strip 201. The second conductive connection strip 222 is connected to the second connection strip 211, and at least two third conductive connection strips 223 are arranged spaced apart in the first direction Y, located between the first conductive connection strip 221 and the second conductive connection strip 222, with both ends of each third conductive connection strip 223 (i.e., both ends in its extending direction) connected to the first conductive connection strip 221 and the second conductive connection strip 222, respectively, that is, there is a third slit S3 between adjacent third conductive connection strips 223, and the four sides of this third slit S3 are closed. For example, the number of third slits S3 included in the conductive connection portion 22 is not limited, and the conductive connection portion 22 may include multiple third slits S3.

[0080] For example, as shown in Figure 3, by designing a slot (i.e., the third slit S3) inside the conductive connection portion 22, on the one hand, the optical efficiency loss above the conductive connection portion 22 can be reduced, thereby improving the optical efficiency of the entire electrode structure. On the other hand, the first electrode portion 20 and the second electrode portion 21 can be connected and made electrically conductive by at least two wires (i.e., the third conductive connection strip 223). In this way, even if impurity particles cause one of the wires to break, the other wires for making electrical contact between the first electrode portion 20 and the second electrode portion 21 can be connected, thereby significantly reducing the occurrence rate of pixel defects, that is, improving the yield of the display panel that is subsequently formed.

[0081] For example, in one example, two third conductive connection strips 223 are installed to ensure stable connection and conductivity between the first electrode section 20 and the second electrode section 21, while appropriately reducing the proportion of the conductive connection section 22 in the electrode structure. In other words, more design space can be provided for the first electrode section 20 and the second electrode section 21. The areas of the first electrode section 20 and the second electrode section 21 may both be larger than the area of ​​the conductive connection section 22. Since the first slit S1 of the first electrode section 20 and the second slit S2 of the second electrode section 21 are both semi-open designs, and the third slit S3 of the conductive connection section 22 is a sealed design, the optical efficiency of the first electrode section 20 and the second electrode section 21 is preferable to the optical efficiency of the conductive connection section 22. In this way, by making the areas of the first electrode section 20 and the second electrode section 21 larger than the area of ​​the conductive connection section 22, the optical efficiency of the entire electrode structure can be improved, thereby improving the quality of the display panel when the electrode structure is used in a display panel. Furthermore, since a third slit S3 is made in the conductive connection portion 22, the situation in which impurity particles adhere to the conductive connection portion 22 during the electrode structure fabrication process can be mitigated, thereby mitigating the situation in which the resistance value of the conductive connection portion 22 increases due to the adhesion of impurity particles, and subsequently mitigating the effect on the driving of the pixels.

[0082] However, it should be understood that the third conductive connection strip 223 is not limited to being installed in pairs, but may be installed in pairs, pairs, pairs, etc., depending on the specific circumstances, and the embodiments of this disclosure do not limit this.

[0083] For example, in order to further reduce the proportion of the conductive connection portion 22 in the electrode structure, the lengths of the first conductive connection strip 221 and the second conductive connection strip 222 may both be smaller than the lengths of the first connection strip 201 and the second connection strip 211. As should be understood, the lengths described herein are sizes in the first direction Y.

[0084] For example, in one case, the length of the first connecting strip 201 in the first direction Y is smaller than the length of the second connecting strip 211 in the first direction Y.

[0085] For example, in one example, the ratio of the length of the first connecting strip 201 in the first direction Y to the length of the second connecting strip 211 in the first direction Y is 0.1 to 0.9, for example, the ratio is 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, or 0.9.

[0086] For example, as shown in Figures 2 and 3, the entire structure connecting the first connecting strip 201, the conductive connection portion 22, and the second connecting strip 211 is bent, with one end of the first connecting strip 201 connected to one end of the conductive connection portion 22, and the other end of the conductive connection portion 22 connected to one end of the second connecting strip 211, and the first connecting strip 201 and the second connecting strip 211 are located on different sides of the conductive connection portion 22 in the second direction X.

[0087] For example, the second width of the first conductive connection strip 221 in the second direction X may be equal to the second width of the first connection strip 201 in the second direction X, and the second width of the second conductive connection strip 222 in the second direction X may be equal to the second width of the second connection strip 211 in the second direction X.

[0088] For example, as shown in Figure 3, the third conductive connection strip 223 may extend in the third direction Q. The first width of the third conductive connection strip 223 in the fourth direction P may be equal to the first width of the first electrode strip 202 in the fourth direction P. Also, the first width of the third slit S3 between adjacent third conductive connection strips 223 in the fourth direction P may be equal to the first width of the first slit S1 between adjacent first electrode strips 202 in the fourth direction P, and the first width of the second slit S2 between adjacent second electrode strips 212 in the fourth direction P. In this way, the optical efficiency of the conductive connection portion 22, the first electrode portion 20, and the second electrode portion 21 can be made equal, thereby improving the display effect of the display panel when the electrode structure is used in a display panel.

[0089] Furthermore, a fourth slit S4 is provided between the third conductive connection strip 223 and the adjacent first electrode strip 202, and a fifth slit S5 is provided between the third conductive connection strip 223 and the adjacent second electrode strip 212. The first width in the fourth direction (P) of the fourth slit S4, the fifth slit S5, and the first slit S1, second slit S2, and third slit S3 described above is all equal, thereby equalizing the optical efficiency at the conductive connection portion 22, the first electrode portion 20, the second electrode portion 21, and the three parties, thereby improving the display effect of the display panel when the electrode structure is used in a display panel.

[0090] In one embodiment of the present disclosure, as shown in Figures 2 and 3, the second electrode portion 21 may further include a signal connection portion 213, which may be located on one side away from the conductive connection portion 22 of a plurality of second electrode strips 212 and connected to a second connection strip 211. For example, when the electrode structure of the embodiment of the present disclosure is a common electrode, the signal connection portion 213 may be connected to a common line of the array substrate, that is, the signal connection portion 213 can be applied to receiving a common signal, but the embodiments of the present disclosure are not limited thereto. When the electrode structure of the embodiment of the present disclosure is a pixel electrode, the signal connection portion 213 may further be connected to the source and drain electrodes of transistors on the array substrate, and the signal connection portion 213 is used to receive signals transmitted from the source and drain electrodes, such as data signals.

[0091] Note that the dashed lines in Figures 2 and 3 have no actual meaning and are merely used to distinguish the structures described above, thereby making it easier to understand the positional relationships between them.

[0092] Furthermore, it should be understood that the shape of the signal connection portion 213 is not limited to the shapes shown in Figures 2 and 3, but may be other shapes, determined by the specific circumstances, and the embodiments of this disclosure do not limit this. The entire electrode structure described in the embodiments of this disclosure is an integrated structure.

[0093] Embodiments of the present disclosure further provide a display panel, which may be a liquid crystal display panel. For example, Figure 4 is a schematic diagram of the local cross-sectional structure of a display panel according to one embodiment of the present disclosure, and as shown in Figure 4, the display panel may include a cellular array substrate 3 and a counter substrate 4, and may further include liquid crystal molecules 5 located between the counter substrate 4 and the array substrate 3.

[0094] The display panel of the embodiment of this disclosure will be described in detail below with reference to Figures 2 to 8.

[0095] As shown in Figures 5 to 7, the array substrate 3 may include a first base 30, a plurality of subpixel units formed on the first base 30, a plurality of scan lines 31, a plurality of first common lines 32, and a plurality of columns of data lines 33.

[0096] For example, Figure 5 is a schematic diagram of the planar structure of a display panel according to one embodiment of the present disclosure. As shown in Figure 5, the first base 30 may have a plurality of sub-pixel regions 301 arranged in an array in the row direction X (second direction) and the column direction Y (first direction), a first wiring region 302 located between two adjacent rows of sub-pixel regions 301, and a second wiring region 303 located between two adjacent columns, with the first wiring region 302 overlapping the second wiring region 303.

[0097] As shown in Figure 5, a plurality of subpixel units are formed on the first base 30, and each subpixel unit includes a pixel electrode 34 located at least partially within the subpixel region 301, a common electrode 35, and a transistor 36 located at least partially within the first wiring region 302. The subpixel units may also further include memory capacitors (not shown).

[0098] For example, Figure 6 is a schematic diagram of the enlarged structure of part A shown in Figure 5. As shown in Figures 5 and 6, the transistor 36 may include an active layer 360, a gate 361, a first pole 362 and a second pole 363 installed on the same layer, and an insulating layer may be further installed between the gate 361 and the active layer 360 to insulate the gate 361 and the active layer 360 from each other. The insulating layer may be made of an inorganic material, such as silicon oxide or silicon nitride. The gate 361 may be installed on the same layer as the scan line 31, and the gate 361 may belong to a part of the scan line 31 as described above.

[0099] For example, the transistor 36 may be a top-gate thin-film transistor or a bottom-gate thin-film transistor. In the embodiments of this disclosure, the description will mainly be based on the example that the transistor 36 is a bottom-gate thin-film transistor. When the transistor 36 is a bottom-gate thin-film transistor, the gate 361 is formed on the first base 30, and the material of the gate 361 may include a metallic material or an alloy material, such as molybdenum, aluminum, and titanium, thereby ensuring good conductivity. An insulating layer is formed on the first base 30 and covers the gate 361, and the insulating layer may be made of an inorganic material, such as silicon oxide or silicon nitride. The active layer 360 is formed on one side of the insulating layer away from the first base 30, and the first electrode 362 and the second electrode 363 are each connected to two doping regions of the active layer 360. The material of the first electrode 362 and the second electrode 363 may include a metallic material or an alloy material, for example, a single-layer or multilayer metal structure formed of molybdenum, aluminum and titanium, for example, the multilayer structure is a multimetallic laminate, for example, a three-layer metallic laminate of titanium, aluminum and titanium (Al / Ti / Al).

[0100] It should be understood that the number of transistors 36 in the subpixel unit may be set to multiple types, and these transistors 36 can be further divided into N-type transistors, P-type transistors, etc.

[0101] For example, as shown in Figures 5 and 6, the pixel electrode 34 may be connected to a first electrode 362, the first electrode 362 of the transistor 36 may be a drain electrode, and the second electrode 363 may be a source electrode. However, the embodiments of this disclosure are not limited thereto, and the first electrode 362 of the transistor 36 may be a source electrode and the second electrode 363 may be a drain electrode, depending on the specific circumstances. The orthographic projection of the common electrode 35 on the first base 30 may be superimposed on the orthographic projection of the pixel electrode 34 on the first base 30.

[0102] For example, at least one of the pixel electrode 34 and the common electrode 35 is an electrode structure described in any of the embodiments described above, thereby improving the optical efficiency around the pixel and improving the quality of the display panel when the electrode structure is used in a display panel. The row direction X described in the embodiments of this disclosure may also be the second direction X described above, and the column direction Y may also be the first direction Y described above.

[0103] For example, Figure 7 is a schematic diagram of the cross-sectional structure along the CC direction in Figure 6. As shown in Figure 7, the first base 30 may be a single-layer structure, and the first base 30 may be a glass substrate. However, the embodiments of this disclosure are not limited thereto. The first base 30 may further be a multilayer structure, and the material of the first base 30 is not limited to glass but may be other materials, such as polyimide (PI), which will depend on the specific circumstances.

[0104] In the embodiments of this disclosure, as shown in Figure 7, the pixel electrode 34 may be located on one side of the common electrode 35 away from the first base 30, that is, the common electrode 35 may be fabricated on the first base 30 before the pixel electrode 34. For example, the common electrode 35 may be a plate-shaped electrode, i.e., the common electrode 35 is a complete solid with no slots, and the pixel electrode 34 may have the electrode structure described in any of the embodiments described above, and the electric field generated between the pixel electrode 34 and the common electrode 35 deflects all liquid crystal molecules between the electrodes and directly above the electrodes, thereby improving the operating efficiency of the liquid crystal and increasing the light transmission efficiency.

[0105] As should be understood, in the embodiments of this disclosure, the positional relationship between the pixel electrode 34 and the common electrode 35 is not limited to the relationship described above. For example, the pixel electrode 34 may be located on one side of the common electrode 35 that is closer to the first base 30, and the common electrode 35 has the electrode structure described in any of the embodiments described above, while the pixel electrode 34 is a plate-shaped electrode.

[0106] In the embodiments of this disclosure, the pixel electrode 34 may be made of indium tin oxide (ITO) material in order to ensure the light transmittance of the array substrate. However, the embodiments of this disclosure are not limited thereto, and the pixel electrode 34 may be made of transparent material such as indium zinc oxide (IZO) or zinc oxide (ZnO). In other words, since the material used for the pixel electrode 34 is different from the material used for the gate 361, first electrode 362, and second electrode 363 of the transistor 36, the pixel electrode 34 may be made using a different patterning process than the gate 361, first electrode 362, and second electrode 363 of the transistor 36.

[0107] For example, as shown in Figure 7, the common electrode 35 may be located on one side of the first pole 362 and second pole 363 of the transistor 36 that is closer to the first base 30, and the common electrode 35 may be formed on the first base 30 before the gate 361 of the transistor 36 is formed. That is, when fabricating the array substrate, the common electrode 35 may be formed on the first base 30 in a patterning process first, and then the gate 361 of the transistor 36 may be formed on the first base 30 in another patterning process. Although both the common electrode 35 and the gate 361 are formed on the first base 30, the common electrode 35 and the gate 361 are disconnected from each other (i.e., not connected). It should be understood that the common electrode 35 may also be formed on the first base 30 after the gate 361 of the transistor 36 has been formed, and this common electrode 35 may be located on the side of the gate 361 that is further away from the first base 30, depending on the specific circumstances.

[0108] Similarly, in order to ensure the light transmittance of the array substrate, the pixel electrode 34 may be made of a transparent conductive material such as ITO, and the pixel electrode 34 may be formed on one side away from the first base 30 of the first pole 362 and second pole 363 of the transistor 36, and as should be understood, there is an additional insulating layer between the first pole 362 and second pole 363 of the transistor 36 of the pixel electrode 34, and the pixel electrode 34 may be connected to the first pole 362 of the transistor via a second via hole structure H2. Specifically, when the pixel electrode 34 has the electrode structure described in the above embodiment, the pixel electrode 34 may be connected to the first pole 362 of the transistor via a second via hole structure H2 by a signal connection portion 213, and as should be understood, this signal connection portion 213 may be located within the first wiring region 302.

[0109] For example, when the pixel electrode 34 has the electrode structure described in the above embodiment, the opening directions of the slots in the first electrode portion 20 of two adjacent pixel electrodes 34 in the first direction Y and the second direction X are opposite, and the opening directions of the slots in the second electrode portion 21 are opposite. The overall shape of each electrode structure of the array substrate 3 may differ slightly, for example, some electrode structures may require avoidance design due to other structures of the array substrate 3. However, as should be understood, the overall shape of each electrode structure of the array substrate 3 does not have to be exactly the same, but the overall design concept is the same. That is, both the first electrode portion 20 and the second electrode portion 21 are half-slot designs, and the first width of the entire conductive connection portion 22 in the fourth direction P is greater than the first width of the first electrode strip 202 in the fourth direction P and the first width of the second electrode strip 212 in the fourth direction P.

[0110] For example, as shown in Figure 5, at least one row of scan lines 31 may be located within one first wiring region 302, in other words, at least one row of scan lines 31 may be placed within each first wiring region 302, and as should be understood, the entire scan line 31 can be considered to extend in the row direction X. The scan line 31 is connected to the gate 361 of the transistor 36 of the subpixel unit, and the scan line 31 described above may be located on the same layer as the gate 361 of the transistor 36 and has an integrated structure, and the scan line 31 is configured to provide a scan signal to the subpixel unit.

[0111] For example, as shown in Figure 5, at least one row of first common lines 32 may be located within one first wiring region 302, in other words, at least one row of first common lines 32 may be installed within each first wiring region 302, and as should be understood, the entire first common line 32 can be considered to extend in the row direction X, and the first common line 32 may be connected to a common electrode 35 and configured to provide a common signal to the subpixel unit.

[0112] For example, the first common line 32 may be installed on the same layer as the scan line 31, and the common electrode 35 described above may be installed on the first base 30 before the scan line 31. Therefore, in order to connect the first common line 32 and the common electrode 35, the first common line 32 and the common electrode 35 can be superimposed and spliced ​​together during the manufacturing process of the first common line 32.

[0113] For example, as shown in Figure 5, one row of scan lines 31 and one row of first common lines 32 may be placed within each first wiring region 302. It should be understood that the scan lines 31 and the first common lines 32 are disconnected from each other, that is, the orthographic projection of the scan line 31 on the first base 30 is not superimposed on the orthographic projection of the first common line 32 on the first base 30. It should be noted that the invention is not limited to having one row of scan lines 31 and one row of first common lines 32 within the first wiring region 302; two rows of scan lines 31 may be placed, or the first common lines 32 may not be placed at all, depending on the specific circumstances, and the embodiments of this disclosure are not limited thereto. The embodiments of this disclosure mainly describe the case in which one row of scan lines 31 and one row of first common lines 32 are placed within each first wiring region 302.

[0114] For example, as shown in Figure 5, at least one row of data lines 33 may be located within one second wiring region 303, in other words, at least one row of data lines 33 may be placed within each second wiring region 303, and as should be understood, the entire data line 33 can be considered to extend in the column direction Y, and the orthographic projection of the data line 33 on the first base 30 is superimposed with the orthographic projection of the scan line 31 and the first common line 32 on the first base 30. For example, the data line 33 may be connected to the second pole 363 of the transistor 36 of the subpixel unit and configured to provide a data signal to the subpixel unit.

[0115] For example, the data lines 33 in the embodiments of this disclosure may be placed on the same layer as the first pole 362 and second pole 363 of the transistor 36 of the subpixel unit, that is, they may be manufactured using the same patterning process, thereby reducing mask costs. However, embodiments of this disclosure are not limited thereto, and they may be manufactured using different patterning processes, depending on the specific circumstances.

[0116] For example, as shown in Figure 5, a row of data lines 33 may be installed within each second wiring region 303, and these data lines 33 may be connected to the second pole 363 of each sub-pixel unit in the same row, that is, the data lines 33 can provide data signals to the sub-pixel units in the same row.

[0117] In embodiments of this disclosure, the data lines 33 of each column may be arranged symmetrically with respect to their central axis, wherein the central axis described herein is a line that passes through the center of the data line 33 and extends in the column direction Y.

[0118] For example, in a single row of subpixel units, the spacing between the first pole 362 of each subpixel unit and the data line 33 connected to it in the row direction X is equal, thereby ensuring that the coupling capacitance between the transistor 36 and the data line 33 of each subpixel unit in each row is approximately the same, and further ensuring uniformity of the optical efficiency at each subpixel unit location in each row. In addition, in a single row of subpixel units, the spacing between the first pole 362 of each subpixel unit and the data line 33 connected to it in the row direction X is equal, and the overlap area between the first pole 362 and the gate 361 of that row must be maintained to match that of other rows.

[0119] For example, as shown in Figure 5, the array substrate may further include a second common line 37, which may be located on the same layer as the data lines 33 and spaced apart from each other. The second common line 37 extends in a first direction Y, the intermediate portion of the orthographic projection of the second common line 37 on the first base 30 is located in a first wiring region 302, and both ends of the second common line 37 are each located within a sub-pixel region 301. In embodiments of this disclosure, both ends of the second common line 37 are each connected to a common electrode 35 of two adjacent sub-pixels in the first direction Y via a first via-hole structure H1.

[0120] For example, Figure 8 is an enlarged schematic diagram of the first via hole structure in Figure 5. As shown in Figure 8, the first via hole structure H1 includes a first via hole section H11, a second via hole section H12, and a via hole connection section H13. The via hole connection section H13 is installed on the same layer as the pixel electrode 34, spaced apart from each other. The via hole connection section H13 is connected to the second common line 37 via the first via hole section H11, and the via hole connection section H13 is connected to the common electrode 35 via the second via hole section H12.

[0121] For example, as shown in Figures 5 to 7, the opposing substrate 4 may further include a second base 41, a spacer 42 located on one side of the second base 41 closer to the array substrate 3, and a shielding layer 40 located on one side of the spacer 42 closer to the second base 41. The specific structure of the second base 41 can be described by referring to the description of the first base 30 and will not be repeated here. The orthographic projection of the shielding layer 40 on the first base 30 can completely cover the first wiring region 302 and the second wiring region 303, and can cover at least some of the subpixel regions 30. Multiple spacers 42 may be installed, and the installation of spacers 42 can improve the uniformity of the thickness of the entire display panel, improve the tolerance of the display panel to fluctuations in liquid crystal molecules, and further improve the yield of the display panel.

[0122] For example, the multiple spacers 42 may include main spacers and auxiliary spacers. The main spacers primarily serve as support, with one end away from the second base 41 in contact with the array substrate 3 when the display panel is not subjected to external pressure. The auxiliary spacers maintain a constant distance between the end away from the second base 41 and the array substrate 1 when the display panel is not subjected to external pressure. In other words, a step (height difference) exists between the main spacers and the auxiliary spacers, and fine adjustments can be made to the thickness of the display panel by adjusting the step between the main spacers and the auxiliary spacers.

[0123] For example, the height of the main spacer is greater than the height of the auxiliary spacer, and when the display panel is subjected to external pressure, the main spacer is first compressed by all the pressure, and when the main spacer is compressed until the height difference between the main spacer and the auxiliary spacer becomes zero, both the main spacer and the auxiliary spacer are subjected to external pressure.

[0124] Furthermore, both the main spacers and auxiliary spacers may be arranged according to a predetermined period. During the manufacturing process, it is necessary to monitor the size and height of different types of spacers. Because the size of the spacers is small and the number of main spacers is generally small, it is difficult for the equipment to accurately identify the position of the main spacers based on size alone. Therefore, the equipment is usually designed to lack spacers at certain positions around the main spacers (i.e., no spacers are installed), thereby allowing for faster and more accurate identification and monitoring of the main spacer's position. For example, by designing the equipment without installing any spacers below the main spacers, the position where no spacers are installed can be quickly determined during monitoring. Then, according to the design rules described above, it can be clearly identified that the spacers above the position where no spacers are installed are the main spacers.

[0125] In the embodiments of this disclosure, the surface of the spacer 42 closest to the first base 30 may be the top surface, and the surface away from the first base 30 may be the bottom surface. As shown in Figure 5, the orthographic projection of the top surface of the spacer 42 on the first base 30 is located within the orthographic projection of the scan line 31 on the first base 30. In other words, the outer contour of the orthographic projection of the top surface of the spacer 42 on the first base 30 is located inside the outer contour of the orthographic projection of the scan line 31 on the first base 30. This ensures the flatness of the support area of ​​the spacer 42, thereby ensuring that the spacer 42 is stably supported on the array substrate 3. In the embodiments of this disclosure, the orthographic projection of the spacer 42 on the first base 30 does not overlap with the orthographic projection of the data line 33 and the transistor on the first base 30.

[0126] As should be understood, the orthographic projection of the top surface of the spacer 42 in the embodiments of the present disclosure may be located within the orthographic projection of the bottom surface of the spacer 42 in the first base 30, meaning that the entire spacer 42 may resemble a cone shape, but the embodiments of the present disclosure are not limited thereto, and the orthographic projection of the top surface of the spacer 42 in the embodiments of the present disclosure may completely overlap with the orthographic projection of the bottom surface of the spacer 42 in the first base 30, depending on the specific circumstances.

[0127] The orthographic projection of the bottom surface of the spacer 42 on the first base 30 may be located within the orthographic projection of the scan line 31 on the first base 30, but the embodiments of this disclosure are not limited thereto, and the contour of the spacer 42 in the column direction Y may extend beyond the contour of the scan line 31 in the column direction Y.

[0128] For example, to prevent the spacer 42 from moving due to external force and damaging the alignment film, causing red spots, an obstruction wall can be installed around the spacer 42. Specifically, the orthographic projection of the spacer 42 on the first base 30 is located within the orthographic projection of the scan line 31 on the first base 30, and the scan line 31 is shielded by the shielding layer 40. Therefore, even if the spacer 42 moves in the row direction X, it remains within the range shielded by the shielding layer 40 and does not fundamentally affect the display effect. Based on this, it is not necessary to install obstruction walls on both opposing sides of the spacer 42 in the row direction X, thereby reducing the difficulty of the design.

[0129] Furthermore, as shown in Figure 5, transistors are installed on opposite sides of the spacer 42 in the row direction X. In the array substrate 3, the total height of the region where the transistors are located is greater than the total height of the region where the spacer 42 is located. In other words, these transistors can act as an obstruction wall, preventing the spacer 42 from sliding in the row direction X.

[0130] To prevent the spacer 42 from sliding too far in the column direction Y due to external force, a first obstruction wall 38a and a second obstruction wall 38b can be installed on the array substrate 3 as shown in Figures 5 and 6. These first obstruction wall 38a and second obstruction wall 38b are located on opposite sides of the scan line 31 in the column direction Y, and the orthographic projection of the spacer 42 on the first base 30 may be located between the orthographic projections of the first obstruction wall 38a and the second obstruction wall 38b on the first base 30. In other words, the first obstruction wall 38a and the second obstruction wall 38b may be installed on opposite sides of the spacer 42 in the column direction Y.

[0131] Furthermore, at least a portion of the first obstruction wall 38a and the second obstruction wall 38b may be located in the subpixel region 301, and the first obstruction wall 38a and the second obstruction wall 38b may be shielded by the shielding layer 40.

[0132] For example, both the first inhibiting wall 38a and the second inhibiting wall 38b are located in the same layer as the scan line 31 and include a first inhibiting layer 381 spaced apart from each other, and a second inhibiting layer 382 located in the same layer as the data line 33 and spaced apart from each other, wherein the orthographic projection of the second inhibiting layer 382 on the first base 30 is superimposed on the orthographic projection of the first inhibiting layer 381 on the first base. For example, as shown in Figures 5 to 7, the distance between the first inhibiting layer 381 and the scan line 31 in the first direction Y is defined as the first interval W1, and the distance between the second inhibiting layer 382 and the scan line 31 in the first direction Y is defined as the second interval W2, and this second interval W2 is larger than the first interval W1, that is, the first inhibiting layer 381 is installed protruding in a direction closer to the spacer 42 compared to the second inhibiting layer 382, ​​and this protruding portion can act as a support when the spacer is subjected to force and moves, thereby mitigating the situation in which the spacer 42 falls into the gap between the scan line 31 and the first inhibiting layer 381 and cannot be restored to its original position, and the distance between the second inhibiting layer 382 and the spacer 42 in the embodiment of this disclosure is the distance between the first inhibiting layer 381 and the spacer 42 By making the gap larger than the threshold, compared to a solution in which the gap between the second inhibiting layer 382 and the spacer 42 and the gap between the first inhibiting layer 381 and the spacer 42 are designed to be equal, the warping angle of the spacer 42 can be reduced when the external stress on the spacer 42 is the same. Thus, when the external stress on the spacer 42 is a force in the horizontal direction (e.g., the first direction Y), the resistance in the vertical direction (i.e., the thickness direction of the display panel) can be reduced. In this case, it becomes more difficult for the spacer 42 to cross the inhibiting wall and damage the alignment film in the light-transmitting region (i.e., the region of the sub-pixel region 301 not covered by the shielding layer 40), that is, the risk of damaging the alignment film is reduced. In addition, the amount of vertical strain of the display panel is reduced, and T-DNU (Touch-Dark Non-uniformity) is also improved.

[0133] Furthermore, the surface of the spacer 42 closest to the first base 30 in the embodiment of this disclosure may be the top surface, and the size W4 of the top surface of the spacer 42 in the first direction Y may be larger than the first spacing W1, thereby mitigating the situation in which the spacer 42 falls into the gap between the scan line 31 and the first inhibiting layer 381 during the movement process and cannot be restored to its original state.

[0134] For example, the ratio of the size W4 of the top surface of the spacer 42 in the first direction Y to the first spacing W1 is 2 or more, thereby further mitigating the situation in which the spacer 42 falls into the gap between the scan line 31 and the first inhibiting layer 381 during the movement process and cannot be restored to its original state.

[0135] For example, the distance between the second inhibiting layer 382 and the spacer 42 in the first direction Y is defined as the third distance W3, and the ratio of the third distance W3 to the size of the top surface of the spacer 42 in the first direction Y is 0.5 or more. Such a design can reduce the risk of the spacer 42 crossing the inhibiting wall, thereby reducing the risk of damaging the alignment film in the light-transmitting region. Furthermore, the ratio of the third distance W3 to the size W4 of the top surface of the spacer 42 in the first direction Y may be 1 or more.

[0136] For example, the ratio of the third interval W3 to the size of the data line 33 in the second direction X is 2 to 4, and the size of the data line 33 in the second direction X may be 5 μm to 7 μm, for example 5 μm, 5.5 μm, 6 μm, 6.5 μm, 7 μm, etc., and in this case the third interval W3 may be 10 μm to 28 μm, for example 10 μm, 13 μm, 17 μm, 21 μm, 25 μm, 28 μm, etc.

[0137] As should be understood, the orthographic projection of the second inhibiting layer 382 described above on the first base 30 lies within the orthographic projection of the first inhibiting layer 381 on the first base 30. Thus, it is possible to ensure that the film layers that primarily play an inhibiting role in the first inhibiting wall 38a and the second inhibiting wall 38b (i.e., the second inhibiting layer 382) have sufficient width in the first direction Y, thereby better inhibiting the sliding of the spacer 42 in the first direction Y. In other words, as shown in Figure 7, the entire longitudinal section of the first inhibiting wall 38a and the second inhibiting wall 38b in the embodiment of this disclosure can be considered to be "L" shaped, where the longitudinal section refers to the plane parallel to the thickness direction and the first direction Y of the display panel.

[0138] Furthermore, the first inhibiting layer 381 of the second inhibiting wall 38b described above may be part of the structure of the first common line 32. The first interval W1 and second interval W2 between the second inhibiting wall 38b and the scan line 31, and the third interval W3 between the second inhibiting wall 38b and the spacer 42 may or may not be equal to the first interval W1 and second interval W2 between the first inhibiting wall 38a and the scan line 31, and the third interval W3 between the first inhibiting wall 38a and the spacer 42, and this is determined by the specific circumstances.

[0139] In the embodiments of this disclosure, the shielding layer 40 described above can cover not only the first wiring region 302 and the second wiring region 303, but also some sub-pixel regions 301, specifically some common electrodes 35 and some pixel electrodes 34. A coupled electric field exists in the region of the pixel electrode 34 near the scan lines 31 and data lines 33, causing disorder in the liquid crystal arrangement during the display process, resulting in defective regions and causing light leakage at the edges of black display pixels. Therefore, a shielding layer 40 is required to shield these defective regions.

[0140] For example, if a coupled electric field exists between the pixel electrode 34 and the scan line 31, meaning a defect region exists in the part of the pixel electrode 34 close to the scan line 31, then to shield this defect region, the shielding layer 40 can cover at least 5 μm of the edge of the pixel electrode 34 in the column direction Y. When the color film layer is located on the opposing substrate, the shielding layer needs to be wider to account for the cell formation accuracy of the upper and lower substrates, but it must not exceed 10 μm, thereby avoiding excessively affecting the aperture ratio of the pixels.

[0141] Furthermore, coupled electric fields similarly exist at the edges of the data line 33 and the pixel electrode 34, meaning that a defect region exists in the portion of the pixel electrode 34 close to the data line 33 in the embodiment of this disclosure. For example, when the liquid crystal molecule 5 is a negative liquid crystal molecule, the electric field does not cause liquid crystal rotation, and the shielding layer 40 can cover approximately 1 μm of the edge of the pixel electrode 34, thereby shielding the shadow region near the data line 33. When the liquid crystal molecule 5 is a positive liquid crystal molecule, the coupled electric field between the data line 33 and the pixel electrode 34 does not cause obvious black display light leakage, but it significantly increases the crosstalk phenomenon of the liquid crystal molecules. In this case, the shielding layer 40 can cover at least 6 μm of the edge of the pixel electrode 34, thereby shielding the coupled electric field region.

[0142] The color film layer used in the liquid crystal display panel may be located on the opposing substrate 4 or on the array substrate 3, depending on the specific circumstances.

[0143] Based on the above, the liquid crystal display panel of the embodiment of this disclosure can be used in display products with 4K resolution or 8K resolution.

[0144] Embodiments of this disclosure further provide electronic devices, including display panels as described in any of the embodiments above.

[0145] Based on the embodiments of this disclosure, the specific type of electronic device is not particularly limited and may be any type of electronic device common in the art, specifically, for example, liquid crystal display screens, mobile devices such as mobile phones and laptops, wearable devices such as watches, VR devices, etc. Those skilled in the art can make a corresponding selection based on the specific application of the display device, which will not be repeated here.

[0146] Furthermore, the electronic device may include, in addition to the display panel, other necessary components and components, and, taking a display as an example, may further include a backlight module, casing, main circuit board, power lines, etc., and in this art, corresponding supplements can be made according to the specific usage requirements of the electronic device, and these will not be described again here.

[0147] Furthermore, the terms "located on," "formed on," and "installed on" as used herein may indicate that one layer is directly formed or installed on another layer, or that one layer is indirectly formed or installed on another layer, i.e., that there are other layers between the two layers.

[0148] The terms "one," "one," "the said," and "at least one" are used to indicate the existence of one or more elements / components / etc., while the terms "includes" and "possess" indicate open inclusion, meaning that other elements / components / etc. may exist in addition to those listed.

[0149] In this disclosure, unless otherwise specified, the term “placed in the same layer” means that two layers, members, components, elements, or parts can be formed in the same patterning process, and these two layers, members, components, elements, or parts are generally formed from the same material.

[0150] In this disclosure, unless otherwise specified, the term "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The term "primary patterning process" refers to the process of forming patterned layers, components, parts, etc., using a single mask.

[0151] The following points need to be explained.

[0152] (1) The drawings of the embodiments of this disclosure relate only to the structures relating to the embodiments of this disclosure, and other structures should refer to conventional designs.

[0153] (2) Where there is no inconsistency, features of identical and different embodiments of the present disclosure may be combined.

[0154] The foregoing are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure, which is determined by the appended claims. [Explanation of symbols]

[0155] 10 slot electrodes 11 slots 20 1st electrode part 201 First connection strip 201a First side 201b 2nd side 202 First electrode strip 21 Second electrode part 211 Second connection strip 211a 3rd side 211b 4th side 212 Second electrode strip 213 Signal connection section 22 Conductive connection part 221 First conductive connection strip 222 Second conductive connection strip 223 Third conductive connection strip 3 Array substrates 30 1st Base 301 subpixel area 302 1st wiring area 303 2nd wiring area 31 scan lines 32 1st common line 33 data lines 34 pixel electrodes 35 Common electrode 36 transistors 360 active layer Gate 361 362 1st pole 363 2nd pole 37 Second common line 38a First inhibitory wall 38b Second inhibitory wall 381 First Inhibition Layer 382 Second Inhibition Layer 4 Opposite substrate 40 Shielding layer 41 2nd base 42 Spacers 5. Liquid crystal molecules

Claims

1. A display panel comprising an array substrate (3) and a counter substrate (4) arranged in a cellular configuration, The array substrate (3) includes a first base (30) and a scan line (31), a data line (33), a first obstruction wall (38a), and a second obstruction wall (38b) formed on one side of the first base (30) closer to the opposing substrate (4), wherein the data line (33) extends in a first direction (Y), the scan line (31) extends in a second direction (X), the first direction (Y) intersects with the second direction (X), the first obstruction wall (38a) and the second obstruction wall (38b) are located on opposite sides of the scan line (31) in the first direction (Y), and both the first obstruction wall (38a) and the second obstruction wall (38b) are installed in the same layer as the scan line (31). The structure includes a first external stress inhibiting layer (381) spaced apart from each other, and a second external stress inhibiting layer (382) installed in the same layer as the data line (33) and spaced apart from each other, wherein the orthographic projection of the second external stress inhibiting layer (382) on the first base (30) is superimposed on the orthographic projection of the first external stress inhibiting layer (381) on the first base (30), the distance between the first external stress inhibiting layer (381) and the scan line (31) in the first direction (Y) is defined as the first interval (W1), and the distance between the second external stress inhibiting layer (382) and the scan line (31) in the first direction (Y) is defined as the second interval (W2), the second interval (W2) being greater than the first interval (W1), The opposing substrate (4) includes a second base (41) and a spacer (42) located on one side of the second base (41) closer to the array substrate (3), the surface of the spacer (42) closer to the first base (30) is the top surface, the orthographic projection of the top surface of the spacer (42) on the first base (30) is located within the orthographic projection of the scan line (31) on the first base (30) and between the orthographic projections of the first obstruction wall (38a) and the second obstruction wall (38b) on the first base (30), and the size (W4) of the top surface of the spacer (42) in the first direction (Y) is larger than the first spacing (W1) of the display panel.

2. The display panel according to claim 1, wherein the ratio of the size (W4) of the top surface of the spacer (42) in the first direction (Y) to the first interval (W1) is 2 or more.

3. The display panel according to claim 2, wherein the distance between the second external stress inhibiting layer (382) and the spacer (42) in the first direction (Y) is defined as the third distance (W3), and the ratio of the third distance (W3) to the size (W4) of the top surface of the spacer (42) in the first direction (Y) is 0.5 or more.

4. The display panel according to claim 3, wherein the ratio of the third interval (W3) to the size (W4) of the top surface of the spacer (42) in the first direction (Y) is 1 or more.

5. The display panel according to claim 3, wherein the ratio of the third interval (W3) to the size of the data line (33) in the second direction (X) is 2 to 4.

6. The display panel according to any one of claims 1 to 5, wherein the orthographic projection of the second external stress inhibiting layer (382) on the first base (30) lies within the orthographic projection of the first external stress inhibiting layer (381) on the first base (30), and the first direction (Y) is perpendicular to the second direction (X).

7. The display panel according to claim 6, wherein the array substrate (3) is formed on the first base (30) and further includes a first common line (32) extending in the second direction (X), the first common line (32) is located in the same layer as the scan line (31) and is spaced apart from each other, and the first external stress inhibiting layer (381) of the second inhibiting wall (38b) is a part of the structure of the first common line (32).

8. The array substrate (3) further includes a plurality of subpixel units arranged in an array on the first base (30) in the second direction (X) and the first direction (Y), Each subpixel unit includes a pixel electrode (34), a common electrode (35), and a transistor (36), the transistor (36) including a gate (361), a first pole (362), and a second pole (363), the gate (361) being connected to the scan line (31), the first pole (362) being connected to the pixel electrode (34), and the second pole (363) being connected to the data line (33). The display panel according to claim 7, wherein the orthographic projection of the common electrode (35) on the first base (30) is superimposed on the orthographic projection of the pixel electrode (34) on the first base (30), and the common electrode (35) is connected to the first common line (32).

9. The pixel electrode (34) is located on one side of the common electrode (35) away from the first base (30), and the pixel electrode (34) includes a first electrode portion (20), a second electrode portion (21), and a conductive connection portion (22). The first electrode portion (20) includes a first connecting strip (201) extending in the first direction (Y), and a plurality of first electrode strips (202) arranged at intervals in the first direction (Y), wherein the first connecting strip (201) has a first side (201a) and a second side (201b) facing the second direction (X), and the plurality of first electrode strips (202) are located on the first side (201a) of the first connecting strip (201), connected to the first connecting strip (201), and the ends of adjacent first electrode strips (202) that are away from the first connecting strip (201) are open. The second electrode portion (21) is arranged with a gap between it and the first electrode portion (20) in the first direction (Y), and the second electrode portion (21) includes a second connecting strip (211) extending in the first direction (Y), and a plurality of second electrode strips (212) arranged with a gap between them in the first direction (Y), the second connecting strip (211) is located away from the second side (201b) on the first side (201a), and the second connecting strip (211) is the second It has a third side (211a) and a fourth side (211b) facing in direction (X), the third side (211a) is located near the first side (201a) of the fourth side (211b), the plurality of second electrode strips (212) are located on the third side (211a) of the second connecting strip (211) and connected to the second connecting strip (211), and the ends of adjacent second electrode strips (212) that are away from the second connecting strip (211) are open. The display panel according to claim 8, wherein the conductive connection portion (22) is located between the first electrode portion (20) and the second electrode portion (21), and both ends of the conductive connection portion (22) are connected to the first connection strip (201) and the second connection strip (211), respectively, and the area of ​​the conductive connection portion (22) is larger than the area of ​​the first electrode strip (202) and the area of ​​the second electrode strip (212).

10. The conductive connection portion (22) includes a first conductive connection strip (221) and a second conductive connection strip (222) arranged at intervals in the second direction (X) and both extending in the first direction (Y), and at least two third conductive connection strips (223) located between the first conductive connection strip (221) and the second conductive connection strip (222) and arranged at intervals in the first direction (Y), wherein both ends of each third conductive connection strip (223) are connected to the first conductive connection strip (221) and the second conductive connection strip (222), respectively. The display panel according to claim 9, wherein the first conductive connection strip (221) is connected to the first connection strip (201), and the second conductive connection strip (222) is connected to the second connection strip (211).

11. The first electrode strip (202), the second electrode strip (212), and the third conductive connection strip (223) all extend in a third direction (Q), and the first widths of the first electrode strip (202), the second electrode strip (212), and the third conductive connection strip (223) are equal. The display panel according to claim 10, wherein the first width is the size in the fourth direction (P), the third direction (Q) is perpendicular to the fourth direction (P), and the third direction (Q) intersects the first direction (Y) and the second direction (X).

12. The display panel according to claim 9, wherein the array substrate (3) is installed in the same layer as the data lines (33) and further includes a second common line (37) spaced apart from each other, the second common line (37) extending in the first direction (Y), and both ends of the second common line (37) are each connected via a first via-hole structure (H1) to a common electrode (35) of two adjacent sub-pixel units in the first direction (Y).

13. The display panel according to claim 12, wherein the first via hole structure (H1) includes a first via hole section (H11), a second via hole section (H12), and a via hole connection section (H13), the via hole connection section (H13) is installed in the same layer as the pixel electrode (34) and spaced apart from each other, the via hole connection section (H13) is connected to the second common line (37) via the first via hole section (H11), and the via hole connection section (H13) is connected to the common electrode (35) via the second via hole section (H12).

14. The display panel according to claim 9, wherein the area of ​​the first electrode portion (20) and the area of ​​the second electrode portion (21) are both larger than the area of ​​the conductive connection portion (22).

15. The display panel according to claim 11, wherein the ends of adjacent first electrode strips (202) away from the first connecting strip (201) are not connected, and the ends of adjacent second electrode strips (212) away from the second connecting strip (211) are not connected.

16. The display panel according to claim 15, wherein there is a first slit (S1) between adjacent first electrode strips (202), the stretching direction of the first electrode strips (202) and the first slit (S1) is the same, the first slit (S1) is semi-open, and there is a second slit (S2) between adjacent second electrode strips (212), the stretching direction of the second electrode strips (212) and the second slit (S2) is the same, the second slit (S2) is semi-open, and the opening directions of the first slit (S1) and the second slit (S2) are opposite.

17. The display panel according to claim 16, wherein the first width of the first slit (S1) in the fourth direction (P) is equal to the first width of the second slit (S2) in the fourth direction (P).

18. The display panel according to claim 17, wherein the first width of the first slit (S1) in the fourth direction (P) is 1 to 4 times the first width of the first electrode strip (202) in the fourth direction (P).

19. The display panel according to claim 18, wherein the first width of the first electrode strip (202) in the fourth direction (P) and the first width of the second electrode strip (212) in the fourth direction (P) are both 1.8 μm to 3 μm, and the first width of the first slit (S1) in the fourth direction (P) and the first width of the second slit (S2) in the fourth direction (P) are both 3 μm to 7 μm.

20. The display panel according to claim 16, wherein a third slit (S3) is provided between adjacent third conductive connection strips (223), and the four sides of the third slit (S3) are closed.

21. The display panel according to claim 20, wherein the conductive connection portion (22) includes a plurality of the third slits (S3).

22. The display panel according to claim 20, wherein the first width of the third conductive connection strip (223) in the fourth direction (P) is equal to the first width of the first electrode strip (202) in the fourth direction (P), and the first widths of the third slit (S3), the first slit (S1), and the second slit (S2) in the fourth direction (P) are equal.

23. The display panel according to claim 22, wherein a fourth slit (S4) is provided between the third conductive connection strip (223) and the adjacent first electrode strip (202), and a fifth slit (S5) is provided between the third conductive connection strip (223) and the adjacent second electrode strip (212), and the first widths of the first slit (S1), the second slit (S2), the third slit (S3), the fourth slit (S4), and the fifth slit (S5) are equal in the fourth direction (P).

24. The display panel according to claim 11, wherein the first width of the first electrode strip (202) in the fourth direction (P) and the first width of the second electrode strip (212) in the fourth direction (P) are smaller than the first width of the entire conductive connection portion (22) in the fourth direction (P).

25. The display panel according to claim 11, wherein the second width of the first connecting strip (201) in the second direction (X) is equal to the second width of the second connecting strip (211) in the second direction (X), and the second widths of the first connecting strip (201) and the second connecting strip (211) in the second direction (X) are equal to or greater than the first width of the first electrode strip (202) and the second electrode strip (212) in the fourth direction (P).

26. The display panel according to claim 10, wherein the length of the first conductive connection strip (221) in the first direction (Y) and the length of the second conductive connection strip (222) in the first direction (Y) are both smaller than the length of the first connection strip (201) in the first direction (Y) and smaller than the length of the second connection strip (211) in the first direction (Y).

27. The display panel according to claim 26, wherein the length of the first connecting strip (201) in the first direction (Y) is smaller than the length of the second connecting strip (211) in the first direction (Y).

28. The display panel according to claim 27, wherein the ratio of the length of the first connecting strip (201) in the first direction (Y) to the length of the second connecting strip (211) in the first direction (Y) is 0.1 to 0.

9.

29. The display panel according to claim 9, wherein the entire connection of the first connecting strip (201), the conductive connecting portion (22), and the second connecting strip (211) is bent, one end of the first connecting strip (201) is connected to one end of the conductive connecting portion (22), the other end of the conductive connecting portion (22) is connected to one end of the second connecting strip (211), and the first connecting strip (201) and the second connecting strip (211) are located on different sides of the conductive connecting portion (22) in the second direction (X).

30. The display panel according to claim 10, wherein the second width of the first conductive connection strip (221) in the second direction (X) is equal to the second width of the first connection strip (201) in the second direction (X), and the second width of the second conductive connection strip (222) in the second direction (X) is equal to the second width of the second connection strip (211) in the second direction (X).

31. The display panel according to claim 11, wherein the conductive connection portion (22) includes a conductive connection strip (22a), the conductive connection strip (22a) extends in a third direction (Q), and the third direction (Q) intersects the first direction (Y) and the second direction (X).

32. The display panel according to claim 31, wherein the third direction (Q) is perpendicular to the fourth direction (P), and the ratio of the first width of the conductive connection strip (22a) in the fourth direction (P) to the first width of the first electrode strip (202) in the fourth direction (P) is 1.5 to 5.

5.

33. The display panel according to claim 32, wherein the first width of the conductive connection strip (22a) in the fourth direction (P) is 5 μm to 10 μm, and the first width of the first electrode strip (202) in the fourth direction (P) is 1.8 μm to 3 μm.

34. The display panel according to claim 32, wherein the second width of the first connecting strip (201) in the second direction (X) and the second width of the second connecting strip (211) in the second direction (X) are both 2.3 μm to 2.7 μm, the first width of the conductive connecting strip (22a) in the fourth direction (P) is 2.5 μm to 3.0 μm, and the first width of the first electrode strip (202) and the second electrode strip (212) in the fourth direction (P) are both 1.8 μm to 2.6 μm.

35. The display panel according to claim 9, wherein the second electrode portion (21) further includes a signal connection portion (213), the signal connection portion (213) is located on one side of the plurality of second electrode strips (212) away from the conductive connection portion (22), and is connected to the second connection strip (211).

36. The display panel according to claim 9, wherein the first connection strip (201) and the second electrode strip (212) are arranged mirror images with respect to the second direction (X).

37. An electronic device comprising a display panel according to any one of claims 1 to 36.

Images