Background calibration of digital-to-analog converters

Abstract

To provide a technique for enabling background calibration of a digital-to-analog converter (DAC) with minimal processing overhead.SOLUTION: A single frequency bin can be used to calibrate errors between bits. A low frequency feedback path may be included in a low frequency low power ADC to determine an error signal present in a calibration bin. When this error signal is minimized, bits are calibrated. A described background calibration technique provides very efficient and optimal calibration at a DAC output for both static and dynamic errors.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Priority Claim This application claims priority to U.S. Provisional Patent Application No. 63 / 314,614, titled "BACKGROUND CALIBRATION OF DIGITAL-TO-ANALOG CONVERTERS," filed on 28 February 2022, which is incorporated herein by reference in its entirety.

[0002] This technology provides a way to enable background calibration of digital-to-analog converters (DACs) with minimal processing overhead. [Background technology]

[0003] Integrated circuits process electrical signals for a wide range of electronic applications. Data converters are a crucial part of electronic devices, responsible for converting signals between the digital and analog domains. However, the circuits within data converters and those driving them are not perfect, and as a result, the conversion output may not be perfect. Imperfection or non-idealization can lead to unwanted noise or spurs appearing in the output, potentially degrading the performance of the data converter. If not removed or calibrated, noise or spurs can also affect other parts of the signal chain. [Overview of the project] [Means for solving the problem]

[0004] This disclosure describes various techniques that enable background calibration of digital-to-analog converters (DACs) with minimal processing overhead. Inter-bit errors can be calibrated using a single frequency bin. A low-frequency feedback path can be included in the low-frequency, low-power ADC to determine the error signal present in the calibration bin. Once this error signal is minimized, the bits are calibrated. The background calibration techniques described provide highly efficient and optimal calibration at both static and dynamic errors in the DAC output.

[0005] In some embodiments, the Disclosure relates to a background method for measuring the non-idealism of a DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the plurality of which sum their outputs to produce an analog output of the DAC, the method comprising: providing digital data to the DAC cells to generate an output spectrum at the analog output of the DAC; generating a first digitally encoded calibration stimulus having a first fundamental energy in a first frequency bin; scaling the first digitally encoded calibration stimulus by a first weighting coefficient, and while the DAC cells are generating the output spectrum, the first weighted calibration stimulus is used in the plurality of redundant DAC cells. The method includes: providing a subset of DAC cells to generate a first analog tone; scaling a first digitally encoded calibration stimulus by a second weighting coefficient and providing the second weighted calibration stimulus to a second subset of redundant DAC cells to generate a second analog tone, wherein the second weighting coefficient is selected such that the first and second analog tones have opposite polarities; and detecting an error tone in a first frequency bin resulting from the first and second analog tones at the analog output of the DAC.

[0006] In some aspects, the present disclosure relates to a background method for measuring non-idealities of a DAC having a plurality of DAC cells that sum outputs to generate an analog output of the DAC and a plurality of redundant DAC cells. The method includes generating a first digitally encoded calibration stimulus having a first fundamental energy at a first frequency bin; scaling the first digitally encoded calibration stimulus by a first weighting factor to generate a first weighted calibration stimulus; providing the first weighted calibration stimulus to the redundant DAC cells to generate a first analog tone; while the first weighted calibration stimulus is being provided to the redundant DAC cells, providing digital data and an inverted version of the first weighted calibration stimulus to the DAC cells to generate an output spectrum and a second analog tone; and detecting an error tone resulting from the first analog tone and the second analog tone in the analog output of the DAC.

[0007] In some embodiments, the Disclosure relates to a background method for measuring either or both of the static error between DAC cells and the timing error between DAC cells of a multi-gigabit-per-second DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of which are summed to produce an analog output of the DAC, the method comprising: providing digital data to the DAC cells to generate an output spectrum at the analog output of the DAC; generating a first digitally encoded calibration stimulus having a first fundamental energy in a first frequency bin; scaling the first digitally encoded calibration stimulus by a first weighting coefficient; and providing the first weighted calibration stimulus to a first subset of redundant DAC cells while the DAC cells generate the output spectrum, thereby providing the first analog to The process includes generating a tone, scaling a first digitally encoded calibration stimulus by a second weighting coefficient, and providing the second weighted calibration stimulus to a second subset of redundant DAC cells while the DAC cells generate an output spectrum, thereby generating a second analog tone, wherein the second weighting coefficient is selected such that the first and second analog tones have opposite polarities, and the sum of the first and second analog tones produces an error tone, and detecting an error tone in a first frequency bin resulting from the first and second analog tones by detecting the energy in the analog output of the DAC at a first frequency bin at the analog output of the DAC.

[0008] In some aspects, the present disclosure relates to a digital-to-analog converter (DAC) having background calibration. The digital-to-analog converter receives digital data and includes a plurality of DAC cells for generating an output spectrum, a stimulus generator for generating a first digitally encoded calibration stimulus having a first fundamental energy at a first frequency bin, one or more reference DAC cells for receiving a weighted version of the first digitally encoded calibration stimulus and generating a first analog tone, and one or more calibration DAC cells for receiving a further weighted version of the first digitally encoded calibration stimulus and generating a second analog tone, wherein the second analog tone has a polarity opposite to that of the first analog tone, and the outputs of the DAC cells, reference DAC cells, and calibration DAC cells are summed to form the analog output of the DAC. The digital-to-analog converter further includes a sense ADC at the analog output of the DAC for sensing an error tone resulting from the first analog tone and the second analog tone.

[0009] In some aspects, the present disclosure relates to a digital-to-analog converter (DAC) having background calibration. The digital-to-analog converter includes a stimulus generator for generating a first digitally encoded calibration stimulus having a first fundamental energy at a first frequency bin, receives digital data and a weighted version of the first digitally encoded calibration stimulus, and includes a plurality of DAC cells for generating an output spectrum and a first analog tone at the analog output of the DAC, and one or more calibration DAC cells for receiving a further weighted version of the first digitally encoded calibration stimulus and generating a second analog tone, wherein the second analog tone has a polarity opposite to that of the first analog tone, and the outputs of the DAC cells and calibration DAC cells are summed to form the analog output of the DAC. The digital-to-analog converter further includes a sense ADC at the analog output of the DAC for sensing an error tone resulting from the first analog tone and the second analog tone.

[0010] To provide a more complete understanding of this disclosure and its features and advantages, refer to the following description in conjunction with the attached drawings, where similar reference numbers indicate similar parts. [Brief explanation of the drawing]

[0011] [Figure 1] Examples of segmented digital-to-analog converters (DACs) according to some embodiments of the present disclosure. [Figure 2] Some embodiments of the present disclosure are exemplary DACs having background calibration using a reference DAC cell and a calibration DAC cell. [Figure 3] The present disclosure provides an exemplary DAC having background calibration for the main DAC, according to some embodiments of this disclosure. [Figure 4] This is another exemplary DAC having background calibration for the main DAC, according to some embodiments of the present disclosure. [Figure 5] This disclosure presents an exemplary DAC having background calibration and correction according to several embodiments of this disclosure. [Modes for carrying out the invention]

[0012] overview A DAC maps digital words to analog outputs. DAC bits can have amplitude and timing errors. These errors (or sometimes referred to herein as “non-idealisms”) result in distortion and degradation of the DAC’s dynamic range. Background calibration of static and dynamic errors, and flexible approaches for generating test patterns as stimuli are described.

[0013] DAC Basics Analog signals from the real world, such as temperature, pressure, sound, and images, are routinely converted into digital representations that can be easily processed by modern digital systems. In many systems, this digital information needs to be converted back into analog form to perform some real-world function. The circuit that performs this step is a DAC (Digital-Analog Converter), and their outputs can be used to drive a variety of devices. Loudspeakers, video displays, motors, mechanical servos, radio frequency (RF) transmitters, and temperature control are just a few diverse examples.

[0014] A DAC is a circuit, device, or system that generates a quantized (individual step) analog output in response to a digital input code. The digital input is generated within the digital domain, for example, from transistor logic (TTL), emitter-coupled logic (ECL), complementary metal-oxide-semiconductor (CMOS) circuitry, or low-voltage differential signaling (LVDS), digital logic, or a processor. The DAC converts the digital input to an analog output. The analog output of the DAC may be either voltage or current. In some cases, the digital input may include binary coded bits or thermometer coded bits. The bits of the digital input are provided to drive or control the circuitry within the DAC to generate the analog output.

[0015] To generate an output, a reference quantity is divided into binary and / or linear fractions. One or more DAC cells are implemented for each of these fractions. Digital inputs drive switching to individual DAC cells having appropriate weights corresponding to those fractions. Each portion of the digital input drives its respective DAC cell to deliver the aggregated output of the DAC cells representing the digital input. DAC cells may include current sources, voltage sources, resistors, capacitors, etc. DAC cells can be actuated by digital inputs, i.e., digital input codes, to generate an analog output. In some embodiments, the outputs of the DAC cells are summed or combined to produce an aggregated output.

[0016] In some cases, the segmented DAC can use different circuit architectures and / or encodings for different segments of the digital input. A segmented architecture where the full resolution of the converter is distributed among two or more sub-DACs can be used for both current and voltage output DACs. The sub-DACs of the overall DAC do not have to have the same resolution. In some cases, the DAC may be provided with redundant circuitry, for example, additional circuitry or DAC cells included in the design.

[0017] FIG. 1 shows an exemplary segmented DAC 100 according to some embodiments of the present disclosure. As shown in FIG. 1, a digital input signal or digital input code can be provided to a segmentation unit that separates the digital input signal / code into its most significant bit d MSB , intermediate significant bit d ISB , and least significant bit d LSB . The most significant bit d MSB can be provided to decoder block 102. The intermediate significant bit d ISB can be provided to decoder block 104. Decoder block 102 and decoder block 104 can decode the most significant bit d MSB and the intermediate significant bit d ISB from binary coding to thermometer coding, such that unary (i.e., DAC cells having the same bit weight) DAC cells for the MSB segment and the ISB segment can convert the most significant bit d MSB and the intermediate significant bit d ISB into the respective analog outputs of the MSB and ISB segments. The least significant bit d LSB can be provided to delay block 106 (to provide or emulate the delay of decoder blocks 102 and 104). A binary weighted DAC cell can convert the least significant bit d LSB into the analog output of the LSB segment. The full resolution of the segmented DAC 100 is B = B MSB + B ISB + B LSBAnd for the maximum effective bit segment, B MSB Regarding the number of bits and intermediate effective bits, see B ISB For the number of bits and minimum effective bits, see B LSB Assume there is a number of bits. For the maximum effective bit segment, Unari DAC cell 108 has at least 2 BMSB-1 It can include DAC cells, and these all have the same (ideal) bit weights w MSB =2 (BLSB+BISB) The Unari DAC cell 110 has at least 2 for the intermediate effective bit segment. BISB-1 It can include DAC cells, and these all have the same (ideal) bit weight w ISB =2 BLSB The binary DAC cell 112 has different binary bit weights w LSB[k] =2 k k=[0:B LSB B has -1] LSB It may have DAC cells. Different segments generate their respective analog outputs based on their respective digital inputs to different segments. The combiner 114 combines, sums, or adds up the outputs of each segment having a DAC cell (for example, a segment having a unidirectional DAC cell 108, a unidirectional DAC cell 110, or a binary DAC cell 112) to generate the overall analog output of the DAC 100.

[0018] In some cases, decoder blocks 102 and 104 (either one or both) may implement additional logic to shuffle the Unali DAC cells 108 and 110 to average out cell mismatches in order to reduce distortion in the analog output.

[0019] In segmented DACs, as shown in Figure 1, a balance is struck between the accuracy of the converter and the complexity of the design. One advantage of segmentation is that it reduces the number of resistors (or current sources) required to achieve a given resolution by allowing different DAC architectures to be used for different segments of the digital input code, thereby enabling a smaller die size. For this reason, segmenting high-resolution DACs is common. To achieve high speed, current-steering DAC cells are typically used.

[0020] Errors in DAC Segmented DACs, or conventional DACs, are not perfect, and calibrating unari or binary DAC cells can present challenges for designers. Like many other devices manufactured using complex manufacturing processes, various imperfections / non-idealities can affect DAC performance.

[0021] One example is circuit imperfections that affect the performance of individual elements of a DAC (referred to herein as a "DAC cell"). These imperfections may be due to manufacturing variations typically referred to as "static mismatch" or "DC error." For example, static mismatch can be caused by the size of devices that differ from their ideal size, such as resistors, current sources, or transistors. As a result, the "bit weights" of the DAC cell deviate from their ideal values, leading to an "amplitude error."

[0022] Another example involves timing errors, typically referred to as "AC errors" (where AC stands for alternating current) or "dynamic errors," which can be caused, for example, by clock jitter, switch mismatches, and driver mismatches. Timing errors can be global (e.g., associated with a global clock signal) or they can be local to a particular DAC cell. Timing errors can cause a "wrong" amount of "bit weight" to be delivered to the analog output when transitions in the analog output of a DAC cell occur earlier or later than ideal time, or when transitions deviate from ideal transitions. In some cases, clock jitter can affect the on-up of a particular DAC cell with respect to a reference DAC cell (i.e., two DAC cells are not turned on simultaneously when they are expected to be on at the same time). In these scenarios, DAC cells turn on / off earlier or later than ideal time, resulting in errors in the analog output. In some cases, the DAC cell itself may have transition asymmetry, where the rise and fall of the analog output behave differently. For example, a transition asymmetry due to a switch mismatch, such as a mismatch in a pair of differential switches involved in steering current toward a particular output, can affect the performance of a particular DAC cell, causing it to exhibit different behavior in rising and falling transitions. In another example, a transition asymmetry due to a driver mismatch, such as a timing mismatch in the signal path driving a pair of differential switches involved in steering current toward a particular output, can also affect the performance of a particular DAC cell, causing it to deviate from the ideal in rising and falling transitions. These timing-related imperfections can also result in duty cycle errors where the period during which the DAC cell is "on" differs from the ideal period (e.g., too long or too short compared to a reference or ideal period).

[0023] Another example is drift, such as thermal drift or aging, which changes the characteristics of a device over time and causes it to deviate from its ideal state.

[0024] Many of the examples above result in distortion in the analog output and therefore affect the overall performance of the DAC. For some errors, designers have chosen to use larger devices to mitigate part of the error. However, increasing device size and therefore increasing area and power consumption is not always desirable. Rather than trying to increase the size of the device, designers have addressed performance issues through calibration.

[0025] Disadvantages of certain calibration techniques Various schemes have been proposed for measuring and calibrating DAC errors. For example, a square wave of a specific frequency and an inverted version thereof can be used as a calibration stimulus to control (1) a reference DAC cell and (2) a calibration DAC cell (and more calibration cells if a desired weight should be achieved to balance the reference DAC cell), and the analog output can be measured to determine the timing skew. However, such approaches can be limited and may not be practical for some applications. One reason why a square wave as a calibration stimulus is undesirable is that it generates uniform harmonics at the output of the DAC. Such uniform harmonics and / or their image can affect the actual signal that the DAC is generating, and if a square wave is applied in the background (i.e., during normal operation of the DAC), it can significantly degrade the performance of the DAC.

[0026] In some techniques, uncorrelated pseudo-random sequences are used as calibration stimuli to a reference DAC cell and a calibration DAC cell. While such sequences do not produce a tone at the output, a broadband observation analog-to-digital converter (ADC) is required to observe the analog output of the DAC, and the digital processing to extract exposed errors using this stimulus is computationally too complex to be practical.

[0027] In some techniques, delta-sigma patterns can be generated as calibration stimuli. However, the delta-sigma converters used to generate the patterns have feedback loops and are too slow for some applications. Furthermore, these techniques are not always suitable for background calibration.

[0028] Extract errors in the background. To calibrate either static or dynamic errors within the DAC in the background, one or more reference bits (e.g., one or more reference DAC cells) can be stimulated with a pattern (or stimulus) to generate a reference tone at the DAC's analog output. Each reference DAC cell will receive the same pattern. The same pattern can then be applied to one or more calibration bits (e.g., one or more calibration DAC cells) to generate a calibration tone with the opposite polarity to the reference tone.

[0029] The goal is to generate a reference tone and a calibration tone that can cancel each other out if there is no mismatch between the reference and calibration bits. One of the applied patterns can be inverted (for example, scaled by a negative amount). One or more patterns can be weighted to ensure that the magnitudes of the reference tone and the calibration tone are ideally the same. Each calibration DAC cell will receive the same pattern.

[0030] The reference tone and calibration tone are intended to have the same magnitude but opposite polarity when the reference DAC cell and calibration DAC cell match each other (or have no errors with each other). If there is a mismatch, an error tone is generated, and the error tone can be observed to compensate / correct the mismatch. Depending on the bit weights of the reference DAC cell and the calibration DAC cell, the pattern can be weighted accordingly to generate reference and calibration tones of similar magnitude.

[0031] In parallel, the normal DAC cell operates to convert digital data to the desired analog output spectrum (as in normal operation), while the reference DAC cell and calibration DAC cell are redundant DAC cells in the DAC that receive patterns simultaneously with the normal DAC cell. It is common for a DAC architecture to have redundant DAC cells and / or a bank of (redundant) DAC cells that can generate attenuated outputs. In many applications, calibration techniques occur during the normal operation of the DAC, and error tones do not significantly affect the DAC. The ability to perform calibration techniques in the background is due to the very small signal amplitude of the error tone.

[0032] When the outputs of the DAC cells are summed, the analog output of the DAC has an error tone resulting from the summed reference tone and calibration tone. The error tone corresponds to the difference error between one or more reference bits and one or more calibration bits. Since the reference tone, calibration tone, and therefore the error tone all occupy a single frequency bin, the difference / mismatch error can be extracted by processing / checking the energy in a single frequency bin.

[0033] In some cases, to minimize the amplitude of the error tone, least mean squares or binary search algorithms can be used to iteratively correct the DAC (within the digital or analog domain). Thus, the algorithm can make the difference / mismatch error smaller and smaller.

[0034] To expose static errors, the pattern preferably causes the DAC cell to generate a tone with fundamental energy at or near DC (or zero frequency). To expose dynamic errors, the pattern preferably causes the DAC cell to generate a tone with fundamental energy at or near Nyquist.

[0035] The pattern does not necessarily have to be a delta-sigma generating pattern, as it may not always be practical to provide a stimulus generator containing a delta-sigma converter with a feedback loop. Rather, the pattern may be a 1-bit sequence approximating a sine wave, such that a DAC cell stimulated by the 1-bit sequence outputs a tone with fundamental energy at the signal frequency bin. The error tone component, which is not associated with the fundamental tone, has an even lower energy than the fundamental tone.

[0036] As calibration progresses, the error tone becomes smaller and smaller, thereby reducing its impact on the normal operation of the DAC.

[0037] Exemplary DAC with background calibration using redundant DAC cells as the reference DAC cell and calibration DAC cell Figure 2 shows an exemplary DAC having background calibration using a reference DAC cell and a calibration DAC cell, according to some embodiments of the present disclosure. The DAC has a (normal or primary) DAC cell 202 and redundant DAC cells. The redundant DAC cells are not used (e.g., for a specified period) to generate the desired output spectrum. The same cells can be used to generate the desired output spectrum at different points in time, at which point some cells within DAC cell 202 become redundant DAC cells (e.g., their roles are swapped or alternating). A subset of the redundant DAC cells is labeled as the reference DAC cell 204, and another subset of the redundant DAC cells is labeled as the calibration DAC cell 206. The outputs of the DAC cells of the DAC are summed to form the final analog output.

[0038] A typical DAC cell 202 is a digital data D data It is successfully receiving [k] and generating the desired output spectrum f(t). Digital data D data [k] and / or D data [k] may be shuffled to implement dynamic element matching so that mismatches within DAC cell 202 are averaged out.

[0039] Calibration stimulus D for calibration cal [k] is generated. The calibration stimulus can be scaled by a first weighting coefficient w1 before being provided to each reference DAC cell 204. The calibration stimulus causes the reference DAC cell 204 to generate a first analog tone u1(t). Calibration stimulus D ca [k] can be scaled by a second weighting coefficient w2 before being provided to each calibration DAC cell. The calibration stimulus causes the calibration DAC cell 206 to generate a second analog tone u2(t).

[0040] The (weighted) calibration stimuli are applied in the background to the reference DAC cell 204 and the calibration DAC cell 206 while the digital data is being applied to the normal DAC cell 202.

[0041] A suitable number of reference DAC cells 204 and a suitable number of calibration DAC cells 206 may be selected to receive calibration stimuli. The first weighting coefficients w1 and the second weighting coefficients w2 are selected such that the first analog tone u1(t) and the second analog tone u2(t) have substantially the same magnitude and opposite polarity. The sum of the first analog tone u1(t) and the second analog tone u2(t) results in an error tone e(t) representing the difference between the reference DAC cell 204 and the calibration DAC cell 206.

[0042] Since the outputs of the DAC cells are summed, the analog output has the desired output spectrum and error tone f(t)+e(t).

[0043] Exemplary DAC with background calibration using redundant DAC cells as calibration DAC cells Instead of comparing a subset of redundant DAC cells to each other (as shown in Figure 3), one or more redundant DAC cells are compared to a normal DAC cell (i.e., the primary DAC). This variation results in another background calibration technique that can be performed while the DAC is operating. One or more calibration bits can be stimulated with a calibration tone, and the same calibration tone or a derivative thereof can be subtracted from the primary DAC output spectral signal path. If there are no errors between the calibration bits and the primary DAC cell, no error tone will be present in the DAC's analog output. One advantage of this technique is that it reduces the number of redundant DAC cells required for the calibration technique.

[0044] Figure 3 shows an exemplary DAC with background calibration for the primary DAC, according to some embodiments of the present disclosure. The DAC has a (normal or primary) DAC cell 302 and a redundant DAC cell 304. The redundant DAC cell is not used to generate the desired output spectrum. The redundant DAC cell 304 is used as a calibration DAC cell. The outputs of the DAC cells of the DAC are summed to form the final analog output.

[0045] Calibration stimulus D for calibration cal [k] is generated. The calibration stimulus can be scaled by a weighting coefficient w1 before being provided to each calibration DAC cell 304. The calibration stimulus causes the calibration DAC cell 206 to generate an analog tone u2(t).

[0046] Weighted calibration stimulus D cal [k]*w1 is digital data D data [k] is provided for digital correction. Where appropriate, the calibration stimulus can be scaled by different weighting coefficients if the bit weights of the calibration DAC cell 304 do not match the cells in the primary DAC cell 302. In the example shown, the weighted calibration stimulus D cal [k]*w1 is D data [k] is subtracted. The normal DAC cell 302 receives the corrected digital data D data [k]-(D calIt receives [k]*w1) and operates successfully to generate the desired output spectrum f(t) and further analog tone u1(t), or f(t)+u1(t). Thus, one or more DAC cells 302 are effectively used as one or more reference DAC cells.

[0047] DAC cell 302 and / or modified digital data D data [k]-(D cal [k]*w1) may be shuffled to implement dynamic element matching so that mismatches within DAC cell 302 are averaged out.

[0048] Calibration stimuli are corrected digital data D data [k]-(D cal While [k]*w1) is applied to the normal DAC cell 302, it is applied to the calibrated DAC cell 304 in the background.

[0049] A suitable number of calibration DAC cells 304 can be selected to receive calibration stimuli. Weighting coefficients w1 and possibly further weighting coefficients are selected such that the first analog tone u1(t) and the second analog tone u2(t) have substantially the same magnitude and opposite polarity. Summing the first analog tone u1(t) and the second analog tone u2(t) results in an error tone e(t) representing the difference between the main DAC cell 302 and the calibration DAC cells 304.

[0050] Since the outputs of the DAC cells are summed, the analog output has the desired output spectrum and error tone f(t)+e(t).

[0051] An exemplary DAC with multi-tone background calibration using redundant DAC cells as calibration DAC cells. Figure 4 shows another exemplary DAC having background calibration for the primary DAC according to some embodiments of the present disclosure. The DAC has a (normal or primary) DAC cell 402, a first redundant DAC cell 404, and a second redundant DAC cell 406. The redundant DAC cells are not used to generate the desired output spectrum. The first redundant DAC cell 404 and the second redundant DAC cell 406 are used as calibration DAC cells and receive different calibration stimuli having fundamental energies in different frequency bins. The outputs of the DAC cells of the DAC are summed to form the final analog output. Errors from the different calibration DAC cells can be extracted simultaneously.

[0052] For calibration, the first calibration stimulus D cal1 [k] is generated. First calibration stimulus D cal1 [k] can be scaled by a weighting coefficient w1 before being provided to each calibration DAC cell 404. The first calibration stimulus causes the calibration DAC cell 404 to generate an analog tone u2(t).

[0053] Second calibration stimulus D cal2 [k] is the base energy of the first calibration stimulus D cal1 [k] is in a different frequency bin and is generated for calibration. Second calibration stimulus D cal2 [k] can be scaled by an additional weighting coefficient w2 before being provided to each calibration DAC cell 406. The second calibration stimulus causes the calibration DAC cell 406 to generate an additional analog tone u4(t).

[0054] First weighted calibration stimulus D cal1 [k]*w1 and second weighted calibration stimulus D cal2 [k]*w2 is digital data D data [k] is provided for digital correction. Where appropriate, each calibration stimulus may be scaled by a different weighting coefficient if the bit weights of calibration DAC cells 404 / 406 do not match the cells in the primary DAC cell 402. In the example shown, the first weighted calibration stimulus D cal1[k]*w1 and second weighted calibration stimulus D cal2 [k]*w2 is D data [k] is subtracted. The normal DAC cell 402 is the corrected digital data D data [k]-(D cal1 [k]*w1)-(D cal2 It receives [k]*w2) and operates successfully to generate the desired output spectrum f(t), analog tone u1(t), and further analog tone u3(t) or f(t)+u1(t)+u3(t). Thus, one or more DAC cells 402 are effectively used as one or more reference DAC cells.

[0055] DAC cell 402 and / or modified digital data D data [k]-(D cal1 [k]*w1)-(D cal2 [k]*w2) may be shuffled to implement dynamic element matching so that mismatches within DAC cell 402 are averaged out.

[0056] Corrected digital data D data [k]-(D cal1 [k]*w1)-(D cal2 While [k]*w2) is applied to the normal DAC cell 402, the first calibration stimulus is applied to the calibrated DAC cell 404 in the background, and the second calibration stimulus is applied to the calibrated DAC cell 406.

[0057] A suitable number of calibration DAC cells 404 can be selected to receive calibration stimuli. Weighting coefficients w1 and possibly further weighting coefficients are selected such that analog tones u1(t) and analog tones u2(t) have substantially the same magnitude and opposite polarity. Summing analog tones u1(t) and analog tones u2(t) results in an error tone e1(t) representing the difference between the primary DAC cell 402 and the calibration DAC cells 404.

[0058] A suitable number of calibration DAC cells 406 can be selected to receive calibration stimuli. Weighting coefficients w2 and possibly further weighting coefficients are selected such that analog tones u3(t) and analog tones u4(t) have substantially the same magnitude and opposite polarity. Summing the first analog tones u3(t) and analog tones u4(t) results in an error tone e2(t) representing the difference between the primary DAC cell 402 and the calibration DAC cells 406.

[0059] Since the outputs of the DAC cells are summed, the analog output has the desired output spectrum and two error tones f(t)+e1(t)+e2(t).

[0060] Exemplary DAC with background calibration and correction Figure 5 shows exemplary DACs with background calibration and correction according to several embodiments of the present disclosure. DAC 502 shows one of the DACs shown in Figures 2 to 4. In addition to DAC 502, a stimulus generator 504, a sense ADC 506, and error extraction logic 508 are provided. The stimulus generator 504 can generate one or more digitally encoded calibration stimuli as described herein. Since the error tone is in a single frequency bin, the sense ADC 506 can be band-limited (it does not need to be a wideband ADC). The error extraction logic 508 can observe the energy in the frequency bin (representing errors in the calibration DAC cell) and perform correction to reduce the observed energy. One way of performing correction is to distort the digital data using distortion logic 510 to compensate for errors in the digital domain. Another way of performing correction is to adjust the circuitry in DAC 502 in the analog domain to compensate for errors.

[0061] Modification form and implementation form It should be noted that the activities discussed above with reference to the drawings are applicable to any integrated circuit involving background calibration of the DAC cells of the DAC. This technique can be repeated by selecting a specific DAC cell to be the calibrated DAC cell. Embodiments described herein can be used to background calibrate DACs having different architectures. Preferably, these embodiments can be applied to DACs where independent elements or cells corresponding to controlling the input bit lines are directly summed at the output, such as current steering or potentially parallel capacitor DACs (which are actually the majority of signal processing DACs). Other architectures, such as resistor arrays (for precision applications) and pipeline capacitor DACs, do not follow this method because they perform partial summing before reaching the output.

[0062] Measuring DAC performance, specifically distortion at the output, is critical for several applications. The calibration scheme of this disclosure provides a flexible and effective method for measuring errors in the background, i.e., while the primary DAC is processing real-time signals. In specific contexts, the functions considered herein can be applied to medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, measurement (which may require high precision), cable infrastructure, military applications (e.g., radar), and other systems where reducing distortion at the DAC output is critical to the application.

[0063] Various components of the apparatus for background calibration DAC cells may include digital or electronic circuits for performing the functions described herein. In some cases, one or more parts of the apparatus may be provided by a processor (e.g., an on-chip processor, an on-chip microprocessor, an on-chip digital signal processor, an off-chip processor, an off-chip microprocessor, and an off-chip digital signal processor) specifically configured to perform the functions described herein. For example, the processor may include one or more application-specific components or programmable logic gates configured to perform the functions described herein. The circuits may operate in the analog domain, the digital domain, or the mixed-signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-temporary computer medium.

[0064] In one exemplary embodiment, any number of electrical circuits shown in the figure can be mounted on a substrate of the associated electronic device. The substrate may be a general circuit board capable of holding various components of the internal electronic system of the electronic device and further providing connectors for other peripherals. More specifically, the substrate can provide electrical connections that allow other components of the system to communicate electrically. All suitable processors (including digital signal processors, microprocessors, support chipsets, etc.), non-temporary computer-readable memory elements, etc., can be suitably coupled to the substrate based on specific configuration needs, processing requirements, computer design, etc. Other components such as external storage, additional sensors, audio / video display controllers, peripherals, etc., may be attached to the substrate as plug-in cards, via cables, or incorporated into the substrate itself. In various embodiments, the functions described herein may be implemented in emulation form as software or firmware operating within one or more configurable (e.g., programmable) elements located within a structure that supports these functions. The software or firmware providing the emulation may be provided on a non-temporary computer-readable storage medium containing instructions that enable the processor to perform those functions.

[0065] In another exemplary embodiment, the electrical circuit shown in the figure may be implemented as a standalone module (for example, a device having associated components and circuits configured to perform a specific application or function) or as a plug-in module into application-specific hardware of an electronic device. Note that certain embodiments of this disclosure may be readily contained in part or in whole in a system-on-chip (SOC) package. An SOC represents an IC that integrates components of a computer or other electronic system onto a single chip. This may include digital functions, analog functions, mixed-signal functions, and often RF functions, all of which may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which multiple separate ICs are located within a single electronic package and are configured to interact closely with each other through the electronic package. In various other embodiments, calibration functionality may be implemented on one or more silicon cores of application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and other semiconductor chips.

[0066] It should also be noted that all specifications, dimensions, and relationships outlined herein (e.g., the number of processors, logic operations, etc.) are provided for illustrative and teaching purposes only. Such information may vary significantly without departing from the spirit of this disclosure and / or the examples. This specification applies to only one non-limiting example, and therefore should be construed as such. In the foregoing description, exemplary embodiments were described with reference to the arrangement of a particular processor and / or component. Various modifications and changes can be made to such embodiments without departing from the scope of this disclosure and / or the examples. Accordingly, the description and drawings should be considered illustrative rather than limiting.

[0067] It should be noted that interactions can be described in terms of two, three, four, or more electrical components using the numerous examples provided herein. However, this is done solely for clarity and illustrative purposes. It should be understood that the system can be enhanced in any preferred manner. Any of the components, modules, and elements illustrated in the drawings can be combined into a variety of possible configurations according to alternatives of similar designs, all of which are clearly within the broad scope of this specification. In certain particular cases, it may be easy to describe one or more of the functionality of a given flowset by referring to only a limited number of electrical elements. It should be understood that the electrical circuits in the figures and their teachings are readily expandable and can accommodate a large number of components as well as more complex / sophisticated arrangements and configurations. Therefore, the examples provided should not limit the scope of the electrical circuits or hinder the broad teachings, as they may be applicable to many other architectures.

[0068] It should be noted that in this specification, references to various features (e.g., elements, structures, modules, components, steps, operations, features, etc.) included in "one embodiment," "exemplary embodiment," "a certain embodiment," "another embodiment," "several embodiments," "various embodiments," "other embodiments," "alternative embodiments," etc., mean that any such features are included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiment.

[0069] It is also important to note that the calibration-related functions shown in the figures represent only some of the possible functions that may be performed by or within the system shown. Some of these operations may be deleted or removed as needed, or they may be substantially modified or changed without departing from the scope of this disclosure. In addition, the timing of these operations may be considerably changed. The aforementioned operation flow is provided for the purposes of examples and discussion. Substantial flexibility is provided by the embodiments described herein in that any preferred arrangement, timeline, configuration, and timing mechanism may be provided without departing from the teachings of this disclosure.

[0070] Numerous other variations, substitutions, alterations, changes, and modifications may be apparent to those skilled in the art, and it is intended that all such variations, substitutions, alterations, changes, and modifications are encompassed within the scope of this disclosure. Furthermore, all optional features of the above apparatus may be implemented in relation to the methods or processes described herein, and specific examples in the embodiments may be used in part in one or more embodiments. [Examples]

[0071] Example 1. A background method for measuring the non-idealism of a DAC having a plurality of DAC cells and a plurality of redundant DAC cells, wherein the outputs are summed to produce an analog output of the DAC, the method comprising: providing digital data to the DAC cells to generate an output spectrum at the analog output of the DAC; generating a first digitally encoded calibration stimulus having a first fundamental energy in a first frequency bin; scaling the first digitally encoded calibration stimulus by a first weighting coefficient and providing the first weighted calibration stimulus to a first subset of redundant DAC cells while the DAC cells generate the output spectrum. A background method comprising: generating a first analog tone; scaling a first digitally encoded calibration stimulus by a second weighting coefficient and providing the second weighted calibration stimulus to a second subset of redundant DAC cells while the DAC cells generate an output spectrum, thereby generating a second analog tone, wherein the second weighting coefficient is selected such that the first and second analog tones have opposite polarities; and detecting an error tone in a first frequency bin resulting from the first and second analog tones at the analog output of the DAC.

[0072] Example 2. The background method according to Example 1, wherein the digital data is shuffled to average out the non-ideal characteristics of the DAC cells.

[0073] Example 3. The background method according to any one of the above examples, wherein the DAC cells are shuffled to average out the non-ideality of the DAC cells.

[0074] Example 4. The background method according to any one of the above examples, wherein the redundant DAC cells include a bank of DAC cells having the minimum effective bit weight.

[0075] Example 5. The background method according to any one of Examples 1 to 4, wherein a first subset of redundant DAC cells includes multiple redundant DAC cells, and a second subset of redundant DAC cells includes multiple redundant DAC cells.

[0076] Example 6. The background method according to any one of Examples 1 to 4, wherein a first subset of redundant DAC cells includes a single redundant DAC cell, and a second subset of redundant DAC cells includes multiple redundant DAC cells.

[0077] Example 7. The background method according to any one of Examples 1 to 4, wherein a first subset of redundant DAC cells includes multiple redundant DAC cells, and a second subset of redundant DAC cells includes a single redundant DAC cell.

[0078] Example 8. The background method according to any one of Examples 1 to 4, wherein a first subset of redundant DAC cells includes a single redundant DAC cell, and a second subset of redundant DAC cells includes a single redundant DAC cell.

[0079] Example 9. The background method according to any one of the above examples, wherein one or more redundant DAC cells receive a portion of the digital data, and a subset of DAC cells become one or more redundant DAC cells to receive weighted calibration stimuli.

[0080] Example 10. The background method according to any one of the above examples, wherein the first weighting coefficient and the second weighting coefficient have opposite polarities.

[0081] Example 11. The background method according to any one of the above examples, wherein the first weighting coefficient and the second weighting coefficient have the same magnitude.

[0082] Example 12. The background method according to any one of the above examples, wherein the first weighting coefficient and the second weighting coefficient have different magnitudes.

[0083] Example 14. The background method according to any one of the above examples, wherein the first and second weight coefficients are selected from +1, -1, positive weight values, and negative weight values.

[0084] Example 15. The background method according to any one of the above examples, wherein the sum of the first analog tone and the second analog tone produces an error tone.

[0085] Example 16. A background method according to any one of the above embodiments, wherein detecting an error tone includes detecting energy in the analog output of the DAC at a first frequency bin.

[0086] Example 15. The background method according to any one of the above examples, further comprising iteratively minimizing error tones by pre-distorting the digital data.

[0087] Example 16. The background method according to any one of the above examples, further comprising iteratively minimizing error tones by adjusting a first subset of redundant DAC cells or a second subset of redundant DAC cells in the analog domain.

[0088] Example 17. The background method according to any one of the above examples, wherein the first digitally encoded calibration stimulus is a 1-bit sequence approximating a sine wave.

[0089] Example 18. A background method according to any one of the above examples, wherein generating a first digitally encoded calibration stimulus is performed without feedback.

[0090] Example 19. A background method according to any one of the above embodiments, wherein generating a first digitally encoded calibration stimulus includes filtering a multi-bit sequence encoding a sine wave to generate a 1-bit sequence that approximates a sine wave.

[0091] Example 20. A background method according to any one of the above examples, wherein generating a first digitally encoded calibration stimulus includes a low-pass filter of a multi-bit sequence encoding a sine wave.

[0092] Example 21. The background method according to any one of the above examples, wherein the first frequency bin is not in the output spectrum and bandwidth.

[0093] Example 22. The background method according to any one of the above examples, wherein the first frequency bin is selected so as not to interfere with the output spectrum.

[0094] Example 23. The background method according to Example 1, further comprising: generating a second digitally encoded calibration stimulus having a second fundamental energy in a second frequency bin, wherein the second frequency bin is different from that of a first frequency bin; scaling the second digitally encoded calibration stimulus by a third weighting coefficient and providing the third weighted calibration stimulus to a third subset of redundant DAC cells while the DAC cells generate an output spectrum to generate a third analog tone; scaling the third digitally encoded calibration stimulus by a fourth weighting coefficient and providing the fourth weighted calibration stimulus to a fourth subset of redundant DAC cells while the DAC cells generate an output spectrum to generate a fourth analog tone, wherein the fourth weighting coefficient is selected such that the third and fourth analog tones have opposite polarities; and detecting further error tones resulting from the third and fourth analog tones at the analog output of the DAC.

[0095] Example 24. The background method according to any one of the above examples, wherein the DAC is a multi-gigabit per second DAC.

[0096] Example 25. A background method according to any one of the above examples, wherein the non-ideality includes static errors between DAC cells.

[0097] Example 26. A background method according to any one of the above examples, wherein the non-ideality includes timing errors between DAC cells.

[0098] Example 100. A background method for measuring the non-idealism of a DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of which are summed to produce an analog output of the DAC, the background method comprising: generating a first digitally encoded calibration stimulus having a first fundamental energy in a first frequency bin; scaling the first digitally encoded calibration stimulus by a first weighting coefficient to generate a first weighted calibration stimulus; providing the first weighted calibration stimulus to a redundant DAC cell to generate a first analog tone; providing the DAC cell with digital data and an inverted version of the first weighted calibration stimulus while the first weighted calibration stimulus is being provided to the redundant DAC cell to generate an output spectrum and a second analog tone; and detecting an error tone resulting from the first analog tone and the second analog tone in the analog output of the DAC.

[0099] Example 101. The background method according to Example 100, further comprising: generating a second digitally encoded calibration stimulus having a second fundamental energy in a second frequency bin; scaling the second digitally encoded calibration stimulus by a second weighting coefficient to generate a second weighted calibration stimulus; providing the second weighted calibration stimulus to a further redundant DAC cell to generate a third analog tone, wherein an inverted version of the second weighted calibration stimulus is further provided to the DAC cell along with digital data and an inverted version of the first weighted calibration stimulus to further generate an output spectrum and a second analog tone and a fourth analog tone; and detecting further error tones arising from the third analog tone and the fourth analog tone at the analog output of the DAC.

[0100] Example 102. Any one of Examples 2 to 26 may be an optional feature of Example 100 or 101.

[0101] Example 200. A digital-to-analog converter (DAC) having background calibration, comprising: a plurality of DAC cells for receiving digital data and generating an output spectrum; a stimulus generator for generating a first digitally encoded calibration stimulus having a first fundamental energy in a first frequency bin; one or more reference DAC cells for receiving a weighted version of the first digitally encoded calibration stimulus and generating a first analog tone; one or more calibration DAC cells for receiving a further weighted version of the first digitally encoded calibration stimulus and generating a second analog tone, wherein the second analog tone has opposite polarity to the first analog tone, and the outputs of the DAC cells, the reference DAC cells, and the calibration DAC cells are summed to form the analog output of the DAC; and a sense ADC at the analog output of the DAC for sensing error tones arising from the first analog tone and the second analog tone.

[0102] Example 201. A DAC having background calibration of Example 200, further comprising distortion logic that distorts the digital data before it is provided to the DAC cell.

[0103] Example 202. A DAC having the background calibration described in Example 200 or 201, wherein the reference DAC cell and / or calibration DAC cell are adjustable in response to a sensed error tone.

[0104] Example 203. A DAC having background calibration according to any one of Examples 200 to 202, wherein the stimulus generator includes a low-pass filter that receives a multi-bit sinusoidal signal and generates a single bit sequence that approximates a sine wave.

[0105] Example 204. A DAC having a background calibration as described in any one of Examples 200 to 203, wherein the stimulus generator does not have feedback.

[0106] Example 205. A DAC having the background calibration described in any one of Examples 200-204, further comprising error extraction logic for measuring energy in a first frequency bin.

[0107] Example 206. A DAC having any one of the background calibrations from Examples 200 to 205, which can implement any of the methods from Examples 1 to 26.

[0108] Example 300. A digital-to-analog converter (DAC) having background calibration, comprising: a stimulus generator for generating a first digitally encoded calibration stimulus having a first fundamental energy in a first frequency bin; a plurality of DAC cells for receiving digital data and a weighted version of the first digitally encoded calibration stimulus and generating an output spectrum and a first analog tone at the analog output of the DAC; one or more calibration DAC cells for receiving a further weighted version of the first digitally encoded calibration stimulus and generating a second analog tone, wherein the second analog tone has opposite polarity to the first analog tone, and the outputs of the DAC cells and the calibration DAC cells are summed to form the analog output of the DAC; and a sense ADC at the analog output of the DAC for sensing an error tone resulting from the first analog tone and the second analog tone.

[0109] Example 301. A DAC having the background calibration described in Example 300, further comprising one or more further calibration DAC cells, the stimulus generator further generates a second digitally encoded calibration stimulus having a second fundamental energy in a second frequency bin different from a first frequency bin; the DAC cell further receives a weighted version of the second digitally encoded calibration stimulus and further generates a third analog tone at the analog output of the DAC; the DAC further receives a further weighted version of the second digitally encoded calibration stimulus and further generates a fourth analog tone; and the sense ADC senses further error tones resulting from the third and fourth analog tones.

[0110] Example 302. A DAC having the background calibration of Example 300 or Example 301 can implement any of the methods of Examples 100 to 102. [Explanation of symbols]

[0111] 100 DAC 102 Decoder Blocks 104 Decoder Blocks 106 Delay Block 108 Unari DAC Cell 110 Unari DAC Cell 112 Binary DAC Cells 202 DAC cells 204 Reference DAC Cell 206 Calibration DAC Cells 302 DAC cells 304 redundant DAC cells 402 DAC cells 404 First redundant DAC cell 406 Second redundant DAC cell 502 DAC 504 Stimulator 506 Sense ADC 508 Error Extraction Logic 510 Distortion Logic

Claims

1. A method for measuring the non-ideality of a DAC having multiple DAC cells (202) that sum their outputs by a combiner to generate an analog output of the DAC, wherein the multiple DAC cells (202) include multiple redundant DAC cells (204, 206), While the redundant DAC cells (204, 206) are not being used to generate output, digital data is provided to the DAC cell (202) that is not one of the redundant DAC cells (204, 206), thereby generating output at the analog output of the DAC. Generating a first digitally encoded constructive stimulus, which includes generating a first digitally encoded calibration stimulus having a first magnitude in a first frequency bin, and comprising filtering a multi-bit sequence encoding a sine wave to generate a 1-bit sequence approximating the sine wave without using a feedback loop, The first digitally encoded calibration stimulus is scaled by a first weighting coefficient, and the first weighted calibration stimulus is provided to a subset (204) of the first redundant DAC cells of the DAC, while the DAC cell (202) that is not the redundant DAC cell (204, 206) generates the output, thereby generating a first analog tone. The method involves scaling the first digitally encoded calibration stimulus by a second weighting coefficient and providing the second weighted calibration stimulus to a subset (206) of the second redundant DAC cells of the DAC, while the DAC cell (202) that is not the redundant DAC cell (204, 206) generates the output, thereby generating a second analog tone, wherein the second weighting coefficient is selected such that the first analog tone and the second analog tone have opposite polarities. The analog output of the DAC includes detecting an error tone in the first frequency bin, which is generated from the first analog tone and the second analog tone. A method in which a portion of the redundant DAC cells (204, 206) are swapped with a portion of DAC cells (202) that are not redundant DAC cells (204, 206) that generate outputs with analog outputs over different periods.

2. The method according to claim 1, wherein the digital data or the DAC cell (202) is shuffled to average out the non-ideality of the DAC cell (202).

3. The subset (204) of the first redundant DAC cell of the redundant DAC cell includes a plurality of redundant DAC cells, and the subset (206) of the second redundant DAC cell of the redundant DAC cell includes a plurality of redundant DAC cells. The subset (204) of the first redundant DAC cell of the redundant DAC cell includes a single redundant DAC cell, and the subset (206) of the second redundant DAC cell of the redundant DAC cell includes multiple redundant DAC cells. The subset (204) of the first redundant DAC cell of the redundant DAC cell includes a plurality of redundant DAC cells, and the subset (206) of the second redundant DAC cell of the redundant DAC cell includes a single redundant DAC cell. The subset (204) of the first redundant DAC cell of the redundant DAC cell includes a single redundant DAC cell, and the subset (206) of the second redundant DAC cell of the redundant DAC cell includes a single redundant DAC cell. The method according to claim 1, wherein the method is any one of the following.

4. The method according to claim 1, wherein the sum of the first analog tone and the second analog tone generates the error tone.

5. The method according to claim 1, wherein detecting the error tone includes detecting the magnitude of the analog output of the DAC in the first frequency bin.

6. The method according to claim 1, further comprising iteratively minimizing the error tone by using a least mean squares or binary search algorithm, and / or iteratively minimizing the error tone by adjusting a subset of the first redundant DAC cells (204) or a subset of the second redundant DAC cells (206) of the redundant DAC cells in the analog domain.

7. The method according to claim 1, wherein the first digitally encoded calibration stimulus is a one-bit sequence approximating a sine wave.

8. The method according to claim 1, performed as background calibration.

9. To generate a second digitally encoded calibration stimulus having a second magnitude in a second frequency bin, wherein the second frequency bin is different from the first frequency bin. The second digitally encoded calibration stimulus is scaled by a third weighting coefficient, and the third weighted calibration stimulus is provided to a subset of the third redundant DAC cells of the redundant DAC cells while the DAC cell generates the output, thereby generating a third analog tone. The method involves scaling a third digitally encoded calibration stimulus by a fourth weighting coefficient, and providing the fourth weighted calibration stimulus to a subset of the fourth redundant DAC cells of the redundant DAC cells while the DAC cell generates the output, thereby generating a fourth analog tone, wherein the fourth weighting coefficient is selected such that the third analog tone and the fourth analog tone have opposite polarities. The method according to claim 1, further comprising detecting an additional error tone arising from the third analog tone and the fourth analog tone at the analog output of the DAC.

10. A background method for measuring the non-ideality of a DAC having multiple DAC cells, wherein the outputs are summed by a combiner to generate an analog output of the DAC, the multiple DAC cells include multiple redundant DAC cells, Generating a first digitally encoded constructive stimulus, which includes generating a first digitally encoded calibration stimulus having a first magnitude in a first frequency bin, and comprising filtering a multi-bit sequence encoding a sine wave to generate a 1-bit sequence approximating the sine wave without using a feedback loop, The first digitally encoded calibration stimulus is scaled by a first weighting coefficient to generate a first weighted calibration stimulus, The first weighted calibration stimulus is provided to the redundant DAC cell of the DAC to generate the first analog tone, While the first weighted calibration stimulus is provided to the redundant DAC cell of the DAC, digital data and an inverted version of the first weighted calibration stimulus are provided to the non-redundant DAC cell of the DAC to generate an output and a second analog tone. The analog output of the DAC includes detecting an error tone generated from the first analog tone and the second analog tone, A method in which a portion of the redundant DAC cells are swapped with a portion of non-redundant DAC cells that generate outputs with analog outputs over different periods of time.

11. To generate a second digitally encoded calibration stimulus having a second magnitude in a second frequency bin, The second digitally encoded calibration stimulus is scaled by a second weighting coefficient to generate a second weighted calibration stimulus, The method involves providing the second weighted calibration stimulus to a further redundant DAC cell to generate a third analog tone, wherein an inverted version of the second weighted calibration stimulus is further provided to the DAC cell along with the digital data and the inverted version of the first weighted calibration stimulus to generate a fourth analog tone along with the output and the second analog tone. The method according to claim 10, further comprising detecting an additional error tone arising from the third analog tone and the fourth analog tone at the analog output of the DAC.

12. A background method for measuring either or both of the static error between DAC cells and the timing error between DAC cells of a multi-gigabit-per-second DAC having multiple DAC cells, wherein the multiple DAC cells include multiple redundant DAC cells, the multiple DAC cells include multiple redundant DAC cells. Providing digital data to a DAC cell of the DAC that is not a redundant DAC cell, and generating an output at the analog output of the DAC, Generating a first digitally encoded constructive stimulus, which includes generating a first digitally encoded calibration stimulus having a first magnitude in a first frequency bin, and comprising filtering a multi-bit sequence encoding a sine wave to generate a 1-bit sequence approximating the sine wave without using a feedback loop, The first digitally encoded calibration stimulus is scaled by a first weighting coefficient, and the first weighted calibration stimulus is provided to a subset of the first redundant DAC cells of the DAC while the DAC cells that are not redundant DAC cells generate the output, thereby generating a first analog tone. The method involves scaling the first digitally encoded calibration stimulus by a second weighting coefficient, and providing the second weighted calibration stimulus to a subset of the second redundant DAC cells of the DAC while the DAC cells that are not redundant DAC cells generate the output, thereby generating a second analog tone, wherein the second weighting coefficient is selected such that the first analog tone and the second analog tone have opposite polarities, and the second weighting coefficient differs from the first weighting coefficient, and the sum of the first analog tone and the second analog tone generates an error tone. The analog output of the DAC includes detecting the magnitude of the first frequency bin in the analog output of the DAC by detecting the first frequency bin, thereby detecting the error tone in the first frequency bin resulting from the first analog tone and the second analog tone. A method in which a portion of the redundant DAC cells are swapped with a portion of non-redundant DAC cells that generate outputs with analog outputs over different periods of time.

13. The method according to claim 12, further comprising iteratively minimizing the error tone by using a least mean squares or binary search algorithm.

14. The method of claim 12, further comprising iteratively minimizing the error tone by adjusting a subset of the first redundant DAC cells or a subset of the second redundant DAC cells in the analog domain.

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