Wiring board
The wiring board design with a continuous seed layer and electroplating layer on the inner wall surface of the opening addresses filler detachment issues, enhancing adhesion and integrity between the wiring and insulating layers.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SHINKO ELECTRIC IND CO LTD
- Filing Date
- 2025-04-10
- Publication Date
- 2026-06-24
Smart Images
Figure 0007879975000001 
Figure 0007879975000002 
Figure 0007879975000003
Abstract
Description
Technical Field
[0001] The present invention relates to a wiring board.
Background Art
[0002] There is known a wiring board having an insulating layer covering a first wiring layer, an opening exposing an upper surface of the first wiring layer formed in the insulating layer, and a second wiring layer filling the opening and extending over the upper surface of the insulating layer.
[0003] The second wiring layer is formed, for example, as follows. First, an opening exposing the upper surface of the first wiring layer is formed in the insulating layer. Then, after performing a pretreatment for plating on the entire surface of the insulating layer including the inside of the opening, a seed layer is formed. Next, selective electrolytic plating is performed with the seed layer as a base to form an electrolytic plating layer. Thereafter, an unnecessary seed layer is removed by etching using the electrolytic plating layer as a mask, and a second wiring layer composed of the seed layer and the electrolytic plating layer is formed (see, for example, Patent Document 1).
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] However, there are cases where the insulating layer contains a filler. In this case, there is a risk that the filler exposed on the inner wall surface of the opening during the pretreatment for plating may fall off. When the filler falls off, since the pretreatment for plating is not performed in the recess formed at the portion where the filler has fallen off, the inside of the recess becomes a non-deposited portion of the seed layer. Since the growth of electrolytic plating is inhibited at the non-deposited portion of the seed layer, the adhesion between the second wiring layer and the insulating layer decreases.
[0006] The present invention has been made in view of the above points, and aims to provide a wiring substrate with improved adhesion between the wiring layer and the insulating layer. [Means for solving the problem]
[0007] The wiring board comprises an insulating layer containing a filler that covers a first wiring layer, an opening formed in the insulating layer that exposes the upper surface of the first wiring layer, and a second wiring layer that fills the opening and is electrically connected to the first wiring layer, and extends from within the opening to the upper surface of the insulating layer. The second wiring layer includes via wiring that fills the opening and is electrically connected to the first wiring layer, and a wiring pattern and / or pads formed on the via wiring. A recess is formed on the inner wall surface of the opening, which is the trace of the filler removal. The second wiring layer has a structure in which an electroplated layer is laminated on a seed layer, and at least the inner wall surface of the opening and the inside of the opening A catalyst is adsorbed on the surface of the filler exposed from the wall surface, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening. The seed layer is formed on the catalyst continuously along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening. The electroplating layer is formed on the seed layer continuously along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening, filling the opening, including the interior of the recess. [Effects of the Invention]
[0008] According to the disclosed technology, it is possible to provide a wiring board with improved adhesion between the wiring layer and the insulating layer. [Brief explanation of the drawing]
[0009] [Figure 1] This is a cross-sectional view illustrating a wiring board according to the first embodiment. [Figure 2] This is a diagram (part 1) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 3] This is a diagram (part 2) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 4] This is a diagram (part 3) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 5] This is a diagram (part 4) illustrating the manufacturing process of a wiring board according to the first embodiment. [Figure 6] This is a diagram (part 1) illustrating a method for manufacturing a wiring board according to a comparative example. [Figure 7] This is a diagram (part 2) illustrating a method for manufacturing a wiring board according to a comparative example. [Figure 8] This is a cross-sectional view illustrating a wiring board according to the second embodiment. [Figure 9] This is a diagram (part 1) illustrating the manufacturing process of a wiring board according to the second embodiment. [Figure 10] This is a diagram (part 2) illustrating the manufacturing process of a wiring board according to the second embodiment. [Figure 11] This is a cross-sectional view illustrating a semiconductor package according to an application example of the first embodiment. [Modes for carrying out the invention]
[0010] The embodiments for carrying out the invention will be described below with reference to the drawings. In each drawing, the same reference numerals are used for identical components, and redundant explanations may be omitted.
[0011] <First Embodiment> [Structure of the wiring board according to the first embodiment] Figure 1 is a cross-sectional view illustrating a wiring board according to the first embodiment, where Figure 1(a) is an overall view and Figure 1(b) is a partial enlarged view of part A in Figure 1(a).
[0012] Referring to Figure 1, the wiring board 1 is a wiring board in which a wiring layer and an insulating layer are laminated on both sides of a core layer 10.
[0013] Specifically, in the wiring board 1, on one surface 10a of the core layer 10, a wiring layer 12, an insulating layer 13, a wiring layer 14, an insulating layer 15, a wiring layer 16, a solder resist layer 17, and a wiring layer 18 are sequentially laminated. On the other surface 10b of the core layer 10, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, and a solder resist layer 27 are sequentially laminated.
[0014] In the first embodiment, for convenience, the side of the solder resist layer 17 of the wiring board 1 is regarded as the upper side or one side, and the side of the solder resist layer 27 is regarded as the lower side or the other side. Also, the surface on the side of the solder resist layer 17 of each part is regarded as one surface or the upper surface, and the surface on the side of the solder resist layer 27 is regarded as the other surface or the lower surface. However, the wiring board 1 can be used in an upside-down state or arranged at an arbitrary angle. Also, the plan view means viewing the object from the normal direction of one surface 10a of the core layer 10, and the planar shape means the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.
[0015] As the core layer 10, for example, a so-called glass epoxy substrate obtained by impregnating a glass cloth with an insulating resin such as an epoxy resin can be used. As the core layer 10, a substrate obtained by impregnating a woven fabric or non-woven fabric of glass fiber, carbon fiber, aramid fiber, etc. with an epoxy resin or the like may also be used. The thickness of the core layer 10 is, for example, about 60 to 1000 μm. The core layer 10 is provided with through holes 10x penetrating in the thickness direction. The planar shape of the through holes 10x is, for example, circular.
[0016] The wiring layer 12 is formed on one surface 10a of the core layer 10. Also, the wiring layer 22 is formed on the other surface 10b of the core layer 10. The wiring layer 12 and the wiring layer 22 are electrically connected by a through-wiring 11 formed in the through-hole 10x. The wiring layers 12 and 22 are each patterned into a predetermined planar shape. As the material of the wiring layers 12 and 22 and the through-wiring 11, for example, copper (Cu) or the like can be used. The thickness of the wiring layers 12 and 22 is, for example, about 10 to 40 μm. Note that the wiring layer 12, the wiring layer 22, and the through-wiring 11 may be integrally formed.
[0017] The insulating layer 13 is an interlayer insulating layer formed so as to cover the wiring layer 12 on one surface 10a of the core layer 10. As the material of the insulating layer 13, for example, a non-photosensitive thermosetting resin mainly composed of an epoxy-based resin or the like can be used. The thickness of the insulating layer 13 is, for example, about 25 to 40 μm. The insulating layer 13 contains a filler such as silicon dioxide (SiO2), for example. The particle size of the filler is, for example, about 0.1 to 10 μm. The content of the filler is, for example, about 30 to 80% by weight.
[0018] The insulating layer 13 has a via hole 13x which is an opening. The via hole 13x penetrates the insulating layer 13 and exposes the upper surface of the wiring layer 12. The wiring layer 14 fills the via hole 13x and is electrically connected to the wiring layer 12, and extends from within the via hole 13x to the upper surface of the insulating layer 13. Specifically, the wiring layer 14 includes a via wiring filled in the via hole 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 via the via wiring. The via hole 13x is, for example, an inverted frustum-shaped recess in which the diameter of the opening on the insulating layer 15 side is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 12. The material of the wiring layer 14 and the thickness of the wiring pattern are, for example, the same as those of the wiring layer 12.
[0019] The insulating layer 15 is an interlayer insulating layer formed to cover the wiring layer 14 on the upper surface of the insulating layer 13. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. The insulating layer 15 contains, for example, the same fillers as the insulating layer 13.
[0020] The insulating layer 15 has via holes 15x, which are openings. The via holes 15x penetrate the insulating layer 15 and expose the upper surface of the wiring layer 14. The wiring layer 16 fills the via holes 15x and is electrically connected to the wiring layer 14, extending from within the via holes 15x to the upper surface of the insulating layer 15. In detail, the wiring layer 16 includes via wiring filled within the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 via the via wiring. The via holes 15x are, for example, inverted frustoconical recesses in which the diameter of the opening that opens towards the solder resist layer 17 is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 14. The material and thickness of the wiring pattern of the wiring layer 16 are, for example, the same as those of the wiring layer 12.
[0021] The solder resist layer 17 is a protective insulating layer located on the outermost side of the wiring substrate 1, and is formed to cover the wiring layer 16 on the upper surface of the insulating layer 15. The solder resist layer 17 can be formed from, for example, a photosensitive resin mainly composed of epoxy resin. The thickness of the solder resist layer 17 is, for example, about 15 to 35 μm.
[0022] The solder resist layer 17 contains fillers 171, such as silicon dioxide (SiO2) or barium sulfate (BaSO4). The particle size of the fillers 171 is, for example, about 0.3 to 4 μm. The content of fillers 171 is, for example, about 30 to 60% by weight.
[0023] The solder resist layer 17 has an opening 17x. The opening 17x penetrates the solder resist layer 17 and exposes the upper surface of the wiring layer 16. The wiring layer 18 fills the opening 17x and is electrically connected to the wiring layer 16, extending from within the opening 17x to the upper surface of the solder resist layer 17. In detail, the wiring layer 18 includes via wiring filled within the opening 17x and pads formed on the upper surface of the solder resist layer 17. The pads constituting the wiring layer 18 are electrically connected to the wiring layer 16 via wiring. The opening 17x is, for example, an inverted frustoconical recess in which the diameter of the opening opening on the surface side of the solder resist layer 17 is larger than the diameter of the bottom surface of the opening formed by the upper surface of the wiring layer 16.
[0024] The planar shape of the pads constituting the wiring layer 18 is, for example, circular with a diameter of approximately 35 to 85 μm. The pitch of the pads constituting the wiring layer 18 is, for example, approximately 40 to 100 μm. The thickness of the pads constituting the wiring layer 18 is, for example, approximately 10 to 30 μm. The pads constituting the wiring layer 18 function as electronic component mounting pads for electrically connecting to electronic components such as semiconductor chips.
[0025] The wiring layer 18 has a seed layer 181 and an electroplating layer 182, with the electroplating layer 182 laminated on the seed layer 181. The seed layer 181 is continuously formed in the region located around the opening 17x on the upper surface of the solder resist layer 17, on the inner wall surface of the opening 17x, and on the upper surface of the wiring layer 16 exposed within the opening 17x. The material of the seed layer 181 is, for example, copper. The thickness of the seed layer 181 is, for example, about 0.3 to 1 μm. The material of the electroplating layer 182 is, for example, copper. The material of the electroplating layer 182 may be nickel or tin in addition to copper.
[0026] As shown in Figure 1(b), the filler 171 contained in the solder resist layer 17 may partially protrude from the inner wall of the opening 17x, or a recess 17y, which is the trace left by the detachment of the filler 171 contained in the solder resist layer 17, may be formed on the inner wall surface of the opening 17x. In such cases, the seed layer 181 is also formed on the surface of the filler 171 exposed from the inner wall surface of the opening 17x, and on the inner wall surface of the recess 17y.
[0027] In other words, the seed layer 181 is formed with a substantially uniform thickness in the region surrounding the opening 17x on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed within the opening 17x. The reason for this will be explained in the section on the manufacturing method of the wiring board 1.
[0028] The electroplating layer 182 is formed on the seed layer 181. The electroplating layer 182 fills the opening 17x and extends above the upper surface of the seed layer 181 located around the opening 17x. Here, the portion of the wiring layer 18 that is filled into the opening 17x is called a via, and the portion that protrudes from the upper surface of the solder resist layer 17 is called a pad.
[0029] Furthermore, a metal layer may be formed on the surface of the pads constituting the wiring layer 18, or an organic coating may be formed by applying an anti-oxidation treatment such as OSP (Organic Solderability Preservative) treatment. Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which Ni and Au layers are stacked in that order), a Ni / Pd / Au layer (a metal layer in which Ni, Pd, and Au layers are stacked in that order), and a Sn layer.
[0030] The insulating layer 23 is an interlayer insulating layer formed to cover the wiring layer 22 on the other surface 10b of the core layer 10. The material and thickness of the insulating layer 23 are, for example, the same as those of the insulating layer 13. The insulating layer 23 contains, for example, the same fillers as the insulating layer 13.
[0031] The insulating layer 23 has via holes 23x, which are openings. The via holes 23x penetrate the insulating layer 23 and expose the underside of the wiring layer 22. The wiring layer 24 fills the via holes 23x and is electrically connected to the wiring layer 22, extending from within the via holes 23x to the underside of the insulating layer 23. In detail, the wiring layer 24 includes via wiring filled within the via holes 23x and a wiring pattern formed on the underside of the insulating layer 23. The wiring pattern of the wiring layer 24 is electrically connected to the wiring layer 22 via the via wiring. The via holes 23x are, for example, frustoconical recesses in which the diameter of the opening that opens towards the insulating layer 25 is larger than the diameter of the bottom of the opening formed by the underside of the wiring layer 22. The material and thickness of the wiring pattern of the wiring layer 24 are, for example, the same as those of the wiring layer 12.
[0032] The insulating layer 25 is an interlayer insulating layer formed to cover the wiring layer 24 on the lower surface of the insulating layer 23. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. The insulating layer 25 contains, for example, the same fillers as the insulating layer 13.
[0033] The insulating layer 25 has via holes 25x, which are openings. The via holes 25x penetrate the insulating layer 25 and expose the underside of the wiring layer 24. The wiring layer 26 fills the via holes 25x and is electrically connected to the wiring layer 24, extending from within the via holes 25x to the underside of the insulating layer 25. In detail, the wiring layer 26 includes via wiring filled within the via holes 25x and a wiring pattern formed on the underside of the insulating layer 25. The wiring pattern of the wiring layer 26 is electrically connected to the wiring layer 24 via the via wiring. The via holes 25x are, for example, frustoconical recesses in which the diameter of the opening that opens towards the solder resist layer 27 is larger than the diameter of the bottom of the opening formed by the underside of the wiring layer 24. The material and thickness of the wiring pattern of the wiring layer 26 are, for example, the same as those of the wiring layer 12.
[0034] The solder resist layer 27 is a protective insulating layer located on the outermost side of the wiring substrate 1, and is formed to cover the wiring layer 26 on the underside of the insulating layer 25. The material and thickness of the solder resist layer 27 are, for example, the same as those of the solder resist layer 17. The solder resist layer 27 contains, for example, the same fillers as the solder resist layer 17.
[0035] The solder resist layer 27 has an opening 27x, and a portion of the lower surface of the wiring layer 26 is exposed within the opening 27x. The planar shape of the opening 27x is, for example, circular. The wiring layer 26 exposed within the opening 27x can be used as a pad for electrically connecting to a mounting substrate (not shown), such as a motherboard. If necessary, the aforementioned metal layer may be formed on the lower surface of the wiring layer 26 exposed within the opening 27x, or an anti-oxidation treatment such as OSP treatment may be applied to form an organic coating.
[0036] [Manufacturing method for a wiring board according to the first embodiment] Figures 2 to 5 illustrate the manufacturing process of a wiring board according to the first embodiment. Figures 2, 4(a), 4(c), and 5 are cross-sectional views corresponding to Figure 1(a), and Figures 3 and 4(b) are cross-sectional views corresponding to Figure 1(b). Here, an example of the process for manufacturing one wiring board is shown, but it is also possible to manufacture multiple parts that will become wiring boards and then separate them into individual wiring boards.
[0037] First, in the process shown in Figure 2(a), through-wiring 11, wiring layers 12 and 22 are formed in the core layer 10. Specifically, for example, a laminate is prepared in which plain, unpatterned copper foil is formed on one surface 10a and the other surface 10b of the core layer 10, which is a so-called glass epoxy substrate. Then, in the prepared laminate, after thinning the copper foil on each surface as necessary, through-holes 10x that penetrate the core layer 10 and the copper foil on each surface are formed by laser processing using a CO2 laser or the like.
[0038] Next, if necessary, desmear treatment is performed to remove any resin residue from the core layer 10 that has adhered to the inner wall surface of the through-hole 10x. Then, a seed layer (copper, etc.) is formed to cover the copper foil on each surface and the inner wall surface of the through-hole 10x by methods such as electroless plating or sputtering, and an electroplated layer (copper, etc.) is formed on the seed layer by an electroplating method that uses the seed layer as a power supply layer. As a result, the through-hole 10x is filled with the electroplated layer formed on the seed layer, and wiring layers 12 and 22 are formed on one surface 10a and the other surface 10b of the core layer 10, with the copper foil, seed layer, and electroplated layer laminated together. Next, the wiring layers 12 and 22 are patterned into a predetermined planar shape by methods such as subtractive plating.
[0039] Next, in the process shown in Figure 2(b), a non-photosensitive thermosetting resin mainly composed of a semi-cured film-like epoxy resin is laminated to one surface 10a of the core layer 10 to cover the wiring layer 12, and then cured to form an insulating layer 13. Similarly, a non-photosensitive thermosetting resin mainly composed of a semi-cured film-like epoxy resin is laminated to the other surface 10b of the core layer 10 to cover the wiring layer 22, and then cured to form an insulating layer 23. Alternatively, instead of laminating with a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied and then cured to form the insulating layers 13 and 23. The thickness of each insulating layer 13 and 23 is, for example, about 25 to 40 μm.
[0040] Each of the insulating layers 13 and 23 contains a filler, for example, silicon dioxide (SiO2). The particle size of the filler is, for example, about 0.1 to 10 μm. The filler content is, for example, about 30 to 80% by weight.
[0041] Next, via holes 13x are formed in the insulating layer 13, which are openings that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12. Similarly, via holes 23x are formed in the insulating layer 23, which are openings that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. The via holes 13x and 23x can be formed, for example, by a laser processing method using a CO2 laser. After forming the via holes 13x and 23x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surfaces of the wiring layers 12 and 22 exposed at the bottom of the via holes 13x and 23x, respectively.
[0042] Next, the via holes 13x are filled and electrically connected to the wiring layer 12, forming a wiring layer 14 that extends from within the via holes 13x to the upper surface of the insulating layer 13. The wiring layer 14 includes via wiring filled within the via holes 13x and a wiring pattern formed on the upper surface of the insulating layer 13. The material and thickness of the wiring pattern of the wiring layer 14 are, for example, the same as those of the wiring layer 12. The wiring pattern of the wiring layer 14 is electrically connected to the wiring layer 12 exposed at the bottom of the via holes 13x.
[0043] Furthermore, the via holes 23x are filled and electrically connected to the wiring layer 22, forming a wiring layer 24 that extends from within the via holes 23x to the lower surface of the insulating layer 23. The wiring layer 24 includes via wiring filled within the via holes 23x and a wiring pattern formed on the lower surface of the insulating layer 23. The material and thickness of the wiring pattern of the wiring layer 24 are, for example, the same as those of the wiring layer 12. The wiring layer 24 is electrically connected to the wiring layer 22 exposed at the bottom of the via holes 23x. The wiring layers 14 and 24 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.
[0044] Next, an insulating layer 15 is formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14, using the same formation method as the insulating layer 13. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. Then, via holes 15x are formed using the same formation method as those of the via holes 13x. Furthermore, an insulating layer 25 is formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24, using the same formation method as the insulating layer 13. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. Then, via holes 25x are formed using the same formation method as those of the via holes 13x. Each of the insulating layers 15 and 25 contains, for example, the same filler as the insulating layer 13.
[0045] After forming via holes 15x and 25x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surfaces of the wiring layers 14 and 24 that are exposed at the bottom of the via holes 15x and 25x, respectively.
[0046] Next, the via holes 15x are filled and electrically connected to the wiring layer 14, forming a wiring layer 16 that extends from within the via holes 15x to the upper surface of the insulating layer 15. The wiring layer 16 includes via wiring filled within the via holes 15x and a wiring pattern formed on the upper surface of the insulating layer 15. The material and thickness of the wiring pattern of the wiring layer 16 are, for example, the same as those of the wiring layer 12. The wiring pattern of the wiring layer 16 is electrically connected to the wiring layer 14 exposed at the bottom of the via holes 15x.
[0047] Furthermore, the via holes 25x are filled and electrically connected to the wiring layer 24, forming a wiring layer 26 that extends from within the via holes 25x to the lower surface of the insulating layer 25. The wiring layer 26 includes via wiring filled within the via holes 25x and a wiring pattern formed on the lower surface of the insulating layer 25. The material and thickness of the wiring pattern of the wiring layer 26 are, for example, the same as those of the wiring layer 12. The wiring layer 26 is electrically connected to the wiring layer 24 exposed at the bottom of the via holes 25x. The wiring layers 16 and 26 can be formed using various wiring formation methods such as the semi-additive method and the subtractive method.
[0048] Next, in the process shown in Figure 2(c), a solder resist layer 17 is formed on the upper surface of the insulating layer 15 so as to cover the wiring layer 16. Also, a solder resist layer 27 is formed on the lower surface of the insulating layer 25 so as to cover the wiring layer 26. The solder resist layer 17 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin to the upper surface of the insulating layer 15 by screen printing, roll coating, or spin coating so as to cover the wiring layer 16. Alternatively, for example, a film-like photosensitive epoxy insulating resin may be laminated to the upper surface of the insulating layer 15 so as to cover the wiring layer 16. The method for forming the solder resist layer 27 is the same as for the solder resist layer 17.
[0049] The solder resist layers 17 and 27 contain fillers 171, such as silicon dioxide (SiO2) or barium sulfate (BaSO4). The particle size of the fillers 171 is, for example, about 0.3 to 4 μm. The content of fillers 171 is, for example, about 30 to 60% by weight.
[0050] Next, in the process shown in Figure 2(d), the solder resist layers 17 and 27 are exposed and developed to form an opening 17x in the solder resist layer 17 that exposes a portion of the upper surface of the wiring layer 16 (photolithography method). Also, an opening 27x is formed in the solder resist layer 27 that exposes a portion of the lower surface of the wiring layer 26 (photolithography method). The planar shape of each of the openings 17x and 27x is, for example, circular. The diameters of each of the openings 17x and 27x can be arbitrarily designed to match the object to be connected (semiconductor chip, etc.).
[0051] Figure 3(a) is an enlarged view of section B in Figure 2(d). As shown in Figure 3(a), when an opening 17x is formed in the solder resist layer 17, for example, the filler 171 is exposed on the inner wall surface of the opening 17x. Also, although not shown, when an opening 27x is formed in the solder resist layer 27, for example, the filler is exposed on the inner wall surface of the opening 27x.
[0052] Next, in the process shown in Figure 3(b), a first alkaline treatment is performed as a pretreatment for electroless plating. Specifically, for example, the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed inside the opening 17x are treated with a treatment solution made by adding an appropriate amount of surfactant to 1.5-2% sodium hydroxide, at a temperature of about 50-60°C for about 4-5 minutes. Examples of surfactants include octylphenol ethoxylate (ether compound).
[0053] The first alkaline treatment cleans and conditions the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed within the opening 17x. In Figure 3(b), the cleaned and conditioned surfaces are shown with dashed lines for convenience.
[0054] Here, cleaning is a surface cleaning process for the solder resist layer 17 in order to form a seed layer (electroless plating layer) on the surface of the solder resist layer 17. Conditioning is a surface adjustment process for the solder resist layer 17.
[0055] In this embodiment, a seed layer is formed on the surface of the solder resist layer 17 by electroless plating. Cleaning and conditioning facilitate the adsorption of a catalyst (such as palladium) for depositing electroless plating onto the surface of the solder resist layer 17. The presence of the catalyst allows for the formation of a good electroless plating layer on the surface of the solder resist layer 17. In other words, a good seed layer for forming an electroplating layer can be formed on the surface of the solder resist layer 17.
[0056] Furthermore, the first alkali treatment wets and swells the resin constituting the solder resist layer 17. This treatment reduces the force with which the solder resist layer 17 holds the filler 171 at the opening 17x, making it easier for the filler 171 to detach from the solder resist layer 17.
[0057] Next, in the process shown in Figure 3(c), an ultrasonic cleaning treatment is performed. The ultrasonic cleaning treatment is, for example, ultrasonic water washing by applying ultrasonic vibrations at a frequency of 35 to 50 kHz, and the treatment time is about 3 to 10 minutes. The ultrasonic cleaning treatment removes the filler 171 that had become prone to falling off in the process shown in Figure 3(b), and after removal, a recess 17y is formed on the inner wall surface of the opening 17x, which is the trace of where the filler 171 was removed. The removed filler 171 is removed from inside the opening 17x by the ultrasonic cleaning treatment. Even if there is filler 171 that has fallen off before the ultrasonic cleaning treatment, the fallen filler 171 is also removed from inside the opening 17x by the ultrasonic cleaning treatment. The recess 17y is in a state where cleaning and conditioning have not been performed. In Figure 3(c), the surface that has been cleaned and conditioned is shown with a dashed line for convenience.
[0058] Next, in the process shown in Figure 3(d), a second alkali treatment is performed. The second alkali treatment is performed under conditions that make it less likely for the filler 171 to detach from the solder resist layer 17 than the first alkali treatment.
[0059] The second alkaline treatment can be carried out, for example, using the same type of treatment solution as the first alkaline treatment. In this case, the second alkaline treatment can be carried out under the following conditions: that one or more of the following conditions are met: (1) the treatment temperature of the first alkaline treatment > the treatment temperature of the second alkaline treatment, (2) the treatment time of the first alkaline treatment > the treatment time of the second alkaline treatment, and (3) the treatment solution concentration of the first alkaline treatment > the treatment solution concentration of the second alkaline treatment.
[0060] In other words, when the second alkaline treatment is performed using the same type of treatment solution as the first alkaline treatment, the second alkaline treatment may be performed in a manner that satisfies one of the following conditions: (1), (2), or (3); (1) and (2); (1) and (3); (2) and (3); or (1), (2), and (3).
[0061] Specifically, for example, the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed within the opening 17x are treated with a solution of 1-1.5% sodium hydroxide with an appropriate amount of surfactant at a temperature of about 40-50°C for about 3-4 minutes. This is an example of a second alkaline treatment that satisfies all of the conditions of (1), (2), and (3).
[0062] The second alkaline treatment cleans and conditions the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed within the opening 17x. In Figure 3(d), the cleaned and conditioned surfaces are shown with dashed lines for convenience.
[0063] The second alkali treatment is performed under conditions that make it less likely for the filler 171 to detach from the solder resist layer 17 than the first alkali treatment, so the resin constituting the solder resist layer 17 is less likely to become wet. Therefore, no new filler 171 detaches during the second alkali treatment. In other words, the conditions for the second alkali treatment should be determined so that no new filler 171 detaches during the second alkali treatment.
[0064] Next, in the process shown in Figure 4(a), a seed layer 181 is continuously formed on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed within the opening 17x. Additionally, a seed layer 281 is continuously formed on the lower surface of the solder resist layer 27, the inner wall surface of the opening 27x, and the lower surface of the wiring layer 26 exposed within the opening 27x. The material of the seed layers 181 and 281 is, for example, copper. The thickness of the seed layers 181 and 281 is, for example, about 0.3 to 1 μm. The seed layers 181 and 281 can be formed, for example, by electroless plating.
[0065] Figure 4(b) is an enlarged view of section B in Figure 4(a). As shown in Figure 4(b), the seed layer 181 is also formed on the surface of the filler 171 exposed from the inner wall surface of the opening 17x, and on the inner wall surface of the recess 17y. In other words, the seed layer 181 is formed with a substantially uniform thickness on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, the surface of the filler 171 exposed from the inner wall surface of the opening 17x, the inner wall surface of the recess 17y, and the upper surface of the wiring layer 16 exposed within the opening 17x. The same applies to the seed layer 281.
[0066] Next, in the process shown in Figure 4(c), a resist layer 310 is formed on the upper surface of the seed layer 181. A resist layer 320 is also formed on the lower surface of the seed layer 281. The resist layers 310 and 320 can be formed, for example, by laminating a photosensitive dry film resist.
[0067] Next, in the process shown in Figure 5(a), the resist layer 310 is exposed and developed to form an opening 310x in the resist layer 310 that exposes a portion of the seed layer 181. The opening 310x is made to match the shape of the electroplating layer formed on the seed layer 181.
[0068] Next, in the process shown in Figure 5(b), copper or the like is deposited on the seed layer 181 exposed within the opening 310x by an electroplating method powered from the seed layer 181, thereby selectively forming an electroplated layer 182. The electroplated layer 182 fills the opening 17x and is formed to extend above the upper surface of the seed layer 181 surrounding the opening 17x.
[0069] Next, in the process shown in Figure 5(c), the resist layers 310 and 320 are removed. The resist layers 310 and 320 can be removed, for example, using a stripping solution. After removing the resist layers 310 and 320, etching is performed using the electroplating layer 182 as a mask to remove the seed layer 181 exposed from the electroplating layer 182 and form the wiring layer 18.
[0070] When the seed layer 181 and the electroplating layer 182 are made of copper, an etching solution such as a hydrogen peroxide / sulfuric acid aqueous solution, a sodium persulfate aqueous solution, or an ammonium persulfate aqueous solution can be used. Simultaneously with the removal of the seed layer 181, the seed layer 281 is also removed. Thus, a wiring board 1 is obtained.
[0071] Figures 6 and 7 illustrate a method for manufacturing a wiring board according to a comparative example. In the method for manufacturing a wiring board according to the comparative example, in the step shown in Figure 6(a), an opening 17x is formed in the solder resist layer 17, similar to the step shown in Figure 3(a). Also, in the step shown in Figure 6(b), an alkaline treatment is performed as a pretreatment for electroless plating, similar to the step shown in Figure 3(a). However, in the method for manufacturing a wiring board according to the comparative example, the alkaline treatment is performed only once, corresponding to the first alkaline treatment in the method for manufacturing a wiring board according to the first embodiment, and there is no second alkaline treatment step. Furthermore, there is no ultrasonic cleaning step.
[0072] When alkali treatment is performed in the process shown in Figure 6(b), the resin constituting the solder resist layer 17 becomes wet and swells. As a result, as shown in Figure 6(c), the force with which the solder resist layer 17 holds the filler 171 at the opening 17x is reduced, and the filler 171 detaches from the solder resist layer 17.
[0073] In the manufacturing method of the wiring board according to the comparative example, ultrasonic cleaning is not performed, so the filler 171 that has detached from the solder resist layer 17 is not removed from inside the opening 17x. Furthermore, in the manufacturing method of the wiring board according to the comparative example, the second alkali treatment is not performed, so the inner wall surface of the recess 17y and a portion of the surface of the filler 171 that has detached into the opening 17x are not cleaned and conditioned. In Figure 6(c), the cleaned and conditioned surface is shown with a dashed line for convenience.
[0074] Next, as shown in Figure 6(d), a seed layer 181a is formed on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed within the opening 17x by electroless plating or the like. No catalyst is adsorbed on the inner wall surface of the recess 17y that has not been cleaned and conditioned, and electroless plating does not deposit there. Similarly, no catalyst is adsorbed on some parts of the surface of the detached filler 171 that has not been cleaned and conditioned, and electroless plating does not deposit there. As a result, the seed layer 181a is not formed continuously, but has discontinuous portions.
[0075] Next, the same steps as those shown in Figures 4(c) to 5(c) in the manufacturing method of the wiring board according to the first embodiment are performed. As a result, as shown in Figure 7(a), a wiring layer 18a is formed on the seed layer 181a, and the wiring board 1X according to the comparative example is completed. In the wiring board 1X, the electroplating layer 182a does not deposit near the areas where the seed layer 181a is not formed, so for example, voids B1 to B4 are formed in the opening 17x.
[0076] Next, consider the case where the wiring layer 18a of the wiring board 1X is electrically connected to the electrode pad 120 of the semiconductor chip 110 via a bump 130, such as a solder bump, as shown in Figure 7(b). As shown in Figure 7(a), voids B1 to B4 are formed within the opening 17x, and the locations where voids B1 to B4 exist are prone to becoming the starting points for cracks C1 and C2 when electrical or thermal loads are applied. If cracks C1 or C2 occur, it may cause poor electrical conductivity between the wiring layer 18a and the electrode pad 120, reducing the reliability of the connection between the wiring board 1X and the semiconductor chip 110.
[0077] In contrast, the method for manufacturing a wiring substrate according to the first embodiment includes, as described above, a step of sequentially performing a first alkali treatment, an ultrasonic cleaning treatment, and a second alkali treatment on the upper surface of the solder resist layer 17, the inner wall surface of the opening 17x, and the upper surface of the wiring layer 16 exposed inside the opening 17x, between the step of forming the opening 17x and the step of forming the wiring layer 18.
[0078] Therefore, since there are no areas that have not been cleaned or conditioned, the seed layer 181a is formed continuously without any undeposited areas. As a result, there are no areas where the electroplating layer 182 does not deposit, so no voids are formed within the opening 17x, and no cracks originating from voids occur.
[0079] As a result, the adhesion between the solder resist layer 17 and the wiring layer 18 is improved, and good adhesion is obtained between them. This avoids problems such as swelling of the wiring layer 18 due to poor adhesion between the solder resist layer 17 and the wiring layer 18.
[0080] Furthermore, since ultrasonic cleaning is performed on the wiring board 1, there is no residue of filler 171 at the bottom of the opening 17x. This ensures connection strength at the connection between the wiring layer 16 and the wiring layer 18 within the opening 17x, and improves the reliability of the connection between the wiring layer 16 and the wiring layer 18.
[0081] Furthermore, when the wiring layer 18 of the wiring board 1 is electrically connected to the electrode pad 120 of the semiconductor chip 110 via the bump 130, there is no risk of poor electrical conduction between the wiring layer 18 and the electrode pad 120. Therefore, the reliability of the connection between the wiring board 1 and the semiconductor chip 110 can be improved.
[0082] <Second Embodiment> In the second embodiment, an example is shown in which the method for manufacturing a wiring board according to the present invention is applied to the internal wiring of a wiring board. In the second embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.
[0083] [Structure of the wiring board according to the second embodiment] First, the structure of the wiring board according to the second embodiment will be described. Figure 8 is a cross-sectional view illustrating the wiring board according to the second embodiment, where Figure 8(a) is an overall view and Figure 8(b) is a partial enlarged view of section C in Figure 8(a).
[0084] Referring to Figure 8, in the wiring board 1A, the wiring layer 14 has the same structure as the wiring layer 18 of the first embodiment. That is, the wiring layer 14 has a seed layer 141 and an electroplating layer 142, with the electroplating layer 142 laminated on the seed layer 141. The wiring layers 16, 24, and 26 may have the same structure as the wiring layer 14.
[0085] The seed layer 141 is continuously formed in the region surrounding the via holes 13x on the upper surface of the insulating layer 13, on the inner wall surface of the via holes 13x, and on the upper surface of the wiring layer 12 exposed within the via holes 13x. The material of the seed layer 141 is, for example, copper. The thickness of the seed layer 141 is, for example, about 0.3 to 1 μm.
[0086] As shown in Figure 8(b), the filler 173 contained in the insulating layer 13 may partially protrude from the inner wall of the via hole 13x, or a recess 13y, which is the trace left by the detachment of the filler 173 contained in the insulating layer 13, may be formed on the inner wall surface of the via hole 13x. In such cases, the seed layer 141 is also formed on the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, and on the inner wall surface of the recess 13y.
[0087] In other words, the seed layer 141 is formed with a substantially uniform thickness in the area surrounding the via holes 13x on the upper surface of the insulating layer 13, the inner wall surface of the via holes 13x, the surface of the filler 173 exposed from the inner wall surface of the via holes 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed within the via holes 13x. The reason for this will be explained in the section on the manufacturing method of the wiring board 1A.
[0088] The electroplating layer 142 is formed on the seed layer 141. The electroplating layer 142 fills the via holes 13x and extends above the upper surface of the seed layer 141 located around the via holes 13x. Here, the portion of the wiring layer 14 that is filled into the via holes 13x is referred to as via wiring, and the portion that protrudes from the upper surface of the insulating layer 13 is referred to as the wiring pattern.
[0089] Furthermore, the wiring pattern constituting the wiring layer 14 may be routed from above the via holes 13x to any position on the upper surface of the insulating layer 13. In other words, the seed layer 141 may be routed from above the via holes 13x to any position on the upper surface of the insulating layer 13, and in that case as well, the electroplating layer 142 is laminated on the seed layer 141.
[0090] [Manufacturing method for a wiring board according to the second embodiment] Next, a method for manufacturing a wiring board according to the second embodiment will be described. Figures 9 and 10 illustrate the manufacturing process of a wiring board according to the second embodiment. Figures 9 and 10 are cross-sectional views corresponding to Figure 8(b). Here, an example of the process for manufacturing one wiring board is shown, but it is also possible to manufacture multiple parts that will become wiring boards and then separate them into individual wiring boards.
[0091] First, after performing the same steps as in Figure 2(a) of the first embodiment, a non-photosensitive thermosetting resin mainly composed of a semi-cured film-like epoxy resin is laminated to one surface 10a of the core layer 10 to cover the wiring layer 12, and then cured to form an insulating layer 13. Similarly, a non-photosensitive thermosetting resin mainly composed of a semi-cured film-like epoxy resin is laminated to the other surface 10b of the core layer 10 to cover the wiring layer 22, and then cured to form an insulating layer 23. Alternatively, instead of laminating with a film-like epoxy resin, a liquid or paste-like epoxy resin may be applied and then cured to form the insulating layers 13 and 23. The thickness of each insulating layer 13 and 23 is, for example, about 25 to 40 μm.
[0092] Each of the insulating layers 13 and 23 contains a filler 173, such as silicon dioxide (SiO2). The particle size of the filler 173 is, for example, about 0.1 to 10 μm. The content of the filler 173 is, for example, about 30 to 80% by weight.
[0093] From this point forward, only one side 10a of the core layer 10 will be illustrated and explained, but the same process is followed for the other side 10b of the core layer 10.
[0094] Next, in the process shown in Figure 9(a), via holes 13x are formed in the insulating layer 13, which are openings that penetrate the insulating layer 13 and expose the upper surface of the wiring layer 12. Also, via holes 23x are formed in the insulating layer 23, which are openings that penetrate the insulating layer 23 and expose the lower surface of the wiring layer 22. Filler 173 is exposed on the inner wall surfaces of via holes 13x and 23x. Via holes 13x and 23x can be formed, for example, by a laser processing method using a CO2 laser. After forming via holes 13x and 23x, it is preferable to perform a desmear treatment to remove resin residue adhering to the surfaces of the wiring layers 12 and 22 that are exposed at the bottom of the via holes 13x and 23x, respectively.
[0095] Next, in the process shown in Figure 9(b), a first alkaline treatment is performed as a pretreatment for electroless plating. The details of the first alkaline treatment are as described in the process shown in Figure 3(b).
[0096] The first alkaline treatment cleans and conditions the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, and the upper surface of the wiring layer 12 exposed inside the via hole 13x. In Figure 9(b), the cleaned and conditioned surfaces are shown with dashed lines for convenience.
[0097] Here, cleaning is a surface cleaning treatment of the insulating layer 13 in order to form a seed layer (electroless plating layer) on the surface of the insulating layer 13. Conditioning is a surface adjustment treatment of the insulating layer 13.
[0098] In this embodiment, a seed layer is formed on the surface of the insulating layer 13 by electroless plating. Cleaning and conditioning facilitate the adsorption of a catalyst (such as palladium) for depositing electroless plating onto the surface of the insulating layer 13. The presence of the catalyst allows for the formation of a good electroless plating layer on the surface of the insulating layer 13. In other words, a good seed layer for forming an electroplating layer can be formed on the surface of the insulating layer 13.
[0099] Furthermore, the first alkaline treatment cleans and conditions the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, the surface of the filler 173 exposed from the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed inside the via hole 23x.
[0100] Furthermore, the first alkali treatment causes the resin constituting the insulating layer 13 to become wet and swell. This treatment reduces the force with which the insulating layer 13 holds the filler 173 within the via hole 13x, making it easier for the filler 173 to detach from the insulating layer 13. Furthermore, the first alkali treatment causes the resin constituting the insulating layer 23 to become wet and swell. This treatment reduces the force with which the insulating layer 23 holds the filler 173 within the via hole 23x, making it easier for the filler 173 to detach from the insulating layer 23.
[0101] Next, in the process shown in Figure 9(c), an ultrasonic cleaning treatment is performed. The details of the ultrasonic cleaning treatment are as described in the process shown in Figure 3(c).
[0102] The ultrasonic cleaning process removes the filler 173 that was prone to falling off in the process shown in Figure 9(b). After removal, a recess 13y is formed on the inner wall surface of the via hole 13x, which is the trace left by the removal of the filler 173. The removed filler 173 is removed from inside the via hole 13x by the ultrasonic cleaning process. Even if there is any filler 173 that has fallen off before the ultrasonic cleaning process, the fallen filler 173 is also removed from inside the via hole 13x by the ultrasonic cleaning process. The recess 13y formed on the inner wall surface of the via hole 13x is in an uncleaned and unconditioned state. In Figure 9(c), the cleaned and conditioned surface is shown with a dashed line for convenience.
[0103] Next, in the process shown in Figure 9(d), a second alkaline treatment is performed. The details of the second alkaline treatment are as described in the process shown in Figure 3(d).
[0104] The second alkaline treatment cleans and conditions the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed within the via hole 13x. In Figure 9(d), the cleaned and conditioned surfaces are shown with dashed lines for convenience.
[0105] Furthermore, the second alkaline treatment cleans and conditions the lower surface of the insulating layer 23, the inner wall surface of the via hole 23x, the surface of the filler 173 exposed from the inner wall surface of the via hole 23x, the inner wall surface of the recess formed in the inner wall surface of the via hole 23x, and the lower surface of the wiring layer 22 exposed inside the via hole 23x.
[0106] Next, in the process shown in Figure 10(a), seed layers 141 are continuously formed on the upper surface of the insulating layer 13, the inner wall surface of the via holes 13x, and the upper surface of the wiring layer 12 exposed within the via holes 13x. Also, seed layers are continuously formed on the lower surface of the insulating layer 23, the inner wall surface of the via holes 23x, and the lower surface of the wiring layer 22 exposed within the via holes 23x. The material of the seed layers 141 is, for example, copper. The thickness of the seed layers 141 is, for example, about 0.3 to 1 μm. The seed layers 141 can be formed, for example, by electroless plating. The material, thickness, and manufacturing method of the seed layer formed on the lower surface of the wiring layer 22 are the same as those of the seed layers 141.
[0107] The seed layer 141 is also formed on the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, and on the inner wall surface of the recess 13y. In other words, the seed layer 141 is formed with a substantially uniform thickness on the upper surface of the insulating layer 13, the inner wall surface of the via hole 13x, the surface of the filler 173 exposed from the inner wall surface of the via hole 13x, the inner wall surface of the recess 13y, and the upper surface of the wiring layer 12 exposed inside the via hole 13x. The same applies to the seed layer formed on the lower surface of the wiring layer 22.
[0108] Next, in the process shown in Figure 10(b), wiring layers 14 and 24 are formed. Specifically, for example, a resist layer having an opening that matches the shape of the wiring layer 14 is formed on the seed layer 141. Then, by an electroplating method powered from the seed layer 141, copper or the like is deposited on the seed layer 141 exposed within the opening of the resist layer, thereby selectively forming an electroplated layer 142. Next, after removing the resist layer, etching is performed using the electroplated layer 142 as a mask, and the seed layer 141 exposed from the electroplated layer 142 is removed, thereby forming a wiring layer 14 in which the electroplated layer 142 is laminated on the seed layer 141. The wiring layer 24 can be formed by the same method.
[0109] After the process shown in Figure 10(b), an insulating layer 15 is formed on the upper surface of the insulating layer 13 so as to cover the wiring layer 14, using the same formation method as the insulating layer 13. The material and thickness of the insulating layer 15 are, for example, the same as those of the insulating layer 13. Also, an insulating layer 25 is formed on the lower surface of the insulating layer 23 so as to cover the wiring layer 24, using the same formation method as the insulating layer 13. The material and thickness of the insulating layer 25 are, for example, the same as those of the insulating layer 13. Then, the same process as in Figures 9(a) to 10(b) is performed to form a wiring layer 16 on one side of the insulating layer 15, with an electroplated layer formed on a seed layer. Also, a wiring layer 26 is formed on the other side of the insulating layer 25, with an electroplated layer formed on a seed layer.
[0110] Next, the wiring board 1A is completed by performing the same steps as in Figures 2(c) to 5(c) of the first embodiment.
[0111] Thus, the method for manufacturing a wiring board according to the present invention may be applied to the internal wiring (wiring layers 14, 16, 24, and 26) of the wiring board 1A. This will produce the same effects as in the first embodiment.
[0112] <Application examples of the first embodiment> The application example of the first embodiment shows an example of a semiconductor package in which a semiconductor chip is mounted on a wiring board according to the first embodiment. In the application example of the first embodiment, descriptions of components that are the same as those described in the previously described embodiments may be omitted.
[0113] Figure 11 is a cross-sectional view illustrating a semiconductor package according to an application example of the first embodiment. Referring to Figure 11, the semiconductor package 100 includes a wiring board 1 shown in Figure 1, a semiconductor chip 110, electrode pads 120, bumps 130, underfill resin 140, and bumps 150.
[0114] The semiconductor chip 110 is formed by creating a semiconductor integrated circuit (not shown) on a thin semiconductor substrate (not shown) made of, for example, silicon. Electrode pads 120 electrically connected to the semiconductor integrated circuit (not shown) are formed on the semiconductor substrate (not shown).
[0115] The bump 130 is formed on the electrode pad 120 of the semiconductor chip 110 and is electrically connected to the wiring layer 18 of the wiring board 1. The underfill resin 140 is filled between the semiconductor chip 110 and the upper surface of the wiring board 1. The bump 150 is formed on the lower surface of the wiring layer 26 that is exposed at the bottom of the opening 27x of the solder resist layer 27. The bump 150 is connected to, for example, a motherboard. The bumps 130 and 150 are, for example, solder bumps. As materials for the solder bumps, for example, alloys containing Pb, alloys of Sn and Cu, alloys of Sn and Ag, alloys of Sn, Ag and Cu, etc. can be used.
[0116] In this way, a semiconductor package 100 can be realized by mounting a semiconductor chip 110 on a wiring board 1 according to the first embodiment. As mentioned above, no voids are formed in the opening 17x of the wiring board 1, and no cracks originating from voids occur. Therefore, there is no risk of poor electrical conductivity between the wiring layer 18 and the electrode pad 120, and the reliability of the connection between the wiring board 1 and the semiconductor chip 110 can be improved.
[0117] In addition, in the semiconductor package 100, a wiring board 1A may be used instead of the wiring board 1.
[0118] Although preferred embodiments have been described in detail above, the invention is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.
[0119] For example, although the above embodiment shows an example of applying the present invention to a wiring board having a core layer manufactured by a build-up method, the present invention may also be applied to a coreless wiring board manufactured by a build-up method. Furthermore, the present invention is not limited to these examples and can be applied to various types of wiring boards. [Explanation of symbols]
[0120] 1. 1A Wiring Board 10 core layers 10a One side 10b The other side 10x through holes 11. Through-wiring 12, 14, 16, 18, 22, 24, 26 wiring layer 13, 15, 23, 25 Insulating layer 13x, 15x, 23x, 25x Beer Hall 13y, 17y recess 17, 27 Solder resist layer 17x, 27x opening 100 semiconductor packages 110 semiconductor chips 120 electrode pads 130, 150 bump 140 Underfill resin Seed layers 141, 181 142, 182 Electroplating layer 171, 173 Filler
Claims
1. An insulating layer containing a filler covers the first wiring layer, An opening formed in the insulating layer that exposes the upper surface of the first wiring layer, The opening is filled and electrically connected to the first wiring layer, and a second wiring layer extends from within the opening to the upper surface of the insulating layer, The second wiring layer includes via wiring that fills the opening and is electrically connected to the first wiring layer, and wiring patterns and / or pads formed on the via wiring. A recess is formed on the inner wall surface of the opening, which is the trace left by the removal of the filler. The aforementioned second wiring layer has a structure in which an electroplated layer is laminated on a seed layer. At least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening are adsorbed with catalyst. The seed layer is formed on the catalyst continuously along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening. The electroplated layer is formed on the seed layer continuously along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening, and fills the opening, including the interior of the recess.
2. The wiring substrate according to claim 1, wherein the seed layer is formed on the catalyst with substantially uniform thickness, continuously along at least the inner wall surface of the opening, the surface of the filler exposed from the inner wall surface of the opening, the inner wall surface of the recess, and the upper surface of the first wiring layer exposed within the opening.
3. The wiring board according to claim 1 or 2, wherein the content of the filler is 30 to 80% by weight.
4. The aforementioned insulating layer is the outermost insulating layer, The wiring board according to any one of claims 1 to 3, wherein the second wiring layer includes a pad formed on the via wiring.
5. The wiring board according to claim 4, wherein the pad is an electronic component mounting pad for electrically connecting to an electronic component.
6. The aforementioned insulating layer is an interlayer insulating layer, The wiring board according to any one of claims 1 to 3, wherein the second wiring layer includes a wiring pattern formed on the via wiring.
7. The insulating layer is made of a photosensitive resin containing the filler, The wiring board according to claim 4 or 5, wherein the filler is silicon dioxide or barium sulfate.
8. The insulating layer is made of a non-photosensitive resin containing the filler, The wiring board according to claim 6, wherein the filler is silicon dioxide.