Output circuit for analog neural memory in deep learning artificial neural networks

Abstract

To provide an output circuit for an analog neural memory in a deep learning artificial neural network.SOLUTION: An output block includes current-to-voltage converters ITV3501-1 to 3501-i (where i is the number of pairs of bit lines W+ and W- received by an output block 3500), a multiplexer 3502, sample-and-hold circuits 3503-1 to 3503-k, a channel multiplexer 3504, and an analog-to-digital converter 3505. Here, k may be the same as or different from i. The output block 3500 receives the differential weight outputs W+ and W- from bit line pairs in an array and ultimately generates a digital output DOUTx representing the output of one of the bit line pairs from the analog-to-digital converter 3505.SELECTED DRAWING: Figure 35A

Description

Technical Field

[0001] (Claiming Priority) This application claims priority to U.S. Provisional Patent Application No. 63 / 190,240, filed May 19, 2021, titled "Hybrid Output Architecture for Analog Neural Memory in a Deep Learning Artificial Neural Network", and U.S. Patent Application No. 17 / 463,063, filed August 31, 2021, titled "Output Circuit for Analog Neural Memory in a Deep Learning Artificial Neural Network", which are hereby incorporated by reference in their entirety.

[0002] (Field of the Invention) A number of embodiments are disclosed for a hybrid output architecture for analog neural memory in a deep learning artificial neural network.

Background Art

[0003] An artificial neural network mimics a biological neural network (the central nervous system of an animal, particularly the brain), can depend on a number of inputs, and is used to estimate or approximate a generally unknown function. An artificial neural network generally includes layers of interconnected "neurons" that exchange messages with each other.

[0004] Figure 1 shows an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to inputs and learn. Typically, a neural network contains multiple layers of inputs. Typically, there are hidden layers of one or more neurons and one output layer of neurons that provides the output of the neural network. At each level, neurons make decisions individually or collectively based on the data they receive from synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical neural networks rely on a very large number of synapses, which enables high connectivity between neurons and thus very high levels of parallel processing. In principle, such complexity can be achieved by digital supercomputers or dedicated graphics processing unit clusters. However, in addition to their high cost, these approaches also suffer from poor energy efficiency compared to biological networks, which consume far less energy because they primarily perform low-precision analog calculations. CMOS analog circuits have been used in artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses required.

[0006] The applicant previously disclosed, in U.S. Patent Application No. 15 / 594,439, incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory arrays operate as analog neural memories. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and therefrom produce a first plurality of outputs, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each of which includes spaced source and drain regions formed in a semiconductor substrate with a channel region extending between them, a floating gate isolated and disposed above a first portion of the channel region, and a non-floating gate isolated and disposed above a second portion of the channel region. Each of the plurality of memory cells is configured to store weight values ​​corresponding to many electrons in the floating gate. The plurality of memory cells are configured to produce a first plurality of outputs by multiplying the first plurality of inputs by the stored weight values.

[0007] Non-volatile memory cell Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("'130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed insulated above a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0008] By applying a high-voltage positive voltage to the word line terminal 22, erasure is performed on the memory cell 210 (electrons are removed from the floating gate), causing the electrons in the floating gate 20 to pass through the insulator between them to the word line terminal 22 via a Fowler-Nordheim (FN) tunnel.

[0009] The memory cell 210 is programmed by source-side injection (SSI) of hot electrons by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are added to the floating gate). The electron flow flows from the drain region 16 towards the source region 14. The electrons are accelerated and generate heat when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 via the gate oxide due to the electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain area 16 and the word line terminal 22 (turning on the portion of the channel area 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel area 18 below the floating gate 20 is also turned on, and current flows through the channel area 18, which is detected as the erased state, or the "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel area below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel area 18, which is detected as the programmed state, or the "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 110 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 in Figure 3 [Table 1]

[0012] Other types of flash memory cells are also known, including other split-gate memory cell configurations. For example, Figure 3 shows a four-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or can be connected to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 in Figure 3 [Table 2]

[0014] Figure 4 shows a different type of flash memory cell, a 3-gate memory cell 410. Memory cell 410 is identical to memory cell 310 in Figure 3, except that memory cell 410 does not have a separate control gate. The erase operation (erasure occurs through the use of an erase gate) and read operation are the same as those in Figure 3, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage must be applied to the source line to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0016] Figure 5 shows a different type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 in Figure 2, except that a floating gate 20 extends above the entire channel region 18, and a control gate 22 (where coupled to the word line) extends above the floating gate 20, separated by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, and programming is performed by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, by electrons flowing from the source region 14 to the drain region 16, and by a read operation similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that can be applied to the terminals of the memory cell 510 and the circuit board 12 for performing read, erase, and program operations. Table 4: Operation of flash memory cell 510 in Figure 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase-change memory), MRAM (magnetoresistive random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon tube) memory, OTP (bilevel or multilevel one-time programmable), and CeRAM (strongly correlated electron memory).

[0019] Two modifications are made to utilize a memory array containing one of the non-volatile memory cell types in the artificial neural network described above. First, lines are configured to allow each memory cell to be programmed, erased, and read individually without adversely affecting the memory state of other memory cells in the array, as will be further described below. Second, sequential (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely erased state to a completely programmed state. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed independently and continuously, with minimal disturbance to other memory cells, from a completely programmed state to a completely erased state, and vice versa. This means that the cell memory is analog, or can store at least one of a large number of discontinuous values ​​(e.g., 16 or 64 different values), which allows every cell in the memory array to be tuned very precisely and individually, and makes the memory array ideal for memory and fine-tuning of the synaptic weights of a neural network.

[0021] Neural networks using non-volatile memory cell arrays Figure 6 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array in this embodiment. While this example uses a non-volatile memory array neural network for a facial recognition application, it is also possible to implement other suitable applications using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). The synapse CB1, going from input layer S0 to layer C1, scans the input image with a 3x3 pixel overlapping filter (kernel), applying different sets of weights to some instances and shared weights to others, and shifts the filter by one pixel (or more than two pixels depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as the filter or kernel) are provided to synapse CB1, where these nine input values ​​are multiplied by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined, which is then given by the first synapse of CB1 to generate one of the pixels in the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of 3 pixels is added to the right and a column of 3 pixels is dropped to the left), thereby providing the 9 pixel values ​​of this newly positioned filter to synapse CB1, where they are multiplied by the same weights as above, determining a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of the input layer S0 for all three colors and all bits (precision values). The process is then repeated with different sets of weights to generate different feature maps of layer C1 until all feature maps of layer C1 have been computed.

[0023] In this example, layer C1 contains 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel; therefore, each feature map is a two-dimensional array, and thus in this example, layer C1 constitutes 16 layers of two-dimensional arrays (note that the layers and arrays referred to herein are logical relationships, not necessarily physical relationships; i.e., arrays are not necessarily oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scan. All C1 feature maps can target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared across all scans used to generate this first map) can identify circular edges, and a second map (generated using a second set of weights different from the first) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0024] Before moving from layer C1 to layer S1, an activation function P1 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. The purpose of the pooling function P1 is to average neighbor positions (or use the max function), reduce dependence on edge positions, and reduce data size before moving to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2, moving from layer S1 to layer C2, scans the maps in layer S1 with a 4x4 filter, shifting by 1 pixel. In layer C2, there are 22 12x12 feature maps. Before moving from layer C2 to layer S2, an activation function P2 (pooling) is applied that pools values ​​from non-overlapping, consecutive 2x2 regions within each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3, which goes from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 are connected to all maps in layer S2 via each synapse of CB3. There are 64 neurons in layer C3. Synapse CB4, which goes from layer C3 to output layer S3, completely connects C3 to S3; that is, all neurons in layer C3 are connected to all neurons in layer S3. The output in S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can, for example, indicate the identification or classification (classification) of the content of the original image.

[0025] Each layer of a synapse is implemented using an array or a portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for that purpose. The vector matrix multiplication (VMM) array 32 contains non-volatile memory cells and is used as synapses between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of non-volatile memory cells 33, erase gate and word line gate decoders 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, each of which decoders decodes its respective input to the non-volatile memory cell array 33. Inputs to the VMM array 32 can be from the erase gate and word line gate decoders 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bit line decoder 36 can also decode the output of the non-volatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, it stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the weights stored in it by the inputs, adds them up for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the last layer. By having the non-volatile memory cell array 33 perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and the calculations are more power-efficient due to being performed in memory.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing operational amplifier or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for its convolution. The differential summer 38 is configured to perform the summing of positive and negative weights.

[0029] The summed output values ​​of the differential adder 38 are then fed to an activation function block 39, which rectifies the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The rectified output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in Figure 6), and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving input from the previous layer of the neuron or from an input layer such as an image database), and the summing operational amplifier 38 and activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 in Figure 7 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog level, binary level, or digital bits (in this case, a DAC is provided to convert the digital bits to the appropriate input analog level), and the outputs can be analog level, binary level, or digital bits (in this case, an output ADC is provided to convert the output analog level to digital bits).

[0031] Figure 8 is a block diagram showing the use of multiple layers of the VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in Figure 8, the input (indicated as Inputx) is converted from digital to analog by the digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be voltage or current. Input D / A conversion of the first layer can be performed by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM array 32a. Input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to the input VMM array 32a.

[0032] The output generated by input VMM array 32a is then provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is then provided as input to input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as the synaptic and neuron layers of a convolutional neural network (CNN). VMM arrays 32a, 32b, 32c, 32d, and 32e can each be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different parts of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping parts of the same physical non-volatile memory array. The example shown in Figure 8 includes five layers (32a, 32b, 32c, 32d, 32e), namely one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will understand that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers.

[0033] Vector Matrix Multiplication (VMM) Array Figure 9 shows a neuron VMM array 900, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, another reference array may be located at the bottom.

[0034] In the VMM array 900, control gate lines such as the control gate line 903 extend in the vertical direction (thus, the reference array 902 in the row direction is orthogonal to the control gate line 903), and erase gate lines such as the erase gate line 904 extend in the horizontal direction. Here, the input to the VMM array 900 is provided to the control gate lines (CG0, CG1, CG2, CG3), and the output of the VMM array 900 appears on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current of each source line (SL0 and SL1 respectively) performs a summation function of all the currents from the memory cells connected to that particular source line.

[0035] As described herein for the neural network, the non-volatile memory cells of the VMM array 900, i.e., the memory cells 310 of the VMM array 900, are preferably configured to operate in the subthreshold region.

[0036] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids = Io * e (Vg-Vth) / nVt = w * Io * e (Vg) / nVt Where w = e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k * T / q, where k is the Boltzmann constant, T is the Kelvin temperature, q is the electronic charge, n is the slope factor = 1+(Cdep / Cox), Cdep is the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * * u * Cox * (n - 1) * Vt 2It is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV logarithmic converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or a transistor: Vg=n * Vt * log[Ids / wp * Io] In the formula, wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector matrix multiplier (VMM) array with current input, the output current is as follows: Iout=wa * Io * e (Vg) / nVt That is to say Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt In the formula, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. Note that the transistor threshold voltage is a function of the substrate bias voltage, and the substrate bias voltage, denoted as Vsb, can be modulated to compensate for various conditions at such temperatures. The threshold voltage Vth can be expressed as follows:

number

number

[0039] Word lines or control gates can be used as inputs to memory cells for input voltage.

[0040] Alternatively, the flash memory cells of the VMM array described herein can also be configured to operate in a linear region. Ids=β * (Vgs-Vth) * Vds; β=u * Cox * Wt / L W=α(Vgs-Vth) In other words, the weight W in the linear region is proportional to (Vgs - Vth).

[0041] Word lines, control gate lines, bit lines, or source lines can be used as inputs to memory cells operating within the linear region. Bit lines or source lines can be used as outputs to memory cells.

[0042] For IV linear converters, a memory cell (such as a reference memory cell or peripheral memory cell) or transistor operating in the linear domain can be used to linearly convert input / output currents into input / output voltages.

[0043] Alternatively, the memory cells of the VMM array described herein can also be configured to operate in the saturation region. Ids=1 / 2 * β * (Vgs-Vth) 2 ; β=u * Cox * Wt / L Wα(Vgs-Vth) 2 That is, the weight W is (Vgs - Vth) 2 It is proportional to.

[0044] Word lines, control gates, or erase gates can be used as inputs to memory cells operating within a saturation region. Bit lines or source lines can be used as outputs to output neurons.

[0045] Alternatively, the memory cells of the VMM array described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturated) for each layer or multilayer of a neural network.

[0046] Other embodiments for the VMM array 32 shown in Figure 7 are described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in the above application, source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] Figure 10 shows a neuron VMM array 1000, particularly suited to the memory cell 210 shown in Figure 2 and used as a synapse between the input layer and the next layer. The VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. The reference arrays 1001 and 1002, arranged in the column direction of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1014 (partially shown) with current inputs flowing in. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference miniarray matrix (not shown).

[0048] The memory array 1003 serves two purposes. First, it stores the weights used by the VMM array 1000 in each memory cell. Second, the memory array 1003 effectively multiplies the weights stored in it by the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1001 and 1002 and supplied to the word lines WL0, WL1, WL2, and WL3), then adds all the results (memory cell currents) to produce outputs on each bit line (BL0~BLN), which become inputs to the next layer or the last layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, voltage inputs are supplied to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0 to BLN during the read (inference) operation. The current in each bit line BL0 to BLN is a function of the sum of the currents from all non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents of the VMM array 1000. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] Figure 11 shows a neuron VMM array 1100, which is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of a first nonvolatile reference memory cell, and a reference array 1102 of a second nonvolatile reference memory cell. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000 except that the word lines in the VMM array 1100 extend in the vertical direction. Here, the input is the word lines (WLA0, WLB0, WLA1, WLB 1 The outputs are provided to WLA2, WLB2, WLA3, and WLB3, and appear on the source lines (SL0, SL1) during read operations. The current on each source line is a function of the sum of all currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents of the VMM array 1100. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] Figure 12 shows a neuron VMM array 1200, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of a synapse and neuron between the input layer and the next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 function to convert the current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1212 (partially shown) with current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1212 includes corresponding multiplexer 1205 and cascoding transistor 1204, respectively, to ensure a constant voltage across the bit lines (such as BLR0) of the first and second non-volatile reference memory cells during read operations. The reference cells are tuned to a target reference level.

[0053] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200. Second, the memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted into input voltages by the reference arrays 1201 and 1202 and supplied to the control gates (CG0, CG1, CG2, and CG3)), then adds all the results (cell currents) to produce an output, which appears in BL0~BLN and becomes the input to the next layer or the last layer. By having the memory array perform the multiplication and addition functions, the need for separate multiplication and addition logic circuits is eliminated, and power efficiency is also improved. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3), and the output appears in the bit lines (BL0~BLN) during read operations. The current in each bit line is a function of the sum of all currents from the memory cells connected to that particular bit line.

[0054] The VMM array 1200 implements one-way tuning of non-volatile memory cells within the memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is applied to the floating gate (e.g., an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations is restarted from the beginning. As shown, two rows sharing the same erase gate (e.g., EG0 or EG1) are erased together (known as page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents of the VMM array 1200. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] Figure 13 shows a neuron VMM array 1300, which is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapse and neuron between the input layer and the next layer. The VMM array 1300 is a memory array 1303 of nonvolatile memory cells and , the 1 non-volatile reference memory cell Reference array 1301The VMM array 1300 comprises a reference array 1302 of a second non-volatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, and the CG lines CG0, CG1, CG2, and CG3, as well as the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400 except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be completely erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate by using separate EG lines. As shown, the reference arrays 1301 and 1302 convert the input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of the diode-connected reference cells via the multiplexer 1314), and these voltages are applied to the memory cells in the row direction. Current outputs (neurons) are located in the bit lines BL0 to BLN, and each bit line sums up all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents of the VMM array 1300. The columns in the table show the voltages applied to the word lines of selected cells, word lines of unselected cells, bit lines of selected cells, bit lines of unselected cells, control gates of selected cells, control gates of unselected cells in the same sector as the selected cell, control gates of unselected cells in a different sector than the selected cell, erase gates of selected cells, erase gates of unselected cells, source lines of selected cells, and source lines of unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] Figure 22 shows a neuron VMM array 2200 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In the VMM array 2200, inputs INPUT0...., INPUTN These are bit lines BL0, ..., BL N The signals are received at each of these points, and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] Figure 23 shows a neuron VMM array 2300 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapse and neuron between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3 respectively, and outputs OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0060] Figure 24 shows a neuron VMM array 2400 that is particularly suitable for the memory cell 210 shown in Figure 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0061] Figure 25 shows a neuron VMM array 2500 that is particularly suitable for the memory cell 310 shown in Figure 3 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Each is received and output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N It is generated in [location].

[0062] Figure 26 shows a neuron VMM array 2600 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapse and neuron between the input layer and the next layer. In this example, the input 0、 ..., INPUT n These are the vertical control gate lines CG0, ..., CG N The signal is received, and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] Figure 27 shows a neuron VMM array 2700 that is particularly suitable for the memory cell 410 shown in Figure 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N These are bit lines BL0, ..., BL N The signals are received by the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, which are coupled to each other. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] Figure 28 shows a neuron VMM array 2800, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are word lines WL0, ..., WL M Received at, output OUTPUT0, ..., OUTPUT N These are bit lines BL0, ..., BL N They are generated in each respective location.

[0065] Figure 29 shows a neuron VMM array 2900 that is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM These are control gate lines CG0, ..., CG M Received at: Output OUTPUT0, ..., OUTPUT N These are the vertical source lines SL0, ..., SL N Each is generated, and each source line SL i It is coupled to the source lines of all memory cells in column i.

[0066] Figure 30 shows a neuron VMM array 3000, which is particularly suitable for the memory cell 310 shown in Figure 3, the memory cell 510 shown in Figure 5, and the memory cell 710 shown in Figure 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M These are control gate lines CG0, ..., CG M Received at: Output OUTPUT0, ..., OUTPUT N These are vertical bit lines BL0, ..., BL N Each bit line BL is generated in its respective place. i It is coupled to the bit lines of all memory cells in column i.

[0067] Long-term and short-term memory Prior art includes the concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTMs allow neural networks to store information for a predetermined period and use that information in subsequent operations. A conventional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an exemplary LSTM1400. In this example, the LSTM1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives the input vector x0 and generates the output vector h0 and the cell state vector c0. Cell 1402 receives the input vector x1, the output vector (hidden state) h0 from cell 1401, and the cell state c0 from cell 1401, and generates the output vector h1 and the cell state vector c1. Cell 1403 receives the input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402, and generates the output vector h2 and the cell state vector c2. Cell 1404 receives the input vector x3, the output vector (hidden state) h2 from cell 1403, and the cell state c2 from cell 1403, and generates the output vector h3. Additional cells can also be used, and an LSTM with four cells is just one example.

[0069] Figure 15 shows an exemplary implementation of LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a preceding cell, and an output vector h(t-1) from a preceding cell, and generates the cell state vector c(t) and output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each applying a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and an adder device 1509 for adding two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0071] Figure 16 shows an LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the reader's convenience, the same numbering method used in LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each contain multiple VMM arrays 1601 and activation function blocks 1602. Thus, VMM arrays are found to be particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508, and adder device 1509 are implemented in a digital or analog manner. Activation function block 1602 can be implemented in a digital or analog manner.

[0072] Figure 17 shows an alternative example of LSTM cell 1600 (and another example of one implementation of LSTM cell 1500). In Figure 17, sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-division multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (including the activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, and a value f(t) * Register 1704 for storing c(t-1) when its value is output from multiplier device 1703 via multiplexer 1710, and value i(t) * Register 1705 for storing u(t) when its value is output from multiplier device 1703 via multiplexer 1710, and value o(t) * The set includes register 1706 and multiplexer 1709 for storing c~(t) when its value is output from multiplier device 1703 via multiplexer 1710.

[0073] While an LSTM cell 1600 includes multiple sets of VMM arrays 1601 and their respective activation function blocks 1602, an LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in embodiments of the LSTM cell 1700. Compared to the LSTM cell 1600, the LSTM cell 1700 requires only one-quarter the space for the VMMs and activation function blocks, thus requiring less space than the LSTM cell 1600.

[0074] It can be further understood that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below reduce the circuitry required outside the VMM array itself.

[0075] Gated regression unit Analog VMM implementations can be used in gated recurrent unit (GRU) systems. A GRU is a gate mechanism within an iterative neural network. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] Figure 18 shows an exemplary GRU1800. In this example, the GRU1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and produces output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and produces output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and produces output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and produces output vector h3. Additional cells are also available, and a GRU with four cells is just an example.

[0077] Figure 19 shows an exemplary implementation of a GRU cell 1900 that may be used in cells 1801, 1802, 1803, and 1804 of Figure 18. The GRU cell 1900 takes an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and produces an output vector h(t). The GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to the components from the output vector h(t-1) and the input vector x(t). The GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding two vectors, and a complementary device 1908 for subtracting the input from 1 to produce an output.

[0078] Figure 20 shows GRU cell 2000, an example of an implementation of GRU cell 1900. For the reader's convenience, the same numbering method used in GRU cell 1900 is used in GRU cell 2000. As can be seen from Figure 20, the sigmoid function devices 1901 and 1902, and the tanh device 1903, each contain multiple VMM arrays 2001 and activation function blocks 2002. Thus, it can be seen that VMM arrays are used in particular in GRU cells used in specific neural network systems. The multiplier devices 1904, 1905, 1906, the adder device 1907, and the complementary device 1908 are implemented in a digital or analog manner. The activation function block 2002 can be implemented in a digital or analog manner.

[0079] Figure 21 shows an alternative example of GRU cell 2000 (and another example of one implementation of GRU cell 1900). In Figure 21, GRU cell 2100 utilizes VMM array 2101 and activation function block 2102, and when configured as a sigmoid function, it applies a number between 0 and 1 to control the extent to which each component of the input vector contributes to the output vector. In Figure 21, the sigmoid function devices 1901 and 1902, and the tanh device 1903, share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding two vectors, a complementary device 2109 for subtracting the input from 1 to generate an output, a multiplexer 2104, and a value h(t-1) * Register 2106 for holding r(t) when its value is output from multiplier device 2103 via multiplexer 2104, and value h(t-1) * A register 2107 holds the value of z(t) when its value is output from the multiplier device 2103 via the multiplexer 2104, and the value h^(t) *The register 2108 holds (1-z((t)) when its value is output from the multiplier device 2103 via the multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, GRU cell 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in embodiments of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because it requires only one-third the space for the VMM and activation function blocks.

[0081] It can be further understood that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a considerable amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array may be analog level, binary level, pulse, time-modulated pulse, or digital bit (in which case a DAC is required to convert the digital bit to an appropriate input analog level), and the output may be analog level, binary level, timing pulse, pulse, or digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] For each memory cell in a VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W = W+-W-). In the case of two blended memory cells, two memory cells are required to implement the weight W as the average of two cells.

[0084] Figure 31 shows the VMM system 3100. In some embodiments, the weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). In the VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connected to memory cells that store the positive weights W+, and the other half of the bit lines are designated as W- lines, i.e., bit lines connected to memory cells that implement the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3101 and 3102, which receive current from the W+ and W- lines. The outputs of the W+ lines and the W- lines are combined to effectively give W = W+ - W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. Up to this point, we have described W- lines that are alternately scattered between W+ lines, but in other embodiments, W+ and W- lines can be arbitrarily placed anywhere within the array.

[0085] Figure 32 shows another embodiment. In the VMM system 3210, positive weights W+ are implemented in the first array 3211, and negative weights W- are implemented in the second array 3212, which is separate from the first array, and the resulting weights are appropriately combined by an adder circuit 3213.

[0086] Figure 33 shows the VMM system 3300. The weights W stored in the VMM array are stored as differential pairs, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). The VMM system 3300 comprises arrays 3301 and 3302. Half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connected to memory cells that store the positive weights W+, and the other half of the multiple bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connected to memory cells that implement the negative weights W-. The W- lines are interspersed alternately between the W+ lines. Subtraction operations are performed by adders, such as adders 3303, 3304, 3305 and 3306, which receive current from the W+ and W- lines. The outputs of the W+ line and the W- line from each of the arrays 3301 and 3302 are combined together to effectively give W=W+-W- for each pair of (W+, W-) cells in all pairs of (W+, W-) lines. Furthermore, the W values ​​from each of the arrays 3301 and 3302 can be further combined via adders 3307 and 3308, such that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adders 3307 and 3308 is the difference of one of the two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system holds a charge, i.e., the number of electrons, in a very specific and precise quantity within a floating gate, corresponding to the erase / program. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] Similarly, the read operation must be able to accurately distinguish between N different levels.

[0089] In VMM systems, there is a need for an improved output block that can quickly and accurately receive outputs from arrays and identify the values ​​represented by those outputs. [Overview of the project]

[0090] Numerous embodiments of output circuits for analog neural memory in deep learning artificial neural networks are disclosed.

[0091]

[0092]

[0093]

[0094]

[0095]

[0096]

[0097]

[0098]

[0099]

[0100]

[0101]

[0102]

[0103]

[0104]

[0105]

[0106]

[0107]

[0108]

[0109]

[0110]

[0111]

[0112]

[0113]

[0114]

[0115]

[0116]

[0117]

[0118]

[0119]

[0120]

[0121]

[0122]

[0123]

[0124]

[0125]

[0126]

[0127]

[0128]

[0129]

[0130]

[0131]

[0132]

[0133]

[0134]

[0135]

[0136]

[0137]

[0138]

[0139]

[0140]

[0141] [Brief explanation of the drawing]

[0142] [Figure 1] This is a diagram illustrating an artificial neural network. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows another prior art split-gate flash memory cell. [Figure 6] This diagram illustrates various levels of exemplary artificial neural networks that utilize one or more non-volatile memory arrays. [Figure 7] This is a block diagram illustrating a vector matrix multiplication system. [Figure 8] This is a block diagram illustrating an exemplary artificial neural network that utilizes one or more vector-matrix multiplication systems. [Figure 9] Another embodiment of the vector-matrix multiplication system is shown. [Figure 10] Another embodiment of the vector-matrix multiplication system is shown. [Figure 11] Another embodiment of the vector-matrix multiplication system is shown. [Figure 12] Another embodiment of the vector-matrix multiplication system is shown. [Figure 13]Another embodiment of the vector-matrix multiplication system is shown. [Figure 14] This demonstrates prior art long- and short-term memory systems. [Figure 15] This shows an example cell used in long- and short-term memory systems. [Figure 16] Figure 15 shows one embodiment of an exemplary cell. [Figure 17] Another embodiment of the exemplary cell shown in Figure 15 is presented. [Figure 18] This shows a prior art gated regression unit system. [Figure 19] An exemplary cell for use in a gated regressive unit system is shown. [Figure 20] Figure 19 shows one embodiment of an exemplary cell. [Figure 21] Another embodiment of the exemplary cell in Figure 19 is shown. [Figure 22] Another embodiment of the vector-matrix multiplication system is shown. [Figure 23] Another embodiment of the vector-matrix multiplication system is shown. [Figure 24] Another embodiment of the vector-matrix multiplication system is shown. [Figure 25] Another embodiment of the vector-matrix multiplication system is shown. [Figure 26] Another embodiment of the vector-matrix multiplication system is shown. [Figure 27] Another embodiment of the vector-matrix multiplication system is shown. [Figure 28] Another embodiment of the vector-matrix multiplication system is shown. [Figure 29] Another embodiment of the vector-matrix multiplication system is shown. [Figure 30] Another embodiment of the vector-matrix multiplication system is shown. [Figure 31] Another embodiment of the vector-matrix multiplication system is shown. [Figure 32]Another embodiment of the vector-matrix multiplication system is shown. [Figure 33] Another embodiment of the vector-matrix multiplication system is shown. [Figure 34] Another embodiment of the vector-matrix multiplication system is shown. [Figure 35A] An embodiment of the output block is shown. [Figure 35B] An embodiment of the output block is shown. [Figure 36] Another embodiment of the output block is shown. [Figure 37A] Another embodiment of the output block is shown. [Figure 37B] Another embodiment of the output block is shown. [Figure 38A] Another embodiment of the output block is shown. [Figure 38B] Another embodiment of the output block is shown. [Figure 39A] Another embodiment of the output block is shown. [Figure 39B] Another embodiment of the output block is shown. [Figure 40A] Another embodiment of the output block is shown. [Figure 40B] Another embodiment of the output block is shown. [Figure 40C] Another embodiment of the output block is shown. [Figure 41] This shows a serial analog-to-digital converter circuit. [Figure 42] This shows a successive approximation register analog-to-digital converter circuit. [Figure 43] This shows a pipelined successive register analog-to-digital converter circuit. [Figure 44A] This shows a hybrid successive approximation register and a serial analog-to-digital converter circuit. [Figure 44B] This shows a hybrid successive approximation register and a serial analog-to-digital converter circuit. [Figure 45] This shows an algorithmic analog-to-digital converter block. [Figure 46] This shows the tracking reference generator used in the output block. [Modes for carrying out the invention]

[0143] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array.

[0144] Overview of the VMM System Figure 34 shows a block diagram of the VMM system 3400. The VMM system 3400 comprises a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit line driver 3405, an input circuit 3406, an output circuit 3407, a control logic 3408, and a bias generator 3409. The VMM system 3400 further comprises a high-voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage analog precision level generator 3413. The VMM system 3400 further comprises an algorithm controller 3414 (for program / erase or weight adjustment), an analog circuit 3415, a control engine 3416 (which may include, but is not limited to, special functions such as arithmetic functions, startup functions, and embedded microcontroller logic), and a test control logic 3417. The systems and methods described below may be implemented in the VMM system 3400.

[0145] The input circuit 3406 may include circuits such as a DAC (digital-to-analog converter), DPC (digital-to-pulse converter, digital-to-time-modulated pulse converter), AAC (analog-to-analog converter such as a current-to-voltage converter or logarithmic converter), PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The output circuit 3407 may include circuits such as an ADC (analog-to-digital converter for converting neuron analog output to digital bits), AAC (analog-to-analog converter such as a current-to-voltage converter, logarithmic converter), APC (analog-to-pulse converter, analog-to-time-modulated pulse converter), or any other type of converter.

[0146] The output circuit 3407 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement statistical normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) of the neuron output. The output circuit 3407 may implement a temperature compensation function for the neuron output or array output (such as a bit line output) to improve the accuracy of the array (neuron) output, such as by keeping the array's power consumption nearly constant or keeping the IV slope nearly the same.

[0147] Figure 35A shows output block 3500. The output block includes current-to-voltage converters (ITVs) 3501-1 to 3501-i (where i is the number of pairs of bit lines W+ and W- that output block 3500 receives), a multiplexer 3502, sample-and-hold circuits 3503-1 to 3503-i, a channel multiplexer 3504, and an analog-to-digital converter (ADC) 3505. Output block 3500 receives differential weight outputs W+ and W- from the bit line pairs in the array and ultimately generates a digital output, DOUTx, which represents one of the bit line pairs (e.g., W+ and W- lines) from ADC 3505.

[0148] Each of the current-voltage converters 3501-1 to 3501-i receives analog bit-line current signals BLw+ and BLw- (which are bit-line outputs generated in response to the input and stored W+ and W- weights, respectively) and converts them into differential voltages ITVO+ and ITVO-.

[0149] Next, ITVO+ and ITVO- are received by the multiplexer 3502, which time-division multiplexes the outputs from the current-voltage converters 3501-1 to 3501-I to S / H circuits 3503-1 to 3503k, where k may be the same as or different from i.

[0150] Each of the S / H circuits 3503-1 to 3503-k samples the differential voltage it receives and holds them as differential outputs.

[0151] Next, the channel multiplexer 3504 receives the control signal and selects one of the bit lines W+ channel and W- channel, i.e., one of the bit line pairs, and outputs the differential voltage held by each sample-and-hold circuit 3503 to the ADC 3505, which converts the analog differential voltage output by each sample-and-hold circuit 3503 into a set of digital bits, DOUTx. As shown, the S / H 3503 may be shared across multiple ITV circuits 3501, and the ADC 3505 may operate with multiple ITV circuits in a time-division multiplexing scheme. Each S / H 3503 may be a simple capacitor or a capacitor followed by a buffer (e.g., an operational amplifier).

[0152] The ADC3505 can have a hybrid ADC architecture, which means it has two or more ADC architectures to perform conversions. For example, if DOUTx is an 8-bit output, the ADC3505 may include an ADC subarchitecture for generating bits B7-B4 and another ADC subarchitecture for generating bits B3-B0 from differential inputs ITVSH+ and ITVSH-. In other words, the ADC circuit 3505 has multiple ADC subarchitectures. Bua - May include articulation.

[0153] Optionally, one ADC subarchitecture may be shared across all channels, while another ADC subarchitecture may not be shared across all channels.

[0154] In another embodiment, the channels mux3504 and ADC3505 may be removed, and instead, the output may be an analog differential voltage from the S / H3503, which may be buffered by an operational amplifier. For example, the use of analog voltages may be implemented in an all-analog neural network (i.e., one where no digital output or digital input is required for the neural memory array).

[0155] Figure 35B shows the output block 3550. The output block consists of current-to-voltage converters (ITVs) 3551-1 to 3551-i (where i is the number of pairs of bit lines W+ and W- that output block 3550 receives), a multiplexer 3552, a differential-to-single-ended converter (Diff-to-S converter) 3553, a sample-and-hold circuit 3554-1 to 3554-k (where k is the same as or different from i), and a channel multiplexer 355 5 And, Analog-to-Digital Converter (ADC) 355 6 The Diff-to-S converter 3553 is used to convert the differential output from the ITV3551 signal provided by mux3552 to a single-ended output. The single-ended output is then input to S / H3554, mux3555, and ADC3556.

[0156] Figure 36 shows output block 3600. The output block includes adders 3601-1 to 3601-i (such as current mirror circuits, where i is the number of pairs of bit lines BLw+ and BLw- that output block 3600 receives), current-to-voltage converters (ITVs) 3602-1 to 3602-i, a multiplexer 3603, sample-and-hold circuits 3604-1 to 3604-k (where k is the same as or different from i), a channel multiplexer 3605, and an ADC 3606. Output block 3600 receives differential weight outputs BLw+ and BLw- from the bit line pairs in the array and finally generates a digital output, DOUTx, from the ADC 3606, which represents one output of the bit line pair at a time.

[0157] Current summing circuits 3601-1 to 3601-i each receive current from a bit line pair, subtract the BLw- value from BLw-, and output the result as the summed current.

[0158] The current-voltage converters 3602-1 to 3602-i receive an output summation current and convert each summation current into differential voltages ITVO+ and ITVO-, which are then received by the multiplexer 3603 and selectively supplied to the sample-and-hold circuits 3604-1 to 3604-k.

[0159] Each sample-and-hold circuit 3604 receives the differential voltages ITVOMX+ and ITVOMX-, samples the received differential voltages, and holds them as differential voltage outputs OSH+ and PSH-.

[0160] The channel multiplexer 3605 receives a control signal to select one of the bit line pairs, namely channels BLw+ and BLw-, and outputs the voltages held by the respective sample-and-hold circuits 3604 to the ADC 3606, which converts the voltages into a set of digital bits as DOUTx.

[0161] Figure 37A shows the current-voltage converter 3700. The current-voltage converter 3700 includes operational amplifiers 3701 and 3702 configured as shown, and variable resistors 3703, 3704, and 3705. The current-voltage converter 3700 receives differential output currents, BLw+ from the W+ bit line and BLw- from the W- bit line, as shown as a variable current source, and generates a single-ended output Vout. The output voltage Vout is given by = (BLw+ - Blw-) * R is the value of resistors 3703, 3704, and 3705, respectively, and each has a value equal to R. The variable resistor in Figure 37A can be used to scale the output.

[0162] Figure 37B shows the current-voltage converter 3710. The current-voltage converter 3710 includes operational amplifiers 3711, 3712, and 3713 configured as shown, and variable resistors 3714, 3715, 3716, and 3717. The current-voltage converter 3710 receives the output current BLw+ from the W+ bit line, indicated as a variable current source, and generates the output Vout+ of that line, and receives the output current Blw- from the W- bit line, indicated as a variable current source, and generates the output Vout- of that line. Thus, unlike output block 3700, output block 3710 does not produce a single-ended output, but rather a differential voltage representing the difference values ​​BLw+ and BLw-, respectively. The output voltage is Vout+ = Iw+ * R and Vout- = -Rw- * R is the value of resistors 3714, 3715, 3716, and 3717, respectively. The variable resistor in Figure 37B can be used to scale the output.

[0163] Optionally, the differential output voltages Vout+ and Vout- can be input to the ADC3718, which converts them into a set of digital output bits, Doutx.

[0164] Figure 38A shows the current-voltage converter 3800. The current-voltage converter 3800 includes operational amplifiers 3801 and 3802, variable capacitors 3803, 3805, and 3806, and controlled switches 3804 and 3807, configured as shown. The current-voltage converter 3800 receives a differential output current BLw+ from the W+ bit line, indicated as a variable current source, and BLw- from the W- bit line, indicated as a variable current source, to generate a single-ended output Vout. The output voltage Vout is given by = (Iw+ - Iw-) * The integral time t_integration is given by t_integration / C, and capacitors 3803, 3805, and 3806 each have a capacitance value equal to C. A control circuit (not shown) controls the opening and closing of switches 3804 and 3807 to provide the integral time t_integration.

[0165] Figure 38B shows the current-voltage converter 3810. The current-voltage converter 3810 includes operational amplifiers 3811, 3812, and 3813, variable capacitors 3815, 3816, 3817, and 3819, and switches 3814, 3818, and 3820. The current-voltage converter 3810 receives the output current BLw+ from the W+ bit line, designated as a variable current source, and generates the output Vout+ of that line, and receives the output current BLw- from the W- bit line, designated as a variable current source, and generates the Vout- of that line. Thus, unlike output block 3800, output block 3810 generates two voltages representing the difference values ​​BLw+ and BLw-, respectively. The output voltage is Vout+ = BLw+ * t_integration / C and Vout- = BLw- * The integral time t_integration is C, and capacitors 3815, 3816, 3817, and 3819 each have a capacitance value equal to C. A control circuit (not shown) controls the opening and closing of switches 3814, 3818, and 3820 to provide the integral time t_integration.

[0166] Optionally, the differential output voltages Vout+ and Vout- can be input to the ADC3821, which converts them into a set of digital output bits, Doutx.

[0167] Figure 39A shows the current-voltage converter 3900. The current-voltage converter 3900 includes an operational amplifier 3901 configured as shown, variable integrating resistors 3902 and 3903, controlled switches 3904, 3905, 3906, and 3907, and sample-and-hold capacitors 3908 and 3909. The current-voltage converter 3900 receives differential currents BLw+ from the W+ bit line and BLw- from the W- bit line, and outputs voltages Vout+ and Vout-, respectively. The output voltage is Vout+ = (Blw+) * R and Vout- = (BLw-) *R is the value of resistors 3902 and 3903, respectively. Capacitors 3908 and 3909 function as retaining S / H capacitors to maintain the output voltage when resistors 3902 and 3903 and the input current are interrupted. A control circuit (not shown) controls the opening and closing of switches 3904, 3905, 3906, and 3907 to provide the integral time.

[0168] Optionally, the differential output voltages Vout+ and Vout- can be input to the ADC3910, which converts them into a set of digital output bits, Doutx.

[0169] Figure 39B shows a differential voltage-to-single-ended voltage converter (Diff-to-S) 3950. The Diff-to-S converter 3950 includes an operational amplifier 3951 and variable integrating resistors 3952 and 3953. Output voltage Vout - (Vin1 - Vin2) * (R_3852 / R_3953). This is used, for example, as block 3553 in Figure 35B.

[0170] Figure 40A shows output block 4000, which is a hybrid output conversion block. Output block 4000 includes multiple subarchitectures, such as the SAR and serial ADC subarchitectures, as shown. Output block 4000 receives differential signals Iw+ and Iw-. The successive approximate register analog-to-digital converter SAR4001 converts the differential signals Iw+ and Iw- into upper digital bits, and then the serial block ADC4002 converts the remaining signals after the upper bit conversion into lower bits, outputting all output digital bits together. In one example, for 8-bit ADC conversion, SAR ADC4001 converts a portion of the received differential voltage into MSB bits B7-B4, and serial ADC4002 converts a portion of the received differential voltage into LSB bits B3-B0.

[0171] Figure 40B shows the output block 4010. The output block 4010 includes multiple subarchitectures, such as algorithmic ADC and serial ADC subarchitectures, as shown. The output block 4010 receives differential signals Iw+ and Iw-. The algorithmic analog-to-digital converter 4003 converts the differential signals Iw+ and Iw- into upper-order digital bits, and then the serial ADC block 4004 converts the remaining signals after the upper-order bit conversion into lower-order bits, outputting all output digital bits together. In one example, for 8-bit ADC conversion, the algorithmic ADC 4003 converts a portion of the received differential voltage into MSB bits B7-B4, and the serial ADC 4004 converts a portion of the received differential voltage into LSB bits B3-B0.

[0172] Figure 40C shows output block 4020. Output block 4020 receives differential signals Iw+ and Iw-. Output block 4020 includes a hybrid analog-to-digital converter that converts the differential signals Iw+ and Iw- into digital bits by combining different conversion schemes (such as those shown in Figures 40A and 40B) into a single block.

[0173] Figure 41 shows a configurable serial analog-to-digital converter 4100. The serial analog-to-digital converter 4100 is shown as a neuron output current I, which is a variable current source. NEU The integrator 4170 includes an integrator 4170 that integrates the signal into an integrating capacitor 4102 (Cint). The integrator 4170 includes a differential amplifier 4101, controlled switches 4108 and 4110, and a control circuit (not shown) that controls the opening and closing of switches 4108 and 4110 to provide integration time.

[0174] In one embodiment, VRAMP4150 is provided to the inverting input of comparator 4104. A digital output (count value) 4121 is generated by ramping VRAMP4150 until the output of comparator 4104, indicated as EC4105, switches polarity, and counter 4120 counts clock pulses from the start of ramping VRAMP4150 and stops when the output of comparator 4104 switches polarity in response to an AND gate 4140 that prevents the passage of clock 4141 from reaching counter 4120 as a pulse sequence 4142.

[0175] In another embodiment, VREF4155 is provided to the inverting input of comparator 4104. VC4110 is ramped down by ramp current 4151 (IREF) until VOUT4103 reaches VREF4155, at which point the output EC4105 of comparator 4104 switches polarity and disables the count of counter 4120. Thus, counter 4120 is enabled with the closing of switch S2 (it is disabled after S2 is opened, when the output EC4105 of comparator 4104 switches polarity). S3 is used for initialization (equalization) at the start of operation. The (n-bit) ADC4100 can be configured to have lower precision (less than n bits) or higher precision (more than n bits) depending on the target application. The configurability of accuracy is achieved, without limitation, by configuring the capacitance of capacitor 4102, the current 4151 (IREF), the ramping speed of VRAMP 4150, or the clock frequency of clock 4141.

[0176] In another embodiment, the ADC circuit of a VMM array is configured to have a precision lower than n bits, and the ADC circuit of another VMM array is configured to have a precision higher than n bits.

[0177] In another embodiment, one instance of the serial ADC circuit 4100 of a single neuron (array output) circuit is configured to generate an ADC circuit with higher precision than n bits by combining the integrating capacitor 4102 of the two instances of the serial ADC circuit 4100, for example, by combining one instance of the serial ADC circuit 4100 of an adjacent neuron circuit with another instance of the serial ADC circuit 4100 of an adjacent neuron circuit.

[0178] Figure 42 shows a configurable SAR (successive approximation register) analog-to-digital converter 4200 used in a neuron output circuit (array output circuit). This circuit is a successive approximation converter based on charge redistribution using binary capacitors. The successive approximation converter includes a binary CDA (capacitor digital-to-analog converter) 4201, a comparator 4202, and SAR logic and register 4203. As shown, GndV 4204 is a low-voltage reference level, e.g., ground level. The SAR logic and register 4203 provides a digital output 4206. Other non-binary capacitor structures may be implemented using weighted reference voltage or output correction.

[0179] Figure 43 shows a pipelined SAR ADC circuit 4300 that can be used to increase the number of bits in a pipelined manner in combination with the following SAR ADC. The SAR ADC circuit 4300 includes a binary CDA 4301, a comparator 4302 (operating as an operational amplifier or comparator), an operational amplifier / comparator 4303, and SAR logic and registers 4304. As shown, GndV 3104 is a low-voltage reference level, e.g., ground level. The SAR logic and registers 4304 provide a digital output 4306. Vin is the input voltage, VREF is the reference voltage, and GndV is a low voltage such as the ground voltage. The V residue is generated by capacitor 4305 and provided as input to the next stage of the SAR ADC conversion sequence.

[0180] Figure 44A shows a hybrid SAR+ serial ADC circuit 4400 that can be used to increase the number of bits in a hybrid manner. The SAR ADC circuit 4400 consists of a binary CDAC4401 and a comparator 440 2 and The SAR logic and register 4403 are included. As shown, GndV is a low-voltage reference level, e.g., ground level during SAR ADC operation. The SAR logic and register 4403 provide a digital output. Vin is the input voltage. VREFRAMP is used as the reference ramp voltage during serial ADC operation with appropriate control circuits and signal multiplexing (not shown).

[0181] Other hybrid ADC architectures that may be used include SAR ADC + sigma-delta ADC, flash ADC + serial ADC, pipelined ADC + serial ADC, serial ADC + SAR ADC, and other architectures.

[0182] Figure 44B shows a hybrid differential SAR + serial ADC circuit 4400 that can be used to increase the number of bits in a hybrid configuration.

[0183] Figure 45 shows an algorithmic ADC output block 4500. The output block 4500 includes a sample-and-hold circuit 4501, a 1-bit analog-to-digital converter 4502, a 1-bit digital-to-analog converter 4503, an adder 4504, an operational amplifier 4505, and controlled switches 4506 and 4507, configured as shown. The operational amplifier 4505 is shown configured to provide a gain of 2.

[0184] Figure 46 shows an output circuit described herein, as well as a tracking voltage reference generator 4600 used to generate a reference voltage that can be used by components of such output circuits, such as Figures 37A, 37B, 38A, 38B, 41, 42, 43, 44A, and 44B.

[0185] The tracking voltage reference generator 4600 includes a bias current generator 4601 and a variable resistor 4602, and the output VREFx4603=i * R is generated, where i is the bias current from 4601 and R is the resistance of the variable resistor 4602.

[0186] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

1. An output circuit for generating an output from an array of nonvolatile memory cells, wherein the array includes nonvolatile memory cells arranged in rows and columns, and the output circuit is A first analog-to-digital converter for converting a first current from a first bit line coupled to a first column of the array and a second current from a second bit line coupled to a second column of the array into a first set of bits, wherein the first current and the second current form a differential signal; An output circuit comprising: a second analog-to-digital converter for converting the remainder of a signal after conversion by the first analog-to-digital converter into a second set of bits, and providing the first set of bits and the second set of bits as the output.

2. The output circuit according to claim 1, wherein the second analog-to-digital converter includes a series output circuit that receives a portion of bits from the first analog-to-digital converter and arranges the portion of bits and the remainder of the bits in series.

3. The output circuit according to claim 1, wherein the first analog-to-digital converter and the second analog-to-digital converter each include a successive approximation register analog-to-digital converter.

4. The output circuit according to claim 3, wherein each of the successive approximation register analog-to-digital converters includes one or more capacitors.

5. The output circuit according to claim 1, wherein the first analog-to-digital converter and the second analog-to-digital converter each include an algorithmic analog-to-digital converter.

6. The output circuit according to claim 1, wherein the array of non-volatile memory cells is a neural network memory array.

7. The output circuit according to claim 6, wherein each nonvolatile memory cell in the array of nonvolatile memory cells is capable of storing one of three or more possible values.

8. The output circuit according to claim 1, wherein each of the non-volatile memory cells in the array is a split-gate flash memory cell.

9. The output circuit according to claim 1, wherein one or more of the first analog-to-digital converter and the second analog-to-digital converter are shared between the array of nonvolatile memory cells and one or more other arrays of nonvolatile memory cells.

Images