Address generation for adaptive double-device data correction and sparing.

Abstract

To provide a memory controller, a method, a system, a program, and a storage medium for implementing error correction in adaptive double device data correction sparing.SOLUTION: Adaptive double device data correction sparing uses memory addresses in ascending order. The last sparing address is stored as a memory address. Each system address for a processor memory transaction is converted to a memory address. The memory address is compared with the last sparing address to determine the error code correction format for the processor memory transaction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to memory management, and more particularly, to memory error management.

Background Art

[0002] Spare techniques are used to withstand hard dynamic random access memory (DRAM) failures or hard errors. A hard error refers to an error associated with a physical device that prevents the physical device from correctly performing a read and / or write operation, and is distinguished from a transient error that is an intermittent failure. Techniques for single device data correction (SDDC), double device data correction (DDDC), and adaptive double device data correction (ADDDC) that provide error checking and correction to protect against memory failures caused by hard failures in DRAM are known.

[0003] SDDC checks and corrects single-bit or multi-bit memory failures that affect an entire single DRAM device. DDDC provides error checking and correction to protect against memory failures in two series-connected DRAM devices. ADDDC can be implemented at a rank or bank granularity. A rank is a set of DRAM devices connected to the same chip select. A bank is an array of memory locations within a DRAM device.

[0004] The sparing operation copies the content of the memory to another location or another format. Examples of the sparing operation include rank sparing in which data from a defective rank is copied to a spare rank, and device sparing in which the content of a defective DRAM device is copied to another DRAM device.

Brief Description of Drawings

[0005] Features of embodiments of the claimed subject matter will become apparent by reference to the drawings as the following detailed description progresses, in which similar reference numerals indicate similar parts.

[0006] [Figure 1] This is a block diagram of the memory subsystem, including the memory and the memory controller. [Figure 2] This is a block diagram of one embodiment of a system having a memory subsystem including at least one memory module coupled to a memory controller. [Figure 3] This diagram shows cache lines stored in two memory regions operating in a non-lockstep configuration. [Figure 4] This figure shows the cache lines stored in the faulty and non-faulty memory regions within memory, operating in a lockstep configuration after ADDDC sparing is complete. [Figure 5] This figure shows an example of a spare address for ADDDC mode using the system address. [Figure 6] This figure shows the method performed in the memory controller to execute a spare copy. [Figure 7] This is a block diagram of one embodiment of a computer system including a memory controller.

[0007] The following detailed description proceeds with reference to exemplary embodiments of the claimed subject matter, but many substitutions, modifications, and variations thereof will be apparent to those skilled in the art. Therefore, the claimed subject matter is intended to be interpreted broadly and defined as set forth in the attached claims. [Modes for carrying out the invention]

[0008] The spare copy operation copies data from one rank (a set of dynamic random access memory (DRAM) devices connected to the same chip select) to another rank if a spare rank is available, or copies data to the same location using a different error correction code (ECC) format to acquire a spare device. The spare device can be used to store data from the failed DRAM device. The data may be split between the spare DRAM device and another non-failed DRAM device.

[0009] To perform a spare copy using the Adaptive Double Device Data Correction (ADDDC) format, the first half of the cache line is written to the original location (the faulty location within the faulty DRAM device), and the second half of the cache line is written to the non-faulty location (the non-faulty location within the non-faulty DRAM device). Similarly, the original cache line in the non-faulty location is stored in both the faulty and non-faulty locations. Therefore, data must be read from both the faulty and non-faulty locations and then written back to avoid data loss. The faulty and non-faulty locations have different system addresses, which are typically non-contiguous system addresses.

[0010] Processor memory transactions are executed while a spare copy is running. Each memory address for a processor memory transaction is compared to the last spare copy memory address. If the memory address for a processor memory transaction is less than or equal to the last spare copy memory address, a new error correction code format is used. Otherwise, the old error correction code format is used.

[0011] In ADDDC sparing, there are two system addresses that need to be copied for each faulty system address or location on the failed memory device. In rank-based ADDDC sparing, the two system addresses share a common bank / row / column. In bank-based ADDDC sparing, the two system addresses share a common row / column. Each memory address for a processor memory transaction is compared to the last spare copy memory address using the bank / row / column, so the order must be the same in both formats. This is further complicated when the bank / row / column comes from different system address bits in different decryption modes, when address exclusive OR (XOR) is applied, and / or when decryption is performed using modulo operations.

[0012] In addition, the system address is logged when an ECC error is detected during a sparing read, and the memory address region specified in the system address (e.g., 1-level memory, 2-level memory) can support different ECC formats.

[0013] ADDDC can be implemented at a certain rank or bank granularity. Instead of using system addresses, ADDDC sparing uses memory addresses (bank / row / column addresses (for ADDDC implemented at rank granularity) or row / column addresses (for ADDDC implemented at bank granularity)) in ascending order. The last sparing address is stored as a memory address. Each system address for a processor memory transaction is translated to a processor memory address. The processor memory address is compared to the last sparing address, and the ECC format for the processor memory address is determined using only the fields common between the failed and non-failed addresses. Reverse address translation is implemented to translate the processor memory address back to a system address for error logging and to determine the attributes available at the system address.

[0014] Figure 1 is a block diagram of the memory subsystem 104, which includes memory 140 and memory controller 106.

[0015] Memory 140 is volatile memory. Volatile memory is memory whose state (and therefore the data stored on it) is uncertain when power to the device is cut off. Dynamic volatile memory requires the data stored in the device to be refreshed in order to maintain its state. One example of dynamic volatile memory is DRAM (Dynamic Random Access Memory), or several variations of synchronous DRAM (SDRAM). The memory subsystem described herein is DDR3 (Double Data Rate Version 3), certified by JEDEC (Joint Electronic Device Engineering) on ​​June 27, 2007. DDR4 (DDR version 4, i.e., the initial JESD79-4 specification published by JEDEC in September 2012), DDR4E (Extended DDR version 4, currently under discussion by JEDEC), LPDDR3 (Low Power DDR version 3, i.e., JESD209-3B by JEDEC in August 2013), LPDDR4 (Low Power Double Data Rate (LPDDR) version 4, i.e., JESD209-4, first published by JEDEC in August 2014), WIO2 (Wide I / O2 (Wide I It may be compatible with many memory technologies, including O2), i.e., JESD229-2), first published by JEDEC in August 2014; HBM (High Bandwidth Memory DRAM, i.e., JESD235), first published by JEDEC in October 2013; DDR5 (DDR version 5, currently under discussion by JEDEC); LPDDR5, first published by JEDEC in January 2020; HBM2 (HBM version 2), first published by JEDEC in January 2020; or other or combinations of memory technologies, and technologies based on derivative or extended versions of such specifications. JEDEC standards are available at www.jedec.org.

[0016] The memory 140 comprises one or more devices 146. In one embodiment, the memory device 146 is a DRAM device. The memory address 122 may include a rank address, bank address, row address, and column to identify row 142 and column in bank 144 in device 146 in rank 148 in the memory 140.

[0017] The address decoding circuit 112 in the memory controller 106 translates the received system address 120 into a memory address 122. The memory address 122 may contain bits to identify the DIMM and rank within the memory 140. The system address 120 can be used to access all locations within the memory 140, or to access only locations for one channel (channel address) within the memory 140.

[0018] Sparing operations are performed by a sparing circuit 130. Sparing operations copy the contents of memory to a different location or format. Examples of sparing operations include rank sparing, in which data from a faulty rank is copied to a spare rank, and device sparing, in which the contents of a faulty DRAM device are copied to another DRAM device. The sparing circuit 130 generates a memory address 122. The reverse address decoding circuit 114 converts the memory address 122 to a converted system address used for error logging and sparing operations.

[0019] The memory 140 can be a 3D stacked (3DS) DIMM having subranks that do not have a physical chip select. In one embodiment, subranks are grouped using banks. In rank ADDDC, faulty addresses and non-faulty addresses have the same subrank value. In another embodiment, subranks are grouped using ranks in rank ADDDC.

[0020] Figure 2 is a block diagram of one embodiment of a system 200 having a memory subsystem including at least one memory module 270 coupled to a memory controller 220. The memory controller 220 comprises an address decoding circuit 112, a reverse address decoding circuit 114, a sparing circuit 130, and a scheduler 110, as discussed in relation to Figure 1. The system 200 comprises a processor 210 and elements of the memory subsystem within the computing device. The processor 210 represents a processing unit of a computing platform capable of running an operating system (OS) and applications, the OS and applications may be collectively referred to as the memory host or user. The OS and applications perform operations that result in memory access. The processor 210 may include one or more separate processors. Each separate processor may include a single processing unit, a multicore processing unit, or a combination thereof. The processing unit may be a main processor such as a CPU (Central Processing Unit), a peripheral processor such as a GPU (Graphics Processing Unit), or a combination thereof. Memory access may also be initiated by a device such as a network controller or a storage controller. Such devices can be integrated with a processor within several systems (e.g., within a system-on-a-chip (SoC)), or attached to a processor via a bus (e.g., Peripheral Component Interconnect Express (PCIe)), or a combination of both.

[0021] References to memory devices may apply to volatile memory technology or non-volatile memory technology. References to “RAM” or “RAM device” in this specification may apply to any memory device that enables random access, whether volatile or non-volatile. References to “DRAM” or “DRAM device” may refer to a volatile random-access memory device. A memory device or DRAM may refer to the die itself, a packaged memory product containing one or more dies, or both. In one embodiment, a system having volatile memory that needs to be refreshed may also include non-volatile memory.

[0022] Memory controller 220 represents one or more memory controller circuits or devices for system 200. Memory controller 220 represents control logic that generates memory access commands in response to the execution of operations by processor 210. Memory controller 220 accesses one or more memory devices 240. Memory device 240 can be a DRAM device by any of those referred to above. Memory controller 220 includes I / O interface logic 222 for coupling to a memory bus. I / O interface logic 222 (and I / O interface logic 242 of memory device 240) can include pins, pads, connectors, signal lines, traces, or wires, or other hardware for connecting devices, or combinations thereof. I / O interface logic 222 can include a hardware interface. As shown, I / O interface logic 222 includes at least a driver / transceiver for signal lines. Generally, wires within an integrated circuit interface couple with pads, pins, or connectors to interface connect signal lines or traces or other wires between devices. I / O interface logic 222 can include drivers, receivers, transceivers, or terminations, or other circuits or combinations of circuits for exchanging signals on signal lines between devices.

[0023] Signal exchange includes at least one of transmission or reception. The I / O interface logic 222 from the memory controller 220 is shown as coupled to the I / O interface logic 242 of the memory device 240. On the other hand, in one implementation of system 200 in which a group of memory devices 240 are accessed in parallel, it will be understood that multiple memory devices may have I / O interfaces to the same interface of the memory controller 220. In one implementation of system 200 with one or more memory modules 270, the I / O interface logic 242 may include the interface hardware of the memory modules in addition to the interface hardware of the memory devices themselves. Other memory controllers 220 may include separate interfaces to other memory devices 240.

[0024] The bus between the memory controller 220 and the memory device 240 can be a double data rate (DDR) high-speed DRAM interface for transferring data, which is implemented as multiple signal lines connecting the memory controller 220 to the memory device 240. The bus may typically include at least a clock (CLK) 232, a command / address (CMD) 234, data (write data (DQ) and read data (DQ0)) 236, and zero or more control signal lines 238. In one embodiment, the bus or connection between the memory controller 220 and the memory may be referred to as the memory bus. The signal lines for the CMD may be referred to as the "C / A bus" (or ADD / CMD bus, or any other name indicating the transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for the data (write DQ and read DQ) may be referred to as the "data bus". In addition to the explicitly indicated lines, it will be understood that the bus may include at least one of the following: strobe signaling lines, alert lines, auxiliary lines, or other signal lines, or a combination thereof. It will also be understood that serial bus technology can be used for connections between the memory controller 220 and the memory device 240. An example of serial bus technology is the 8B10B encoding and transmission of high-speed data in which the clock is embedded across a single differential pair of signals in each direction.

[0025] In one embodiment, one or more of CLK232, CMD234, Data236, or Control238 can be routed to memory device 240 through logic 280. Logic 280 can be or can include a register or buffer circuit. Logic 280 can reduce the load on the interface to I / O interface 222, thereby enabling faster signaling or reduced errors, or both. The reason for the load reduction is that I / O interface 222 recognizes only the termination of one or more signals in logic 280 instead of the termination of the signal lines in all one or more parallel memory devices 240. Although I / O interface logic 242 is not specifically shown as including a driver or transceiver, it will be understood that I / O interface logic 242 includes the hardware necessary to couple to the signal lines. Additionally, for the sake of brevity of explanation, I / O interface logic 242 does not show all the signals corresponding to those shown with respect to I / O interface 222. In one embodiment, all signals of I / O interface 222 have corresponding parts in I / O interface logic 242. Part or all of the signal lines interfacing I / O interface logic 242 can be provided from logic 280. In one embodiment, a particular signal from I / O interface 222 is coupled through logic 280 rather than directly to I / O interface logic 242, while one or more other signals can be directly coupled from I / O interface 222 to I / O interface logic 242 via I / O interface 272 without being buffered through logic 280. Signal 282 represents the signal that interfaces memory device 240 through logic 280.

[0026] In the example of system 200, it will be understood that the bus between the memory controller 220 and the memory device 240 includes an auxiliary command bus CMD234 and an auxiliary data bus 236. In one embodiment, the auxiliary data bus 236 may include bidirectional lines for read data and write / command data. In another embodiment, the auxiliary data bus 236 may include a unidirectional write signal line for writing data from the host to memory, as well as a unidirectional line for reading data from the memory device 240 to the host. Depending on the selected memory technology and system design, the control signals 238 may be associated with a bus or subbus such as a strobe line DQS. Based on the design of system 200, or based on the implementation if the design supports multiple implementations, the data bus may have a wider or narrower bandwidth per memory device 240. For example, the data bus may support memory devices 240 having an x32 interface, an x16 interface, an x8 interface, or another interface. In the notation "xW", W is an integer that refers to the interface size or width of the interface of the memory device 240, which represents the number of signal lines for exchanging data with the memory controller 220. This number is often, but not limited to, a binary number. The interface size of the memory device is a control factor for the number of memory devices that can be used simultaneously in the system 200 or that can be coupled in parallel on the same signal lines. In one embodiment, a high-bandwidth memory device, a wide interface device, or a stacked memory configuration, or a combination thereof, can enable wider interfaces such as an x128 interface, an x256 interface, an x512 interface, an x1024 interface, or other data bus interface widths.

[0027] The memory devices 240 represent memory resources for the system 200. In one embodiment, each memory device 240 is a separate memory die. Each memory device 240 includes I / O interface logic 242 having a bandwidth (e.g., x16, x8, or some other interface bandwidth) determined by the device implementation. The I / O interface logic 242 enables each memory device 240 to interface with the memory controller 220. The I / O interface logic 242 may include a hardware interface and may match the I / O interface logic 222 of the memory controller 220, but on the memory device side. In one embodiment, multiple memory devices 240 are connected in parallel to the same command and data bus. In another embodiment, multiple memory devices 240 are connected in parallel to the same command bus and to different data buses. For example, the system 200 may be configured with multiple memory devices 240 coupled in parallel, with each memory device responding to commands and accessing its own internal memory resources 260. For write operations, each memory device 240 can write a portion of the entire data word, and for read operations, each memory device 240 can fetch a portion of the entire data word. As a non-limiting example, a particular memory device may each provide or receive 8 bits of a 128-bit data word, or 8 or 16 bits (depending on the x8 or x16 device) of a 256-bit data word for a read or write transaction. The remaining bits of this word are provided or received in parallel by other memory devices.

[0028] In one embodiment, the memory device 240 can be organized into a memory module 270. In one embodiment, the memory module 270 represents a dual inline memory module (DIMM). The memory module 270 may include multiple memory devices 240, and the memory module may include support for multiple separate channels to the included memory devices arranged on them.

[0029] Each memory device 240 includes a memory resource 260, which represents an individual array of memory locations or storage locations for data. Typically, the memory resource 260 is managed as rows of data and accessed via control of word lines (rows) and bit lines (individual bits within a row). The memory resources 260 can be organized as separate banks of memory, where a bank refers to an array of memory locations within the memory device 240. In one embodiment, a bank of memory is divided into subbanks, each having at least some of the shared circuitry for the subbanks (e.g., drivers, signal lines, control logic).

[0030] In one embodiment, the memory device 240 comprises one or more registers 244. The registers 244 represent one or more storage devices or storage locations that provide configuration or settings for the operation of the memory device. In one embodiment, the registers 244 may provide storage locations for the memory device 240 to store data for access by the memory controller 220 as part of a control or management operation. In one embodiment, the registers 244 include one or more mode registers. In one embodiment, the registers 244 include one or more multipurpose registers. The configuration of locations in the registers 244 can configure the memory device 240 to operate in different “modes,” where command information can trigger different operations within the memory device 240 based on the mode. In addition, or in alternative forms, different modes can also trigger different operations from address information or other signal lines, depending on the mode. The settings in the registers 244 can indicate configurations for I / O settings (e.g., timing, termination, driver configuration, or other I / O settings).

[0031] The memory controller 220 includes a scheduler 110 which represents logic or circuitry for generating and instructing transactions to be sent to the memory device 240. From one perspective, the main function of the memory controller 220 is to schedule memory access and other transactions to the memory device 240. Such scheduling may include generating transactions itself to implement data requests by the processor 210 and maintaining data integrity (for example, using commands related to refresh).

[0032] A transaction may include one or more commands and may result in the transfer of commands or data, or both, in one or more timing cycles, such as a clock cycle or a unit interval. A transaction may be for access, such as reading or writing, or related commands or combinations thereof, and other transactions may include memory management commands for configuration, setting, data integrity, or other commands or combinations thereof.

[0033] The memory controller 220 typically includes logic to improve the performance of the system 200 by enabling the selection and ordering of transactions. Therefore, the memory controller 220 can select which of the pending transactions should be sent to the memory device 240 and in what order, which is typically achieved using logic far more complex than a simple first-in, first-out algorithm. The memory controller 220 manages the sending of transactions to the memory device 240 and manages the timing associated with the transactions. In one embodiment, the transactions have deterministic timing, which is managed by the memory controller 220 and can be used to determine how to schedule the transactions.

[0034] Referring again to the memory controller 220, the memory controller 220 includes command (CMD) logic 224, which represents logic or circuitry for generating commands to be sent to the memory device 240. Command generation can refer to the preparation of commands prior to scheduling or queued commands ready for transmission. In general, signaling in the memory subsystem includes address information within or accompanying the command that indicates or selects one or more memory locations on which the memory device should execute the command. In response to the scheduling of a transaction for the memory device 240, the memory controller 220 can issue such commands via I / O 222 to cause the memory device 240 to execute them. The memory controller 220 can implement compliance with standards or specifications through access scheduling and control.

[0035] Referring again to logic 280, in one embodiment, logic 280 buffers a specific signal 282 from the host to the memory device 240. In one embodiment, logic 280 buffers data signal lines 236 as data 286 and command (or command and address) lines of CMD234 as CMD284. In one embodiment, data 286 is buffered but contains the same number of signal lines as data 236. Therefore, both are shown as having X signal lines. In contrast, CMD234 has fewer signal lines than CMD284. Hence, P > N. The N signal lines of CMD234 operate at a higher data rate than the P signal lines of CMD284. For example, P can be equal to 2N, and CMD284 can operate at half the data rate of CMD234.

[0036] In one embodiment, the memory controller 220 includes a refresh logic 226. The refresh logic 226 is used for volatile memory resources 260 that may need to be refreshed to maintain a deterministic state. In one embodiment, the refresh logic 226 indicates the location for the refresh and the type of refresh to be performed. The refresh logic 226 can perform an external refresh by sending a refresh command. For example, in one embodiment, the system 200 supports whole-bank refresh and bank-specific refresh. A whole-bank refresh results in a refresh of a selected bank 292 within all parallel-coupled memory devices 240. A bank-specific refresh results in a refresh of a specified bank 292 within a specified memory device 240.

[0037] System 200 may include a memory circuit that is or may include a logic 280. As far as the circuit is considered to be a logic 280, it may refer to a circuit or component (such as one or more discrete elements or one or more elements of a logic chip package) that buffers the command bus. As far as the circuit is considered to include a logic 280, the circuit may include pins of one or more component packages and may include signal lines. The memory circuit includes an interface to N signal lines of the CMD234, which operate at a first data rate. The N signal lines of the CMD234 are host-side with respect to the logic 280. The memory circuit may also include an interface to P signal lines of the CMD284, which operate at a second data rate lower than the first data rate. The P signal lines of the CMD284 are memory-side with respect to the logic 280. Logic 280 can be considered as control logic that receives command signals and provides them to memory devices, or it may internally include control logic (e.g., its processing elements or logic core) that receives command signals and provides them to memory devices.

[0038] Figure 3 shows cache lines stored in two regions 302 and 304 within memory 140, operating in a non-lockstep configuration. These regions can be memory rank 148 or memory bank 144. The error correction code (ECC) format used in the non-lockstep configuration is Single Data Device Correction (SDDC).

[0039] Each cache line stored in memory 140 includes an upper half and a lower half. Cache line 306 at address A in region 302 includes the upper half 306a and the lower half 306b of address A. Cache line 308 at address B in region 304 includes the upper half 308a and the lower half 308b of address B. In one embodiment, cache lines 306 and 308 have 64 bytes, and the upper halves 306a and 308a and the lower halves 306b and 308b of cache lines 306 and 308 each have 32 bytes.

[0040] After a failure is detected in memory regions 302 and 304, the failed memory region is paired with a non-faulty memory region. The failed and non-faulty memory regions are the same size. The ECC (Error Correction Code) format is changed from SDDC to ADDDC when cache lines in the failed or non-faulty memory region are copied to both the failed and non-faulty memory regions in virtual lockstep (VLS) mode.

[0041] Figure 4 shows the cache lines stored in the faulty memory area 402 and the non-faulty memory area 404 within memory 140, operating in a lockstep configuration after the completion of ADDDC sparing. The faulty memory area 402 is paired with the non-faulty memory area 404. Cache lines in the faulty memory area 402 or the non-faulty memory area 404 are copied by the sparing circuit 130 in the memory controller 106 to both the faulty memory area 402 and the non-faulty memory area 404 in a virtual lockstep format. The lower half of address A 306b and the lower half of address B 308b are referred to as "primary" and are not copied. The upper half of address A 306a and the upper half of address B 308a are referred to as "buddies" and are copied. That is, the upper half of address A 306a is copied to the non-faulty memory area 404, and the upper half of address B 308a is copied to the faulty memory area 402.

[0042] To perform data transfer between the faulty memory area 402 and the non-faulty memory area 404, the sparering circuit 130 walks through all memory addresses in the faulty memory area 402. Data from the faulty addresses in the faulty memory area 402 (the lower half of address A 306b and the upper half of address A 306a) and data from the associated addresses in the non-faulty memory area 404 (the lower half of address B 308b and the upper half of address B 308a) are read and stored in the memory controller 106.

[0043] The spare circuit 130 writes the lower half of address A 306b and the upper half of address B 308a to the faulty area 402, and the upper half of address A 306a and the lower half of address B 308b to the non-faulty area 404. This process can be called a spare copy. The spare copy can be periodically paused to allow other memory access requests (e.g., CPU memory access requests) to be executed within memory 140.

[0044] Figure 5 shows an example of spared addresses for ADDDC mode using system addresses. In the example shown, the spared circuit 130 (also called the spared engine) checks through system addresses 0-15 (binary 0000-1111) 500. Sparing completes spare copies for addresses 502 (system addresses 0-4) and 506 (system addresses 8-12). Addresses 502 and 504 use the ADDDC format for ECC. Addresses 504 and 508 use the SDDC format for ECC. The last fault-to-reach spare system address 510 is 4, and the last non-fault-to-reach spare system address 512 is 12. In rank-based ADDDC sparedling, two system addresses share a common bank / row / column. In bank-based ADDDC sparedling, two system addresses share a common row / column. In the example shown in Figure 5, for rank-based sparing, the most significant bit of the system address corresponds to the rank (rank 0 or rank 1) in the corresponding memory address, and the other three bits correspond to the bank / row / column in the corresponding memory address.

[0045] Returning to Figure 1, the address decoder 112 in the memory controller 106 translates the system address 120 into the memory address 122. The memory address 122 is in bank / row / column format. ADDDC sparing uses memory addresses in ascending order. The memory address contains either a bank / row / column address (for ADDDC implemented at rank granularity) or a row / column address (for ADDDC implemented at bank granularity). The sparing circuit 130 in the memory controller 106 operates on memory address 122, incrementing memory address 122 to perform the sparing operation. The last sparing address is stored as the memory address (last sparing memory address). Each system address 120 for a processor memory transaction is translated into a processor memory address in the address decoder 112. The processor memory address is compared to the last spare copy memory address, and only the bits common between the failed and non-failed addresses are used to determine the ECC format (ADDDC or SDDC) for the processor memory address. In rank-based ADDDC sparing, two system addresses share a common bank / row / column (the memory address includes the row address, column address, and bank address). In bank-based ADDDC sparing, two system addresses share a common row / column (the memory address includes the row address and column address). If the processor memory address is smaller than or equal to the last spare copy memory address, the ADDDC format is used. Otherwise, the SDDC format is used.

[0046] In order to translate the processor memory address back to the system address for error logging within the error circuit 130, and to determine the attributes available at the system address, reverse address translation is implemented in reverse address decoding 114. The attributes at the system address can indicate whether the system address is for one-level memory or for near memory of two-level memory.

[0047] Figure 6 shows the method performed by the memory controller 106 to execute a spare copy.

[0048] In block 600, the first address pair for sparering is reverse-translated from memory address 122 to system address 120 by the sparering circuit 130 in the memory controller 106.

[0049] In block 602, a spare copy of the current sparering address pair is performed. The reverse address translation may take multiple cycles (for example, to handle division by a value that is not a power of 2, such as division by 3). The reverse address translation for the next sparering address pair is performed while the sparering copy of the current address pair is in progress to hide the reverse translation time.

[0050] If all faulty addresses have been copied in block 604, processing continues to block 612. Otherwise, processing continues to block 606.

[0051] If the spare period for performing a spare operation (also known as a spare window) has expired in block 606, the process continues to block 608. Otherwise, the process continues to block 602 to perform a spare copy of the next pair of spare addresses.

[0052] In block 608, the processor memory operation is released. The processor memory address is compared with the last spared address pair to determine the ECC format to use.

[0053] If the processor time for executing a processor memory operation (also known as a CPU transaction window) has expired in block 610, the process continues to block 602 to execute the next sparing operation. Otherwise, the process continues to block 608 to execute the next processor memory operation.

[0054] At block 612, the spare copy is completed.

[0055] Figure 7 is a block diagram of one embodiment of a computer system 700 including a memory controller 106. The computer system 700 can be a computing device including, but is not limited to, a server, a workstation computer, a desktop computer, a laptop computer, and / or a tablet computer.

[0056] The computer system 700 includes a system-on-a-chip (SOC or SoC) 704 that combines a processor, graphics, memory, and input / output (I / O) control logic into a single SoC package. The SoC 704 includes at least one central processing unit (CPU) module 708, a memory controller 106, and a graphics processor unit (GPU) 710. In other embodiments, the memory controller 106 may be external to the SoC 704. The CPU module 708 includes at least one processor core 702 and a level 2 (L2) cache 706. The memory controller 106 is communicatively coupled to memory 140. The memory controller 106 includes a reverse address decoding circuit 114 and a sparing circuit 130, as discussed in relation to Figure 1.

[0057] Although not shown, each of the processor cores 702 may internally include one or more instruction / data caches, execution units, prefetch buffers, instruction queues, branch address calculation units, instruction decoders, floating-point units, retirement units, etc. The CPU module 708 can, according to one embodiment, support a single-core or multi-core general-purpose processor, such as those provided by Intel® Corporation.

[0058] The graphics processor unit (GPU) 710 may comprise one or more GPU cores and a GPU cache capable of storing graphics-related data of the GPU cores. The GPU cores may internally include one or more execution units and one or more instruction and data caches. In addition, the graphics processor unit (GPU) 710 may include one or more vertex processing units, rasterization units, media processing units, and other graphics logic units not shown in Figure 7, such as codecs.

[0059] Within the I / O subsystem 712, one or more I / O adapters 716 exist to translate host communication protocols used within the processor core 702 into protocols compatible with specific I / O devices. Some of the protocols for which adapters can be used for translation include Peripheral Component Interconnect (PCI) Express (PCIe), Universal Serial Bus (USB), Serial Advanced Technology Attachment (SATA), and IEEE 1594 "Firewire®".

[0060] The I / O adapter 716 can communicate with an external I / O device 724, which may include, for example, a display and / or touchscreen display 748, a printer, a keypad, a keyboard, a user interface device including wired and / or wireless communication logic, a storage device including a hard disk drive ("HDD"), a solid-state drive ("SSD"), removable storage media, a digital video disc (DVD) drive, a compact disc (CD) drive, a RAID independent disk redundancy array (RAID), a tape drive, or other storage devices. The storage devices may be communicatively and / or physically coupled together via one or more buses using one or more of a variety of protocols, which include, but are not limited to, SAS (Serial Attached SCSI (Small Computer System Interface)), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express) over PCIe (Peripheral Component Interconnect Express), and SATA (Serial ATA (Advanced Technology Attachment)).

[0061] In addition, one or more wireless protocol I / O adapters may be present. Examples of wireless protocols used include, in particular, personal area networks such as IEEE 802.15 and Bluetooth® 4.0, wireless local area networks such as IEEE 802.11-based wireless protocols, and cellular protocols.

[0062] Memory 140 can store the operating system 746. The operating system 746 is software that manages computer hardware and software, including memory allocation and access to I / O devices. Examples of operating systems include Microsoft® Windows®, Linux®, iOS®, and Android®.

[0063] The power supply 740 provides power to the components of the system 700. More specifically, the power supply 740 typically interfaces with one or more power supply units 742 within the system 700 to provide power to the components of the system 700. In one example, the power supply unit 742 includes an AC-DC (alternating current to direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy (e.g., solar power) power supply 740. In one example, the power supply 740 includes a DC power source such as an external AC-DC converter. In one example, the power supply 740 or power supply unit 742 includes wireless charging hardware for charging by proximity to a charging magnetic field. In one example, the power supply 740 may include an internal battery or fuel cell power source.

[0064] Various embodiments and aspects of the present invention are described with reference to the details discussed below, and the accompanying drawings illustrate various embodiments. The following description and drawings are illustrative of the present invention and should not be construed as limiting the invention. Numerous specific details are described in order to provide a complete understanding of the various embodiments of the present invention. However, in certain examples, well-known or prior art details are omitted in order to provide a concise description of embodiments of the present invention.

[0065] Any reference in this specification to “one embodiment” or “an embodiment” means that certain features, structures, or characteristics described in relation to that embodiment may be included in at least one embodiment of the present invention. The phrase “in one embodiment” appearing in various parts of this specification does not necessarily refer to the same embodiment.

[0066] Flow diagrams, as shown herein, provide examples of sequences of various process actions. Flow diagrams can illustrate actions to be performed by software or firmware routines and physical actions. In one embodiment, a flow diagram can illustrate the states of a finite state machine (FSM), which can be implemented in hardware and / or software. The order of actions is shown in a specific sequence or order, but can be modified unless otherwise specified. Therefore, the embodiments shown should be understood as examples, processes can be executed in different orders, and some actions can be executed in parallel. In addition, one or more actions can be omitted in various embodiments, and therefore not all actions are required in all embodiments. Other process flows are also possible.

[0067] Various operations or functions described herein may be described or defined as software code, instructions, configurations, and / or data to the extent described herein. Content may be directly executable ("object" or "executable" format), as source code, or as differential code ("delta" or "patch" code). Software content of embodiments described herein may be provided via a manufactured product on which the content is stored, or by operating a communication interface to transmit data through the communication interface. Machine-readable storage media include any mechanism that can cause a machine to perform the described functions or operations and stores information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable / non-recordable media (e.g., read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism for interface connection to any medium, such as hardwired, wireless, or optical, for communication with another device, such as a memory bus interface, a processor bus interface, an internet connection, or a disk controller. A communication interface can be configured to prepare for providing data signals that describe software content by providing configuration parameters and / or transmitting signals. A communication interface can be accessed via one or more commands or signals transmitted to it.

[0068] The various components described herein can be means for performing the operations or functions described herein. Each component described herein includes software, hardware, or a combination thereof. Components can be implemented as software modules, hardware modules, dedicated hardware (e.g., application-specific hardware, application-specific integrated circuits (ASICs), digital signal processors (DSPs), etc.), embedded controllers, hardwired circuits, etc.

[0069] In addition to those described herein, various modifications can be made to the disclosed embodiments and implementations of the present invention without departing from their scope.

[0070] Therefore, the examples and illustrations herein should be construed as illustrative and not restrictive. The scope of the present invention should be determined by referring only to the following claims. [Other possible items] [Item 1] It is a memory controller, A sparering circuit that stores the last sparering address as a memory address for memory, converts the system address for processor memory transactions to a processor memory address, compares the processor memory address with the last sparering address to determine the error correction code format for the processor memory address, A reverse address decoding circuit receives the processor memory address from the sparering circuit and converts the processor memory address into a second system address for error logging. A memory controller equipped with the following features. [Item 2] The memory controller described in item 1, wherein the error correction code format is adaptive double-device data correction (ADDDC) or single-device data correction (SDDC). [Item 3] The error correction code format is adaptive double device data correction (ADDDC), and the sparering circuit ensures that memory addresses are used in ascending order, as described in item 1 of the memory controller. [Item 4] The aforementioned sparering circuit is a memory controller as described in item 3, which performs rank-based ADDDC sparering. [Item 5] The aforementioned sparering circuit is a memory controller as described in item 3, which performs bank-based ADDDC sparering. [Item 6] The memory is a dynamic random access memory, as described in item 5. [Item 7] The memory address refers to the memory controller described in item 6, including the row address, column address, and bank address. [Item 8] A method performed by the memory controller, In a sparering circuit, there is a step in which the last sparering address is stored as a memory address for memory, The sparering circuit includes the step of converting a system address for a processor memory transaction to a processor memory address, The sparering circuit includes the step of comparing the processor memory address with the last sparering address to determine the error correction code format for the processor memory address, In the reverse address decoding circuit, the step of converting the processor memory address to a second system address for error logging is included. A method that includes [a certain feature]. [Item 9] The method according to item 8, wherein the error correction code format is adaptive double-device data correction (ADDDC) or single-device data correction (SDDC). [Item 10] The error correction code format is adaptive double device data correction (ADDDC), and the sparing circuit is configured to use memory addresses in ascending order, as described in item 8. [Item 11] The sparering circuit performs rank-based ADDDC sparering, as described in item 10. [Item 12] The sparering circuit performs bank-based ADDDC sparering, as described in item 10. [Item 13] The memory is a dynamic random access memory, as described in item 8. [Item 14] It is a system, Processor and Memory and A memory controller that is communicatively coupled to the processor and the memory. Equipped with, The aforementioned memory controller A sparering circuit that stores the last sparering address as a memory address, converts the system address for a processor memory transaction to a processor memory address, compares the processor memory address with the last sparering address to determine the error correction code format for the processor memory address, A reverse address decoding circuit receives the processor memory address from the sparering circuit and converts the processor memory address into a second system address for error logging. A system that has [Item 15] The error correction code format is adaptive double-device data correction (ADDDC) or single-device data correction (SDDC), as described in item 14. [Item 16] The error correction code format is adaptive double device data correction (ADDDC), and the sparering circuit is configured to use memory addresses in ascending order, as described in item 14. [Item 17] The aforementioned sparering circuit is a system described in item 16 that performs rank-based ADDDC sparering. [Item 18] The aforementioned sparering circuit performs bank-based ADDDC sparering, as described in item 16. [Item 19] The memory is a dynamic random access memory, as described in item 14 of the system. [Item 20] A display that is communicatively coupled to the aforementioned processor, or Battery coupled to the aforementioned processor The system described in item 14, further comprising one or more of the above.

Claims

1. It is a memory controller, A sparering circuit that stores the last sparering address as a memory address for memory, converts the system address for processor memory transactions to a processor memory address, compares the processor memory address with the last sparering address to determine the error correction code format for the processor memory address, A reverse address decoding circuit receives the processor memory address from the sparering circuit and converts the processor memory address into a second system address for error logging. A memory controller equipped with the following features.

2. The memory controller according to claim 1, wherein the error correction code format is adaptive double device data correction (ADDDC) or single device data correction (SDDC).

3. The memory controller according to claim 1, wherein the error correction code format is adaptive double device data correction (ADDDC), and the sparering circuit uses memory addresses in ascending order.

4. The memory controller according to claim 3, wherein the sparering circuit performs rank-based ADDDC sparering.

5. The memory controller according to claim 3, wherein the sparering circuit performs bank-based ADDDC sparering.

6. The memory controller according to claim 5, wherein the memory is a dynamic random access memory.

7. The memory controller according to claim 6, wherein the memory address includes a row address, a column address, and a bank address.

8. A method performed by the memory controller, In a sparering circuit, there is a step in which the last sparering address is stored as a memory address for memory, The sparering circuit includes the step of converting a system address for a processor memory transaction to a processor memory address, The sparering circuit includes the step of comparing the processor memory address with the last sparering address to determine the error correction code format for the processor memory address, In the reverse address decoding circuit, the step of converting the processor memory address to a second system address for error logging is... A method that includes [a certain feature].

9. The method according to claim 8, wherein the error correction code format is adaptive double-device data correction (ADDDC) or single-device data correction (SDDC).

10. The method according to claim 8, wherein the error correction code format is adaptive double device data correction (ADDDC), and the sparing circuit uses memory addresses in ascending order.

11. The method according to claim 10, wherein the sparering circuit performs rank-based ADDDC sparering.

12. The method according to claim 10, wherein the sparering circuit performs bank-based ADDDC sparering.

13. The method according to claim 8, wherein the memory is a dynamic random access memory.

14. An apparatus comprising means for performing the method described in any one of claims 8 to 13.

15. A computer program that, when executed, includes code that causes a computer to perform the method described in any one of claims 8 to 13.

16. It is a system, Processor and Memory and A memory controller that is communicatively coupled to the processor and the memory. Equipped with, The aforementioned memory controller A sparering circuit that stores the last sparering address as a memory address, converts the system address for a processor memory transaction to a processor memory address, compares the processor memory address with the last sparering address to determine the error correction code format for the processor memory address, A reverse address decoding circuit receives the processor memory address from the sparering circuit and converts the processor memory address into a second system address for error logging. A system that has

17. The system according to claim 16, wherein the error correction code format is adaptive double-device data correction (ADDDC) or single-device data correction (SDDC).

18. The system according to claim 16, wherein the error correction code format is adaptive double device data correction (ADDDC), and the sparing circuit uses memory addresses in ascending order.

19. The system according to claim 18, wherein the sparering circuit performs rank-based ADDDC sparering.

20. The system according to claim 18, wherein the sparering circuit performs bank-based ADDDC sparering.

21. The system according to claim 16, wherein the memory is a dynamic random access memory.

22. A display that is communicatively coupled to the aforementioned processor, or Battery coupled to the aforementioned processor The system according to claim 16, further comprising one or more of the above.

23. A computer-readable recording medium for storing the computer program described in claim 15.

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