Methods for manufacturing devices and semiconductor devices (rear power rails and power grids for density scaling)

Abstract

To provide a semiconductor integrated circuit device configured to reduce cell-to-cell spacing and cell height of standard cells such as standard CMOS cells, and methods for fabricating such semiconductor devices.SOLUTION: A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source / drain element of the first transistor to the first interconnect structure, and a second contact connecting a source / drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacently to the second cell, and the first transistor is disposed adjacently to the second transistor. The first and second cells are disposed between the first and second interconnect structures.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] This disclosure relates in general to techniques for density scaling of semiconductor integrated circuits, and in particular to techniques for reducing the inter-cell spacing and cell height of standard cells, such as standard CMOS (complementary metal-oxide-semiconductor) cells. Typically, complex logic designs are constructed using upright cells built from standard cells. Thus, continuous scaling of logic is achieved by reducing the size of standard cells. Continuous innovation in semiconductor process technology is enabling higher integration densities and device scaling. As the semiconductor industry moves beyond the 7nm technology node, non-planar semiconductor field-effect transistor (FET) device structures such as nanosheet FET devices, nanowire FET devices, vertical FET devices, and fin-type FET devices have made it possible to scale FET devices to smaller dimensions (smaller footprints) while increasing device width (or FET channel width) and therefore increasing drive current per given footprint area. Scaling of FET devices and other structural-level scaling boosters can reduce the cell height of a standard cell. However, such a reduction in cell height leads to a decrease in the number of pin access points for connecting to power and signal wiring in back-end (BEOL) interconnect structures, which can limit the scaling of block-level area due to reduced routability.

[0002] Power is supplied to a semiconductor chip by a power supply network, which includes a network of vias and is wiring connected to the positive (VDD) and negative (VSS) terminals of the chip to supply power to the integrated circuit on the semiconductor chip. In some conventional semiconductor integrated circuit designs, the VDD and VSS power rails, which are part of the power supply network, are implemented in the lower layers (e.g., Mint and M1 layers) of the back-end (BEOL) interconnect structure. Such designs present scaling challenges, for example, with respect to reducing inter-cell spacing, because sufficient lateral cell spacing (e.g., NN spacing, or PP spacing) must exist between FET devices in adjacent cells to prevent short circuits between adjacent source / drain contacts of adjacent FET devices in adjacent cells connected to the power rails in the lower layers of the BEOL interconnect structure. Therefore, high-density integrated designs suffer from congestion in the interconnect design of BEOL circuits, which can lead to reliability problems.

[0003] In some conventional semiconductor integrated circuit designs, embedded power rails are used as structural scaling boosters to reduce standard cell height in order to increase integration density. For example, embedded power rails (e.g., embedded VDD rails and embedded VSS rails) can be manufactured as part of the front-end (FEOL) to free up space for signal tracks in the Mint and M1 layers of the BEOL interconnect structure (thereby reducing cell height), and pitch scaling can provide low-resistance local power distribution in highly integrated designs that suffer from increased BEOL resistance. However, integrating embedded power rails within FEOL process modules to achieve high-density scaling is difficult for a variety of reasons.

[0004] For example, in some conventional schemes, embedded power rails are formed as part of a FEOL process module by etching trenches into the semiconductor substrate in the cell boundary region between adjacent cells, and the trenches are filled with a liner and metallic material to form a high aspect ratio embedded power rail (BPR) on the front of the semiconductor substrate. Such schemes result in the formation of relatively thin embedded power rails of, for example, 5 nm when the inter-cell spacing is 50 nanometers (nm) or less, resulting in embedded power rails with relatively high resistance. Furthermore, such conventional designs further include forming front via contacts to connect the embedded power rail (VBPR) to front source / drain contacts formed as part of a middle-of-line (MOL) process module. Thus, these designs present scaling challenges, for example, with respect to reducing cell height and inter-cell spacing, because sufficient lateral cell spacing (e.g., NN spacing and PP spacing) must exist between adjacent FET devices of adjacent cells, while preventing short circuits of such via contacts to the source / drain contacts of adjacent FET devices of adjacent cells, and providing sufficient space for the via contacts connecting the front source / drain contacts to the embedded power rail. Therefore, the VBPR features high aspect ratio via contacts (e.g., narrow and high) that provide a relatively high resistance connection between the front source / drain contacts and the BPR. Furthermore, in conventional designs that implement a FEOL embedded power rail providing front power from a higher metal level of the BEOL interconnect structure, it is necessary to form additional front via contacts as part of the MOL module to provide a connection from the embedded power rail to the BEOL interconnect structure.

[0005] Furthermore, some conventional semiconductor integrated circuit designs utilize embedded power rails in conjunction with power supply provided by a back-end power distribution network. In such conventional designs, the size of the embedded power rails can be increased by back-end processes, but these designs still utilize front via contacts to connect the embedded power rails to front MOL source / drain contacts formed as part of a middle-of-line (MOL) process module. Therefore, these designs present scaling challenges, for example, with respect to reducing cell height and inter-cell spacing, because sufficient lateral cell spacing (e.g., NN spacing and PP spacing) must exist between adjacent FET devices in adjacent cells, while preventing such via contacts from short-circuiting to the source / drain contacts of adjacent FET devices in adjacent cells, and providing sufficient space for the via contacts connecting the front source / drain contacts to the embedded power rails. [Overview of the project] [Problems that the invention aims to solve]

[0006] Next, exemplary embodiments of semiconductor integrated circuit devices configured to reduce the inter-cell spacing and cell height of standard cells, such as standard CMOS cells, and methods for manufacturing such semiconductor devices will be described in more detail. [Means for solving the problem]

[0007] For example, an exemplary embodiment includes a device comprising a first interconnection structure, a second interconnection structure, a first cell containing a first transistor, a second cell containing a second transistor, a first contact connecting the source / drain elements of the first transistor to the first interconnection structure, and a second contact connecting the source / drain elements of the second transistor to the second interconnection structure. The first cell is positioned adjacent to the second cell, and the first transistor is positioned adjacent to the second transistor. The first and second cells are positioned between the first and second interconnection structures.

[0008] Advantageously, the implementation of the second interconnection structure, and the connection of the first contact to the first interconnection structure and the second contact to the second interconnection structure, reduces the inter-cell spacing between adjacent first and second transistors, thus avoiding potential short circuits between the first and second contacts.

[0009] Another exemplary embodiment comprises a device having a first cell having a first transistor, a second cell having a second transistor, and an isolation structure. The first and second cells are arranged adjacent to each other, and the first and second transistors are arranged adjacent to each other. The isolation structure is located in the cell boundary region between the first and second cells. The isolation structure has a first portion located on the first active channel structure of the first transistor and the second active channel structure of the second transistor, and a second portion located between the first and second active channel structures. The first portion of the isolation structure has a first width substantially equal to the spacing between the first and second active channel structures. The second portion of the isolation structure has a second width smaller than the first width. The space between the second portion of the isolation structure and each of the first and second active channel structures defines the gate extension lengths of the first and second transistors.

[0010] Advantageously, the implementation of isolation structures positioned in the cell boundary region between the first and second cells makes it possible to reduce the inter-cell spacing between the first and second cells. In some embodiments, the isolation structures are formed using a self-alignment process that enables precise control of the thickness and alignment of the dielectric isolation between adjacent first and second active channel structures of the first and second transistors in the first and second cells, as well as precise control of the gate extension of the first and second transistors. The implementation of isolation structures positioned in the cell boundary region between the first and second cells allows for relaxation of tolerances in late gate-cut processes that may be implemented to isolate metal gate electrodes between adjacent cells without affecting the clearly defined inter-cell spacing present between adjacent first and second cells, due to the narrower portion at the bottom of the self-alignment isolation structure.

[0011] Another exemplary embodiment comprises a device having a first cell containing a first transistor and a second cell containing a second transistor. The first and second cells are arranged adjacent to each other. The first and second transistors have a fork-sheet type field-effect transistor pair with an insulating wall positioned between the first and second transistors. The insulating wall is aligned with the cell boundary between the first and second cells. The width of the insulating wall defines the inter-cell spacing between the first and second cells.

[0012] Advantageously, the implementation of a fork-sheet field-effect transistor pair having an insulating wall aligned to the cell boundary between the first and second cells allows for a reduction in the inter-cell spacing between the first and second cells. In some embodiments, the insulating wall is formed using a self-alignment process that allows for precise control of the thickness and alignment of the insulating wall, and thus precise control of dielectric isolation in the cell boundary region between the fork-sheet field-effect transistor pair. The implementation of an insulating wall positioned in the cell boundary region between the first and second cells allows for a relaxation of tolerances in late gate-cut processes that may be implemented to isolate metal gate electrodes between adjacent cells without affecting the clearly defined inter-cell spacing present between adjacent first and second cells.

[0013] Another exemplary embodiment comprises a method for manufacturing a semiconductor device. First and second cells are formed on a substrate. The first cell has a first transistor, and the second cell has a second transistor. The first and second cells are arranged adjacent to each other, and the first and second transistors are arranged adjacent to each other. A first contact is formed to connect to the source / drain elements of the first transistor. A first interconnection structure is formed to connect to the first contact. The substrate is etched to form an opening that exposes the back surface of the source / drain elements of the second transistor. A second contact is formed within the opening that connects to the source / drain elements of the second transistor. A second interconnection structure is formed to connect to the second contact.

[0014] Another exemplary embodiment comprises a method of manufacturing a semiconductor device. A first nanosheet channel structure of a first transistor and a second nanosheet channel structure of a second transistor are formed on a substrate. The first and second nanosheet channel structures are disposed adjacent to each other and separated by a space defining an inter-cell spacing between a first cell and a second cell including the respective first and second transistors. A conformal sacrificial spacer layer is formed on adjacent sidewalls of the first and second nanosheet channel structures. A dielectric isolation structure is formed between the conformal sacrificial spacer layers on the sidewalls of the first and second nanosheet channel structures. The conformal sacrificial spacer layers on the sidewalls of the first and second nanosheet channel structures are selectively etched away to form a space between the dielectric isolation structure and the sidewalls of the first and second nanosheet channel structures, and the space defines a gate extension length of the first and second transistors. The space is filled with a metal material to form a first metal gate structure of the first transistor and a second metal gate structure of the second transistor.

[0015] Other embodiments are described in the detailed description of the following embodiments, which are to be read in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0016] [Figure 1A] FIG. is a schematic diagram of a semiconductor integrated circuit device implementing a backside power rail and a backside power distribution network to enable density scaling, according to an exemplary embodiment of the present disclosure. [Figure 1B] FIG. is a schematic diagram of a semiconductor integrated circuit device implementing a backside power rail and a backside power distribution network to enable density scaling, according to an exemplary embodiment of the present disclosure.

[0017] [Figure 2]A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This is a schematic side cross-sectional view of the initial device structure of a semiconductor integrated circuit device in the early stages of manufacturing, having a semiconductor substrate, an insulating layer, and a nanosheet stacked structure formed on the insulating layer, according to an exemplary embodiment of the present disclosure.

[0018] [Figure 3A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. A schematic diagram of the next intermediate structure of the semiconductor integrated circuit device is constructed by patterning the nanosheet stack structure shown in Figure 2 to form a patterned nanosheet stack structure according to an exemplary embodiment of the present disclosure. [Figure 3B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. A schematic diagram of the next intermediate structure of the semiconductor integrated circuit device is constructed by patterning the nanosheet stack structure shown in Figure 2 to form a patterned nanosheet stack structure according to an exemplary embodiment of the present disclosure.

[0019] [Figure 4A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This is a schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, constructed by forming a dummy gate structure to form the source / drain elements of a transistor device, according to an exemplary embodiment of the present disclosure. [Figure 4B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This is a schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, constructed by forming a dummy gate structure to form the source / drain elements of a transistor device, according to an exemplary embodiment of the present disclosure. [Figure 4C]A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This is a schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, constructed by forming a dummy gate structure to form the source / drain elements of a transistor device, according to an exemplary embodiment of the present disclosure.

[0020] [Figure 5A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This diagram schematicly shows the following intermediate structure of the semiconductor integrated circuit device, constructed by forming an interlayer dielectric layer, performing a gate cutting process, and performing a substitution metal gate process, according to an exemplary embodiment of the present disclosure. [Figure 5B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This diagram schematicly shows the following intermediate structure of the semiconductor integrated circuit device, constructed by forming an interlayer dielectric layer, performing a gate cutting process, and performing a substitution metal gate process, according to an exemplary embodiment of the present disclosure.

[0021] [Figure 6A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This diagram schematicly shows the following intermediate structure of the semiconductor integrated circuit device, which is constructed by forming the front gate contacts and source / drain contacts according to an exemplary embodiment of the present disclosure. [Figure 6B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This diagram schematicly shows the following intermediate structure of the semiconductor integrated circuit device, which is constructed by forming the front gate contacts and source / drain contacts according to an exemplary embodiment of the present disclosure. [Figure 6C]A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This diagram schematicly shows the following intermediate structure of the semiconductor integrated circuit device, which is constructed by forming the front gate contacts and source / drain contacts according to an exemplary embodiment of the present disclosure.

[0022] [Figure 7] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. A schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by forming a first interconnection structure (e.g., a BEOL interconnection structure) on the front of the intermediate device structure shown in Figures 6A, 6B, and 6C according to an exemplary embodiment of the present disclosure.

[0023] [Figure 8] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 1A and 1B according to one embodiment of the present disclosure. This diagram shows a schematic side cross-sectional view of the next intermediate structure of the semiconductor integrated circuit device, constructed by executing a back-side process module that forms a second interconnect structure having back-side source / drain contacts and a complete back-side power supply structure on the back of the intermediate device structure shown in Figure 7, according to an exemplary embodiment of the present disclosure.

[0024] [Figure 9] This is a schematic side cross-sectional view of a semiconductor integrated circuit device, according to another exemplary embodiment of the present disclosure, which implements rear power rails and a rear power distribution network to enable density scaling.

[0025] [Figure 10A] This is a schematic diagram of a semiconductor integrated circuit device, according to another exemplary embodiment of the present disclosure, which implements rear power rails and a rear power distribution network to enable density scaling. [Figure 10B]This is a schematic diagram of a semiconductor integrated circuit device, according to another exemplary embodiment of the present disclosure, which implements rear power rails and a rear power distribution network to enable density scaling.

[0026] [Figure 11] Figures 10A and 10B schematically illustrate a method for manufacturing the semiconductor integrated circuit device according to exemplary embodiments of the present disclosure. Figures 10A and 10B schematically illustrate a method for manufacturing the semiconductor integrated circuit device according to exemplary embodiments of the present disclosure.

[0027] [Figure 12] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. The following schematic side cross-sectional view shows an intermediate structure of a semiconductor integrated circuit device constructed by forming a sacrificial spacer layer on the sidewall of a patterned nanosheet stacked structure according to exemplary embodiments of the present disclosure.

[0028] [Figure 13] A schematic diagram illustrates a method for fabricating the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. The following schematic side cross-sectional view shows an intermediate structure of a semiconductor integrated circuit device constructed by forming self-aligned dielectric isolation elements between patterned nanosheet stacked structures, according to exemplary embodiments of the present disclosure.

[0029] [Figure 14A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This is a schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, constructed by forming a dummy gate structure to form the source / drain elements of a transistor device, according to exemplary embodiments of the present disclosure. [Figure 14B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This is a schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, constructed by forming a dummy gate structure to form the source / drain elements of a transistor device, according to exemplary embodiments of the present disclosure. [Figure 14C] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This is a schematic diagram of the following intermediate structure of a semiconductor integrated circuit device, constructed by forming a dummy gate structure to form the source / drain elements of a transistor device, according to exemplary embodiments of the present disclosure.

[0030] [Figure 15A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This is a schematic diagram of the following intermediate structure of the semiconductor integrated circuit device, constructed according to exemplary embodiments of the present disclosure by performing a substitution metal gate process to form interlayer dielectric layers and replace dummy gates with metal gates. [Figure 15B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This is a schematic diagram of the following intermediate structure of the semiconductor integrated circuit device, constructed according to exemplary embodiments of the present disclosure by performing a substitution metal gate process to form interlayer dielectric layers and replace dummy gates with metal gates.

[0031] [Figure 16A] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit devices shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This schematic diagram shows the following intermediate structure of a semiconductor integrated circuit device constructed by performing a late gate-cut process to form an upper gate-cut element on a self-aligned dielectric isolation element to isolate the metal gate structure of transistor devices in adjacent cells, according to exemplary embodiments of the present disclosure. [Figure 16B] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit devices shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This schematic diagram shows the following intermediate structure of a semiconductor integrated circuit device constructed by performing a late gate-cut process to form an upper gate-cut element on a self-aligned dielectric isolation element to isolate the metal gate structure of transistor devices in adjacent cells, according to exemplary embodiments of the present disclosure. [Figure 16C] A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit devices shown in Figures 10A and 10B according to exemplary embodiments of the present disclosure. This schematic diagram shows the following intermediate structure of a semiconductor integrated circuit device constructed by performing a late gate-cut process to form an upper gate-cut element on a self-aligned dielectric isolation element to isolate the metal gate structure of transistor devices in adjacent cells, according to exemplary embodiments of the present disclosure.

[0032] [Figure 17A] This is a schematic diagram of a semiconductor integrated circuit device, according to another exemplary embodiment of the present disclosure, which implements rear power rails and a rear power distribution network to enable density scaling. [Figure 17B] This is a schematic diagram of a semiconductor integrated circuit device, according to another exemplary embodiment of the present disclosure, which implements rear power rails and a rear power distribution network to enable density scaling.

[0033] [Figure 18] Figures 17A and 17B schematically illustrate a method for manufacturing the semiconductor integrated circuit device according to exemplary embodiments of the present disclosure. Figures 17A and 17B schematically illustrate a schematic side cross-sectional view of an intermediate structure of a semiconductor integrated circuit device in an intermediate stage of manufacturing, according to exemplary embodiments of the present disclosure, comprising a semiconductor substrate, an insulating layer, a plurality of patterned nanosheet stacks disposed on the insulating layer, and a hard mask layer disposed on the patterned nanosheet stacks.

[0034] [Figure 19]A schematic diagram illustrates a method for manufacturing the semiconductor integrated circuit device shown in Figures 17A and 17B according to exemplary embodiments of the present disclosure. The schematic side cross-sectional view shows the following intermediate structure of a semiconductor integrated circuit device constructed by patterning a nanosheet stack to form a sacrificial spacer layer on the sidewall of the patterned nanosheet stack to further form a nanosheet channel structure for the transistor pair of forksheet transistors, according to exemplary embodiments of the present disclosure.

[0035] [Figure 20] A schematic diagram illustrates a method for fabricating the semiconductor integrated circuit device shown in Figures 17A and 17B according to exemplary embodiments of the present disclosure. The following schematic side cross-sectional view shows an intermediate structure of a semiconductor integrated circuit device constructed by forming self-aligned dielectric isolation elements between patterned nanosheet stacked structures, according to exemplary embodiments of the present disclosure. [Modes for carrying out the invention]

[0036] Next, exemplary embodiments of semiconductor integrated circuit devices having a rear-facing grid, rear-facing power rails, and rear-facing source / drain contacts, and methods for manufacturing such semiconductor devices, will be described in more detail to reduce the inter-cell spacing and cell height of standard cells such as standard CMOS cells. For illustrative purposes, exemplary embodiments of the present invention will be discussed in relation to complementary transistor structures having nanosheet FET devices. However, it should be understood that the exemplary embodiments discussed herein are readily applicable to various types of gate-all-around (GAA) FET devices, such as nanowire FETs, and other types of GAA FET devices having gate structures formed around all sides of the active channel layer. Furthermore, the exemplary techniques disclosed herein can be implemented in fin-type FET (FinFET) devices.

[0037] Please understand that the various layers, structures, and regions shown in the attached drawings are schematic diagrams and not drawn to scale. Furthermore, for the sake of simplicity, one or more types of layers, structures, and regions commonly used to form semiconductor devices or structures may not be explicitly shown in the given drawings. This does not mean that layers, structures, and regions not explicitly shown are omitted from actual semiconductor structures. Furthermore, please understand that the embodiments discussed herein are not limited to the specific materials, features, and process steps shown and described herein. In particular, with respect to semiconductor process steps, it should be emphasized that the descriptions provided herein are not intended to encompass all process steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain process steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, are intentionally omitted herein for the sake of brevity.

[0038] Identical or similar reference numbers are used throughout the drawings to indicate identical or similar features, elements, or structures, and it should be understood that detailed descriptions of identical or similar features, elements, or structures are not repeated for each drawing. Furthermore, the terms “about” or “substantially” used herein with respect to thickness, width, percentage, range, etc., mean that they are not exact but are close or approximate. For example, the terms “about” or “substantially” used herein mean that there is a small error, such as less than 1% of the stated quantity. The phrase “on” used herein to describe the formation of a feature (e.g., a layer) “on” a side or surface means that the feature (e.g., a layer) may be formed “directly on” (i.e., in direct contact) the implicit side or surface, or that the feature (e.g., a layer) may be formed “indirectly on” an implicit side or surface having one or more additional layers positioned between the feature (e.g., a layer) and the implicit side or surface.

[0039] To provide spatial context for the different structural directions of the semiconductor structures shown throughout the drawings, XYZ Cartesian coordinates are shown in each drawing. As used herein, the terms “vertical,” “vertical direction,” or “vertical height” refer to the Z direction of the Cartesian coordinates shown in the drawings, and as used herein, the terms “horizontal,” “horizontal direction,” or “lateral direction” refer to the X direction, the Y direction, or both of the Cartesian coordinates shown in the drawings.

[0040] Figures 1A and 1B are schematic diagrams of a semiconductor integrated circuit device 100, according to exemplary embodiments of the present disclosure, which implements rear power rails and rear power distribution networks to enable density scaling. More specifically, Figure 1A is a schematic side section view (XZ plane) of the semiconductor integrated circuit device 100 along line 1A-1A in Figure 1B, and Figure 1B is a schematic plan view of the semiconductor device along line 1B-1B in Figure 1A. The semiconductor integrated circuit device 100 comprises a plurality of cells, including a first cell C1, a second cell C2, and a third cell C3. For ease of explanation, Figures 1A and 1B show the full cell height CH of the first cell C1 and the half cell heights of the second and third cells C2 and C3. The first cell C1 is located between the second cell C2 and the third cell C3. In the exemplary embodiments discussed herein, cells C1, C2, and C3 have CMOS cells.

[0041] Cells C1, C2, and C3 have a plurality of nanosheet FET devices 120-1, 120-2, 120-3, and 120-4 arranged on an insulating substrate layer 105 (e.g., an embedded oxide (BOX) layer 105). In some embodiments, nanosheet FET devices 120-1 and 120-2 are N-type nanosheet FET devices (NFET devices), and nanosheet FET devices 120-3 and 120-4 are P-type nanosheet FET devices (PFET devices). More specifically, in the exemplary embodiments shown in Figures 1A and 1B, the second cell C2 has a plurality of NFET devices 120-1 (adjacent PFET devices of cell C2 are not shown), the first cell C1 has a plurality of NFET devices 120-2 and a plurality of PFET devices 120-3, and the third cell C3 has a plurality of PFET devices 120-4 (adjacent NFET devices of cell C3 are not shown). NFET devices 120-1 and 120-2 have source / drain elements 122, and PFET devices 120-3 and 120-4 have source / drain elements 124.

[0042] As further shown in Figure 1B, the semiconductor integrated circuit device 100 has a plurality of gate structures G1, G2, and G3 that extend in the X direction across cells C1, C2, and C3. In some embodiments, the gate structures G1, G2, and G3 have substitutional metal gate (RMG) structures, such as high-k metal gate (HKMG) structures, encapsulated by gate sidewall spacers 134, gate cut elements 137, and gate capping layers 138. As shown in Figure 1B, in an exemplary embodiment, the NFET device 120-2 of the first cell C1 shares a common metal gate structure with its adjacent PFET device 120-3. The gate structures G1, G2, and G3 of different cells C1, C2, and C3 are separated by gate cut elements 137 formed in the cell boundary regions between adjacent cells.

[0043] In exemplary embodiments, nanosheet FET devices 120-1, 120-2, 120-3, and 120-4 each have a stacked nanosheet channel structure having three active nanosheet channel layers 112, 114, and 116 (see Figure 1A). In particular, NFET devices 120-1 and 120-2 each have a stacked nanosheet channel structure encapsulated by their respective metal gate structures and connected to source / drain elements 122 on the opposite side of gate structures G1, G2, and G3. Similarly, PFET devices 120-3 and 120-4 each have a stacked nanosheet channel structure encapsulated by their respective metal gate structures and positioned between source / drain elements 124 on the opposite side of gate structures G1, G2, and G3.

[0044] Furthermore, as shown in Figures 1A and 1B, the front surface of the semiconductor integrated circuit device 100 includes a first insulating layer 140, a second insulating layer 142, front gate contacts 151, 152, and 153, front source / drain contacts 160, 161, 162, and 163, and a BEOL interconnect structure 170. The BEOL interconnect structure 170 has multiple levels of wiring and via structures that connect wiring between different wiring levels. For example, as shown in Figure 1A, the BEOL interconnect structure 170 has dielectric layers 171 and 172 having a first metallization level, and an additional BEOL metallization level 173 placed on top of the first level of metallization.

[0045] More specifically, the dielectric layer 171 has a plurality of via contacts 174 and 175 formed therein, and the dielectric layer 172 has a first metallization level M1 (or sometimes indicated as M0 or Mint) having a plurality of metal tracks T1, T2, T3, T4, T5, T6, T7, and T8 having a given pitch P. In some embodiments, the metal tracks T1-T8 provide local interconnects for distributing signals to, from, and between nanosheet FET devices 120-1, 120-2, 120-3, and 120-4, while some upper metal levels 173 of the BEOL interconnect structure 170 have semi-global and global wiring. As shown in Figure 1A, the via contacts 174 and 175 connect their respective front source / drain contacts 160 and 161 to their respective corresponding metal tracks T3 and T6 of the first metallization level. Although not specifically shown, the dielectric layer 171 has other via contacts connecting the gate contacts 151, 152, and 153, as well as the source / drain contacts 162 and 163, to the metal track at the first metallization level.

[0046] As further shown in Figures 1A and 1B, the back of the semiconductor integrated circuit device 100 has back source / drain contacts 181, 182, 183, and 184 (formed in the insulating substrate layer 105), as well as a complete back power supply structure 190. The back power supply structure 190 has a back dielectric layer 192 formed on the insulating substrate layer 105, a plurality of back power rails 194 and 196 formed within the back dielectric layer 192, and a back power distribution network 198. In the exemplary embodiments of Figures 1A and 1B, the back source / drain contacts 181 and 183 connect the source / drain elements 122 of the NFET devices of cells C1 and C2 to the back power rails 194, and the back source / drain contacts 182 and 184 connect the source / drain elements 124 of the PFET devices of cells C1 and C3 to the back power rails 194.

[0047] The rear power grid 198 has one or more levels of wiring configured to distribute a positive supply voltage (e.g., VDD) and a negative supply voltage (e.g., VSS, ground (GND) = 0V) to the rear power rails 194 and 196. For example, in an exemplary embodiment, the rear power grid 198 connects the negative supply voltage (VSS) to the rear power rail 194 and the positive supply voltage (VDD) to the rear power rail 196. In this configuration, rear source / drain contacts 181 and 184 (connected to the rear power rail 194) connect some source / drain elements 122 of some NFET devices in the first and second cells C1 and C2 to VSS (or ground), and rear source / drain contacts 182 and 184 connect some source / drain elements 124 of some PFET devices in the first and third cells C1 and C3 to VDD.

[0048] It should be understood that the exemplary layouts of CMOS cells C1, C2, and C3, as well as their configurations such as front and rear source / drain contacts, as shown in Figures 1A and 1B, are presented for illustrative purposes only. The layouts of CMOS cells C1, C2, and C3, as well as the configurations of their front and rear source / drain contacts, will vary depending on the type of standard CMOS cell implemented in a given circuit configuration and the type of semiconductor technology used (e.g., nanosheet FET devices, FinFET devices, etc.). For example, CMOS cells C1, C2, and C3 may have standard cells with groups of transistors and interconnect structures that provide Boolean logic functions (e.g., AND, NAND, OR, NOR, XOR, etc.), memory functions (e.g., latches, flip-flops, etc.), or more complex standard cells (macrocells) such as adders, multiplexers, and memory.

[0049] Figures 1A and 1B show exemplary embodiments in which cells C1, C2, and C3 have a cell height (CH) of 4 tracks. Note that the term “cell height” for a standard cell as used herein refers to the number of parallel tracks (e.g., metal tracks) positioned between a first cell boundary and a second cell boundary, and the distance between the first and second cell boundaries defines the cell height of the standard cell. For example, as shown in Figure 1A, vertical dashed lines are shown defining the first cell boundary B1 between cells C1 and C2, and the second cell boundary B2 between cells C1 and C3. With respect to metal tracks T3, T4, T5, and T6 of pitch P, the cell height (CH) of the first cell is 1 / 2P + P + P + 1 / 2P = 4P (e.g., 4 metal tracks).

[0050] Furthermore, as shown in Figure 1A, another way to define the cell height (CH) of the first cell C1 is: CH = 2CB + S1 + 2W G Here, S1 represents the distance from N to P between the NFET device 120-2 and the PFET device 120-3 of cell C1, CB represents the cell boundary space which is 1 / 2S2 (where S2 represents the inter-cell distance between adjacent cells), and W G This refers to the gate widths of the NFET device 120-2 and PFET device 120-3 in cell C1 (gate width W of the NFET device and PFET device). G (Assuming they are equal) The intercell spacing S2 between adjacent cells C1 and C2 represents the N-to-N spacing between the stacked nanosheet channel layers of NFET devices 120-1 and 120-2, and the intercell spacing S2 between adjacent cells C1 and C3 represents the P-to-P spacing between the stacked nanosheet channel layers of PFET devices 120-3 and 120-4.

[0051] The exemplary device architecture shown in Figures 1A and 1B allows for a reduction in the inter-cell spacing S2 between adjacent cells for high-density integration while avoiding potential short circuits between source / drain contact FET devices in adjacent cells. The reduction in the inter-cell spacing S2 between adjacent cells leads to a smaller cell boundary spacing CB between cells, and therefore a reduction in the cell height. In fact, as shown in Figure 1A, the source / drain element 122 of the NFET device 120-1 in cell C2 is connected to the rear power supply structure 190 through the rear source / drain contact 181, and the source / drain element 122 of the adjacent NFET device 120-2 in the adjacent cell C1 is connected to the front BEOL interconnect structure 170 through the front contact 160. Furthermore, the source / drain elements 124 of the PFET devices 120-4 in cell C3 are connected to the rear power supply structure 190 through rear source / drain contacts 182, and the source / drain elements 124 of the adjacent PFET device 120-3 in the adjacent cell C1 are connected to the front BEOL interconnect structure 170 through front contacts 161. This configuration allows for scaling of the inter-cell spacing S2 while preventing short circuits between the source / drain contacts of adjacent transistors in adjacent cells.

[0052] The exemplary device architectures shown in Figures 1A and 1B offer several advantages over the conventional structures discussed above. For example, as mentioned above, conventional designs that utilize BEOL interconnect structures for both signal and power supply suffer from reduced routableness due to congestion and congestion of MOL source / drain contacts connecting FEOL source / drain elements to the BEOL interconnect structure. Furthermore, scaling of inter-cell spacing between adjacent cells is limited in that a sufficient amount of inter-cell spacing is required to prevent short circuits of front source / drain contacts connected to the source / drain elements of adjacent transistors in adjacent cells.

[0053] Furthermore, as mentioned above, some conventional designs utilize front-mounted power rails formed in the semiconductor substrate beneath the cell's transistors, and contact to the embedded power rails is achieved by extending the front source / drain contacts laterally and connecting the extended portions of the front source / drain contacts to the embedded power rails using FEOL vias that extend between adjacent transistors to the embedded power rails. For example, in a conventional device configuration with the cell architecture of Figure 1A, the rear power rails 194 and 196 make the power rails located within the semiconductor substrate relatively narrow, and the rear source / drain contacts 181 and 182 are not utilized.

[0054] Alternatively, the source / drain element 122 of the NFET device 120-1 in cell C2 is connected to the embedded power rail by forming a front MOL source / drain contact in the ILD layers 140 and 142, with an extended portion overlapping a portion of the gap S2 between cells C2 and C1, and via contacts connecting the extended portion of the MOL source / drain contacts to the embedded power rail. In this case, the via contacts are located in the space S2 between cells C2 and C1. Similarly, the source / drain element 124 of the PFET device 120-4 in cell C3 is connected to the embedded power rail by forming a front MOL source / drain contact in the ILD layers 140 and 142, with an extended portion overlapping a portion of the gap S2 between cells C1 and C3, and via contacts connecting the extended portion of the MOL source / drain contacts to the embedded power rail. In this case, the via contacts are located in the space S2 between cells C3 and C1. The need to form via contacts in the gap S2 between adjacent cells imposes significant limitations on scaling between cells. Furthermore, the use of extended portions of the front source / drain contacts and corresponding via contacts reduces the inter-cell spacing, potentially leading to short circuits and increased parasitic coupling between adjacent FET devices within adjacent cells.

[0055] Figures 2 to 8 schematically illustrate a method for manufacturing a semiconductor integrated circuit device having a rear power rail and a rear power distribution network according to exemplary embodiments of the present disclosure. In particular, for illustrative purposes, Figures 2 to 8 schematically illustrate a method for manufacturing the semiconductor integrated circuit device 100 of Figures 1A and 1B. To begin with, Figure 2 is a schematic side cross-sectional view (XZ plane) of the initial device structure of a semiconductor integrated circuit device in the initial stage of manufacturing, having a semiconductor substrate 102, an insulating layer 105, and a nanosheet stacked structure 110 formed on the insulating layer 105. The nanosheet stacked structure 110 has a stack of epitaxial semiconductor layers 111, 112, 113, 114, 115, 116, and 117, which are then patterned to form a plurality of nanosheet FET devices. In particular, the nanosheet stacked structure 110 has sacrificial nanosheet layers 111, 113, 115, and 117, as well as active nanosheet channel layers 112, 114, and 116, each of which is positioned between the sacrificial nanosheet layers within the nanosheet stacked structure 110.

[0056] While the semiconductor substrate 102 is shown as a general substrate layer, it should be understood that the semiconductor substrate 102 may include one of several different types of semiconductor substrate structures and materials. For example, in some embodiments, the semiconductor substrate 102 is a bulk semiconductor substrate (e.g., a wafer) formed from a crystalline semiconductor material, including, but not limited to, silicon (Si), germanium (Ge), or other types of semiconductor substrate materials commonly used in bulk semiconductor manufacturing processes, such as silicon (Si), germanium (Ge), or silicon-germanium alloys, compound semiconductor materials (e.g., III-V). Note that in each drawing, the XY plane represents a plane parallel to the plane of the semiconductor substrate 102 (e.g., wafer) being processed.

[0057] In some embodiments, the semiconductor substrate 102 is a semiconductor on an insulator (SOI) substrate, and the insulating layer 105 is an embedded oxide (BOX) layer of the SOI substrate. For example, in some embodiments, the SOI substrate 102 may have a layer of single-crystal silicon separated from the bulk substrate by a thin BOX layer 105. In some embodiments, the first sacrificial semiconductor layer 111 (or sacrificial nanosheet layer 111) is formed by converting a single-crystal silicon layer on the BOX layer 104 into a SiGe layer. More specifically, in some embodiments, the conversion process can be carried out by thinning the single-crystal silicon layer, followed by growing epitaxySiGe on the single-crystal silicon layer, followed by SiGe condensation to convert the thin Si / SiGe layer into an SiO2-capped SiGe layer. Finally, the SiO2 is removed, and the remaining SiGe layer becomes the first sacrificial layer 111.

[0058] Epitaxial semiconductor layers are sequentially grown on the nanosheet stacked structure 110. For example, an active nanosheet channel layer 112 is epitaxially grown on a sacrificial nanosheet layer 111, a sacrificial nanosheet layer 113 is epitaxially grown on the active nanosheet channel layer 112, an active nanosheet channel layer 114 is epitaxially grown on the sacrificial nanosheet layer 113, a sacrificial nanosheet layer 115 is epitaxially grown on the active nanosheet channel layer 114, an active nanosheet channel layer 116 is epitaxially grown on the sacrificial nanosheet layer 115, and a sacrificial nanosheet layer 117 is epitaxially grown on the active nanosheet channel layer 116.

[0059] In some embodiments, the epitaxial semiconductor layer of the nanosheet stacked structure 110 has a single crystal (monocrystalline) semiconductor material that is epitaxially grown using known methods such as chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), metal-organic molecular beam epitaxy (MOMBE), rapid thermochemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), or other known epitaxial growth techniques suitable for a given process flow.

[0060] The type of material used to form the epitaxial semiconductor layers 111-117 of the nanosheet stack 110 depends on various factors such as the type of nanosheet FET device (P-type or N-type) and the desired level of etching selectivity between the semiconductor layers, while also providing sufficient lattice matching between the semiconductor layer materials to ensure proper (e.g., defect-free) epitaxial growth of the crystalline semiconductor layer. For example, in some embodiments, the active nanosheet channel layers 112, 114, and 116 of the nanosheet stack structure 110 are formed from epitaxial silicon (or crystalline Si).

[0061] If the active nanosheet channel layers 112, 114, and 116 are formed from crystalline Si, the sacrificial nanosheet layers 111, 113, 115, and 117 (which function as sacrificial layers that are subsequently etched away to release the active nanosheet channel layers 112, 114, and 116) can be formed from an epitaxial silicon-germanium (SiGe) alloy. This allows the epitaxial SiGe material of the sacrificial nanosheet layers 111, 113, 115, and 117 to be selectively etched against the epitaxial Si material of the active nanosheet channel layers 112, 114, and 116 in a subsequent process step, thereby "releasing" the active nanosheet channel layers 112, 114, and 116. In other embodiments, the active nanosheet channel layers 112, 114, and 116 can be formed from an epitaxial SiGe material having a desired Ge concentration (optimized for device performance), and the sacrificial nanosheet layers 111, 113, 115, and 117 can be formed from a sacrificial semiconductor material (e.g., Si) that can be selectively etched with respect to the active nanosheet channel layers 112, 114, and 116. Although the nanosheet stacked structure 110 is shown to include three active nanosheet channel layers 112, 114, and 116, in other embodiments of the present invention, the nanosheet stacked structure 110 can be fabricated with more than three active nanosheet channel layers.

[0062] The thicknesses of the sacrificial nanosheet layers 111, 113, and 115 of the nanosheet stacked structure 110 define the upper and lower spacing size (or channel spacing) of the active nanosheet channel layers 112, 114, and 116 on which the high-k dielectric material and work function metal are subsequently formed. The spacing size and type of work function material placed in the upper and lower spaces of the active nanosheet channel layers 112, 114, and 116 partially define the threshold voltage (Vt) of the nanosheet FET device. In some embodiments, the thicknesses of the sacrificial nanosheet layers 111, 113, 115, and 117 range from about 6 nm to about 20 nm.

[0063] Next, Figures 3A and 3B are schematic diagrams of the next intermediate structure of a semiconductor integrated circuit device, constructed by patterning the nanosheet stack structure 110 of Figure 2 to form a patterned nanosheet stack structure according to an exemplary embodiment of the present disclosure. More specifically, Figures 3A and 3B show the patterning of the nanosheet stack structure 110 of Figure 2 to form a gate width W of a complementary transistor in the cell. G The next steps in the manufacturing process for forming multiple patterned nanosheet stacked structures 110-1, 110-2, 110-3, and 110-4 defining the are schematically shown. Figure 3A is a schematic plan view (XY plane) of the intermediate semiconductor structure, and Figure 3B is a schematic side cross view (XZ plane) of the intermediate semiconductor structure along line 3B-3B shown in Figure 3A.

[0064] In some embodiments, the patterning process is performed by forming an etching mask (e.g., a lithography mask or a hard mask) on the nanosheet laminated structure 110 (Figure 2), the etching mask containing images of the patterned nanosheet laminated structures 110-1, 110-2, 110-3, and 110-4. The nanosheet laminated structure 110 is then etched using a sequence of one or more dry etching processes (e.g., reactive ion etching (RIE)) to etch down through the layers of the nanosheet laminated structure 110 to the embedded insulating layer 105 (or BOX layer 105) to form the patterned nanosheet laminated structures 110-1, 110-2, 110-3, and 110-4. The etching mask can be formed using any suitable patterning process, including, but not limited to, a photolithography process or a multi-patterning process such as a sidewall image transfer (SIT) process, a self-aligned double patterning (SADP) process, or a self-aligned quadruple patterning (SAQP). Etching can be performed using one or more sequential dry etching processes employing chemical etching suitable for etching the material of the epitaxial semiconductor layer of the nanosheet stacked structure 110.

[0065] Next, Figures 4A, 4B, and 4C are schematic diagrams of the following intermediate structures of a semiconductor integrated circuit device, constructed by forming a dummy gate structure and the source / drain elements of a FET device, according to exemplary embodiments of the present disclosure. In particular, Figure 4A is a schematic plan view (XY plane) of the intermediate device structure, Figure 4B is a schematic side cross-sectional view (YZ plane) of the intermediate device structure along line 4B-4B shown in Figure 4A, and Figure 4C is a schematic side cross-sectional view (XZ plane) of the semiconductor structure obtained along line 4C-4C shown in Figure 4A.

[0066] In particular, as schematically shown in Figure 4A, multiple gate structures G1, G2, and G3 are formed across the cell. During the gate formation process, the patterned nanosheet stacked structures 110-1, 110-2, 110-3, and 110-4 (as shown in Figure 3A) are further patterned (in the Y direction) to form individual nanosheet stacked structures for individual NFET devices 120-1 and 120-2 in cells C1 and C2, and individual nanosheet stacked structures for individual PFET devices 120-3 and 120-4 in cells C1 and C3. The additional patterning of the nanosheet stacked structures 110-1, 110-2, 110-3, and 110-4 results in a gate length L of the complementary transistors in the cell, as shown in Figures 4A and 4B. G Define the area.

[0067] As shown in Figures 4A, 4B, and 4C, gate structures G1, G2, and G3 have a dummy gate 130 (e.g., a conformal oxide layer and a dummy gate electrode layer (e.g., a sacrificial polysilicon material or amorphous silicon material)). Furthermore, gate structures G1, G2, and G3 have a gate capping layer 132, a gate sidewall spacer 134, and a buried sidewall spacer 136. In some embodiments, the dummy gate 130 has a conformal dummy gate oxide layer and a dummy gate electrode layer (e.g., a sacrificial polysilicon material or amorphous silicon material). As will be described in more detail below, the dummy gate 130 is then removed as part of a substitution metal gate (RMG) process and replaced with a high-k gate dielectric material and a metallic material to form a high-k metallic gate structure for nanosheet FET devices.

[0068] The intermediate device structures shown in Figures 4A, 4B, and 4C are manufactured using methods well known to those skilled in the art. For example, a thin conformal layer of silicon oxide is deposited over the entire surface of the semiconductor structures shown in Figures 3A and 3B, a layer of polysilicon (or amorphous silicon) is blanket-deposited on the conformal layer of silicon oxide, and then planarized using known techniques. The hard mask layer is formed on the planarized surface of the polysilicon layer by depositing a layer of dielectric material or multiple layers of dielectric material (e.g., SiN, SiOCN, SiBCN). The hard mask layer is then patterned to form a gate-capping layer 132 that defines the images of the gate structures G1, G2, and G3. Next, the gate capping layer 132 is used as an etching hard mask to anisotropically etch (e.g., RIE) the sacrificial polysilicon and oxide layers to the BOX layer 105 (selectively for the epitaxial materials of the patterned nanosheet stacked structures 110-1, 110-2, 110-3, and 110-4), thereby forming the dummy gate 130.

[0069] Next, the gate sidewall spacer 134 is formed by depositing a conformal layer of dielectric material over the entire surface of the semiconductor structure. The conformal layer of dielectric material can be formed from SiN, SiBCN, SiCON, or other types of low-k dielectric materials commonly used to form insulating gate sidewall spacers in FET devices, and can be deposited using known techniques such as atomic layer deposition (ALD), CVD, and PVD. The conformal layer of dielectric material is then patterned by performing an anisotropic dry etching process such as RIE, which etches down the conformal layer of dielectric material in the vertical direction (Z direction). This etching process is selectively performed on the semiconductor materials of the patterned nanosheet stacked structures 110-1, 110-2, 110-3, and 110-4. The etching process results in the formation of the gate sidewall spacer 134 surrounding the dummy gate 130 and gate capping layer 132, as shown in Figures 4A to 4C. The gate sidewall spacer 134 defines the gate region of the nanosheet FET device. After forming the gate sidewall spacer 134, an anisotropic dry etching process (e.g., RIE) is performed to etch down the exposed portions of the nanosheet stacked structures 110-1, 110-2, 110-3, and 110-4 in the source / drain region adjacent to the gate structure to the upper surface of the BOX layer 105. As shown in Figure 4A, the etching process forms the individual nanosheet channel structures of the PFET and NFET devices.

[0070] Next, the exposed sidewall surfaces of the sacrificial nanosheet layers 111, 113, 115, and 117 of the individual nanosheet channel structures of the NFET and PFET devices are laterally recessed using a timed etching process, such that the exposed edges of the sacrificial nanosheet layers 111, 113, 115, and 117 are recessed to a depth defined by the thickness of the gate sidewall spacer 134. In some embodiments, the lateral etching process can be performed using an isotropic wet etching process with an etching solution suitable for selectively etching the semiconductor material (e.g., SiGe) of the sacrificial nanosheet layers 111, 113, 115, and 117 with respect to the semiconductor material (e.g., Si) of the active nanosheet channel layers 112, 114, and 116 and other exposed elements (e.g., the gate capping layer 132 and the gate sidewall spacer 134). In some embodiments, an isotropic dry plasma etching process can be performed to selectively laterally etch the exposed sidewall surfaces of the sacrificial nanosheet layers 111, 113, 115, and 117 with respect to the active nanosheet channel layers 112, 114, and 116 and other exposed elements.

[0071] The next phase of the manufacturing process involves forming embedded gate sidewall spacers 136 within recesses in the sidewalls of the nanosheet channel structure of the NFET and PFET devices. In some embodiments, the embedded gate sidewall spacers 136 are formed from the same dielectric material used to form the gate sidewall spacers 134. For example, the embedded gate sidewall spacers 136 can be formed from SiN, SiBCN, SiCO, SiCON, or any other type of dielectric material used to form the gate sidewall spacers 134 of the gate structures G1, G2, and G3 (e.g., low-k dielectric materials with k less than 5, where k is the relative permittivity). In some embodiments, the embedded gate sidewall spacers 136 are formed by depositing a conformal layer of dielectric material until the recesses are filled with dielectric material, followed by etch-back to remove excess dielectric material from the gate structure and substrate. The dielectric material is deposited using a highly conformal deposition process such as ALD so that the recesses are sufficiently filled with dielectric material. The conformal layer of dielectric material can be etched back using an isotropic (wet or dry) etching process to remove excess dielectric material while leaving the dielectric material in the recesses to form embedded gate sidewall spacers 136. Wet etching processes may include, but are not limited to, buffered hydrofluoric acid (BHF), dilute hydrofluoric acid (DHF), nitrate hydrofluoric acid (HNA), phosphoric acid, HF diluted with ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof.

[0072] Following the formation of the embedded gate sidewall spacers 136, the source / drain elements 122 of NFET devices 120-1 and 120-2 are epitaxially grown on the exposed sidewall surfaces of the active nanosheet channel layers 112, 114, and 116 of the NFET devices using a first epitaxy process, and the source / drain elements 124 of PFET devices 120-3 and 120-4 are epitaxially grown on the exposed sidewall surfaces of the active nanosheet channel layers 112, 114, and 116 of the PFET devices using a second epitaxy process separate from the first epitaxy process. In the first epitaxy process, the exposed sidewall surfaces of the active nanosheet channel layers 112, 114, and 116 of NFET devices 120-1 and 120-2 provide a surface area to serve as a seed for the epitaxial growth of the source / drain elements 122. In the second epitaxy process, the exposed sidewall surfaces of the active nanosheet channel layers 112, 114, and 116 of the PFET devices 120-3 and 120-4 provide a surface area to serve as a seed for the epitaxial growth of the source / drain elements 124. If the source / drain elements 122 of the NFET device are formed before the formation of the source / drain elements 124 of the PFET device, the source / drain elements 122 are covered with a conformal dielectric liner layer and a patterned organic layer to protect them from the epitaxy process used to form the source / drain elements 124 of the PFET device, and vice versa.

[0073] In some embodiments, epitaxial growth of source / drain elements 122 is performed on the exposed edges of the active nanosheet channel layers 112, 114, and 116 of NFET devices 120-1 and 120-2 so as to form source / drain elements 122 where the epitaxial material is bonded (in the X and Z directions) and coupled between adjacent gate structures (e.g., between adjacent gates G1 and G2, and between adjacent gates G2 and G3), as shown in Figure 4A. Similarly, epitaxial growth of source / drain elements 124 is performed on the exposed edges of the active nanosheet channel layers 112, 114, and 116 of PFET devices 120-3 and 120-4 so as to form source / drain elements 124 where the epitaxial material is bonded (in the X and Z directions) and coupled between adjacent gate structures. In other embodiments, epitaxial growth of source / drain elements 122 and 124 is performed so as to form separate, unbonded source / drain elements between adjacent gate structures.

[0074] The source / drain elements 122 and 124 can be epitaxially grown using known methods such as CVD, MOCVD, LPCVD, MBE, VPE, LPE, MOMBE, RTCVD, LEPD, UHVCVD, APCVD, or other known epitaxial growth techniques suitable for a given process flow. The type of epitaxial semiconductor material used to form the source / drain elements of the transistor depends, for example, on the type of transistor (e.g., N-type or P-type) and the epitaxial material of the active nanosheet channel layers 112, 114, and 116. For example, in the case of a PFET device, if the active nanosheet channel layers 112, 114, and 116 are formed from epitaxial Si, the source / drain elements 124 can be formed from epitaxial SiGe material (having a relatively high Ge concentration), or boron-doped SiGe (B:SiGe) epitaxial material, or other suitable epitaxial material. On the other hand, in the case of NFET devices, if the active nanosheet channel layers 112, 114, and 116 are formed from epitaxial Si, the source / drain element 122 can be formed from carbon-doped silicon (Si:C) epitaxial material, phosphorus-doped silicon (Si:P) epitaxial material, or other suitable epitaxial material.

[0075] The source / drain elements 122 and 124 can be doped using known techniques. For example, in some embodiments, the source / drain elements 122 and 124 are “in-situ” doped during the epitaxial growth process by adding a dopant gas to the source deposition gas (i.e., a Si-containing or Ge-containing source gas, or both). Exemplary dopant gases may include boron (B) or gallium (Ga)-containing gases for P-type FETs, or phosphorus (P) or arsenic (As)-containing gases for N-type FETs (e.g., PH3 or AsH3), where the concentration of impurities in the gas phase determines the concentration of impurities in the epitaxially grown semiconductor material. In other embodiments, an “ex-situ” process may be performed to add dopants to the source / drain elements 122 and 124. For example, "ex-situ" processes can be carried out by ion implantation, gas-phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid-phase doping, solid-phase doping, or any suitable combination of these techniques.

[0076] In some embodiments, a conformal layer of dielectric material is deposited to form a protective liner covering the source / drain elements 122 and 124. For example, the protective liner can be formed from a dielectric material such as SiOC, SiCN, SiN, or SiBCN, which has etching selectivity for the dielectric material of the gate capping layer 132 and the gate sidewall spacer 134.

[0077] Next, Figures 5A and 5B are schematic diagrams of the following intermediate structures of a semiconductor integrated circuit device constructed by forming an interlayer dielectric layer and performing a gate-cutting process and a substitution metal gate process, according to exemplary embodiments of the present disclosure. More specifically, Figures 5A and 5B are schematic side cross-sectional views of the intermediate structures shown in Figures 4B and 4C, respectively, after forming a first ILD layer 140 and then performing a gate-cutting process to cut (separate) gates G1, G2, and G3 by forming gate-cutting elements 137 in the cell boundary regions between adjacent cells, and after forming High-k metal gates 150 in place of dummy gates 130 and sacrificial nanosheet layers 111, 113, 115, and 117. The intermediate device structures shown in Figures 5A and 5B are formed using known techniques. For example, following the formation of source / drain elements 122 and 124, the process flow continues with the formation of a first ILD layer 140 to encapsulate the NFET devices 120-1 and 120-2 and PFET devices 120-3 and 120-4 of cells C1, C2, and C3. In some embodiments, the ILD layer 140 is formed by depositing a blanket layer of dielectric / insulating material on the semiconductor structure and planarizing the dielectric / insulating material layer up to a gate capping layer 132, thereby forming the first ILD layer 140.

[0078] The first ILD layer 140 may have any suitable insulating / dielectric material commonly used in semiconductor process technology, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, SiCOH, SiCH, SiCNH, or other types of silicon-based low-k dielectrics (e.g., k less than about 4.0), porous dielectrics, known ULK (ultra-low-k) dielectric materials (k less than about 2.5), or any suitable combination of these materials. The dielectric / dielectric material of the ILD layer 140 is deposited using known deposition techniques such as ALD, CVD, PECVD, PVD, or spin-on deposition. In some embodiments, the dielectric / dielectric material layer is planarized using a standard planarization process such as CMP to remove excess dielectric / dielectric down to the top surface of the gate capping layer 132.

[0079] Following the formation of the ILD layer 140, a gate cutting process is performed to cut gates G1, G2, and G3 in the cell boundary region to separate the gate structure between adjacent cells. In some embodiments, gates G1, G2, and G3 are cut using conventional lithography and etching processes, followed by dielectric filling and planarization processes (e.g., CMP). The gate cutting process forms a gate cutting element 137, as shown in Figure 5B. The gate cutting element 137 is formed with a target width GT such that there is a sufficient amount of space (gate extension region Gext) between the width edges of the nanosheet channel structure (e.g., stacking of active nanosheet channel layers 112, 114, and 116). In some embodiments, the gate cutting element 137 is formed from the same or similar dielectric material as the gate capping layer 132 or the gate sidewall spacer 134, or both.

[0080] Following the gate cutting process, a substitution metal gate process is performed to replace the dummy gate 130 and sacrificial nanosheet layers 111, 113, 115, and 117 with a High-k metal gate 150 (e.g., HKMG structure) using known techniques. For example, in some embodiments, the dummy gate 130 is removed using a process flow that includes removing the gate capping layer 132 to expose the dummy gate 130, and performing some etching processes to remove the dummy gate 130. More specifically, in some embodiments, the gate capping layer 132 is removed by planarizing the surface of the semiconductor structure (e.g., via CMP) up to the top surface of the dummy gate 130. In other embodiments, the dielectric material of the gate capping layer 132 (e.g., SiN) can be selectively etched away with respect to the materials of the gate sidewall spacer 134 (e.g., SiBCN), the gate cutting element 137, and the ILD layer 140 (e.g., silicon oxide) to expose the underlying dummy gate 130. As described above, in some embodiments in which the dummy gate 130 has a dummy gate electrode layer (e.g., a sacrificial polysilicon layer or an amorphous silicon layer) and a dummy gate oxide layer, the dummy gate electrode and gate oxide layer are etched off using known etching techniques and chemical etching.

[0081] For example, the sacrificial polysilicon material of the gate electrode layer can be removed using a selective dry etching or wet etching process with appropriate chemical etching including ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), or SF6 plasma. Etching of the dummy polygate layer is selective to, for example, the dummy gate oxide layer, thereby protecting the active nanosheet channel layers 112, 114, and 116 from etching during the polyetching process. After the polysilicon material has been removed, an oxide etching process is performed to selectively etch away the dummy gate oxide layer to, for example, the active nanosheet channel layers 112, 114, and 116. In this way, the sacrificial material of the dummy gate 130 (e.g., dummy polysilicon and oxide layers) can be etched away without damaging the active nanosheet channel layers 112, 114, and 116.

[0082] After removing the dummy gate 130, an etching process is performed to selectively etch away the sacrificial nanosheet layers 111, 113, 115, and 117 of the nanosheet channel structure of the NFET and PFET devices, thereby freeing the active nanosheet channel layers 112, 114, and 116 of the nanosheet channel structure, thereby forming open gate regions in the areas between the sidewall spacers 134 and in the spaces between and adjacent to the active nanosheet channel layers 112, 114, and 116. The sacrificial nanosheet layers 111, 113, 115, and 117 (e.g., epitaxial SiGe layers) can be selectively etched away relative to the active nanosheet channel layers 112, 114, and 116 (e.g., epitaxial Si layers). In some embodiments, the SiGe material of the sacrificial nanosheet layers 111, 113, 115, and 117 can be selectively etched (with high etching selectivity) using gas-phase HCl (hydrochloric acid) or a wet etching solution containing hydrogen peroxide (H2O2) to etch the epitaxial SiGe material of the sacrificial nanosheet layers 111, 113, 115, and 117 with high selectivity over the epitaxial Si material of the active nanosheet channel layers 112, 114, and 116. Gas-phase HCl (hydrochloric acid) provides high etching selectivity, for example, when the active nanosheet channel layers 112, 114, and 116 are formed from epitaxial Si or epitaxial SiGe having a lower Ge concentration than the epitaxial SiGe material of the sacrificial nanosheet layers 111, 113, 115, and 117.

[0083] Next, the substituted metal gate 150 (e.g., a High-k metal gate) is formed by a process comprising (i) depositing one or more conformal layers of High-k gate dielectric material on the exposed surface of the semiconductor structure to conformally cover the surfaces of the active nanosheet channel layers 112, 114, and 116, and (ii) depositing one or more layers of work function metal to cover the High-k gate dielectric and fill the remaining space in the open gate region to form a metal gate electrode layer. In some embodiments, the High-k gate dielectric layer is preferably formed from a High-k dielectric material having a dielectric constant of about 3.9 or higher. For example, the gate dielectric material may include, but is not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, hafnium zirconium oxide, and nitride films thereof. In other embodiments, the High-k dielectric may include lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, silicon zirconium oxide, silicon zirconium oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, scandium tantalum oxide, and lead zinc niobate. The High-k dielectric material may further contain dopants such as lanthanum and aluminum. In one embodiment of the present invention, the conformal High-k gate dielectric layer is formed with a thickness ranging from about 0.5 nm to about 2.0 nm, which varies depending on the application. The conformal layer of the High-k gate dielectric material is deposited using known methods, such as ALD, which allows for high conformability of the gate dielectric material.

[0084] As is known in the art, the use of high-k gate dielectric materials can be problematic in that such dielectric materials typically do not interface well with silicon layers. For example, high-k gate dielectric materials do not passivate the silicon surface, resulting in numerous interfacial traps and charges, as well as other problems that can degrade device performance. Therefore, in one exemplary embodiment, a channel pre-cleaning process is performed to clean the exposed silicon surfaces of the active nanosheet channel layers 112, 114, and 116 before depositing the high-k dielectric material to form the high-k gate dielectric layer, followed by an oxidation process to grow an ultrathin interfacial silicon oxide layer on the exposed surfaces of the active nanosheet channel layers 112, 114, and 116. It should be understood that the formation of the interfacial silicon oxide layer is an optional step, and in other embodiments of the invention, the high-k dielectric material of the HKMG structure can be formed on the exposed silicon surface of the active nanosheet channel layer without first forming a thin interfacial oxide layer.

[0085] In some embodiments, the interfacial silicon oxide layer is formed by a chemical oxidation process in ozonated deionized water containing ozone, and by using an appropriate oxidation temperature, ozone concentration in the deionized water, and chemical oxidation process time to form a thin interfacial silicon oxide layer. The interfacial layer is formed by oxidizing the exposed silicon surfaces of the active nanosheet channel layers 112, 114, and 116 to form a thin interfacial silicon oxide layer having a thickness ranging from about 5 angstroms to about 10 angstroms (i.e., from about 0.5 nm to about 1 nm).

[0086] In some embodiments, the metal gate 150 is formed of one or more work function metal layers conformally deposited on a High-k gate dielectric layer. The work function metal layers may have one or more types of metallic materials, but are not limited to titanium nitride (TiN), tantalum nitride (TaN), and Al-containing alloys (e.g., TiAlC, TiAl, and AlC, or their nitride alloys). In other embodiments, the work function metal layers may have metallic materials, including compositions or alloys of Zr, W, Hf, Ti, Al, Ru, Pa, ZrAl, WAl, TaAl, HfAl, TaC, TiC, TaMgC, and other types, compositions, or alloys of work function metals commonly used to obtain the target work function of FET devices. The work function metal layers are conformally deposited using known methods such as ALD and CVD, which allow for high conformability of the deposited work function metal layers.

[0087] In some embodiments, the work function metal layer completely fills the space above and below the active nanosheet channel layers 112, 114, and 116. In fact, when the initial spacing between the active nanosheet channel layers 112, 114, and 116 is relatively small (e.g., 7 nm to 10 nm), after the formation of the High-k dielectric layer, conformal deposition of two or more work function metal layers can fill the space above and below the active nanosheet channel layers 112, 114, and 116 (i.e., pinch-off) so that the space is filled with gate dielectric material and work function metal. This is L G This is sufficient for short-channel nanosheet FET devices with a wavelength of approximately 15 nm or less.

[0088] Furthermore, in some embodiments, the remaining portion of the open gate region on the active nanosheet channel layer 116 of the FET device can be filled with work function metal by continuing the deposition process of the last deposited work function metal layer until the open gate region on the active nanosheet channel layer 116 is completely filled with work function metal layer. In other embodiments, the remaining portion of the open gate region can be filled with a low-resistance metal material such as tungsten, ruthenium, cobalt, copper, or aluminum to form a metal gate electrode away from the work function metal.

[0089] Following the deposition of dielectric and metallic materials to form a metal gate 150 (e.g., an HKMG structure), a CMP process is performed to polish the surface of the semiconductor structure down to the ILD layer 140, thereby removing excess portions of the gate dielectric layer, work function layer, and gate electrode layer on the ILD layer 140. Following the formation of the metal gate 150, in some embodiments, a gate capping layer 138 is formed to cover the upper surface of the metal gate 150 before forming a second ILD layer 142. For example, following the formation of the metal gate 150, an etching process can be performed to recess the upper surface of the metal gate 150 to a target level below the upper surface of the ILD layer 140. Then, as shown in Figures 5A and 5B, a layer of dielectric material is deposited on the surface of the semiconductor device structure to fill the area above the recessed surface of the metal gate 150 with dielectric material, planarizing the semiconductor device structure down to the surface of the ILD layer 140, removing excess dielectric material, thereby forming the gate capping layer 138. The gate capping layer 138 can be formed from a dielectric material such as SiN or SiBCN.

[0090] Next, Figures 6A, 6B, and 6C are schematic diagrams of the following intermediate structures of a semiconductor integrated circuit device, constructed by forming front gate contacts and source / drain contacts according to exemplary embodiments of the present disclosure. Figure 6A is a schematic plan view of the intermediate device structure obtained by forming a second ILD layer 142 on a first ILD layer 140, forming gate contacts 151, 152, and 153 on the respective corresponding metal gate structures in cell C1, and forming front source / drain contacts 160, 161, 162, and 163. Figure 6B is a schematic side cross-sectional view of the intermediate device structure along line 6B-6B in Figure 6A, and Figure 6C is a schematic side cross-sectional view of the intermediate device structure along line 6C-6C in Figure 6A. As shown in Figure 6A, gate contacts 151, 152, and 153 are formed offset from each other so that they can connect to desired metal tracks T1-T8 (Figure 1A) that extend in the Y direction across gate structures G1, G2, and G3. The intermediate device structures shown in Figures 6A, 6B, and 6C are formed using any suitable middle-of-line (MOL) process module and material to form the MOL front gate contacts 151, 152, and 153 as well as the front source / drain contacts 160, 161, 162, and 163.

[0091] For example, the front gate contacts 151, 152, and 153, and the front source / drain contacts 160, 161, 162, and 163 are formed by a process that involves patterning / etching the first and second ILD layers 140 and 142 to form via openings within the ILD layer 142 to form via openings up to the metal gate 150, exposing portions of the source / drain elements 122 and 124 (and etching away the exposed portions of the protective liner on the source / drain elements 122 and 124), and then filling the via openings with a metallic material to form the front gate contacts 151, 152, and 153, as well as the front source / drain contacts 160, 161, 162, and 163. In some embodiments, a saliciding process is performed before the via openings are filled with metallic material to form a silicide contact layer on the exposed surface of the epitaxial source / drain elements within the via openings, before forming the source / drain contacts 160, 161, 162, and 163. Generally, the saliciding process involves a reaction between a thin metal film and the epitaxial material of the source / drain elements to form a metallic silicide contact by an annealing process.

[0092] In some embodiments, gate contacts 151, 152, and 153, as well as source / drain contacts 160, 161, 162, and 163, are formed by depositing a thin conformal diffusion barrier layer to cover the surface of the via openings, followed by depositing a metallic material on the diffusion barrier layer to fill the via openings. In some embodiments, the metallic material is any suitable material for forming the MOL contacts, but is not limited to tungsten or cobalt. The diffusion barrier layer prevents outward diffusion of oxygen from, for example, ILD layers 140 and 142, which could oxidize the metallic material used to form the front MOL contacts, while also preventing the metallic material of the contacts from diffusing into the surrounding material of the ILD layers 140 and 142. For example, the diffusion barrier layer may be a thin conformal layer of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), or any other material suitable for use as a diffusion barrier to prevent outward diffusion of the metallic material forming the front MOL contact.

[0093] Next, Figure 7 is a schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by forming an interconnect structure (e.g., a BEOL interconnect structure) on the front of the intermediate device structures of Figures 6A, 6B, and 6C according to exemplary embodiments of the present disclosure. More specifically, Figure 7 schematically shows the next step in the manufacturing process in which a BEOL interconnect structure 170 is formed on the ILD layer 142. As described above, the BEOL interconnect structure 170 has multiple levels of wiring and via structures that connect wiring between different wiring levels. For example, the BEOL interconnect structure 170 has first-level vias 174 and 175, as well as dielectric layers 171 and 172 on which metal (signal) tracks T1-T8 are formed, and a higher BEOL metallization level 173 positioned above the first-level metallization. The BEOL interconnect structure can be manufactured using any suitable BEOL process module, the details of which are well known to those skilled in the art.

[0094] Next, Figure 8 is a schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by performing a back-end process module according to an exemplary embodiment of the present disclosure, which forms a back-end interconnect structure having back-end source / drain contacts and a complete back-end power supply structure on the back of the intermediate device structure of Figure 7. The back-end process module begins by coupling a handler substrate 178 (e.g., a handler wafer) to the BEOL interconnect structure 170 to facilitate back-end processing. In some embodiments, the handler substrate 178 is temporarily coupled to the BEOL interconnect structure 170 using polymer bonding techniques (e.g., crimping or thermocompression bonding) or other suitable techniques. The handler substrate 178 may have a semiconductor substrate or a glass substrate, or any type of substrate material suitable for a given application.

[0095] The next step in the back-side processing module involves removing the semiconductor substrate 102 to expose the back surface of the BOX layer 105. The semiconductor substrate 102 is removed using known techniques such as mechanical grinding, polishing, etching, or any combination of grinding, polishing, and etching. For example, a back-side grinding / polishing process may be performed first to remove most of the semiconductor substrate 102, followed by an etching process to selectively etch the remaining portion of the semiconductor substrate 102 to expose the back surface of the BOX layer 105.

[0096] Next, the BOX layer 105 is patterned to form via holes to expose some source / drain elements 122 of some NFET devices and some source / drain elements 134 of some PFET devices in cells C1, C2, and C2. The via holes are filled with a metallic material to form, for example, back source / drain contacts 181 and 182. The back power supply structure 190 is then constructed by a process that includes forming a back dielectric layer 192 (e.g., silicon oxide, low-k dielectric material, etc.) on the BOX layer 105, patterning the back dielectric layer 192 to form trenches, and filling the trenches with a metallic material to form, for example, back power rails 194 and 195. The back source / drain contacts 181 and 182, as well as the back power rails 194 and 195, can be formed using any suitable metallic material. Furthermore, the etched via holes and trenches can be covered with one or more thin conformal liner layers that function as diffusion barrier and adhesive layers. The rear power distribution network 198 is formed on the rear dielectric layer 192 and rear power rails, for example, using BEOL fabrication techniques. In some embodiments, the rear power distribution network 198 is configured to distribute the positive and negative power supply voltage active components of the FEOL layer. The formation of the rear power distribution network 198 yields a semiconductor integrated circuit device 100 as shown in Figures 1A and 1B. In some embodiments, the handler substrate 178 is not removed and remains as part of the final structure.

[0097] Figure 9 is a schematic side cross-sectional view of a semiconductor integrated circuit device that implements rear power rails and rear power distribution grids to enable density scaling, according to another exemplary embodiment of the present disclosure. More specifically, Figure 9 is a schematic side cross-sectional view of a semiconductor integrated circuit device 200 similar to the semiconductor integrated circuit device 100 of Figures 1A and 1B, except that the front source / drain contacts 161 are connected to local (lateral) interconnect wires 261 so that the source / drain elements 124 of the PFET devices 120-3 of cell C1 can be connected to the metal track T8 of the adjacent cell C3.

[0098] The exemplary embodiment of FIG. 9 utilizes the unused space present within the front MOL layer over a source / drain element that is connected to the back power supply structure 190 by back source / drain contacts (and thus does not have front source / drain contacts). In this regard, cells C1, C2, and C3 can be formed by horizontal wiring of the MOL layer that extends across cell boundaries (e.g., boundaries B1 and B2) so as to enable the source / drain elements of one cell to be connected to the metal (signal) tracks of adjacent cells. The embodiment of FIG. 9 provides a flexible framework for local interconnect routing to avoid local MOL congestion, and the 4-track cells C1, C2, and C3 can utilize additional signal tracks within other adjacent cells.

[0099] As discussed above, the exemplary embodiments of the present disclosure implement back source / drain contacts in conjunction with a complete back power supply framework to eliminate the use of FEOL via contacts for connecting front source / drain contacts to buried power lines, thereby enabling significant scaling of the cell-to-cell spacing S2 between adjacent cells and thus reducing the cell height. A further challenge for even more aggressive scaling of the cell-to-cell spacing S2 between adjacent cells is the gate cut tolerance and the limitations associated with the "gate extension" requirement. As is known in the art, in the case of a nanosheet FET device, the gate extension (G ext ) refers to the distance / length of the gate material that extends beyond the sides of the stacked nanosheet channel structure that defines the gate width W G (or nanosheet width).

[0100] For example, as discussed above, FIG. 5B shows that the gate extension G ext of the nanosheet FET device represents the length of the space that exists between the end of the width of the nanosheet stack and the sidewall of the gate cut element 137. The gate extension G extThis depends on the size (GT) and alignment of the gate cut element 137 formed by the gate cut process. As further shown in Figure 5B, the intercell spacing S2 between NFET devices 120-1 and 120-2 in adjacent cells C2 and C1 depends on the width (GT) of the gate cut element 137 and the gate extension G of adjacent NFET devices 120-1 and 120-2. ext Similarly, the inter-cell spacing S2 between PFET devices 120-3 and 120-4 in adjacent cells C1 and C3 is equal to the width (GT) of the gate cut element 137 and the gate extension G of adjacent PFET devices 120-3 and 120-4. ext It is equal to.

[0101] As the inter-cell spacing S2 expands or contracts, the gate cut GT is properly aligned to ensure sufficient gate extension G for proper operation of the nanosheet FET device. ext It becomes more difficult to guarantee that it exists. Ideally, the gate extension G ext If the target is 10 nm and the gate cut GT is 15 nm, then a cell spacing of approximately 35 nm is desirable. However, due to tolerances of the gate cut GT regarding the size and alignment of the gate cut element 137 formed as a result of the gate cut process, for example, a target cell spacing of approximately 43 nm is required if the gate cut GT is slightly misaligned, in order for the gate extension portion to be 10 nm or more, a target gate extension portion G of 14 nm is required. ext and a target gate cut GT of 15 nm is required. As will be described in more detail below, exemplary embodiments of this disclosure have gate extensions G ext This includes techniques for precisely controlling the size and the alignment of dielectric isolation between nanosheet stacks of adjacent nanosheet FET devices.

[0102] Figures 10A and 10B are schematic diagrams of a semiconductor integrated circuit device 300 that implements a rear power rail and rear power distribution network to enable density scaling, according to another exemplary embodiment of the present disclosure. The semiconductor integrated circuit device 300, as discussed above, has gate extensions G of adjacent FET devices in adjacent cells. ext It is similar to semiconductor integrated circuit device 100 (Figures 1A and 1B), except that it has a self-aligned dielectric isolation structure for precisely controlling the size and the size of dielectric isolation between nanosheet channel stacks of adjacent FET devices in adjacent cells, thereby precisely controlling the inter-cell spacing between adjacent cells.

[0103] Similar to the exemplary semiconductor integrated circuit 100 in Figure 1A, the semiconductor integrated circuit device 300 has a plurality of cells C1, C2, and C3, and cells C1, C2, and C3 have a plurality of nanosheet FET devices 320-1, 320-2, 320-3, and 320-4 arranged on a BOX layer 305. In some embodiments, nanosheet FET devices 320-1 and 320-2 have NFET devices, and nanosheet FET devices 320-3 and 320-4 have PFET devices. NFET devices 320-1 and 320-2 have source / drain elements 322, and PFET devices 320-3 and 320-4 have source / drain elements 324. Furthermore, in exemplary embodiments, nanosheet FET devices 320-1, 320-2, 320-3, and 320-4 each have a stacked nanosheet channel structure having three active nanosheet channel layers 112, 114, and 116.

[0104] Furthermore, similar to the exemplary semiconductor integrated circuit 100 in Figure 1A, the front surface of the semiconductor integrated circuit device 300 shown in Figures 10A and 10B further comprises an ILD layer 340, a High-k metal gate 350 (encapsulating the stacked nanosheet channel structure of nanosheet FET devices 320-1, 320-2, 320-3, and 320-4), front source / drain contacts 360 and 361, and a BEOL interconnect structure 370. The BEOL interconnect structure 370 comprises dielectric layers 371 and 372 having a first metallization level and an additional BEOL metallization level 373 positioned on top of the first level of metallization. The dielectric layer 371 has a plurality of via contacts 374, 375, 376, 377, and 378 formed therein, and the dielectric layer 472 has a first metallization level M1 (or sometimes indicated as M0 or Mint) having a plurality of metal tracks T1, T2, T3, T4, T5, T6, T7, and T8. In some embodiments, the metal tracks T1-T8 provide local interconnects for distributing signals to, from, and between nanosheet FET devices 320-1, 320-2, 320-3, and 320-4, while the upper metal level 373 of the BEOL interconnect structure 370 has semi-global and global wiring. As shown in Figure 10A, the via contacts 374 and 375 connect their respective corresponding front source / drain contacts 360 and 361 to their respective metal tracks T3 and T6 of the first metallization level. Furthermore, as shown in Figure 10B, via contacts 376, 377, and 378 connect their respective corresponding metal gates 150 to the respective metal tracks T1, T4, and T8 of the first metallization level. In some embodiments, the metal gate 350 has a High-k metal gate structure.

[0105] Furthermore, similar to the exemplary semiconductor integrated circuit 100 in Figure 1A, the back of the semiconductor integrated circuit device 300 shown in Figures 10A and 10B has back source / drain contacts 381 and 382 (formed in the BOX layer 105), as well as a complete back power supply structure 390. The complete back power supply structure 390 has a back dielectric layer 392 formed on the BOX layer 305, a plurality of back power rails 394 and 396 formed within the back dielectric layer 392, and a back power distribution network 398. The back source / drain contact 381 connects the source / drain element 322 of the NFET device 320-1 of cell C2 to the back power rail 394, and the back source / drain contact 382 connects the source / drain element 324 of the PFET device 320-4 of cell C3 to the back power rail 394. The rear power distribution network 398 has one or more levels of wiring configured to distribute a positive supply voltage (e.g., VDD) and a negative supply voltage (e.g., VSS, ground (GND) = 0V) to the rear power rails 394 and 396. For example, in an exemplary embodiment, the rear power distribution network 398 connects the negative supply voltage (VSS) to the rear power rail 394 and the positive supply voltage (VDD) to the rear power rail 396.

[0106] Furthermore, as shown in Figures 10A and 10B, the semiconductor integrated circuit device 300 has an upper gate cut element 355 that functions to collectively isolate multiple self-aligned dielectric isolation elements 315 and the gate structures 350 of nanosheet FET devices in adjacent cells. The self-aligned dielectric isolation elements 315 have a wider upper part positioned on a stack of nanosheet channel layers 112, 114, and 116 and a narrower lower part positioned between the stacks of nanosheet channel layers 112, 114, and 116. The upper gate cut element 355 is formed in alignment with the self-aligned dielectric isolation elements 315 in the cell boundary region between adjacent cells, and is formed on the wider upper part of the self-aligned dielectric isolation elements 315 in the cell boundary region, isolating metal gate electrodes 350 in different cells.

[0107] As shown in Figure 10B, the self-aligned dielectric isolation element 315 extends the gate extension portion G of the nanosheet FET devices 320-1, 320-2, 320-3, and 320-4. ext It functions to precisely control the size of. Furthermore, as shown in Figure 10B, the wider upper part of the self-aligned dielectric isolation element 315 in the cell boundary region has a width equal to the inter-cell spacing S2 between adjacent cells, and the narrower lower part of the self-aligned dielectric isolation element 315 in the cell boundary region provides a clearly defined dielectric isolation (or lower gate cut) of the metal gate material between adjacent stacks of nanosheet channel layers of adjacent FET devices in adjacent cells. The narrower lower part of the self-aligned dielectric isolation element 315 in the cell boundary region provides a controlled spacing D of dielectric isolation between adjacent FET devices in adjacent cells, where D represents a lower gate cut size that may have a smaller critical dimension (e.g., 8 nm) than the upper gate cut size defined by the width of the upper gate cut element 355. This configuration allows G ext This can be precisely controlled using the techniques discussed in more detail below, so the inter-cell spacing S2, S2 = D + 2G ext This enables aggressive scaling. For example, in a non-limiting exemplary embodiment, G ext The size of is approximately 10 nm (or less), and D is approximately 8 nm (or less), resulting in an inter-cell spacing S2 of approximately 28 nm (or less).

[0108] Figures 11 to 16C schematically illustrate a method for manufacturing the semiconductor integrated circuit device 300 of Figures 10A and 10B according to another exemplary embodiment of the present disclosure. To begin, Figure 11 is a schematic side cross-sectional view (XZ plane) of an intermediate device structure of the semiconductor integrated circuit device 300 in an intermediate stage of manufacturing, having a semiconductor substrate 302, an insulating layer 305, a plurality of patterned nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4 disposed on the insulating layer 305, and a hard mask layer 306 disposed on the patterned nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4. Similar to the exemplary embodiments discussed above, the patterned nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4 each have a stack of epitaxial semiconductor layers 111, 112, 113, 114, 115, 116, and 117, including sacrificial nanosheet layers 111, 113, 115, and 117, and active nanosheet channel layers 112, 114, and 116.

[0109] Using the hard mask layer 306, the initial nanosheet stacked structure (for example, the nanosheet stacked structure 110 shown in Figure 2) is patterned, and the gate width W of the FET device in the cell is determined. G Patterned nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4 are formed to define the boundaries. In the exemplary embodiment of Figure 11, the intercellular spacing S2 of the cell boundaries between patterned nanosheet stacked structures 310-1 and 310-2, and between patterned nanosheet stacked structures 310-3 and 310-4, can be scaled to about 28 nm (or less). The intermediate structures of Figure 11 are formed using the same or similar materials and techniques as those discussed above in relation to Figures 2, 3A, and 3B, the details of which will not be repeated.

[0110] Next, Figure 12 is a schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by forming a sacrificial spacer layer 304 on the sidewalls of patterned nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4 according to an exemplary embodiment of the present disclosure. The sacrificial spacer layer 304 is formed on the target gate extension length G ext It is formed to a thickness equal to the above. In some embodiments, the sacrificial spacer layer 304 is formed by a process comprising (i) depositing a conformal layer of sacrificial material on the intermediate device structure of Figure 11, and (ii) anisotropically etching the conformal layer sacrificial material to form the sacrificial spacer layer 304.

[0111] In some embodiments, the conformal layer of the sacrificial material has a SiGe alloy material deposited using an atomic layer deposition (ALD) process. The use of SiGe material allows the sacrificial spacer layer 304 to be selectively etched off along with the sacrificial nanosheet layers 111, 113, 115, and 117 during the subsequent process, releasing the active nanosheet channel layers 112, 114, and 116 to form the metal gate 350. The use of ALD deposits a highly conformal layer of the sacrificial material, and therefore the thickness of the conformal layer of the sacrificial material is set to the target gate extension length G ext This allows for precise control. For example, in some embodiments, the sacrificial spacer layer 304 is formed with a thickness of approximately 10 nm. Target gate extension length G ext Following the deposition of a conformal layer of sacrificial material having a thickness equal to , an anisotropic etching process (e.g., a reactive ion etching (RIE) process) is performed to completely remove the horizontal portions of the conformal layer of sacrificial material on the sides of the structure and to recess the vertical portions of the conformal layer of sacrificial material on the hard mask layer 306 to a target level above the tops of the patterned nanosheet laminated structures 310-1, 310-2, 310-3, and 310-4, as shown in Figure 12.

[0112] Next, Figure 13 is a schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by forming a self-aligned dielectric isolation element 315 between patterned nanosheet stacks 310-1, 310-2, 310-3, and 310-4 according to an exemplary embodiment of the present disclosure. In some embodiments, the self-aligned dielectric isolation element 315 is formed by depositing layers of dielectric material to fill the spaces between the patterned nanosheet stacks 310-1, 310-2, 310-3, and 310-4 with the dielectric material, followed by a planarization process (e.g., CMP) to remove excess dielectric material up to the top surface of the hard mask layer 302, as shown in Figure 13. In some embodiments, the self-aligned dielectric isolation element 315 is formed from different dielectric materials having etching selectivity with respect to the dielectric material of the hard mask layer. For example, assuming that the hard mask layer 302 is formed from SiN, the self-aligned dielectric isolation element 315 can be formed using a Low-kSiC material or a Low-kSiOC material, etc.

[0113] Next, Figures 14A, 14B, and 14C are schematic diagrams of the following intermediate structures of a semiconductor integrated circuit device constructed by forming the source / drain elements of an FET device by forming dummy gate structures, according to exemplary embodiments of the present disclosure. Specifically, Figure 14A is a schematic plan view (XY plane) of the intermediate device structure, Figure 14B is a schematic side section view (XZ plane) of the intermediate device structure along line 14B-14B shown in Figure 14A, and Figure 14C is a schematic side section view (YZ plane) of the semiconductor structure obtained along line 14C-14C shown in Figure 14A. Specifically, as schematically shown in Figure 14A, multiple dummy gate structures G1, G2, and G3 are formed across the cell. Compared to the exemplary embodiments shown in Figures 4A to 4C above, the gate structures G1, G2, and G3 are not yet cut at the cell boundary region and do not form separate gate structures. During the gate formation process, the patterned nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4 (as shown in Figure 13) are further patterned (in the Y direction) to form individual nanosheet stacked structures for individual NFET devices 320-1 and 320-2 in cells C1 and C2, and individual nanosheet stacked structures for individual PFET devices 320-3 and 320-4 in cells C1 and C3. The additional patterning of the nanosheet stacked structures 310-1, 310-2, 310-3, and 310-4 results in the gate length L of the transistors in the cells, as shown in Figures 14A and 14C. G Define the area.

[0114] As shown in Figures 14A, 14B, and 14C, the gate structures G1, G2, and G3 have a dummy gate 330 (e.g., a conformal oxide layer and a dummy gate electrode layer (e.g., a sacrificial polysilicon material or amorphous silicon material)). Furthermore, the gate structures G1, G2, and G3 have a gate capping layer 332, a gate sidewall spacer 334, and an embedded sidewall spacer 336. Following the formation of the embedded gate sidewall spacers 136, the source / drain elements 322 of NFET devices 320-1 and 320-2 are epitaxially grown on the exposed sidewall surfaces of the active nanosheet channel layers 112, 114, and 116 of NFET devices 320-1 and 320-2 using a first epitaxy process, and the source / drain elements 324 of PFET devices 320-3 and 320-4 are epitaxially grown on the exposed sidewall surfaces of the active nanosheet channel layers 112, 114, and 116 of PFET devices 320-3 and 320-4 using a second epitaxy process. The intermediate device structures shown in Figures 14A, 14B, and 14C can be fabricated using the same or similar methods discussed above in relation to Figures 4A, 4B, and 4C, and it should be understood that the details will not be repeated.

[0115] The process flow for forming the intermediate device structures shown in Figures 14A, 14B, and 14C differs from the process flow described above in relation to Figures 4A, 4B, and 4C in that the gate cutting process is not yet performed on the gate structures G1, G2, and G3 that straddle the cell boundaries, but rather forms separate dummy gate structures. For example, compared to the exemplary embodiment shown in Figure 4C in which cells C1, C2, and C3 have separate dummy gate structures 130, the exemplary embodiment in Figure 14B shows that cells C1, C2, and C3 have separate dummy gate structures 130 resulting from the gate cutting process. However, as shown in Figure 14B, the self-aligned dielectric isolation element 315 essentially provides (i) a clearly defined gate cut between the stacked nanosheet channel layers of adjacent NFET devices 320-1 and 320-2 of adjacent cells C2 and C1, and (ii) a clearly defined gate cut between the stacked nanosheet channel layers of adjacent PFET devices 320-3 and 320-4 of adjacent cells C1 and C3, even though cells C1, C2, and C3 share a dummy gate 330 that is not cut at this stage of the manufacturing process.

[0116] Next, Figures 15A and 15B are schematic diagrams of the next intermediate structure of a semiconductor integrated circuit device constructed by performing a substitution metal gate process to form an interlayer dielectric layer and replace a dummy gate with a metal gate, according to exemplary embodiments of the present disclosure. More specifically, Figures 15A and 15B are schematic side cross-sectional views of the intermediate structure shown in Figures 14B and 14C, respectively, after forming a first ILD layer 340 and a metal gate 350 in place of a dummy gate 330. In some embodiments, the intermediate device structure shown in Figures 15A and 15B is formed using the same materials and process flow described above in relation to Figures 5A and 5B, the details of which will not be repeated.

[0117] As shown in Figure 15A, during the substitution metal gate process before forming the metal gate 350, the sacrificial spacer layer 304 is etched away along with the sacrificial nanosheet layers 111, 113, 115, and 117, freeing the active nanosheet channel layers 112, 114, and 116, and a clearly defined gate extension region G filled with metallic material is formed to form the metal gate 350 which encapsulates the active nanosheet channel layers 112, 114, and 116. ext This configuration forms the self-aligned dielectric isolation element 315 and the sacrificial spacer layer 304, as described above, which result in clearly defined and highly scaled inter-cell spacing S2 between adjacent cells C1 and C2, and between C1 and C3. As shown in Figure 15A, following the substitution metal gate process, cells C1, C2, and C3 share the metal gate 350 that has not been cut at this stage of the manufacturing process.

[0118] Next, Figures 16A, 16B, and 16C are schematic diagrams of the following intermediate structures of a semiconductor integrated circuit device, constructed by performing a late-gate process to form upper gate-cut elements to isolate the metal gate structures of a nanosheet FET device in adjacent cells, according to exemplary embodiments of the present disclosure. More specifically, Figure 16A is a schematic plan view of an intermediate device structure showing a plurality of upper gate-cut elements 355 formed within the cell boundary regions of gate structures G1, G2, and G3 to isolate the metal gates 350 in different cells C1, C2, and C3. Figure 16B is a schematic side cross-sectional view of the intermediate device structure along line 16B-16B in Figure 16A, and Figure 16C is a schematic side cross-sectional view of the intermediate device structure along line 16C-16C in Figure 16A.

[0119] As shown in Figures 16B and 16C, the upper gate cut element 355 is formed in alignment with the self-aligned dielectric isolation element 315 within the cell boundary region. The upper gate cut element 355 is configured to cut the continuous metal gate electrode 350 formed along the gate structures G1, G2, and G3 following the substitution metal gate process, as shown in Figures 16A and 16B, thereby forming a separate metal gate electrode. This late gate cut process allows the upper gate cut element 355 to extend beyond the narrower portion below the self-aligned dielectric isolation element 315 and into the clearly defined gate extension region G ext This serves to isolate the gate electrodes 350 in adjacent cells without affecting the clearly defined and highly scaled inter-cell spacing S2 present between adjacent cells C1 and C2, and between C1 and C3. Thus, the upper gate cut element 355 can be manufactured with relaxed tolerances.

[0120] In some embodiments, the upper gate cut element 355 is created by a process comprising: (i) forming an etching mask on the intermediate device structure shown in Figures 15A and 15B, wherein the etching mask has an opening that is aligned with the top of the self-aligned dielectric isolation element 315 in the cell boundary region; (ii) etching the exposed portion of the metal gate 350 (exposed through the etching mask opening) up to the top surface of the self-aligned dielectric isolation element 315 in the cell boundary region; (iii) depositing a layer of dielectric material on the ILD layer 340 to fill the etched trench in the metal gate 350 with dielectric material; and (iv) performing a planarization process (e.g., CMP) to remove excess dielectric material down to the ILD layer 340. In some embodiments, the upper gate cut element 355 is formed from a dielectric material such as SiN, SiOCN, SiBCN, SiC or SiOC, or other suitable dielectric material.

[0121] Following the late gate cut process, an additional front process is performed to form the front MOL source / drain contacts 360 and 361, as well as the BEOL interconnect structure 370. Subsequently, a back process is performed to form the rear source / drain contacts 381 and 382, ​​as well as the complete rear power supply structure 390, within the BOX layer 105, resulting in the semiconductor integrated circuit device 300 shown in Figures 10A and 10B. In some embodiments, the front and back processes are performed using the same or similar materials and techniques discussed above in relation to Figures 6A-6C, 7, 8, and 9, the details of which will not be repeated.

[0122] Figures 17A and 17B are schematic diagrams of a semiconductor integrated circuit device 400 that implements a rear power rail and rear power distribution network to enable density scaling, according to another exemplary embodiment of the present disclosure. The semiconductor integrated circuit device 400 is as discussed above, and the semiconductor integrated circuit device 400 is (i) a gate extension portion G of the FET device ext (ii) the size of the dielectric isolation formed in the cell boundary region between the N-type fork-sheet FET pair and the P-type fork-sheet FET pair of adjacent FET devices in adjacent cells is precisely controlled, thereby enabling further scaling of the inter-cell spacing by utilizing fork-sheet FET devices in conjunction with a self-aligned dielectric isolation structure to precisely control the inter-cell spacing between adjacent cells.

[0123] Similar to the exemplary semiconductor integrated circuit 300 in Figures 10A and 10B, the semiconductor integrated circuit device 400 has a plurality of cells C1, C2, and C3, and cells C1, C2, and C3 have a plurality of nanosheet FET devices 420-1, 420-2, 420-3, and 420-4 arranged on a BOX layer 405. In some embodiments, nanosheet FET devices 420-1 and 420-2 are NFET devices, and nanosheet FET devices 420-3 and 420-4 are PFET devices. NFET devices 420-1 and 420-2 have source / drain elements 422, and PFET devices 420-3 and 420-4 have source / drain elements 424. Furthermore, in exemplary embodiments, the nanosheet FET devices 420-1, 420-2, 420-3, and 420-4 each have a stacked nanosheet channel structure having three active nanosheet channel layers 112, 114, and 116.

[0124] Furthermore, similar to the exemplary semiconductor integrated circuit device 300 in Figures 10A and 10B, the front surface of the semiconductor integrated circuit device 400 shown in Figures 17A and 17B further comprises an ILD layer 440, a metal gate 450 (encapsulating the stacked nanosheet channel structure of nanosheet FET devices 420-1, 420-2, 420-3, and 420-4), front source / drain contacts 460 and 461, and a BEOL interconnect structure 470. The BEOL interconnect structure 470 comprises dielectric layers 471 and 472 having a first metallization level and an additional BEOL metallization level 473 positioned on top of the first level of metallization. The dielectric layer 471 has a plurality of via contacts 474, 475, 476, 477, and 478 formed therein, and the dielectric layer 472 has a first metallization level M1 (or sometimes indicated as M0 or Mint) having a plurality of metal tracks T1, T2, T3, T4, T5, T6, T7, and T8. In some embodiments, the metal tracks T1-T8 provide local interconnects for distributing signals to, from, and between nanosheet FET devices 420-1, 420-2, 420-3, and 420-4, while the upper metal level 473 of the BEOL interconnect structure 470 has semi-global and global wiring. As shown in Figure 17A, the via contacts 474 and 475 connect their respective corresponding front source / drain contacts 460 and 461 to their respective metal tracks T3 and T6 of the first metallization level. Furthermore, as shown in Figure 17B, via contacts 476, 477, and 478 connect their respective corresponding metal gates 450 to their respective corresponding metal tracks T1, T4, and T8 of the first metallization level. In some embodiments, the metal gate 4350 has a High-k metal gate structure.

[0125] Furthermore, similar to the exemplary semiconductor integrated circuit device 300 in Figures 10A and 10B, the back of the semiconductor integrated circuit device 400 shown in Figures 17A and 17B has back source / drain contacts 481 and 482 (formed in the BOX layer 405), as well as a complete back power supply structure 490. The complete back power supply structure 490 has a back dielectric layer 492 formed on the BOX layer 405, a plurality of back power rails 494 and 496 formed within the back dielectric layer 492, and a back power distribution network 498. The back source / drain contact 481 connects the source / drain element 422 of the NFET device 420-1 of cell C2 to the back power rail 494, and the back source / drain contact 482 connects the source / drain element 424 of the PFET device 420-4 of cell C3 to the back power rail 494. The rear power distribution network 498 has one or more levels of wiring configured to distribute a positive supply voltage (e.g., VDD) and a negative supply voltage (e.g., VSS, ground (GND) = 0V) to the rear power rails 494 and 496. For example, in an exemplary embodiment, the rear power distribution network 498 connects the negative supply voltage (VSS) to the rear power rail 494 and the positive supply voltage (VDD) to the rear power rail 496.

[0126] As further shown in Figures 17A and 17B, the semiconductor integrated circuit device 400 has a plurality of self-aligned dielectric isolation elements 415 and 417, as well as an upper gate cut element 455 formed in alignment with the self-aligned dielectric isolation element 417 in the cell boundary region to isolate the metal gate 450 of nanosheet FET devices in adjacent cells. The self-aligned dielectric isolation element 415 has a wider upper part located on the stack of nanosheet channel layers 112, 114, and 116 and a narrower lower part located between the stack of nanosheet channel layers 112, 114, and 116. As shown in Figure 17B, the self-aligned dielectric isolation element 415 extends the gate extension G of nanosheet FET devices 420-1, 420-2, 420-3, and 420-4 as discussed above. ext It functions to precisely control the size of [the object].

[0127] On the other hand, the self-aligned dielectric isolation element 417 functions as a dielectric wall for the fork-sheet FET devices formed by adjacent pairs of NFET devices 420-1 and 420-2 of adjacent cells C2 and C1, and for the fork-sheet FET devices formed by adjacent pairs of PFET devices 420-3 and 420-4 of adjacent cells C1 and C3. In this exemplary structural configuration, the self-aligned dielectric isolation element 417 (or alternatively, the fork-sheet dielectric wall 417) is formed to have a controlled thickness that defines the inter-cell spacing S2 between adjacent cells C1 and C2, and between C1 and C3, thereby narrowing the spacing between adjacent NFET devices 420-1 and 420-2, and between adjacent PFET devices 420-3 and 420-4, and thus reducing the cell height and thus the inter-cell spacing. For example, in a non-limiting exemplary embodiment, as shown in Figure 17B, the inter-cell spacing S2 can be reduced to about 10 nm. Aggressive scaling in this respect is further facilitated by the implementation of a complete rear-side power supply structure 490, as shown in Figure 17A, where adjacent pairs of source / drain elements 422 of NFET devices 420-1 and 420-2 are connected to rear-side source / drain contacts 481 and front-side source / drain contacts 460, respectively, thereby avoiding short circuits of the source / drain contacts for the reasons discussed above.

[0128] Figures 18–20 schematically illustrate a method for manufacturing the semiconductor integrated circuit device 400 of Figures 17A and 17B according to another exemplary embodiment of the present disclosure. It should be understood that the process for manufacturing the semiconductor integrated circuit device 400 is identical or similar to the process flows for manufacturing the semiconductor integrated circuit devices 10 and 300 discussed above, and that details will not be repeated. Instead, the process flows schematically shown in Figures 18–20 illustrate additional or slightly modified process steps used in conjunction with the previous process flows discussed above to manufacture the semiconductor integrated circuit device 400.

[0129] First, Figure 18 is a schematic side cross-sectional view (XZ plane) of an intermediate structure of a semiconductor integrated circuit device 400 in an intermediate stage of manufacturing, having a semiconductor substrate 402, an insulating layer 405 (e.g., a BOX layer 405), a plurality of patterned nanosheet stacks 410A and 410B disposed on the insulating layer 405, and a hard mask layer 406 disposed on the patterned nanosheet stacks 410A and 410B. In this manufacturing process, a first nanosheet patterning process is performed to define the N to P spacing S1 of complementary FET devices within a cell. In the exemplary embodiment of Figure 18, the patterned nanosheet stacks 410A and 410B have nanosheet stacks that are used to form NN fork-sheet FET devices and PP fork-sheet FET devices, respectively, across the cell boundary.

[0130] Next, Figure 19 is a schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by forming a sacrificial spacer layer 404 on the sidewalls of patterned nanosheet stacks 410A and 410B according to an exemplary embodiment of the present disclosure, and further patterning the nanosheet stacks 410A and 410B to form patterned nanosheet stacks 410-1, 410-2, 410-3, and 410-4. The sacrificial spacer layer 404 is formed using the same or similar materials and techniques discussed above in relation to Figure 12. The sacrificial spacer layer 404 has a target gate extension length G ext It is formed with a thickness equal to .

[0131] Following the formation of a sacrificial spacer layer 404 on the sidewalls of the patterned nanosheet stacked structures 410A and 410B, another nanosheet patterning process is performed to form trenches in the patterned nanosheet stacked structures 410A and 410B, thereby determining the gate width W of the FET device of the cell. GPatterned nanosheet stacked structures 410-1, 410-2, 410-3, and 410-4 are formed, defining the inter-cell spacing S2 between adjacent cells. For example, as shown in Figure 19, in some embodiments, an organic planarization layer 408 is deposited and patterned and etched down to the exposed portions of the nanosheet stacked structures 410A and 410B to form openings 408-1 and 408-2, which are used to form the patterned nanosheet stacked structures 410-1, 410-2, 410-3, and 410-4. As shown in Figure 19, the openings 408-1 and 408-2 have a width that defines the thickness of the dielectric wall 417 of the fork sheet FET device, and the thickness of the dielectric wall 417 defines the inter-cell spacing S2 between adjacent cells.

[0132] Next, Figure 20 is a schematic side cross-sectional view of the next intermediate structure of a semiconductor integrated circuit device, constructed by forming self-aligned dielectric isolation elements 415 and 417 between patterned nanosheet stacked structures 410-1, 410-2, 410-3, and 410-4 according to exemplary embodiments of the present disclosure. In some embodiments, the self-aligned dielectric isolation elements 415 and 417 are formed using the same materials and process steps discussed above in relation to Figure 13. Following the formation of the intermediate structure shown in Figure 20, additional front and back process modules are performed using the same or similar materials and process steps discussed above to form the resulting semiconductor integrated circuit device 400 shown in Figures 17A and 17B.

[0133] It should be understood that the exemplary methods for manufacturing stacked complementary transistor structures discussed herein can be readily incorporated into semiconductor process flows, semiconductor devices, and integrated circuits having various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be manufactured with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, and inductors. As disclosed herein, integrated circuits can be used in applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, mobile communication devices (e.g., mobile phones), solid-state media storage devices, and functional circuits. Systems and hardware incorporating such integrated circuits are considered part of the exemplary embodiments described herein. Given the teachings of the invention provided herein, those skilled in the art will be able to contemplate other implementations and applications of the exemplary techniques disclosed herein.

[0134] While exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the present invention is not limited to these exact embodiments, and various other changes and modifications can be made herein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. The first interconnection structure, The second interconnection structure, A first cell having a first transistor, A second cell having a second transistor, A first contact connects the front surfaces of the source / drain elements of the first transistor to the first interconnection structure, A second contact connects the back surfaces of the source / drain elements of the second transistor to the second interconnection structure. Equipped with, The first cell is positioned adjacent to the second cell, and the first transistor is positioned adjacent to the second transistor. A device in which the first cell and the second cell are arranged between the first interconnection structure and the second interconnection structure.

2. The device according to claim 1, wherein the first interconnection structure has a signal network and the second interconnection structure has a power distribution network.

3. The device according to claim 1, wherein the distance between the first transistor and the second transistor defines the inter-cell distance between the first cell and the second cell.

4. The device according to claim 1, wherein the first transistor and the second transistor include gate-all-around field-effect transistors.

5. The device according to claim 1, wherein the second interconnection structure comprises a plurality of rear power rails arranged in a dielectric layer and a power distribution network coupled to the plurality of rear power rails.

6. The device according to claim 1, wherein the first transistor and the second transistor include one of an adjacent pair of N-type field-effect transistors and an adjacent pair of P-type field-effect transistors.

7. The device according to claim 1, wherein the first transistor and the second transistor include a fork-sheet type field-effect transistor pair having a dielectric wall disposed between the first transistor and the second transistor, the width of the dielectric wall defining the inter-cell spacing between the first cell and the second cell.

8. The device according to any one of claims 1 to 7, further comprising a lateral interconnection extending from the first cell to the second cell, wherein the lateral interconnection is positioned between the first interconnection structure and the source / drain elements of the second transistor in the second cell, and the lateral interconnection connects the first contact to a signal track of the first interconnection structure in the second cell.

9. A first cell having a first transistor, A second cell having a second transistor, wherein the first cell and the second cell are arranged adjacent to each other, and the first transistor and the second transistor are arranged adjacent to each other, A separation structure is disposed in the cell boundary region between the first cell and the second cell, A first interconnection structure connected to the front of the source / drain elements of the first transistor, A second interconnection structure connected to the back surface of the source / drain elements of the second transistor and Equipped with, The isolation structure has a first portion disposed on the first active channel structure of the first transistor and the second active channel structure of the second transistor, and a second portion disposed between the first active channel structure and the second active channel structure. The first portion of the separation structure has a first width substantially equal to the distance between the first active channel structure and the second active channel structure. The second portion of the separation structure has a second width smaller than the first width, The space between the second portion of the separation structure and the first active channel structure and the second active channel structure defines the gate extension lengths of the first transistor and the second transistor. The first cell and the second cell are arranged between the first interconnection structure and the second interconnection structure. device.

10. The device according to claim 9, wherein the second width is approximately 8 nanometers or less, and the gate extension length is approximately 10 nanometers or less.

11. The device according to claim 9, further comprising a gate cut element disposed on the first portion of the separation structure, wherein the gate cut element and the separation structure are configured to separate the first metal gate structure of the first transistor and the second metal gate structure of the second transistor.

12. The device according to claim 11, wherein the gate cutting element is disposed within the metal material of the first metal gate structure and the second metal gate structure.

13. The device according to claim 9, wherein the first transistor and the second transistor include one of an adjacent pair of N-type field-effect transistors and an adjacent pair of P-type field-effect transistors.

14. The device according to claim 9, wherein the first active channel structure and the second active channel structure have a stacked active nanosheet channel structure.

15. The first interconnection structure, The second interconnection structure, A first contact that connects the source / drain elements of the first transistor to the first interconnection structure, The present invention further comprises a second contact connecting the source / drain elements of the second transistor to the second interconnection structure, The device according to any one of claims 9 to 14, wherein the first cell and the second cell are arranged between the first interconnection structure and the second interconnection structure.

16. The device according to claim 15, wherein the first interconnection structure has a signal network and the second interconnection structure has a power distribution network.

17. The device according to claim 15, further comprising a lateral interconnect extending from the first cell to the second cell, wherein the lateral interconnect is positioned between the first interconnect structure and the source / drain elements of the second transistor in the second cell, and the lateral interconnect connects the first contact to the signal track of the first interconnect structure in the second cell.

18. A first cell having a first transistor, A second cell having a second transistor, A first interconnection structure connected to the front of the source / drain elements of the first transistor, A second interconnection structure connected to the back surface of the source / drain elements of the second transistor and Equipped with, The first cell and the second cell are arranged adjacent to each other, The first transistor and the second transistor include a pair of fork-sheet type field-effect transistors having an insulating wall positioned between the first transistor and the second transistor. The insulating wall is aligned with the cell boundary between the first cell and the second cell. The width of the insulating wall defines the inter-cell spacing between the first cell and the second cell. The first cell and the second cell are arranged between the first interconnection structure and the second interconnection structure. device.

19. The device according to claim 18, wherein the first transistor and the second transistor include one of a pair of N-type nanosheet field-effect transistors and a pair of P-type nanosheet field-effect transistors.

20. The first interconnection structure, The second interconnection structure, A first contact that connects the source / drain elements of the first transistor to the first interconnection structure, The present invention further comprises a second contact connecting the source / drain elements of the second transistor to the second interconnection structure, The device according to claim 18 or 19, wherein the first cell and the second cell are arranged between the first interconnection structure and the second interconnection structure.

21. A method for manufacturing semiconductor devices, A step of forming a first cell and a second cell on a substrate, wherein the first cell includes a first transistor, the second cell includes a second transistor, the first cell and the second cell are arranged adjacent to each other, and the first transistor and the second transistor are arranged adjacent to each other; The steps include forming a first contact connected to the front surface of the source / drain element of the first transistor, The steps include forming a first interconnection structure connected to the front surface of the first contact, The steps include etching the substrate to form an opening that exposes the back surface of the source / drain element of the second transistor, The steps include forming a second contact in the opening connected to the back surface of the source / drain element of the second transistor, The step of forming a second interconnection structure connected to the back surface of the second contact, A method for providing this.

22. The method according to claim 21, wherein the first interconnection structure has a signal network and the second interconnection structure has a power distribution network.

23. A method for manufacturing semiconductor devices, A step of forming a first nanosheet channel structure for a first transistor and a second nanosheet channel structure for a second transistor on a substrate, wherein the first nanosheet channel structure and the second nanosheet channel structure are arranged adjacent to each other and separated by a space defining the intercellular spacing between the first cell and the second cell, each containing the first transistor and the second transistor, respectively. The steps include forming a conformal sacrificial spacer layer on adjacent side walls of the first nanosheet channel structure and the second nanosheet channel structure, The steps include forming a dielectric isolation structure between the conformal sacrificial spacer layer on the sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, A step of selectively etching away the conformal sacrificial spacer layer on the sidewalls of the first nanosheet channel structure and the second nanosheet channel structure to form a space between the dielectric isolation structure and the sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, wherein the space defines and forms the gate extension lengths of the first transistor and the second transistor. The steps include filling the space with a metallic material to form the first metallic gate structure of the first transistor and the second metallic gate structure of the second transistor. A method for providing this.

24. The dielectric isolation structure includes a first portion disposed on the first nanosheet channel structure and the second nanosheet channel structure, and a second portion disposed between the first nanosheet channel structure and the second nanosheet channel structure. The method according to claim 23, wherein the first portion of the dielectric isolation structure has a first width substantially equal to the inter-cell spacing between the first cell and the second cell.

25. The method according to claim 24, further comprising the step of forming a gate cut element on the first portion of the dielectric isolation structure, wherein the gate cut element and the dielectric isolation structure are configured to separate the first metal gate structure of the first transistor and the second metal gate structure of the second transistor.